WO2021012449A1 - Tft器件及其制备方法、tft阵列基板 - Google Patents

Tft器件及其制备方法、tft阵列基板 Download PDF

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Publication number
WO2021012449A1
WO2021012449A1 PCT/CN2019/115245 CN2019115245W WO2021012449A1 WO 2021012449 A1 WO2021012449 A1 WO 2021012449A1 CN 2019115245 W CN2019115245 W CN 2019115245W WO 2021012449 A1 WO2021012449 A1 WO 2021012449A1
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Prior art keywords
layer
tft device
barrier layer
base substrate
tft
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PCT/CN2019/115245
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English (en)
French (fr)
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罗传宝
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/618,827 priority Critical patent/US11411117B2/en
Publication of WO2021012449A1 publication Critical patent/WO2021012449A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • This application relates to the field of flat panel display technology, and in particular to a TFT device, a preparation method thereof, and a TFT array substrate.
  • TFT Thin Film Transistor
  • the development of high-resolution display panels requires the use of molybdenum and copper in the light-shielding layer of thin film transistors to reduce the wiring area of the gate or source/drain.
  • the copper in the light-shielding layer can easily diffuse into the buffer layer and the active layer, resulting in contact resistance And the parasitic capacitance increases, the threshold voltage drifts, the stability of thin film transistors decreases, and the device performance deteriorates; when suitable SiNx is introduced as a buffer layer material to reduce the effect of threshold voltage drift, the vapor deposition of SiNx has an impact on the ITO after etching;
  • the buffer layer is in contact with the source through the signal via to compensate for the voltage change of the metal layer.
  • the fluorine-based oxidizing gas When the fluorine-based oxidizing gas is used to dry the hole on the buffer layer, the fluorine-based oxidizing gas will oxidize the copper ions in the light-shielding layer, resulting in The contact resistance between the light-shielding layer and the source becomes larger, which reduces the electrical characteristics of the TFT.
  • the purpose of this application is to provide a TFT device, a preparation method thereof, and a TFT array substrate. It can solve the problem that the copper in the light shielding layer of the thin film transistor in the prior art is easily diffused into the buffer layer and the active layer.
  • the fluorine-based oxidizing gas causes the copper ions in the light-shielding layer to oxidize , which causes the contact resistance and parasitic capacitance of the TFT device to become larger, and reduces the technical problem of the electrical characteristics of the TFT.
  • the embodiments of the present application provide a TFT device, including a base substrate and a light shielding layer provided on the base substrate; the light shielding layer includes a metal laminated on the base substrate.
  • the barrier layer is used to prevent the copper ions in the metal layer from diffusing into the active layer of the TFT device in a direction away from the base substrate.
  • the barrier layer includes a diffusion barrier layer and an etching barrier layer stacked on the metal layer.
  • the material of the diffusion barrier layer includes one or more materials among molybdenum, titanium and tantalum.
  • the material of the etching barrier layer is indium gallium zinc oxide or indium tin oxide.
  • the material of the etch stop layer is indium gallium zinc oxide, and the etch stop layer is a conductive layer after conduction.
  • the interlayer dielectric layer and the buffer layer in the TFT device are provided with signal vias corresponding to the upper part of the light shielding layer, and the source electrode of the TFT device is electrically connected to the barrier layer through the signal vias .
  • an embodiment of the present application also provides a method for manufacturing a TFT device, the method including:
  • Step S10 providing a base substrate.
  • step S20 a metal layer and a barrier layer are sequentially prepared on the base substrate to form a light shielding layer.
  • the method further includes:
  • Step S201 preparing a diffusion barrier layer on the metal layer.
  • Step S202 preparing an etching barrier layer on the diffusion barrier layer.
  • the material of the etch stop layer is indium gallium zinc oxide, and the etch stop layer is conductively processed to reduce the oxygen content in the metal oxide semiconductor material, so that the resistivity of the metal oxide semiconductor material Fall and become a conductor.
  • a TFT array substrate includes a TFT device, the TFT device includes a base substrate and a light shielding layer provided on the base substrate; the light shielding layer It includes a metal layer and a barrier layer laminated on the base substrate, and the barrier layer is used to block copper ions in the metal layer from diffusing to the TFT device in a direction away from the base substrate.
  • the barrier layer is used to block copper ions in the metal layer from diffusing to the TFT device in a direction away from the base substrate.
  • the light-shielding layer is provided with a barrier layer to prevent copper ions in the metal layer of the light-shielding layer from diffusing into the buffer layer and the active layer, and an etching barrier layer is added to the barrier layer to prevent
  • the buffer layer uses a fluorine-based oxidizing gas to dry-etch the signal vias
  • the copper ions in the metal layer are oxidized by the fluorine-based oxidizing gas, and at the same time, the copper ions are further prevented from continuing to diffuse.
  • the source electrode passes through the signal vias and the etching barrier layer. Sexual connection eliminates TFT threshold voltage drift, thereby improving the electrical characteristics and stability of TFT devices.
  • FIG. 1 is a schematic structural diagram of a TFT device provided by an embodiment of the application.
  • FIG. 2 is a flow chart of a method for manufacturing a TFT device according to an embodiment of the application.
  • FIG. 3a is a schematic diagram of a process of preparing a light-shielding layer in a TFT device according to an embodiment of the application.
  • FIG. 3b is a schematic diagram of a process of preparing an active layer in a TFT device according to an embodiment of the application.
  • FIG. 3c is a schematic diagram of a gate preparation process in a TFT device provided by an embodiment of the application.
  • FIG. 3d is a schematic diagram of a process of preparing an interlayer dielectric layer in a TFT device according to an embodiment of the application.
  • FIG. 3e is a schematic diagram of a process for preparing source/drain electrodes in a TFT device according to an embodiment of the application.
  • FIG. 3f is a schematic diagram of a process of preparing a passivation layer in a TFT device according to an embodiment of the application.
  • This application aims at the fact that copper in the light shielding layer of thin film transistors in the prior art is easily diffused into the buffer layer and the active layer.
  • a fluorine-based oxidizing gas is used to dry-etch holes, the fluorine-based oxidizing gas will oxidize the copper ions in the light-shielding layer
  • the reaction causes the contact resistance and parasitic capacitance of the TFT device to increase, and the technical problem of reducing the electrical characteristics of the TFT device. This embodiment can solve this defect.
  • the present application provides a TFT device 100, which includes a base substrate 101 and a light-shielding layer 102 disposed on the base substrate 101; the light-shielding layer 102 includes a metal layer 1021 and a metal layer 1021 sequentially disposed on the base substrate 101.
  • the barrier layer 1022, the barrier layer 1022 is used to prevent the copper ions in the metal layer 1021 from diffusing into the active layer 104 of the TFT device 100 in the direction away from the base substrate 101, which causes the contact resistance and parasitic capacitance of the TFT device 100 to increase, which affects the TFT Device 100 electrical characteristics.
  • a TFT device 100 includes a light-shielding layer 102 provided on a base substrate 101, a buffer layer 103 provided on the base substrate 101 and covering the light-shielding layer 102, an active layer 104 provided on the buffer layer 103,
  • the gate insulating layer 105 disposed on the active layer 104, the gate 106 disposed on the gate insulating layer 105, the interlayer dielectric layer 107 disposed on the buffer layer 103 and covering the gate 106 and the active layer 104 are disposed on The source electrode 1081 and the drain electrode 1091 on the interlayer dielectric layer 107, the passivation layer 201 provided on the interlayer dielectric layer 107 and covering the source electrode 1081 and the drain electrode 1091, and the pixel electrode layer 2021 provided on the passivation layer 201 .
  • the interlayer dielectric layer 107 and the buffer layer 103 are provided with signal vias 1083 corresponding to the top of the light shielding layer 102; the active layer 104 includes a channel region corresponding to the bottom of the gate insulating layer 105 and sources located on both sides of the channel region.
  • the material of the electrode contact area and the drain contact area, the source contact area and the drain contact area is a conductive metal oxide semiconductor material, and the material of the channel area is a metal oxide semiconductor material that maintains semiconductor characteristics;
  • an interlayer dielectric layer 107 is provided with a source contact hole 1082 and a drain contact hole 1092 corresponding to the source contact area and the drain contact area respectively.
  • the interlayer dielectric layer 107 and the buffer layer 103 are provided with signals corresponding to the light shielding layer 102.
  • the source 1081 and the drain 1091 are electrically connected through the source contact hole 1082 and the drain contact hole 1092, and the source contact area and the drain contact area of the active layer 104, while the source 1081 passes through the signal
  • the hole 1083 is electrically connected to the light shielding layer 102
  • the pixel electrode layer 2021 is connected to the drain 1091 through the pixel via 2022 on the passivation layer 201, wherein the orthographic projection of the light shielding layer 102 on the base substrate 101 covers the active layer 104
  • the orthographic projection on the base substrate 100 enables the light shielding layer 102 to completely cover the active layer 104, prevents the active layer 104 from being irradiated by light, and avoids negative drift of the threshold voltage of the TFT device 100.
  • the light shielding layer 102 is provided with a barrier layer 1022 on the surface of the metal layer 1021.
  • the material of the barrier layer 1022 is preferably the same as that of aluminum. Metals such as molybdenum, titanium and tantalum.
  • a fluorine-based oxidizing gas is used, which causes the copper ions in the metal layer 1021 to be oxidized by the fluorine-based oxidizing gas; in the barrier layer 1022, the diffusion barrier layer 1023 is sequentially arranged on the metal layer 1021 And the etch barrier layer 1024; the diffusion barrier layer 1023 and the etch barrier layer 1024 can prevent copper ions in the metal layer 1021 from diffusing into the buffer layer and the active layer.
  • the material of the etch barrier layer 1024 is indium gallium zinc oxide or Indium tin oxide, the In-O bond in In2O3 in indium gallium zinc oxide can form an energy barrier for the diffusion of copper ions to form an In-O-Cu grid to further prevent the continued diffusion of copper ions, while indium tin oxide
  • the structure containing In-O prevents copper ions from entering the interface between the buffer layer 103 and the active layer 104 to increase the energy barrier; secondly, the etching barrier layer 1024 is also used to prevent the copper ions in the metal layer 1021 from being oxidized.
  • the etching barrier layer 1024 When the material of the etching barrier layer 1024 is indium tin oxide, the etching barrier layer 1024 itself can serve as a conductor, and the source electrode 1081 is electrically connected to the etching barrier layer 1024 through the signal via 1083.
  • the indium gallium zinc oxide is a semiconductor material with poor conductivity.
  • the etching barrier layer 1024 needs to be conductive. Treatment, using ionomers to conduct conductive treatment on the etching barrier layer 1024 to reduce the oxygen element content in the metal oxide semiconductor material of the etching barrier layer 1024, so that the resistivity of the metal oxide semiconductor material is reduced and becomes a conductor.
  • the ion body includes one or more of helium plasma, argon plasma and ammonia plasma.
  • the light-shielding layer in the TFT device is provided with a barrier layer, which prevents the copper ions in the metal layer in the light-shielding layer from diffusing into the buffer layer and the active layer, resulting in an increase in TFT contact resistance and parasitic capacitance, threshold voltage drift, and etching in the barrier layer
  • the barrier layer prevents the copper ions in the metal layer from being oxidized by the fluorine-based oxidizing gas when the fluorine-based oxidizing gas is used to dry the signal vias in the buffer layer, and at the same time, it further prevents the copper ions from continuing to diffuse.
  • the source passes through the signal vias and
  • the etch barrier layer is electrically connected to eliminate the voltage change of the metal layer in the light-shielding layer and ensure the electrical characteristics and stability of the TFT device.
  • an embodiment of the present application provides a flow chart of a method for manufacturing a TFT device, and the method includes:
  • Step S10 providing a base substrate.
  • step S20 a metal layer and a barrier layer are sequentially prepared on the base substrate to form a light shielding layer.
  • step S20 the method further includes:
  • Step S201 preparing a diffusion barrier layer on the metal layer.
  • Step S202 preparing an etching barrier layer on the diffusion barrier layer.
  • the material of the etch stop layer is indium gallium zinc oxide, and the etch stop layer is conductively processed to reduce the oxygen content in the metal oxide semiconductor material, so that the resistance of the metal oxide semiconductor material The rate drops and becomes a conductor.
  • an embodiment of the present application provides a method for preparing a TFT device including:
  • a base substrate 101 is provided, and a metal layer 1021 and a barrier layer 1022 are sequentially prepared on the base substrate 101 by a physical vapor deposition method to form a light shielding layer 102, wherein the barrier layer 1022 includes the metal layer The diffusion barrier layer 1023 and the etching barrier layer 1024.
  • the material of the metal layer 1021 is metal, preferably metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti); the material of the diffusion barrier layer 1023 includes One or more than two materials among molybdenum, titanium and tantalum; the material of the etching barrier layer is indium gallium zinc oxide or indium tin oxide.
  • a buffer layer 103 covering the light-shielding layer 102 is prepared on the base substrate 101, and an active layer 104 is prepared on the buffer layer 103, wherein the buffer layer 103 is a silicon oxide (SiOx) film, a nitride Silicon (SiNx) films, or composite films formed by alternately stacking silicon oxide films and silicon nitride films; the material of the active layer 104 is indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide
  • the active layer 104 is deposited on the buffer layer 103 by one of the magnetron sputtering method, the metal organic chemical vapor deposition method or the pulsed laser evaporation method, and the active layer 104 is to be deposited After completion, an annealing treatment can be carried out, which can be annealed at 400°C in a dry air atmosphere for about 0.5 hours.
  • the active layer 104 is etched using a wet etching process or a dry etching process using oxalic acid as the etching solution. After the etching process, the entire metal oxide film of the active layer 104 will be patterned , Forming an island-shaped metal oxide semiconductor layer.
  • the gate insulating layer 105 is provided on the active layer 104, and the gate 106 is provided on the gate insulating layer 105.
  • the material of the gate insulating layer 105 is generally silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a sandwich structure of the three; the material of the gate 106 is a metal material, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), Tungsten (W), molybdenum (Mo), chromium (Cr), etc.
  • the gate 106 is formed on the gate insulating layer 105 by a physical vapor deposition method, and a gate pattern is formed by a photolithography process.
  • the material of the gate 106 may be a metal material, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), etc.
  • an interlayer dielectric layer 107 covering the gate 106 and the active layer 104 is prepared on the buffer layer 103.
  • the interlayer dielectric layer 107 and the buffer layer 103 correspond to the top of the light shielding layer 102, using fluorine-based oxidation
  • a signal via hole 1083 is formed on the interlayer dielectric layer 107 corresponding to the source doped region, and a fluorine-based oxidizing gas is used to open a source contact hole 1082 on the interlayer dielectric layer 107 corresponding to the drain electrode. Above the doped region, a fluorine-based oxidizing gas is used to open a drain contact hole 1092.
  • a source electrode 1081 and a drain electrode 1091 are prepared on the interlayer dielectric layer 107, wherein the source electrode 1081 is electrically connected to the source doped region through the source contact hole 1082 in the interlayer dielectric layer 107, and the drain The electrode 1091 is electrically connected to the drain doped region through the drain contact hole 1092 in the interlayer dielectric layer 107, and the source electrode 1081 and the light shielding layer 102 are electrically connected through the signal via 1083.
  • a passivation layer 201 covering the source electrode 1081 and the drain electrode 1091 is prepared on the interlayer dielectric layer 107, and a pattern of the passivation layer 201 is formed by a photolithography process.
  • the pattern of the pixel electrode layer 2021 is formed by the engraving process, and the oxalic acid-based chemical solution is used as the etchant of the pixel electrode layer 2021 to prepare the pixel electrode layer 2021, wherein the pixel electrode layer 2021 passes through the pixel via 2022 and the drain on the passivation layer 201 1091 connected.
  • a TFT array substrate including the TFT device of the above-mentioned embodiment.
  • the TFT device includes a base substrate and a light-shielding layer provided on the base substrate; the light-shielding layer includes a stack provided on the base substrate.
  • the upper metal layer and barrier layer, the barrier layer is used to prevent the copper ions in the metal layer from diffusing into the active layer of the TFT device in the direction away from the base substrate.
  • the light shielding layer is provided with a barrier layer to prevent copper ions in the metal layer in the light shielding layer from diffusing into the buffer layer and the active layer, resulting in an increase in TFT contact resistance and parasitic capacitance, threshold voltage drift, and an additional addition in the barrier layer
  • the etching barrier layer prevents the copper ions in the metal layer from being oxidized by the fluorine-based oxidizing gas when the signal via is dry-etched with a fluorine-based oxidizing gas in the buffer layer, and at the same time, it further prevents the continuous diffusion of copper ions, and the source passes the signal through
  • the hole is electrically connected to the etch stop layer to eliminate TFT threshold voltage drift, thereby improving the electrical characteristics and stability of the TFT device.

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Abstract

一种TFT器件（100）及其制备方法、TFT阵列基板，遮光层（102）设置有阻挡层（1022），阻挡金属层（1021）中铜离子扩散到缓冲层（103）和有源层（104）中，阻挡层（1022）中还增设刻蚀阻挡层（1024），防止在缓冲层（103）使用氟系氧化性气体干刻信号过孔（1083）时，造成金属层（1021）中铜离子被氟系氧化性气体氧化，提高TFT器件（100）性能稳定性，源极（1081）通过信号过孔（1083）和遮光层（102）电性连接，消除TFT阈值电压漂移。

Description

TFT器件及其制备方法、TFT阵列基板 技术领域
本申请涉及属于平板显示技术领域，尤其涉及一种TFT器件及其制备方法、TFT阵列基板。
 背景技术
金属氧化物薄膜晶体管(Thin Film Transistor，TFT)在有源矩阵液晶显示和有源矩阵有机电致发光二极管领域得到广泛的应用，具有超高分辨率，大尺寸，高帧率处理和可见光范围内穿透率高等显著优点。
开发高分辨率的显示面板需要在薄膜晶体管的遮光层用钼和铜，减少栅极或者源/漏极的走线面积，遮光层中铜极易扩散到缓冲层和有源层，导致接触电阻和寄生电容增大，阈值电压漂移，薄膜晶体管稳定性下降，器件性能恶化；当引入合适的SiNx作为缓冲层材料以降低阈值电压漂移影响时，因SiNx 的气相沉积对蚀刻后ITO有影响；其次缓冲层通过信号过孔与源极接触以补偿金属层的电压变化，在缓冲层上使用氟系氧化性气体干刻开孔时，氟系氧化性气体使遮光层中铜离子发生氧化反应，导致遮光层与源极的接触电阻变大，降低TFT的电学特性。
综上所述，需要设计出一种TFT器件结构，以解决现有技术中薄膜晶体管的遮光层中铜极易扩散到缓冲层和有源层，使用氟系氧化性气体干刻开孔时，氟系氧化性气体使遮光层中铜离子发生氧化反应，导致TFT器件的接触电阻和寄生电容变大，降低TFT的电学特性的技术问题。
 技术问题
本申请的目的在于提供一种TFT器件及其制备方法、TFT阵列基板。能够解决现有技术中薄膜晶体管的遮光层中铜极易扩散到缓冲层和有源层，使用氟系氧化性气体干刻开孔时，氟系氧化性气体使遮光层中铜离子发生氧化反应，导致TFT器件的接触电阻和寄生电容变大，降低TFT的电学特性的技术问题。
 技术解决方案
为了解决上述问题，本申请实施例提供提供一种TFT器件，包括衬底基板以及设置在所述衬底基板上的遮光层；所述遮光层包括叠层设置在所述衬底基板上的金属层和阻挡层，所述阻挡层用于阻挡所述金属层中铜离子向远离所述衬底基板的方向上扩散到所述TFT器件的有源层中。
其中，所述阻挡层包括叠层设置在所述金属层上的扩散阻挡层和刻蚀阻挡层。
其中，所述扩散阻挡层的材料包括钼、钛和钽中一种或一种以上的材料。
其中，所述刻蚀阻挡层的材料为铟镓锌氧化物或铟锡氧化物。
其中，所述刻蚀阻挡层的材料为铟镓锌氧化物，所述刻蚀阻挡层为导体化后的导电层。
其中，所述TFT器件中层间介质层与缓冲层上设有对应于所述遮光层上方的信号过孔，所述TFT器件中源极通过所述信号过孔和所述阻挡层电性连接。
为了解决上述问题，本申请实施例还提供了一种TFT器件的制备方法，所述方法包括：
步骤S10、提供衬底基板。
步骤S20、在所述衬底基板依次制备金属层、阻挡层，形成遮光层。
其中，在所述步骤S20中，所述方法还包括：
步骤S201、在所述金属层上制备扩散阻挡层。
步骤S202、在所述扩散阻挡层上制备刻蚀阻挡层。
其中，所述刻蚀阻挡层的材料为铟镓锌氧化物，对所述刻蚀阻挡层进行导体化处理，降低金属氧化物半导体材料中的氧元素含量，使金属氧化物半导体材料的电阻率下降，变为导体。
依据本申请的上述目的，还提供提供一种TFT阵列基板，所述TFT阵列基板包括TFT器件，所述TFT器件包括衬底基板以及设置在所述衬底基板上的遮光层；所述遮光层包括叠层设置在所述衬底基板上的金属层和阻挡层，所述阻挡层用于阻挡所述金属层中铜离子向远离所述衬底基板的方向上扩散到所述TFT器件的有源层中。
 有益效果
本申请提供一种TFT器件及其制备方法，遮光层设置有阻挡层，阻挡遮光层中金属层中铜离子扩散到缓冲层和有源层中，阻挡层中还增设刻蚀阻挡层，防止在缓冲层使用氟系氧化性气体干刻信号过孔时，导致金属层中铜离子被氟系氧化性气体氧化，同时进一步阻止铜离子继续扩散，其次源极通过信号过孔和刻蚀阻挡层电性连接，消除TFT阈值电压漂移，从而提升TFT器件的电学特性及稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供一种TFT器件结构示意图。
图2为本申请实施例提供一种TFT器件的制备方法流程图。
图3a为本申请实施例提供一种TFT器件中制备遮光层流程示意图。
图3b为本申请实施例提供一种TFT器件中制备有源层流程示意图。
图3c为本申请实施例提供一种TFT器件中制备栅极流程示意图。
图3d为本申请实施例提供一种TFT器件中制备层间介质层流程示意图。
图3e为本申请实施例提供一种TFT器件中制备源/漏极流程示意图。
图3f为本申请实施例提供一种TFT器件中制备钝化层流程示意图。
 本发明的实施方式
下面结合附图和实施例，对本申请作进一步的详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
本申请针对现有技术中薄膜晶体管的遮光层中铜极易扩散到缓冲层和有源层，使用氟系氧化性气体干刻开孔时，氟系氧化性气体使遮光层中铜离子发生氧化反应，导致TFT器件的接触电阻和寄生电容变大，降低TFT器件的电学特性的技术问题，本实施例能够解决该缺陷。
如图1所示，本申请提供一种TFT器件100，包括衬底基板101以及设置在衬底基板101上的遮光层102；遮光层102包括依次设置在衬底基板101上的金属层1021和阻挡层1022，阻挡层1022用于阻挡金属层1021中铜离子向远离衬底基板101的方向扩散到TFT器件100的有源层104中，导致TFT器件100接触电阻和寄生电容增大，影响TFT器件100电学特性。
具体地，一种TFT器件100包括设于衬底基板101上的遮光层102、设于衬底基板101上且覆盖遮光层102的缓冲层103、设于缓冲层103上的有源层104、设于有源层104上的栅绝缘层105、设于栅绝缘层105上的栅极106、设于缓冲层103上且覆盖栅极106与有源层104的层间介质层107、设于层间介质层107上的源极1081与漏极1091、设于层间介质层107上且覆盖源极1081与漏极1091的钝化层201、以及设于钝化层201上像素电极层2021。
层间介质层107与缓冲层103上设有对应于遮光层102上方的信号过孔1083；有源层104包括对应于栅绝缘层105下方的沟道区以及分别位于沟道区两侧的源极接触区与漏极接触区，源极接触区与漏极接触区的材料为导体化的金属氧化物半导体材料，沟道区的材料为保持半导体特性的金属氧化物半导体材料；层间介质层107上设有分别对应于源极接触区与漏极接触区上方的源极接触孔1082与漏极接触孔1092，层间介质层107与缓冲层103上设有对应于遮光层102上方的信号过孔1083；源极1081与漏极1091分别通过源极接触孔1082与漏极接触孔1092和有源层104的源极接触区与漏极接触区电性连接，同时源极1081通过信号过孔1083和遮光层102电性连接，像素电极层2021通过钝化层201上的像素过孔2022与漏极1091相连，其中，遮光层102在衬底基板101上的正投影覆盖有源层104在衬底基板100上的正投影，从而使遮光层102能够对有源层104进行完全遮盖，防止有源层104受到光线照射，避免了TFT器件100阈值电压产生负漂。
为了解决遮光层102中金属层1021中铜离子扩散到缓冲层103和有源层104中，导致TFT接触电阻和寄生电容增大，阈值电压漂移，TFT器件稳定性下降，性能恶化，影响显示面板的显示品质的问题，本实施例中遮光层102在金属层1021表面增设阻挡层1022，为增加金属层1021中铜离子扩散的阻挡效果，阻挡层1022的材料优选与铝性能无太大差别的钼、钛和钽等金属。
为防止缓冲层103开设信号过孔1083时，使用氟系氧化性气体，导致金属层1021中铜离子被氟系氧化性气体氧化；阻挡层1022中依次设置在金属层1021上的扩散阻挡层1023和刻蚀阻挡层1024；扩散阻挡层1023和刻蚀阻挡层1024均可以阻止金属层1021中铜离子扩散到缓冲层和有源层中，刻蚀阻挡层1024的材料为铟镓锌氧化物或铟锡氧化物，铟镓锌氧化物中的In2O3中的In-O键可形成铜离子扩散的能级壁垒形成In-O-Cu的网格，进一步阻止铜离子继续扩散，而铟锡氧化物中含In-O结构，防止铜离子进入缓冲层103到有源层104界面，增加能级壁垒；其次刻蚀阻挡层1024还用于防止金属层1021中铜离子被氧化。
当刻蚀阻挡层1024的材料为铟锡氧化物时，刻蚀阻挡层1024本身可以作为导体，源极1081通过信号过孔1083和刻蚀阻挡层1024电性连接。
当刻蚀阻挡层1024的材料为铟镓锌氧化物时，铟镓锌氧化物为半导体材料，导电性能较差，为了改善刻蚀阻挡层1024导电性能，需要对刻蚀阻挡层1024进行导体化处理，使用离子体对刻蚀阻挡层1024进行导体化处理，降低刻蚀阻挡层1024的金属氧化物半导体材料中的氧元素含量，使金属氧化物半导体材料的电阻率下降，变为导体，其中，离子体包括氦气等离子体、氩气等离子体及氨气等离子体中的一种或多种。
TFT器件中遮光层设置有阻挡层，阻挡遮光层中金属层中铜离子扩散到缓冲层和有源层中，导致TFT接触电阻和寄生电容增大，阈值电压漂移，阻挡层中还增设刻蚀阻挡层，防止在缓冲层使用氟系氧化性气体干刻信号过孔时，导致金属层中铜离子被氟系氧化性气体氧化，同时进一步阻止铜离子继续扩散，其次源极通过信号过孔和刻蚀阻挡层电性连接，消除遮光层中金属层的电压变化，确保TFT器件的电学特性及稳定性。
依据上述一种TFT器件，如图2所示，本申请实施例提供一种TFT器件的制备方法流程图，该方法包括：
步骤S10、提供衬底基板。
步骤S20、在所述衬底基板依次制备金属层、阻挡层，形成遮光层。
优选地，在步骤S20中，方法还包括：
步骤S201、在所述金属层上制备扩散阻挡层。
步骤S202、在所述扩散阻挡层上制备刻蚀阻挡层。
优选地，所述刻蚀阻挡层的材料为铟镓锌氧化物，对所述刻蚀阻挡层进行导体化处理，降低金属氧化物半导体材料中的氧元素含量，使金属氧化物半导体材料的电阻率下降，变为导体。
具体地，本申请实施例提供一种TFT器件制备方法包括：
如图3a所示，提供衬底基板101，利用物理气相沉积法在衬底基板101依次制备金属层1021、阻挡层1022，形成遮光层102，其中，阻挡层1022包括依次设置在金属层上的扩散阻挡层1023和刻蚀阻挡层1024，金属层1021的材料为金属，优选钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)等金属材料；扩散阻挡层1023的材料包括钼、钛和钽中一种或两种以上的材料；刻蚀阻挡层的材料为铟镓锌氧化物或铟锡氧化物。
如图3b所示，在衬底基板101上制备覆盖于遮光层102的缓冲层103、在缓冲层103上的制备有源层104，其中，缓冲层103为氧化硅(SiOx)薄膜、氮化硅(SiNx)薄膜、或者氧化硅薄膜与氮化硅薄膜交替层叠设置形成的复合薄膜；有源层104的材料为铟镓锌氧化物、铟锌锡氧化物、以及铟镓锌锡氧化物中的一种或多种材料；通过磁控溅镀法、金属有机化学气相沉积法或脉冲雷射蒸镀法中的一种方法在缓冲层103上沉积有源层104，待有源层104沉积完成后，再进行退火处理，可以在400℃干燥空气氛围下退火处理约0.5小时。
退火处理完成后，采用草酸作为刻蚀液的湿法蚀刻工艺或干法刻蚀工艺对有源层104进行刻蚀，经过蚀刻制程后，有源层104的整层金属氧化物薄膜将图案化，形成岛状的金属氧化物半导体层。
如图3c所示，设于有源层104上的栅绝缘层105、设于栅绝缘层105上的栅极106，其中，栅绝缘层105的材料一般为氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiON)、或者三者的夹层结构等；栅极106的材料为金属材料，例如是铜(Cu)、铝(Al)、钛(Ti)、钽(Ta)、钨(W)、钼(Mo)、铬(Cr)等。栅极106经物理气相沉积方法形成于栅绝缘层105上，再经由一次光刻制程形成栅极图案。栅极106的材料可以是金属材料，例如是铜(Cu)、铝(Al)、钛(Ti)、钽(Ta)、钨(W)、钼(Mo)、铬(Cr)等。
如图3d所示，在缓冲层103上制备覆盖于栅极106与有源层104的层间介质层107，层间介质层107与缓冲层103上对应于遮光层102上方，使用氟系氧化性气体开设信号过孔1083，在层间介质层107上对应于于源极掺杂区上方，使用氟系氧化性气体开设源极接触孔1082，在层间介质层107上对应于于漏极掺杂区上方，使用氟系氧化性气体开设漏极接触孔1092。
如图3e所示，在层间介质层107上制备源极1081与漏极1091，其中，源极1081通过层间介质层107中源极接触孔1082与源极掺杂区电性连接，漏极1091通过层间介质层107中漏极接触孔1092与漏极掺杂区电性连接，同时源极1081和遮光层102通过信号过孔1083电性连接。
如图3f所示，在层间介质层107上制备覆盖于源极1081与漏极1091的钝化层201、经光刻工艺形成钝化层201的图案，在钝化层201上，经光刻工艺形成像素电极层2021的图案，使用草酸系药液作为像素电极层2021的蚀刻剂，制备像素电极层2021，其中，像素电极层2021通过钝化层201上的像素过孔2022与漏极1091相连。
依据本申请的上述目的，提供一种TFT阵列基板，包括上述实施例一种TFT器件，TFT器件包括衬底基板以及设置在衬底基板上的遮光层；遮光层包括叠层设置在衬底基板上的金属层和阻挡层，阻挡层用于阻挡金属层中铜离子向远离衬底基板的方向上扩散到TFT器件的有源层中。
本申请的有益效果：遮光层设置阻挡层，阻挡遮光层中金属层中铜离子扩散到缓冲层和有源层中，导致TFT接触电阻和寄生电容增大，阈值电压漂移，阻挡层中还增设刻蚀阻挡层，防止在缓冲层使用氟系氧化性气体干刻信号过孔时，导致金属层中铜离子被氟系氧化性气体氧化，同时进一步阻止铜离子继续扩散，其次源极通过信号过孔和刻蚀阻挡层电性连接，消除TFT阈值电压漂移，从而提升TFT器件的电学特性及稳定性。
综上，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种TFT器件，其包括衬底基板以及设置在所述衬底基板上的遮光层；所述遮光层包括叠层设置在所述衬底基板上的金属层和阻挡层，所述阻挡层用于阻挡所述金属层中铜离子向远离所述衬底基板的方向上扩散到所述TFT器件的有源层中。
  2. 根据权利要求1所述的TFT器件，其中，所述阻挡层包括叠层设置在所述金属层上的扩散阻挡层和刻蚀阻挡层。
  3. 根据权利要求2所述的TFT器件，其中，所述扩散阻挡层的材料包括钼、钛和钽中一种或两种以上的材料。
  4. 根据权利要求2所述的TFT器件，其中，所述刻蚀阻挡层的材料为铟镓锌氧化物或铟锡氧化物。
  5. 根据权利要求2所述的TFT器件，其中，所述刻蚀阻挡层的材料为铟镓锌氧化物，所述刻蚀阻挡层为导体化后的导电层。
  6. 根据权利要求1所述的TFT器件，其中，所述TFT器件中层间介质层与缓冲层上设有对应于所述遮光层上方的信号过孔，所述TFT器件中源极通过所述信号过孔和所述阻挡层电性连接。
  7. 一种TFT器件的制备方法，其中，所述方法包括：
    步骤S10、提供衬底基板；
    步骤S20、在所述衬底基板上叠层制备金属层、阻挡层，形成遮光层。
  8. 根据权利要求7所述的TFT器件的制备方法，其中，在所述步骤S20中，所述方法还包括：
    步骤S201、在所述金属层上制备扩散阻挡层；
    步骤S202、在所述扩散阻挡层上制备刻蚀阻挡层。
  9. 根据权利要求8所述的TFT器件的制备方法，其中，所述刻蚀阻挡层的材料为铟镓锌氧化物，对所述刻蚀阻挡层进行导体化处理，降低金属氧化物半导体材料中的氧元素含量，使金属氧化物半导体材料的电阻率下降，变为导体。
  10. 一种TFT阵列基板，其包括TFT器件，所述TFT器件包括衬底基板以及设置在所述衬底基板上的遮光层；所述遮光层包括叠层设置在所述衬底基板上的金属层和阻挡层，所述阻挡层用于阻挡所述金属层中铜离子向远离所述衬底基板的方向上扩散到所述TFT器件的有源层中。
PCT/CN2019/115245 2019-07-24 2019-11-04 Tft器件及其制备方法、tft阵列基板 WO2021012449A1 (zh)

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Families Citing this family (6)

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Publication number Priority date Publication date Assignee Title
CN110931509B (zh) * 2019-11-25 2022-12-06 Tcl华星光电技术有限公司 阵列基板及其制备方法
CN110942995A (zh) * 2019-11-26 2020-03-31 深圳市华星光电半导体显示技术有限公司 顶栅型氧化物阵列基板及其制备方法
CN111613664A (zh) * 2020-05-26 2020-09-01 深圳市华星光电半导体显示技术有限公司 薄膜晶体管及其制备方法、显示面板
US11217698B2 (en) 2020-05-26 2022-01-04 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Method of manufacturing a thin film transistor
CN112034655A (zh) * 2020-08-19 2020-12-04 武汉华星光电技术有限公司 液晶显示面板
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040155245A1 (en) * 2003-02-12 2004-08-12 Nec Corporation Thin film transistor and method for manufacturing the same
CN107492555A (zh) * 2016-06-13 2017-12-19 三星显示有限公司 晶体管阵列面板
CN108010935A (zh) * 2016-10-27 2018-05-08 乐金显示有限公司 有机发光显示装置及其制造方法
CN109037346A (zh) * 2018-07-27 2018-12-18 京东方科技集团股份有限公司 薄膜晶体管、显示基板及其制作方法、显示装置
CN109887976A (zh) * 2019-03-07 2019-06-14 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法及显示面板和显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108470717B (zh) * 2017-02-22 2021-04-06 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040155245A1 (en) * 2003-02-12 2004-08-12 Nec Corporation Thin film transistor and method for manufacturing the same
CN107492555A (zh) * 2016-06-13 2017-12-19 三星显示有限公司 晶体管阵列面板
CN108010935A (zh) * 2016-10-27 2018-05-08 乐金显示有限公司 有机发光显示装置及其制造方法
CN109037346A (zh) * 2018-07-27 2018-12-18 京东方科技集团股份有限公司 薄膜晶体管、显示基板及其制作方法、显示装置
CN109887976A (zh) * 2019-03-07 2019-06-14 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法及显示面板和显示装置

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