WO2016150075A1 - 薄膜晶体管、薄膜晶体管的制备方法及阵列基板 - Google Patents

薄膜晶体管、薄膜晶体管的制备方法及阵列基板 Download PDF

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WO2016150075A1
WO2016150075A1 PCT/CN2015/086756 CN2015086756W WO2016150075A1 WO 2016150075 A1 WO2016150075 A1 WO 2016150075A1 CN 2015086756 W CN2015086756 W CN 2015086756W WO 2016150075 A1 WO2016150075 A1 WO 2016150075A1
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drain
source
layer
conductive layer
thin film
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PCT/CN2015/086756
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English (en)
French (fr)
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李旭远
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京东方科技集团股份有限公司
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Priority to US14/906,490 priority Critical patent/US10199510B2/en
Publication of WO2016150075A1 publication Critical patent/WO2016150075A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a method of fabricating a thin film transistor, and an array substrate.
  • a thin film transistor using an oxide semiconductor such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO) as an active layer has a high electron mobility; and copper (Cu), silver (Ag), or the like is used.
  • a low-resistivity metal material is used as a thin film transistor of a gate, a source, and a drain, and its resistance can be remarkably lowered; therefore, a thin film transistor in a large-sized display device generally uses an oxide semiconductor as an active layer, and uses Cu, Ag, or the like.
  • a low resistivity metal material acts as a gate, a source, and a drain. Based on the advantages of both of the above, the obtained thin film transistor can achieve higher resolution and higher refresh rate, thereby obtaining a better display effect.
  • a thin film transistor 1 is prepared on a substrate 2, and includes a gate electrode 10, an active layer 11, a source electrode 12, and a drain electrode 13.
  • the active layer 11 is made of an oxide semiconductor material such as IGZO or ITZO, so that the thin film transistor 1 has a high electron mobility; and the active layer 11 is located above the source 12 and the drain 13 (ie, the source). 12.
  • the drain 13 is prepared prior to the active layer 11).
  • the source 12 includes a source first conductive layer 120 and a source second buffer layer 121 disposed under the source first conductive layer 120 and a source first buffer layer 122 disposed above the source first conductive layer 120.
  • the drain 13 includes a drain first conductive layer 130 and a drain second buffer layer 131 disposed under the drain first conductive layer 130 and a drain first buffer layer 132 disposed above the drain first conductive layer 130.
  • the source first conductive layer 120 may be specifically made of Cu to reduce the resistance of the source.
  • the base layer is generally a gate insulating layer when the thin film transistor 1 is a bottom gate structure, and the base layer is generally used when the thin film transistor 1 is a top gate structure.
  • the adhesion between the substrates 2) is small, and therefore, the source second buffer layer 121 is disposed under the source first conductive layer 120.
  • the source second buffer layer 121 may be specifically prepared from molybdenum (Mo), titanium (Ti), chromium (Cr), molybdenum-niobium alloy (MoNb) or the like so that there is a large adhesion between the source 12 and the base layer ( Mo, Ti, Cr and The adhesion between the metal or alloy such as MoNb and the base layer is large, and at the same time, there is a large adhesion between Cu and the above metal or alloy.
  • the source first buffer layer 122 can also be prepared from Mo, Ti, Cr, MoNb, etc., for avoiding contact of the upper surface of the source first conductive layer 120 with the active layer 11, thereby preventing diffusion of Cu atoms to the active layer. In 11, and preventing oxygen in the active layer 11 from being absorbed by the source first conductive layer 120. At the same time, the source first buffer layer 122 can also form a good ohmic contact with the active layer 11.
  • drain first conductive layer 130 The case of the drain first conductive layer 130, the drain second buffer layer 131, and the drain first buffer layer 132 in the drain 13 is similar to that in the source 12 described above, and details are not described herein again.
  • the sidewalls of the source first conductive layer 120 and the drain first conductive layer 130 are in contact with the active layer 11, which causes the source first conductive layer 120 and the drain first conductive layer 130.
  • the easily diffused Cu atoms diffuse into the active layer 11.
  • the source first conductive layer 120 and the drain first conductive layer 130 also absorb oxygen in the active layer 11, thereby changing the composition of the active layer 11 and affecting the electron mobility of the thin film transistor 1, resulting in a thin film transistor.
  • the electrical characteristics and stability of 1 are degraded.
  • the present disclosure proposes a thin film transistor, a method for fabricating a thin film transistor, and an array substrate, which can prevent the composition of the active layer from being damaged, thereby affecting the electrons of the thin film transistor.
  • the mobility is such that the thin film transistor has good electrical characteristics and stability.
  • a thin film transistor including an active layer, a source and a drain, the source including a source first conductive layer and a source first is provided for the purpose of the present disclosure.
  • a buffer layer the source first buffer layer is disposed on the source first conductive layer
  • the drain includes a drain first conductive layer and a drain first buffer layer
  • the drain first buffer layer Provided on the drain first conductive layer; at least a portion of the upper surface of the source first buffer layer and at least a portion of the upper surface of the drain first buffer layer are in contact with a lower surface of the active layer, At least a portion of sidewalls of the source first conductive layer and at least a portion of sidewalls of the drain first conductive layer are in contact with the active layer, the source first conductive layer and the active layer
  • the sidewall of the contact is formed with an oxide layer
  • a sidewall of the drain first conductive layer in contact with the active layer is formed with an oxide layer.
  • the active layer may be prepared using an oxide semiconductor.
  • the source first conductive layer and the drain first conductive layer may have a resistivity of less than 2.83 x 10 -8 ⁇ m.
  • the source first conductive layer may be made of at least one of copper, silver, and gold; and the drain first conductive layer may be made of at least one of copper, silver, and gold. to make.
  • the source may further include a source second buffer layer disposed under the source first conductive layer; the drain may further include being disposed under the drain first conductive layer The drain of the second buffer layer.
  • the oxide layer of the source is obtained by oxidizing the source first conductive layer
  • the oxide layer of the drain is obtained by oxidizing the drain first conductive layer
  • the oxide layer of the source and the oxide layer of the drain have a thickness of not less than 5 nm.
  • a method of fabricating a thin film transistor comprising:
  • the method of fabricating the thin film transistor may further include performing before step S10:
  • the method of fabricating the thin film transistor may further include performing after step S30:
  • step S40 a pattern of the gate is formed.
  • the sidewall of the source first conductive layer and the sidewall of the drain first conductive layer may be plasma-charged using a plasma of at least one of N 2 O and O 2 .
  • the body is processed such that an oxide layer is obtained on the sidewall of the source first conductive layer opposite the drain and on the sidewall of the drain first conductive layer opposite the source.
  • an array substrate comprising the above-described thin film transistor provided by the present disclosure.
  • the source first conductive layer is in contact with the active layer
  • the sidewall of the drain is formed with an oxide layer
  • the sidewall of the drain first conductive layer in contact with the active layer is formed with an oxide layer, thereby preventing diffusion of atoms/molecules of the source first conductive layer and the drain first conductive layer to In the active layer, and avoiding the source first conductive layer, the drain first conductive layer absorbing oxygen or other elements in the active layer.
  • the thin film transistor provided by the present disclosure can prevent the composition structure of the active layer from being damaged by the source first conductive layer and the drain first conductive layer, thereby ensuring the electron mobility of the thin film transistor and making the thin film transistor Maintain good electrical properties and stability.
  • an oxide layer is formed on a sidewall of the source first conductive layer opposite to the drain, and on a sidewall of the drain first conductive layer opposite to the source An oxide layer is formed.
  • the oxide layer can prevent atoms/molecules of the source first conductive layer and the drain first conductive layer from diffusing into the active layer, and avoiding the source first conductive layer and the drain first conductive layer absorbing the active layer Oxygen or other elements.
  • the thin film transistor manufacturing method provided by the present disclosure can prevent the molecular structure of the active layer from being destroyed by the source first conductive layer and the drain first conductive layer, thereby ensuring the electron mobility of the thin film transistor.
  • Thin film transistors maintain good electrical properties and stability.
  • the array substrate provided by the present disclosure adopts the above-mentioned thin film transistor provided by the present disclosure, so that the thin film transistor can maintain good electrical characteristics and stability, so that the display device using the array substrate has a good display effect.
  • FIG. 1 is a schematic structural view of a thin film transistor in a conventional large-size display device
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 is a flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 4 is a schematic view showing a pattern of forming a source and a drain
  • Figure 5 is a schematic view of a pattern forming an oxide layer
  • Figure 6 is a schematic view of a pattern forming an active layer
  • FIG. 7 is a flow chart showing an alternative embodiment of a method of fabricating the thin film transistor of FIG.
  • 1 thin film transistor; 10: gate; 11: active layer; 12: source; 13: drain; 120: source first conductive layer; 121: source second buffer layer; 122: source first Buffer layer; 123: oxide layer; 130: drain first conductive layer; 131: drain second buffer layer; 132: drain first buffer layer; 133: oxide layer.
  • the thin film transistor 1 includes a gate 10, an active layer 11, a source 12 and a drain 13, wherein the source 12 includes a source first conductive layer 120 and a source first buffer layer 122.
  • the source first buffer layer 122 is disposed on the source first conductive layer 120, and the drain 13 includes a drain first conductive layer 130 and a drain first buffer layer 132, the drain A buffer layer 132 is disposed on the drain first conductive layer 130; at least a portion of the upper surface of the source first buffer layer 122 and at least a portion of the upper surface of the drain first buffer layer 132 are The lower surface of the source layer 11 is in contact, at least a portion of the sidewalls of the source first conductive layer 120 and at least a portion of the sidewalls of the drain first conductive layer 130 are in contact with the active layer 11; and the source An sidewall of the first first conductive layer 120 in contact with the active layer 11 is formed with an oxide layer 123, and a sidewall of the drain first conductive layer 130 in contact with the active layer 11 is formed with an oxide layer 133. .
  • the source first buffer layer 122 and the drain first buffer layer 132 are electrically conductive.
  • an oxide layer 123 is formed on a sidewall of the source first conductive layer 120 that is in contact with the active layer 11 to prevent atoms/molecules in the source first conductive layer 120 from diffusing into the source layer.
  • the oxide layer 123 can also reduce or even prevent oxygen or other elements in the active layer 11 from being absorbed by the source first conductive layer 120, so that the composition of the active layer 11 can be prevented from being contacted.
  • the source 12 changes.
  • an oxide layer 133 is formed on the sidewall of the drain first conductive layer 130 in contact with the active layer 11, and it is also possible to prevent the composition of the active layer 11 from being changed by the drain 13 in contact therewith. Therefore, the composition of the active layer 11 can be kept constant without being destroyed by the source 12 and the drain 13, so that the electron mobility of the thin film transistor 1 can be ensured, and the thin film transistor 1 can maintain good electrical characteristics and stability.
  • the flatness of the surface of the source first conductive layer 120 and the drain first conductive layer 130 in contact with the active layer 11 can be improved; the improvement of the flatness also helps to avoid the source.
  • the atoms/molecules in the first first conductive layer 120 and the drain first conductive layer 130 are diffused into the active layer 11, and the source first conductive layer 120 and the drain first conductive layer 130 are prevented from being absorbed in the active layer 11 Oxygen or other elements, thereby further ensuring that the composition of the active layer 11 is not destroyed by the source 12 and the drain 13.
  • the active layer 11 may be prepared using an oxide semiconductor such as IGZO, ITZO, or the like, so that the thin film transistor 1 has a high electron mobility.
  • the resistivity of the source first conductive layer 120 and the drain first conductive layer 130 may be set to be lower than 2.83 ⁇ 10 -8 ⁇ m to make the source 12 of the thin film transistor 1
  • the resistance of the drain 13 is smaller than that of the source and drain electrodes prepared by Al in the prior art.
  • the source first conductive layer 120 may be made of at least one of copper (Cu), silver (Ag), and gold (Au)
  • the drain first conductive layer 130 may be made of copper (Cu). At least one of silver (Ag) and gold (Au) is formed; further, based on the reduction of the fabrication cost of the thin film transistor 1, the source first conductive layer 120 and the drain first conductive layer 130 may be prepared using Cu. .
  • the source 12 may further include a source second buffer layer 121 disposed under the source first conductive layer 120; the drain 13 may further include a first conductive layer 130 disposed on the drain
  • the drain second buffer layer 131 is below.
  • the source second buffer layer 121 and the drain second buffer layer 131 may be prepared using materials such as molybdenum (Mo), titanium (Ti), chromium (Cr), and molybdenum-niobium alloy (MoNb).
  • the base layer is generally a gate insulating layer, and the thin film transistor 1 is In the top gate structure, the base layer generally has a large adhesion between the substrate 2), and between the Cu, Ag, etc. materials for preparing the source first conductive layer 120 and the drain first conductive layer 130 and the base layer.
  • the adhesion is relatively small. Therefore, by providing the source second buffer layer 121 under the source first conductive layer 120 and the drain second buffer layer 131 under the drain first conductive layer 130, the source 12 and the base layer can be increased.
  • the adhesion between the drain 13 and the base layer is such that the source 12 and the drain 13 are more stable.
  • a drain first buffer layer 132 is disposed above the first conductive layer 130, so that the upper surface of the source first conductive layer 120 and the upper surface of the drain first conductive layer 130 are in contact with the active layer 11;
  • the atoms/molecules of the above materials in contact with the layer 11 are not easily diffused and are not easily oxidized, so that the compositional structure of the active layer 11 can be prevented from being changed, so that the thin film transistor 1 has good electrical characteristics and stability.
  • the above materials can also form a good electrical connection and ohmic contact with the active layer 11, so that the resistance between the source 12 and the drain 13 when the thin film transistor 1 is turned on can be reduced.
  • the thin film transistor 1 may be a bottom gate structure as shown in FIG. 2; wherein the "bottom gate” means that the gate 10 of the thin film transistor 1 is located below the active layer 11.
  • the patterns of the gate electrode 10 and the gate insulating layer are first sequentially prepared, and then the patterns of the source electrode 12 and the drain electrode 13 are prepared, and the source electrode 12 and the drain electrode are formed. After the pattern of the poles 13, a pattern of the active layer 11 is prepared such that the active layer 11 is between the source 12 and the drain 13.
  • the thin film transistor 1 may also be a top gate structure; wherein the "top gate” means that the gate of the thin film transistor 1 is located above the active layer 11.
  • the "top gate” means that the gate of the thin film transistor 1 is located above the active layer 11.
  • a pattern of the source 12 and the drain 13 is first prepared, and after the pattern of the source 12 and the drain 13 is formed, a pattern of the active layer 11 is prepared, In order to make the active layer 11 between the source 12 and the drain 13, the pattern of the gate insulating layer and the gate is sequentially formed.
  • an acidic etching solution may be required in preparing the pattern of the source 12 and the drain 13, and the oxide semiconductor is sensitive to the acidic etching solution and is easily corroded by the acidic etching solution. Therefore, if the pattern of the active layer 11 is to be formed first, and the pattern of the source 12 and the drain 13 is formed, it is necessary to form an etch barrier layer after the pattern of the active layer 11 is formed to prevent the active layer 11 from being formed. It is damaged in the etching process in which the source 12 and the drain 13 are subsequently formed.
  • the pattern of the active layer 11 is always prepared after the patterning of the source 12 and the drain 13 is formed, so that the etching stopper can be omitted. , which helps to increase productivity and increase resolution and aperture ratio.
  • the oxide layer 123 of the source 12 may be obtained by oxidizing the source first conductive layer 120
  • the oxide layer 133 of the drain 13 may be obtained by oxidizing the drain first conductive layer 130
  • the oxide layer 123 and the oxide layer 133 may be copper oxide (CuO) or cuprous oxide (Cu) after Cu is oxidized. 2 O); however, it is understood that if the oxide layer 123 and the oxide layer 133 are Cu 2 O, the oxygen in the active layer 11 can still be absorbed by Cu 2 O, thereby further oxidizing Cu 2 O to CuO, thus According to an example, the oxide layer 123 and the oxide layer 133 are CuO.
  • the oxide layer 123 of the source 12 and the oxide layer 133 of the drain 13 have a thickness of not less than 5 nm to ensure Cu atoms in the source first conductive layer 120 and the drain first conductive layer 130. It does not diffuse into the active layer 11, and it is ensured that oxygen or other elements in the active layer 11 are not absorbed by the source first conductive layer 120 and the drain first conductive layer 130.
  • the sidewall of the source first conductive layer 120 in contact with the active layer 11 is formed with an oxide layer 123, and the side of the drain first conductive layer 130 in contact with the active layer 11
  • the wall is formed with an oxide layer 133, which can prevent atoms/molecules of the source first conductive layer 120 and the drain first conductive layer 130 from diffusing into the active layer 11, and avoiding the source first conductive layer 120 and the drain first.
  • the conductive layer 130 absorbs oxygen or other elements in the active layer 11 so that the composition of the active layer 11 is not damaged by the source first conductive layer 120 and the drain first conductive layer 130, so that the thin film transistor can be ensured.
  • the electron mobility of 1 enables the thin film transistor 1 to maintain good electrical characteristics and stability.
  • FIG. 3 is a flow chart of a method of fabricating a thin film transistor provided in accordance with an embodiment of the present disclosure. As shown in FIG. 3, the method for fabricating the thin film transistor includes the following steps S10 to S30:
  • a pattern including the source first conductive layer 120 and the source first buffer layer 122 is formed, and the drain 13 including the drain first conductive layer 130 and the drain first buffer layer 132 is formed.
  • the figure is shown in Figure 4.
  • step S10 the photoresist in the corresponding region is denatured ⁇ developed by deposition (Cu, Ag, etc.) ⁇ coating photoresist ⁇ exposure, and the denatured or undenatured photoresist is removed ⁇ etched. ⁇ removing the remaining photoresist, obtaining a pattern of the source first conductive layer 120 and the drain first conductive layer 130; after obtaining the pattern of the source first conductive layer 120 and the drain first conductive layer 130, The same process steps described above obtain a pattern of the source first buffer layer 122 and the drain first buffer layer 122, and finally obtain a pattern of the source 12 and the drain 13.
  • the source 12 further includes a source second buffer layer 121
  • the drain 13 further includes a drain second buffer layer 131
  • the source first conductive layer 120 and the drain are formed.
  • the pattern of the source second buffer layer 121 and the drain second buffer layer 131 is first formed, that is, sequentially deposited by deposition (Mo, Ti, Cr, MoNb, etc.) ⁇ coating Photoresist ⁇ exposure, denaturation of the photoresist in the corresponding area ⁇ development, denaturation The undenatured photoresist is removed ⁇ etched ⁇ the remaining photoresist is removed, and a pattern of the source second buffer layer 121 and the drain second buffer layer 131 is obtained.
  • deposition Mo, Ti, Cr, MoNb, etc.
  • an oxide layer 123 is formed on a sidewall of the source first conductive layer 120 opposite to the drain electrode 13, and is formed on a sidewall of the drain first conductive layer 130 opposite to the source electrode 12.
  • the oxide layer 133 is as shown in FIG.
  • the sidewalls of the source first conductive layer 120 and the drain first conductive layer 130 may be plasma-treated using plasma of at least one of N 2 O and O 2 .
  • the sidewall surface of the source first conductive layer 120 and the sidewall surface of the drain first conductive layer 130 are oxidized on the sidewall of the source first conductive layer 120 opposite to the drain 13 and at the drain first Oxide layers 123, 133 are obtained on the sidewalls of the conductive layer 130 opposite the source 12.
  • a pattern of the active layer is formed as shown in FIG.
  • the photoresist in the corresponding region may be denatured ⁇ developed by deposition (IGZO, ITZO, etc.) ⁇ coating photoresist ⁇ exposure, and the denatured or undenatured photoresist is removed ⁇ etched ⁇ removed.
  • the remaining photoresist is obtained by patterning the active layer 11 prepared from an oxide semiconductor such as IGZO or ITZO.
  • the thin film transistor includes a gate electrode 10, a gate insulating layer, an active layer 11, a source electrode 12, and a drain electrode 13. Therefore, the method of fabricating the thin film transistor should also include the step of preparing the gate electrode 10. Specifically, as shown in FIG. 3, the method for fabricating the thin film transistor further includes the step S1 performed before the step S10: forming a pattern of the gate electrode 10; in this case, the pattern of the gate electrode 10 is located on the active layer 11. Below the graph, the thin film transistor is a bottom gate structure.
  • the thin film transistor may also have a top gate structure. Accordingly, in addition to the implementation including the step S1, in an alternative embodiment, as shown in FIG. 7, the method of fabricating the thin film transistor may further include the step S40 performed after the step S30: forming a pattern of the gate. In this case, the pattern of the gate electrode 10 is located above the pattern of the active layer 11, and therefore, the thin film transistor is a top gate structure.
  • an oxide layer 123 is formed on a sidewall of the source first conductive layer 120 opposite to the drain electrode 13 and a sidewall of the drain first conductive layer 130 opposite to the source electrode 12
  • the oxide layer 133 is formed, so that the oxide layers 123, 133 can prevent the atoms/molecules of the source first conductive layer 120 and the drain first conductive layer 130 from diffusing to In the active layer 11, and avoiding the source first conductive layer 120 and the drain first conductive layer 130 absorbing oxygen or other elements in the active layer 11, so that the molecular structure of the active layer 11 can be prevented from being sourced.
  • the first conductive layer 120 and the drain first conductive layer 130 are broken, so that the electron mobility of the thin film transistor 1 can be ensured, and the thin film transistor 1 can maintain good electrical characteristics and stability.
  • Embodiments of the present disclosure also provide an array substrate including the thin film transistor provided by the above-described embodiments of the present disclosure.
  • the thin film transistor provided by the above embodiment of the present disclosure is used, so that the thin film transistor can maintain good electrical characteristics and stability, so that the display device using the array substrate can obtain good performance. display effect.

Abstract

一种薄膜晶体管、薄膜晶体管的制备方法及阵列基板。所述薄膜晶体管包括有源层（11）、源极（12）和漏极（13），源极（12）包括源极第一导电层（120）和源极第一缓冲层（122），漏极（13）包括漏极第一导电层（130）和漏极第一缓冲层（132）；源极第一缓冲层（122）的至少部分上表面及漏极第一缓冲层（132）的至少部分上表面与有源层（11）的下表面接触，源极第一导电层（120）的至少部分侧壁及所述漏极第一导电层（130）的至少部分侧壁与所述有源层（11）接触，源极第一导电层（120）、漏极第一导电层（130）的与有源层（11）接触的侧壁形成有氧化层（123，133）。上述薄膜晶体管的有源层（11）的成分结构不会被源极第一导电层（120）、漏极第一导电层（130）破坏，这样就可以保证薄膜晶体管具有较高的电子迁移率，使薄膜晶体管维持良好的电学特性和稳定性。

Description

薄膜晶体管、薄膜晶体管的制备方法及阵列基板 技术领域
本公开涉及显示技术领域，具体地，涉及一种薄膜晶体管、薄膜晶体管的制备方法及阵列基板。
背景技术
采用氧化物半导体，如铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)作为有源层的薄膜晶体管具有较高的电子迁移率；而采用铜(Cu)、银(Ag)等低电阻率金属材料作为栅极、源极和漏极的薄膜晶体管，其电阻可以明显降低；因此，在大尺寸显示装置中的薄膜晶体管一般采用氧化物半导体作为有源层，采用Cu、Ag等低电阻率金属材料作为栅极、源极和漏极。基于上述二者的优点，所制得的薄膜晶体管能够实现更高的分辨率、更高的刷新率，从而获得更好的显示效果。
图1为现有大尺寸显示装置中薄膜晶体管的示意图。如图1所示，薄膜晶体管1制备在基底2上，并且包括栅极10、有源层11、源极12和漏极13。其中，有源层11采用IGZO、ITZO等氧化物半导体材料，以使薄膜晶体管1具有较高的电子迁移率；并且，有源层11位于所述源极12与漏极13上方(即源极12、漏极13先于有源层11制备)。源极12包括源极第一导电层120及设置在源极第一导电层120下方的源极第二缓冲层121、设置在源极第一导电层120上方的源极第一缓冲层122。漏极13包括漏极第一导电层130及设置在漏极第一导电层130下方的漏极第二缓冲层131、设置在漏极第一导电层130上方的漏极第一缓冲层132。
具体地，源极第一导电层120具体可以由Cu制备，以降低源极的电阻。而由于Cu与源极12所在的基层(位于源极12下方，在薄膜晶体管1为底栅结构时，所述基层一般为栅绝缘层，在薄膜晶体管1为顶栅结构时，所述基层一般为基底2)之间的附着力较小，因此，在源极第一导电层120的下方设置源极第二缓冲层121。源极第二缓冲层121具体可以由钼(Mo)、钛(Ti)、铬(Cr)及钼铌合金(MoNb)等制备，以使源极12与基层之间存在较大的附着力(Mo、Ti、Cr和 MoNb等金属或合金与基层之间的附着力较大，同时，Cu与上述金属或合金之间也有较大的附着力)。源极第一缓冲层122同样可以由Mo、Ti、Cr及MoNb等制备，其用于避免源极第一导电层120的上表面与有源层11接触，从而防止Cu原子扩散到有源层11中，以及防止有源层11中的氧被源极第一导电层120吸收。同时，源极第一缓冲层122还可以与有源层11形成良好的欧姆接触。
所述漏极13中漏极第一导电层130、漏极第二缓冲层131、漏极第一缓冲层132的情况与上述源极12中的类似，在此不再赘述。
在上述薄膜晶体管1中，源极第一导电层120、漏极第一导电层130的侧壁与有源层11接触，这就使源极第一导电层120、漏极第一导电层130中的易于扩散的Cu原子会向有源层11中扩散。同时，源极第一导电层120、漏极第一导电层130也会吸收有源层11中的氧，从而使有源层11的成分改变，影响薄膜晶体管1的电子迁移率，导致薄膜晶体管1的电学特性和稳定性的下降。
发明内容
本公开为了至少解决现有技术中存在的技术问题之一，提出了一种薄膜晶体管、薄膜晶体管的制备方法及阵列基板，其可以避免有源层的成分结构被破坏，进而影响薄膜晶体管的电子迁移率，从而使薄膜晶体管具有良好的电学特性和稳定性。
根据本公开的第一方面，为实现本公开的目的而提供一种薄膜晶体管，其可以包括有源层、源极和漏极，所述源极包括源极第一导电层和源极第一缓冲层，所述源极第一缓冲层设置在所述源极第一导电层上，所述漏极包括漏极第一导电层和漏极第一缓冲层，所述漏极第一缓冲层设置在所述漏极第一导电层上；所述源极第一缓冲层的至少部分上表面及所述漏极第一缓冲层的至少部分上表面与所述有源层的下表面接触，所述源极第一导电层的至少部分侧壁及所述漏极第一导电层的至少部分侧壁与所述有源层接触，所述源极第一导电层的与所述有源层接触的侧壁形成有氧化层，所述漏极第一导电层的与所述有源层接触的侧壁形成有氧化层。
根据一个实施例，所述有源层可以采用氧化物半导体制备。
根据另一实施例，所述源极第一导电层和漏极第一导电层的电阻 率可以低于2.83×10-8Ω·m。
根据又一实施例，所述源极第一导电层可以由铜、银、金中的至少一种制成；所述漏极第一导电层可以由铜、银、金中的至少一种制成。
根据再一实施例，所述源极还可以包括设置在所述源极第一导电层下方的源极第二缓冲层；所述漏极还可以包括设置在所述漏极第一导电层下方的漏极第二缓冲层。
根据一个实施例，所述源极的氧化层通过对所述源极第一导电层氧化获得，所述漏极的氧化层通过对所述漏极第一导电层氧化获得。
根据另一实施例，所述源极的氧化层和漏极的氧化层的厚度均不小于5纳米。
根据本公开的第二方面，提供一种薄膜晶体管的制备方法，其包括：
S10，形成包括源极第一导电层、源极第一缓冲层的源极的图形，形成包括漏极第一导电层、漏极第一缓冲层的漏极的图形；
S20，在源极第一导电层的与漏极相对的侧壁上，形成氧化层，以及，在漏极第一导电层的与源极相对的侧壁上，形成氧化层；
S30，形成有源层的图形。
根据一个实施例，所述薄膜晶体管的制备方法还可以包括在步骤S10之前进行的：
S1，形成栅极的图形。
可替代地，所述薄膜晶体管的制备方法还可以包括在步骤S30之后进行的：
步骤S40，形成栅极的图形。
根据另一实施例，在步骤S20中，可以使用N2O、O2中的至少一种的等离子体，对源极第一导电层的侧壁和漏极第一导电层的侧壁进行等离子体处理，从而在源极第一导电层的与漏极相对的侧壁上，以及在漏极第一导电层的与源极相对的侧壁上获得氧化层。
根据本公开的第三方面，还提供一种阵列基板，其包括本公开提供的上述薄膜晶体管。
本公开具有以下有益效果：
在本公开提供的薄膜晶体管中，源极第一导电层的与有源层接触 的侧壁形成有氧化层，漏极第一导电层的与有源层接触的侧壁形成有氧化层，因而可以避免源极第一导电层、漏极第一导电层的原子/分子扩散到有源层中，以及避免源极第一导电层、漏极第一导电层吸收有源层中的氧或其他元素。作为结果，本公开所提供的薄膜晶体管可以使有源层的成分结构不会被源极第一导电层、漏极第一导电层破坏，这样就可以保证薄膜晶体管的电子迁移率，使薄膜晶体管维持良好的电学特性和稳定性。
在本公开提供的薄膜晶体管的制备方法中，在源极第一导电层的与漏极相对的侧壁上形成氧化层，以及，在漏极第一导电层的与源极相对的侧壁上形成氧化层。所述氧化层可以避免源极第一导电层、漏极第一导电层的原子/分子扩散到有源层中，以及避免源极第一导电层、漏极第一导电层吸收有源层中的氧或其他元素。作为结果，本公开所提供的薄膜晶体管制备方法可以使有源层的分子结构不会被源极第一导电层、漏极第一导电层破坏，这样就可以保证薄膜晶体管的电子迁移率，使薄膜晶体管维持良好的电学特性和稳定性。
本公开提供的阵列基板采用本公开提供的上述薄膜晶体管，因而可以使薄膜晶体管维持良好的电学特性和稳定性，从而使采用所述阵列基板的显示装置具有良好的显示效果。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为现有大尺寸显示装置中薄膜晶体管的结构示意图；
图2为根据本公开的实施例提供的薄膜晶体管的结构示意图；
图3为根据本公开的一个实施例的薄膜晶体管的制备方法的流程图；
图4为形成源极和漏极的图形的示意图；
图5为形成氧化层的图形的示意图；
图6为形成有源层的图形的示意图；
图7为图3所示薄膜晶体管的制备方法的一种替代实施例的流程图。
其中，附图标记：
1：薄膜晶体管；10：栅极；11：有源层；12：源极；13：漏极；120：源极第一导电层；121：源极第二缓冲层；122：源极第一缓冲层；123：氧化层；130：漏极第一导电层；131：漏极第二缓冲层；132：漏极第一缓冲层；133：氧化层。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
图2为根据本公开的实施例的薄膜晶体管的结构示意图。如图2所示，薄膜晶体管1包括栅极10、有源层11、源极12和漏极13，其中，所述源极12包括源极第一导电层120和源极第一缓冲层122，所述源极第一缓冲层122设置在所述源极第一导电层120上，所述漏极13包括漏极第一导电层130和漏极第一缓冲层132，所述漏极第一缓冲层132设置在所述漏极第一导电层130上；所述源极第一缓冲层122的至少部分上表面及所述漏极第一缓冲层132的至少部分上表面与所述有源层11的下表面接触，所述源极第一导电层120的至少部分侧壁及所述漏极第一导电层130的至少部分侧壁与所述有源层11接触；且所述源极第一导电层120的与所述有源层11接触的侧壁形成有氧化层123，所述漏极第一导电层130的与所述有源层11接触的侧壁形成有氧化层133。具体地，所述源极第一缓冲层122、漏极第一缓冲层132导电。
在本实施例中，在所述源极第一导电层120的与有源层11接触的侧壁上形成有氧化层123，可以避免源极第一导电层120中的原子/分子扩散到有源层11中，同时，所述氧化层123还可以减少、甚至避免有源层11中的氧或其他元素被源极第一导电层120吸收，从而可以避免有源层11的成分被与其接触的源极12改变。类似地，在漏极第一导电层130的与有源层11接触的侧壁上形成有氧化层133，也可以避免有源层11的成分被与其接触的漏极13改变。因此，有源层11的成分结构可以保持不变，而不被源极12、漏极13破坏，这样就可以保证薄膜晶体管1的电子迁移率，使薄膜晶体管1维持良好的电学特性和 稳定性。
此外，设置氧化层123、133，还可以提高源极第一导电层120、漏极第一导电层130的与有源层11接触的表面的平整度；该平整度的提高也有助于避免源极第一导电层120、漏极第一导电层130中的原子/分子扩散到有源层11中，以及避免源极第一导电层120、漏极第一导电层130吸收有源层11中的氧或其他元素，从而，进一步保证有源层11的成分结构不会被源极12、漏极13破坏。
具体地，所述有源层11可以采用氧化物半导体(如IGZO、ITZO等)制备，以使薄膜晶体管1具有较高的电子迁移率。
在现有薄膜晶体管中，广泛作为栅极、源极和漏极的材料是铝(Al)，其电阻率为2.83×10-8Ω·m。在本公开中，可以将所述源极第一导电层120和漏极第一导电层130的电阻率设置成低于2.83×10-8Ω·m，以使薄膜晶体管1的源极12、漏极13的电阻相比现有技术中采用Al制备的源极、漏极的电阻更小。具体地，所述源极第一导电层120可以采用铜(Cu)、银(Ag)和金(Au)中的至少一种制成，漏极第一导电层130可以采用铜(Cu)、银(Ag)和金(Au)中的至少一种制成；进一步地，基于降低薄膜晶体管1的制备成本的考虑，可以采用Cu制备源极第一导电层120和漏极第一导电层130。
此外，所述源极12还可以包括设置在所述源极第一导电层120下方的源极第二缓冲层121；所述漏极13还可以包括设置在所述漏极第一导电层130下方的漏极第二缓冲层131。具体地，所述源极第二缓冲层121和漏极第二缓冲层131可以采用钼(Mo)、钛(Ti)、铬(Cr)及钼铌合金(MoNb)等材料制备。上述材料与用于设置源极12、漏极13的基层(位于源极12、漏极13下方，在薄膜晶体管1为底栅结构时，所述基层一般为栅绝缘层，在薄膜晶体管1为顶栅结构时，所述基层一般为基底2)之间的附着力较大，而用于制备源极第一导电层120、漏极第一导电层130的Cu、Ag等材料与基层之间的附着力相对较小。因此，通过在源极第一导电层120的下方设置源极第二缓冲层121，在漏极第一导电层130的下方设置漏极第二缓冲层131，可以增大源极12与基层之间的附着力，以及漏极13与基层之间的附着力，从而使源极12与漏极13的稳固性较好。
通过在源极第一导电层120上方设置源极第一缓冲层122，在漏极 第一导电层130上方设置漏极第一缓冲层132，可以避免源极第一导电层120的上表面、漏极第一导电层130的上表面与有源层11接触；同时，与有源层11接触的上述材料的原子/分子不易扩散，且不易被氧化，这样可以避免有源层11的成分结构被改变，从而使薄膜晶体管1具有良好的电学特性和稳定性。此外，上述材料还可以与有源层11之间形成良好的电性连接和欧姆接触，从而可以减小薄膜晶体管1开启时源极12和漏极13之间的电阻。
在本实施例中，所述薄膜晶体管1可以为底栅结构，如图2所示；其中，所谓“底栅”是指薄膜晶体管1的栅极10位于有源层11的下方。具体地，在制备具有上述底栅结构的薄膜晶体管1时，首先依次制备栅极10、栅极绝缘层的图形，而后制备源极12和漏极13的图形，并且在形成源极12和漏极13的图形之后，制备有源层11的图形，以使所述源极12和漏极13之间为有源层11。
除底栅结构外，在本实施例中，所述薄膜晶体管1还可以为顶栅结构；其中，所谓“顶栅”是指薄膜晶体管1的栅极位于有源层11的上方。具体地，在制备具有上述顶栅结构的薄膜晶体管1时，首先制备源极12和漏极13的图形，并且在形成源极12和漏极13的图形之后，制备有源层11的图形，以使所述源极12和漏极13之间为有源层11，最后依次形成栅极绝缘层和栅极的图形。
在实际中，在制备源极12、漏极13的图形时可能需要使用酸性刻蚀液，而氧化物半导体对酸性刻蚀液较为敏感，容易被酸性刻蚀液腐蚀。因此，如果要先形成有源层11的图形，后形成源极12、漏极13的图形，就需要在形成有源层11的图形之后，制备一层刻蚀阻挡层，防止有源层11被后续形成源极12、漏极13的刻蚀工艺中损坏。在本实施例中，无论薄膜晶体管1为底栅结构，还是顶栅结构，有源层11的图形总是在源极12和漏极13的图形形成之后制备，这样可以省去刻蚀阻挡层，从而有助于提高产能，提高分辨率和开口率。
另外，所述源极12的氧化层123可以通过对所述源极第一导电层120氧化获得，所述漏极13的氧化层133可以通过对所述漏极第一导电层130氧化获得；在以Cu制备源极第一导电层120和漏极第一导电层130的情况下，所述氧化层123和氧化层133可以为Cu被氧化后的氧化铜(CuO)或氧化亚铜(Cu2O)；然而可以理解，若所述氧化层 123和氧化层133为Cu2O，则有源层11中的氧仍然可以被Cu2O吸收，从而使Cu2O进一步氧化为CuO，因此，根据一个示例，所述氧化层123和氧化层133为CuO。
根据一个示例，所述源极12的氧化层123和漏极13的氧化层133的厚度均不小于5纳米，以保证源极第一导电层120和漏极第一导电层130中的Cu原子不会扩散到有源层11中，以及保证有源层11中的氧或其他元素不会被源极第一导电层120和漏极第一导电层130吸收。
在本实施例提供的薄膜晶体管1中，源极第一导电层120的与有源层11接触的侧壁形成有氧化层123，漏极第一导电层130的与有源层11接触的侧壁形成有氧化层133，可以避免源极第一导电层120、漏极第一导电层130的原子/分子扩散到有源层11中，以及避免源极第一导电层120、漏极第一导电层130吸收有源层11中的氧或其他元素，从而使有源层11的成分结构不会被源极第一导电层120、漏极第一导电层130破坏，这样就可以保证薄膜晶体管1的电子迁移率，使薄膜晶体管1维持良好的电学特性和稳定性。
图3为根据本公开的实施例提供的薄膜晶体管的制备方法的流程图。如图3所示，所述薄膜晶体管的制备方法包括以下步骤S10～S30：
在S10处，形成包括源极第一导电层120、源极第一缓冲层122的源极12的图形，形成包括漏极第一导电层130、漏极第一缓冲层132的漏极13的图形，如图4所示。
具体地，在步骤S10中，依次通过沉积(Cu、Ag等)→涂覆光刻胶→曝光，使相应区域的光刻胶变性→显影，将变性或未变性的光刻胶去除→刻蚀→去除剩余的光刻胶，获得源极第一导电层120和漏极第一导电层130的图形；在获得源极第一导电层120和漏极第一导电层130的图形之后，通过与上述相同的工艺步骤获得源极第一缓冲层122和漏极第一缓冲层122的图形，并且最终获得源极12和漏极13的图形。
在所述源极12还包括源极第二缓冲层121，所述漏极13还包括漏极第二缓冲层131的情况下，在步骤S10中，在形成源极第一导电层120和漏极第一导电层130的图形前，还需先形成源极第二缓冲层121和漏极第二缓冲层131的图形，即：依次通过沉积(Mo、Ti、Cr、MoNb等)→涂覆光刻胶→曝光，使相应区域的光刻胶变性→显影，将变性 或未变性的光刻胶去除→刻蚀→去除剩余的光刻胶，获得源极第二缓冲层121和漏极第二缓冲层131的图形。所述源极第二缓冲层121和漏极第二缓冲层131的作用在上述薄膜晶体管的实施方式中已有详细描述，在此不再赘述。
在S20处，在源极第一导电层120的与漏极13相对的侧壁上，形成氧化层123，以及，在漏极第一导电层130的与源极12相对的侧壁上，形成氧化层133，如图5所示。
具体地，在步骤S20中，可以使用N2O、O2中的至少一种的等离子体，对源极第一导电层120、漏极第一导电层130的侧壁进行等离子体处理，将源极第一导电层120的侧壁表面和漏极第一导电层130的侧壁表面氧化，在源极第一导电层120的与漏极13相对的侧壁上，以及在漏极第一导电层130的与源极12相对的侧壁上获得氧化层123、133。
在S30处，形成有源层的图形，如图6所示。
在步骤S30中，可以依次通过沉积(IGZO、ITZO等)→涂覆光刻胶→曝光，使相应区域的光刻胶变性→显影，将变性或未变性的光刻胶去除→刻蚀→去除剩余的光刻胶，获得由IGZO、ITZO等氧化物半导体制备出的有源层11的图形。
薄膜晶体管包括栅极10、栅极绝缘层、有源层11、源极12和漏极13，因此，薄膜晶体管的制备方法也应包括制备栅极10的步骤。具体地，如图3所示，所述薄膜晶体管的制备方法还包括在步骤S10之前进行的步骤S1：形成栅极10的图形；在此情况下，栅极10的图形位于有源层11的图形的下方，因此薄膜晶体管为底栅结构。
薄膜晶体管还可以具有顶栅结构。相应地，除包括步骤S1的实施例外，在可替代的实施例中，如图7所示，所述薄膜晶体管的制备方法还可以包括在步骤S30之后进行的步骤S40：形成栅极的图形。在此情况下，栅极10的图形位于有源层11的图形的上方，因此，薄膜晶体管为顶栅结构。
在上述薄膜晶体管的制备方法中，由于源极第一导电层120的与漏极13相对的侧壁形成有氧化层123，以及，漏极第一导电层130的与源极12相对的侧壁形成有氧化层133，因此所述氧化层123、133可以避免源极第一导电层120、漏极第一导电层130的原子/分子扩散到 有源层11中，以及避免源极第一导电层120、漏极第一导电层130吸收有源层11中的氧或其他元素，从而可以使有源层11的分子结构不会被源极第一导电层120、漏极第一导电层130破坏，这样就可以保证薄膜晶体管1的电子迁移率，使薄膜晶体管1维持良好的电学特性和稳定性。
本公开的实施例还提供一种阵列基板，所述阵列基板包括本公开上述实施方式提供的薄膜晶体管。
在本公开的实施例提供的阵列基板中，采用本公开上述实施例提供的薄膜晶体管，因此可以使薄膜晶体管维持良好的电学特性和稳定性，从而使采用所述阵列基板的显示装置获得良好的显示效果。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (12)

  1. 一种薄膜晶体管，包括有源层、源极和漏极，所述源极包括源极第一导电层和源极第一缓冲层，所述源极第一缓冲层设置在所述源极第一导电层上，所述漏极包括漏极第一导电层和漏极第一缓冲层，所述漏极第一缓冲层设置在所述漏极第一导电层上；所述源极第一缓冲层的至少部分上表面及所述漏极第一缓冲层的至少部分上表面与所述有源层的下表面接触，所述源极第一导电层的至少部分侧壁及所述漏极第一导电层的至少部分侧壁与所述有源层接触，其中，所述源极第一导电层的与所述有源层接触的侧壁形成有氧化层，所述漏极第一导电层的与所述有源层接触的侧壁形成有氧化层。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述有源层采用氧化物半导体制备。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述源极第一导电层和漏极第一导电层的电阻率低于2.83×10-8Ω·m。
  4. 根据权利要求1～3任意一项所述的薄膜晶体管，其中，
    所述源极第一导电层由铜、银、金中的至少一种制成；
    所述漏极第一导电层由铜、银、金中的至少一种制成。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述源极还包括设置在所述源极第一导电层下方的源极第二缓冲层；
    所述漏极还包括设置在所述漏极第一导电层下方的漏极第二缓冲层。
  6. 根据权利要求4所述的薄膜晶体管，其中，所述源极的氧化层通过对所述源极第一导电层氧化获得，所述漏极的氧化层通过对所述漏极第一导电层氧化获得。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述源极的氧化层和漏极的氧化层的厚度均不小于5纳米。
  8. 一种薄膜晶体管的制备方法，包括：
    S10，形成包括源极第一导电层、源极第一缓冲层的源极的图形，形成包括漏极第一导电层、漏极第一缓冲层的漏极的图形；
    S20，在源极第一导电层的与漏极相对的侧壁上，形成氧化层，以及，在漏极第一导电层的与源极相对的侧壁上，形成氧化层；以及
    S30，形成有源层的图形。
  9. 根据权利要求8所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括在步骤S10之前进行的：
    S1，形成栅极的图形。
  10. 根据权利要求8所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括在步骤S30之后进行的：
    步骤S40，形成栅极的图形。
  11. 根据权利要求8所述的薄膜晶体管的制备方法，其中，在步骤S20中，使用N2O、O2中的至少一种的等离子体，对源极第一导电层的侧壁和漏极第一导电层的侧壁进行等离子体处理，在源极第一导电层的与漏极相对的侧壁上，以及在漏极第一导电层的与源极相对的侧壁上获得氧化层。
  12. 一种阵列基板，包括权利要求1～7任意一项所述的薄膜晶体管。
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