WO2019104834A1 - 一种tft阵列基板及其制作方法、显示装置 - Google Patents

一种tft阵列基板及其制作方法、显示装置 Download PDF

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WO2019104834A1
WO2019104834A1 PCT/CN2018/071557 CN2018071557W WO2019104834A1 WO 2019104834 A1 WO2019104834 A1 WO 2019104834A1 CN 2018071557 W CN2018071557 W CN 2018071557W WO 2019104834 A1 WO2019104834 A1 WO 2019104834A1
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layer
active layer
insulating layer
active
array substrate
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PCT/CN2018/071557
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French (fr)
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余威
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武汉华星光电半导体显示技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • the present invention relates to the field of display panel manufacturing, and in particular, to a TFT array substrate, a manufacturing method thereof, and a display device.
  • the GE metal layer electrode is fabricated, the GE metal layer is self-aligned plasma-treated as a mask, and then the IGZO surface region of the SD contact is electrically conductive, thereby reducing IGZO and The contact impedance of the SD forms an effect similar to an ohmic contact.
  • the problem with the above manufacturing method is that the oxygen vacancy in the conductive IGZO will increase. During the subsequent processing, oxygen vacancies will spread along the surface to the channel, so that the oxygen vacancy on the upper surface of the IGZO channel region will increase, and the TFT will be turned off. The leakage under the condition increases, and the TFT cannot be effectively turned off, thereby affecting the characteristics of the TFT.
  • the technical problem to be solved by the present invention is to provide a TFT array substrate, a manufacturing method thereof, and a display device, which can prevent oxygen vacancies on the surface of the active layer after plasma treatment from diffusing into the channel region, and reduce oxygen vacancies in the conductive active layer.
  • the effect of diffusion on the leakage current of the TFT improves the yield of the display panel.
  • an embodiment of the present invention provides a TFT array substrate, including: a substrate; a buffer layer and an active layer sequentially disposed on the substrate; and an insulating layer disposed on the active layer, the width of the insulating layer is less than active The width of the layer, and the insulating layer is correspondingly disposed in the middle region of the active layer, and the outer peripheral region of the active layer adjacent to the insulating layer is provided with a groove.
  • one side of the opening edge of the groove is adjacent to the position of the active layer corresponding to the insulating layer.
  • the groove is set to two, and the two grooves are respectively disposed on opposite sides of the active layer on the outer peripheral region of the insulating layer.
  • the depth of the groove in the active layer is smaller than the thickness of the active layer.
  • the insulating layer is covered with a metal layer, and the metal layer is filled in the groove of the active layer.
  • the active layer and the insulating layer are provided with a dielectric layer covering the active layer and the insulating layer, and the dielectric layer is provided with a source and drain metal layer.
  • the present invention also discloses a method for fabricating a TFT array substrate, comprising the steps of: sequentially forming a buffer layer and an active layer on a substrate; depositing an insulating layer on the active layer; coating the insulating layer The photoresist is exposed, and the photoresist is exposed and developed; after etching and photoresist removal, a groove is formed on the active layer near the outer peripheral region of the insulating layer, the width of the insulating layer is smaller than the width of the active layer, and the insulating layer corresponds to Set in the middle of the active layer.
  • one side opening edge of the groove is adjacent to the position of the active layer corresponding to the insulating layer; the groove is set to two, and the two grooves are respectively disposed on the active layer near the outer peripheral area of the insulating layer The opposite sides of the groove; the depth of the groove in the active layer is smaller than the thickness of the active layer.
  • the method further includes: forming a metal layer on the insulating layer, wherein the metal layer is filled in the groove of the active layer; forming a dielectric layer covering the active layer and the insulating layer on the insulating layer and the insulating layer, and the dielectric layer The step of fabricating the source and drain metal layers.
  • the present invention also discloses a display device comprising a TFT array substrate, the TFT array substrate comprising: a substrate; a buffer layer and an active layer sequentially disposed on the substrate; and an insulation disposed on the active layer
  • the width of the insulating layer is smaller than the width of the active layer, and the insulating layer is correspondingly disposed in the middle region of the active layer; the outer peripheral region of the active layer adjacent to the insulating layer is provided with a groove, and the groove is set to two, the two grooves The opposite sides of the outer peripheral region of the active layer adjacent to the insulating layer are respectively disposed.
  • the depth of the groove in the active layer is smaller than the thickness of the active layer.
  • the insulating layer is covered with a metal layer, and the metal layer is filled in the groove of the active layer.
  • the active layer and the insulating layer are provided with a dielectric layer covering the active layer and the insulating layer, and the dielectric layer is provided with a source and drain metal layer.
  • the TFT array substrate provided by the present invention, the manufacturing method thereof, and the display device have the following
  • a buffer layer and an active layer are sequentially disposed on the substrate; an insulating layer is disposed on the active layer, the width of the insulating layer is smaller than the width of the active layer, and the insulating layer is correspondingly disposed in an intermediate portion of the active layer, and the outer layer of the active layer is adjacent to the insulating layer
  • the area is provided with a groove, and a metal layer is arranged in the groove. The oxygen vacancy on the surface of the treated active layer is blocked by the metal layer, so that the oxygen vacancy cannot enter the groove of the active layer.
  • the yield of the display device is improved.
  • FIG. 1 is a schematic view showing the structure of exposing and developing a photoresist by a method for fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic view showing a groove obtained by etching a TFT array substrate and removing a photoresist after the method of fabricating the TFT array substrate.
  • FIG 3 is a schematic view showing the structure of depositing a metal layer on a groove by a method for fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a TFT array substrate according to an embodiment of the present invention.
  • FIG. 4 it is the first embodiment of the TFT array substrate of the present invention.
  • the TFT array substrate in this embodiment includes: a substrate 101; a buffer layer 102 and an active layer 103 sequentially disposed on the substrate 101; and an insulating layer 104 disposed on the active layer 103, wherein: the insulating layer on the active layer 103 A groove T is provided on the outer circumference of the corresponding region 104.
  • the groove T is formed by sequentially forming a buffer layer 102 and an active layer 103 on the substrate 101. After the buffer layer 102 and the active layer 103 are respectively patterned, an insulating layer 104 is deposited on the active layer 103 and coated. The photoresist is exposed, and the photoresist is exposed and developed using a semi-transparent mask 105. Wherein, the groove T is formed at a position on the active layer 103 adjacent to the outer peripheral region of the insulating layer 104. In this configuration, the width of the insulating layer 104 is smaller than the width of the active layer 103, and the insulating layer 104 is correspondingly disposed in the middle region of the active layer 103. .
  • the function of the groove T is to prevent the oxygen vacancies on the surface of the active layer 103 from being blocked by the groove T during the subsequent plasma processing and the anneal process, so that oxygen vacancies cannot enter the channel region of the active layer 103.
  • one side opening edge T1 of the groove T is adjacent to the position of the region on the active layer 103 corresponding to the insulating layer 104. In this way, the production process such as subsequent deposition is simplified.
  • the groove T is set to two, and the two grooves T are respectively disposed on the active layer 103 on opposite sides of the outer peripheral region of the insulating layer 104, and the depth of the groove T in the active layer 103 is smaller than the active The thickness of layer 103. In this way, the production process such as subsequent deposition is simplified.
  • the insulating layer 104 is covered with the metal layer 106 while the metal layer 106 is filled in the recess T of the active layer 103 to form the metal layer 106a as shown.
  • the oxygen vacancies on the surface of the active layer 103 are blocked by the metal layer 106a, so that oxygen vacancies cannot enter the channel region of the active layer 103.
  • the oxygen vacancy diffusion on the surface of the conductive active layer 103 is blocked by the metal layer 106a embedded on both sides of the channel region of the active layer 103, so that oxygen vacancies cannot enter the channel region, thus preventing plasma treatment.
  • the oxygen vacancies on the surface of the active layer 103 diffuse into the channel region, reducing the influence of oxygen vacancy diffusion on the TFT leakage current in the conductive active layer.
  • the active layer 103 and the insulating layer 104 are formed with a dielectric layer 201 covering the active layer 103 and the insulating layer 104.
  • the dielectric layer 201 is provided with a source/drain metal layer 202.
  • the present invention also discloses a method for fabricating the above TFT array substrate, comprising the steps of: sequentially forming a buffer layer 102 and an active layer 103 on a substrate 101; and forming a layer on the active layer 103.
  • the insulating layer 104 is deposited; the photoresist 107 is coated on the insulating layer 104, and the photoresist 107 is exposed and developed.
  • a groove T is formed on the active layer 103 near the outer peripheral region of the insulating layer 104.
  • the width of the insulating layer 104 is smaller than the width of the active layer 103, and the insulating layer 104 is correspondingly disposed in the intermediate portion of the active layer 103.
  • the function of the groove T is to prevent the oxygen vacancies on the surface of the active layer 103 from being blocked by the groove T during subsequent plasma processing and anneal processing, so that oxygen vacancies cannot enter the channel region of the active layer 103.
  • one side opening edge T1 of the groove T is adjacent to the position of the region on the active layer 103 corresponding to the insulating layer 104. In this way, the production process such as subsequent deposition is simplified.
  • the groove T is set to two, and the two grooves T are respectively disposed on the active layer 103 on opposite sides of the outer peripheral region of the insulating layer 104, and the depth of the groove T in the active layer 103 is smaller than the active The thickness of layer 103. In this way, the production process such as subsequent deposition is simplified.
  • the method further includes covering the metal layer 106 on the insulating layer 104 while filling the metal layer 106 in the recess T of the active layer to form the metal layer 106a as shown.
  • the oxygen vacancies on the surface of the active layer 103 are blocked by the metal layer 106a, so that oxygen vacancies cannot enter the channel region of the active layer 103.
  • the oxygen vacancy diffusion on the surface of the conductive active layer 103 is blocked by the metal layer 106a embedded on both sides of the channel region of the active layer 103, so that oxygen vacancies cannot enter the channel region, thus preventing plasma treatment.
  • the oxygen vacancies on the surface of the active layer 103 diffuse into the channel region, reducing the influence of oxygen vacancy diffusion on the TFT leakage current in the conductive active layer.
  • the method further includes: forming a dielectric layer 201 covering the active layer 103 and the insulating layer 104 on the active layer 103 and the insulating layer 104, and forming a source/drain metal layer 202 in the dielectric layer 201.
  • the invention also discloses a display device comprising the above TFT array substrate.
  • the manufacturing process of the display device further comprises covering the dielectric layer 201 and the source/drain metal layer 202 with a flat layer 203, and the flat layer 203 is covered with the anode layer 204.
  • the technical problems to be solved by the display device and the technical effects that can be achieved are the same as those of the above-mentioned TFT array substrate, and the technical effects that can be achieved are not described herein.
  • the TFT array substrate provided by the present invention, the manufacturing method thereof and the display device have the following beneficial effects:
  • a buffer layer and an active layer are sequentially disposed on the substrate; an insulating layer is disposed on the active layer, the width of the insulating layer is smaller than the width of the active layer, and the insulating layer is correspondingly disposed in an intermediate portion of the active layer, and the outer layer of the active layer is adjacent to the insulating layer
  • the area is provided with a groove, and a metal layer is arranged in the groove. The oxygen vacancy on the surface of the treated active layer is blocked by the metal layer, so that the oxygen vacancy cannot enter the groove of the active layer.
  • the yield of the display device is improved.

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Abstract

提供一种TFT阵列基板及其制作方法、一种显示装置。阵列基板包括：基板（101）；依次设置在基板（101）上的缓冲层（102）和主动层（103）；设置在主动层（103）上的绝缘层（104），绝缘层（104）的宽度小于主动层（103）的宽度，且绝缘层（104）对应设置在主动层（103）的中间区域，其中主动层（103）上靠近绝缘层（104）的外周区域形成有凹槽（T）；绝缘层（104）上覆盖有金属层（106），同时金属层（106）填充在主动层（103）的凹槽（T）内。凹槽（T）可阻止等离子处理后的主动层（103）表面的氧空缺扩散到沟道区域，减小导体化主动层（103）时氧空缺扩散对TFT漏电流的影响，提高显示面板的产出良率。

Description

一种TFT阵列基板及其制作方法、显示装置
本申请要求于2017年11月28日提交中国专利局、申请号为201711218906.0、发明名称为“一种TFT阵列基板及其制作方法、显示装置”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示面板制造领域，尤其涉及一种TFT阵列基板及其制作方法、显示装置。
背景技术
传统的top gate IGZO TFT基板制作中，在制作完GE金属层电极后，以GE金属层当光罩进行自对准等离子处理后，使与SD contact的IGZO表面区域导体化，可以减小IGZO与SD的接触阻抗，形成类似欧姆接触的效果。
上述制作方法存在的问题是：导体化的IGZO里面氧空缺会增多，在后续处理过程中，氧空缺会沿表面向沟道扩散，使IGZO沟道区域上表面的氧空缺增多，会使TFT关闭状况下的漏电增大，TFT无法有效关闭，从而影响TFT的特性。
发明内容
本发明所要解决的技术问题在于，提供一种TFT阵列基板及其制作方法、显示装置，可阻止等离子处理后的主动层表面的氧空缺扩散到沟道区域，减小导体化主动层中氧空缺扩散对TFT漏电流的影响，提高显示面板的产出良率。
为了解决上述技术问题，本发明的实施例提供了一种TFT阵列基板，包括：基板；依次设置在基板上的缓冲层和主动层；设置在主动层上的绝缘层，绝缘层的宽度小于主动层的宽度，且绝缘层对应设置在主动层的中间区域，主动层上靠近绝缘层的外周区域设有凹槽。
其中，凹槽的一侧开口边缘紧邻主动层上与绝缘层相对应的区域位置。
其中，凹槽设为两个，该两个凹槽分别设置在主动层上靠近绝缘层的外 周区域的相对两侧。
其中，凹槽在主动层内的深度小于主动层的厚度。
其中，绝缘层上覆盖有金属层，同时金属层填充在主动层的凹槽内。
其中，主动层与绝缘层上设有覆盖主动层和绝缘层的介电层，介电层上设有源漏极金属层。
为解决上述技术问题，本发明还公开了一种TFT阵列基板的制作方法，包括以下步骤：在基板上依次制作缓冲层和主动层；在主动层上整层沉积绝缘层；在绝缘层上涂布光阻，使用对光阻进行曝光、显影；进行刻蚀及光阻去除后，在主动层上靠近绝缘层的外周区域形成凹槽，绝缘层的宽度小于主动层的宽度，且绝缘层对应设置在主动层的中间区域。
其中，凹槽的一侧开口边缘紧邻主动层上与绝缘层相对应的区域位置；凹槽设为两个，该两个凹槽分别设置在所述主动层上靠近所述绝缘层的外周区域的相对两侧；所述凹槽在所述主动层内的深度小于所述主动层的厚度。
其中，还包括：在绝缘层上制作金属层，同时金属层填充在主动层的凹槽内；在主动层上的与绝缘层上制作覆盖主动层和绝缘层的介电层、在介电层上制作源漏极金属层的步骤。
为解决上述技术问题，本发明还公开了一种显示装置，显示装置包括TFT阵列基板，的TFT阵列基板包括：基板；依次设置在基板上的缓冲层和主动层；设置在主动层上的绝缘层，绝缘层的宽度小于主动层的宽度，且绝缘层对应设置在主动层的中间区域；主动层上靠近绝缘层的外周区域设有凹槽，凹槽设为两个，该两个凹槽分别设置在主动层上靠近绝缘层的外周区域的相对两侧。
其中，凹槽在主动层内的深度小于主动层的厚度。
其中，绝缘层上覆盖有金属层，同时金属层填充在主动层的凹槽内。
其中，主动层与绝缘层上设有覆盖主动层和绝缘层的介电层，介电层上设有源漏极金属层。
实施本发明所提供的TFT阵列基板及其制作方法、显示装置，具有如下
有益效果：
第一、基板上依次设置缓冲层和主动层；主动层上设置绝缘层，绝缘层 的宽度小于主动层的宽度，且绝缘层对应设置在主动层的中间区域，主动层上靠近绝缘层的外周区域设有凹槽，凹槽中设有金属层，经处理后的主动层表面的氧空缺由金属层阻隔，使氧空缺无法进入到主动层的凹槽中。
第二，通过减小导体化主动层中氧空缺扩散对TFT漏电流的影响，提高显示装置产出的良率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例通过TFT阵列基板的制作方法对光阻进行曝光、显影的结构示意图。
图2是本发明实施例通过TFT阵列基板的制作方法刻蚀及光阻去除后得到凹槽的示意图。
图3是本发明实施例通过TFT阵列基板的制作方法在凹槽上沉积金属层的结构示意图。
图4是本发明实施例TFT阵列基板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图4所述所示，为本发明TFT阵列基板的实施例一。
本实施例中的TFT阵列基板，包括：基板101；依次设置在基板101上的缓冲层102和主动层103；设置在主动层103上的绝缘层104，其中：主动层103上的与绝缘层104相对应区域的外周设有凹槽T。
具体实施时，凹槽T的形成是：在基板101上依次制作缓冲层102和主动层103，对缓冲层102和主动层103各自图案化处理后，在主动层103上沉积绝缘层104并涂布光阻，使用半透式掩模板105对光阻进行曝光、显影 得到的。其中：凹槽T形成位置是：主动层103上靠近绝缘层104的外周区域，该构造中，绝缘层104的宽度小于主动层103的宽度，且绝缘层104对应设置在主动层103的中间区域。
凹槽T的作用是：使在后续等离子处理及anneal处理过程中，主动层103表面的氧空缺由凹槽T进行阻隔，使氧空缺无法进入到主动层103的沟道区域。
优选的，凹槽T的一侧开口边缘T1紧邻主动层103上与绝缘层104相对应的区域位置。如此，简化后续沉积等制作工艺流程。
优选的，凹槽T设为两个，该两个凹槽T分别设置在主动层103上靠近绝缘层104的外周区域的相对两侧，同时，凹槽T在主动层103内的深度小于主动层103的厚度。如此，简化后续沉积等制作工艺流程。
进一步的，本实施例中，绝缘层104上覆盖有金属层106，同时金属层106填充在主动层103的凹槽T内，形成如图所示的金属层106a。如此，使得经处理后，本实施例中为plasma等离子处理，及后续anneal处理过程中，主动层103表面的氧空缺由金属层106a进行阻隔，使氧空缺无法进入到主动层103的沟道区域。也就是说，导体化主动层103表面的氧空缺扩散时会被镶嵌在主动层103沟道区两侧的金属层106a阻隔，使氧空缺无法进入到沟道区域，如此，能够阻止plasma处理后的主动层103表面的氧空缺扩散到沟道区域，减小导体化主动层中氧空缺扩散对TFT漏电流的影响。
进一步，主动层103与绝缘层104上制作覆盖主动层103和绝缘层104的设有介电层201，介电层201中设有源漏极金属层202。
结合参见图1-图3所示，本发明还公开了一种上述TFT阵列基板的制作方法，包括以下步骤：在基板101上依次制作缓冲层102和主动层103；在主动层103上整层沉积绝缘层104；在绝缘层104上涂布光阻107，使用对光阻107进行曝光、显影。进行刻蚀及光阻去除后，在主动层103上靠近绝缘层104的外周区域形成凹槽T。该制程中，绝缘层104的宽度小于主动层103的宽度，且绝缘层104对应设置在主动层103的中间区域。
凹槽T的作用是：使在后续等离子处理及anneal处理过程中，主动层103表面的氧空缺由凹槽T进行阻隔，使氧空缺无法进入到主动层103的沟 道区域。
优选的，凹槽T的一侧开口边缘T1紧邻主动层103上与绝缘层104相对应的区域位置。如此，简化后续沉积等制作工艺流程。
优选的，凹槽T设为两个，该两个凹槽T分别设置在主动层103上靠近绝缘层104的外周区域的相对两侧，同时，凹槽T在主动层103内的深度小于主动层103的厚度。如此，简化后续沉积等制作工艺流程。
进一步的，还包括在绝缘层104上覆盖金属层106，同时该金属层106填充在主动层的凹槽T内，形成如图所示的金属层106a。如此，使得经处理后，本实施例中为plasma等离子处理，及后续anneal处理过程中，主动层103表面的氧空缺由金属层106a进行阻隔，使氧空缺无法进入到主动层103的沟道区域。也就是说，导体化主动层103表面的氧空缺扩散时会被镶嵌在主动层103沟道区两侧的金属层106a阻隔，使氧空缺无法进入到沟道区域，如此，能够阻止plasma处理后的主动层103表面的氧空缺扩散到沟道区域，减小导体化主动层中氧空缺扩散对TFT漏电流的影响。
进一步的，还包括：在主动层103与绝缘层104上制作覆盖主动层103和绝缘层104的介电层201、在介电层201中制作源漏极金属层202的步骤。
本发明还公开了一种包含上述TFT阵列基板的显示装置，显示装置的制成过程还包括在介电层201和源漏极金属层202上覆盖平坦层203，平坦层203上覆盖阳极层204，在阳极层204上制成像素分离层205和发光层206进而形成OLED驱动器件的步骤。具体实施时，显示装置所要解决的技术问题和能够实现的技术效果与上述TFT阵列基板所要解决的技术问题和能够实现的技术效果相同，不再赘述。
实施本发明所提供的TFT阵列基板及其制作方法、显示装置，具有如下有益效果：
第一、基板上依次设置缓冲层和主动层；主动层上设置绝缘层，绝缘层的宽度小于主动层的宽度，且绝缘层对应设置在主动层的中间区域，主动层上靠近绝缘层的外周区域设有凹槽，凹槽中设有金属层，经处理后的主动层表面的氧空缺由金属层阻隔，使氧空缺无法进入到主动层的凹槽中。
第二，通过减小导体化主动层中氧空缺扩散对TFT漏电流的影响，提高 显示装置产出的良率。

Claims (17)

  1. 一种TFT阵列基板，其中，包括：
    基板；
    依次设置在基板上的缓冲层和主动层；
    设置在所述主动层上的绝缘层，所述绝缘层的宽度小于所述主动层的宽度，且所述绝缘层对应设置在所述主动层的中间区域；
    所述主动层上靠近所述绝缘层的外周区域设有凹槽。
  2. 如权利要求1所述的TFT阵列基板，其中，所述凹槽的一侧开口边缘紧邻所述主动层上与所述绝缘层相对应的区域位置。
  3. 如权利要求2所述的TFT阵列基板，其中，所述凹槽设为两个，该两个凹槽分别设置在所述主动层上靠近所述绝缘层的外周区域的相对两侧。
  4. 如权利要求1所述的TFT阵列基板，其中，所述凹槽在所述主动层内的深度小于所述主动层的厚度。
  5. 如权利要求1所述的TFT阵列基板，其中，所述绝缘层上覆盖有金属层，同时所述金属层填充在所述主动层的凹槽内。
  6. 如权利要求3所述的TFT阵列基板，其中，所述绝缘层上覆盖有金属层，同时所述金属层填充在所述主动层的凹槽内。
  7. 如权利要求4所述的TFT阵列基板，其中，所述绝缘层上覆盖有金属层，同时所述金属层填充在所述主动层的凹槽内。
  8. 如权利要求1所述的TFT阵列基板，其中，所述主动层与所述绝缘层上设有覆盖所述主动层和绝缘层的介电层，所述介电层上设有源漏极金属层。
  9. 如权利要求3所述的TFT阵列基板，其中，所述主动层与所述绝缘层上设有覆盖所述主动层和绝缘层的介电层，所述介电层上设有源漏极金属层。
  10. 一种TFT阵列基板的制作方法，其中，包括以下步骤：
    在基板上依次制作缓冲层和主动层；
    在所述主动层上整层沉积绝缘层；
    在所述绝缘层上涂布光阻，使用对光阻进行曝光、显影；
    进行刻蚀及光阻去除后，在所述主动层上靠近所述绝缘层的外周区域形成凹槽，所述绝缘层的宽度小于所述主动层的宽度，且所述绝缘层对应设置在所述主动层的中间区域。
  11. 如权利要求10所述的TFT阵列基板的制作方法，其中，所述凹槽的一侧开口边缘紧邻所述主动层上与所述绝缘层相对应的区域位置；
    所述凹槽设为两个，该两个凹槽分别设置在所述主动层上靠近所述绝缘层的外周区域的相对两侧；所述凹槽在所述主动层内的深度小于所述主动层的厚度。
  12. 如权利要求10所述的TFT阵列基板的制作方法，其中，还包括：在所述绝缘层上制作金属层，同时所述金属层填充在所述主动层的凹槽内；
    在所述主动层与所述绝缘层上覆盖所述主动层和绝缘层的介电层、在介电层上制作源漏极金属层的步骤。
  13. 如权利要求11所述的TFT阵列基板的制作方法，其中，还包括：在所述绝缘层上制作金属层，同时所述金属层填充在所述主动层的凹槽内；
    在所述主动层与所述绝缘层上覆盖所述主动层和绝缘层的介电层、在介电层上制作源漏极金属层的步骤。
  14. 一种显示装置，其中，所述显示装置包括TFT阵列基板，所述的TFT阵列基板包括：
    基板；
    依次设置在基板上的缓冲层和主动层；
    设置在所述主动层上的绝缘层，所述绝缘层的宽度小于所述主动层的宽度，且所述绝缘层对应设置在所述主动层的中间区域；
    所述主动层上靠近所述绝缘层的外周区域设有凹槽，所述凹槽设为两个，该两个凹槽分别设置在所述主动层上靠近所述绝缘层的外周区域的相对两侧。
  15. 如权利要求14所述的显示装置，其中，所述凹槽在所述主动层内的深度小于所述主动层的厚度。
  16. 如权利要求14所述的显示装置，其中，所述绝缘层上覆盖有金属层，同时所述金属层填充在所述主动层的凹槽内。
  17. 如权利要求14所述的显示装置，其中，所述主动层与所述绝缘层上设有覆盖所述主动层和绝缘层的介电层，所述介电层上设有源漏极金属层。
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