WO2020244313A1 - 阵列基板及其制备方法、显示面板、显示装置 - Google Patents

阵列基板及其制备方法、显示面板、显示装置 Download PDF

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WO2020244313A1
WO2020244313A1 PCT/CN2020/085107 CN2020085107W WO2020244313A1 WO 2020244313 A1 WO2020244313 A1 WO 2020244313A1 CN 2020085107 W CN2020085107 W CN 2020085107W WO 2020244313 A1 WO2020244313 A1 WO 2020244313A1
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layer
active layer
substrate
sublayer
carrier concentration
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PCT/CN2020/085107
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English (en)
French (fr)
Inventor
宋威
赵策
丁远奎
王明
胡迎宾
王庆贺
李伟
倪柳松
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/054,823 priority Critical patent/US11545510B2/en
Publication of WO2020244313A1 publication Critical patent/WO2020244313A1/zh

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    • H01L27/1259—Multistep manufacturing methods
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Definitions

  • the present disclosure relates to the field of display, in particular, to an array substrate and a preparation method thereof, a display panel, and a display device.
  • Thin Film Transistor is currently the main driving element in liquid crystal display panels and active matrix-driven organic light emitting display panels.
  • the performance of thin film transistors directly affects the display performance of the display panel.
  • some thin film transistors in the array substrate are used as driving transistors (DR TFT), and some thin film transistors are used as switching transistors (SW TFT).
  • DR TFT driving transistors
  • SW TFT switching transistors
  • the threshold voltage of the driving transistor and the switching transistor has an important influence on the display quality of the display panel.
  • the present disclosure proposes a method of manufacturing an array substrate.
  • the method includes: providing a substrate with a driving transistor region and a switching transistor region; forming a pre-layer for an active layer on one side of the substrate; The source layer is patterned with a preset layer to form a driving active layer and a switching active layer, wherein the orthographic projection of the driving active layer on the substrate is located in the driving transistor region, and the switch has The orthographic projection of the source layer on the substrate is located in the switching transistor region, and the carrier concentration in the driving active layer is less than the carrier concentration in the switching active layer.
  • the pre-layer for the active layer formed includes two sublayers in which the carrier concentration is different, and the driving active layer is away from the surface of the substrate and the switch The surface of the active layer away from the substrate belongs to the two sublayers, respectively.
  • the carrier concentration in the sublayer close to the substrate among the two sublayers is less than the carrier concentration in the sublayer farther from the substrate.
  • the two sublayers are adjacent and have different materials.
  • the two sublayers are a first sublayer and a second sublayer, and the first sublayer is closer to the substrate than the second sublayer to form the first sublayer.
  • the material of the layer includes indium gallium zinc oxide, the thickness of the first sublayer is 10-50 nm, and the carrier concentration in the first sublayer is 10 15 -10 19 cm 2 V -1 s -1 ;
  • a material forming the second sub-layer comprises indium zinc oxide, the thickness of the second sub-layer is 10 ⁇ 50nm, the carrier concentration in the second sub-layer is 10 18 ⁇ 10 20 cm 2 V - 1 s -1 .
  • the patterning of the pre-layer for the active layer includes the steps of: etching the pre-layer for the active layer into a first part through a patterning process using photoresist;
  • the orthographic projection of the first part on the substrate is located in the driving transistor area, and the first photoresist layer remains on the surface of the first part away from the substrate;
  • the second Part of the orthographic projection on the substrate is located in the switching transistor area, and the second photoresist layer remains on the surface of the second part far from the substrate; and the second photoresist layer
  • the thickness is greater than the thickness of the first photoresist layer; by etching, the first photoresist layer is removed to expose the first part, and the remaining part is left on the surface of the second part away from the substrate Thickness of the second photoresist layer; through the carrier concentration differential treatment, so that the carrier concentration in the first part is less than the carrier concentration in the second part; and removing the remaining thickness of the second Two photoresist layers,
  • the carrier concentration differentiation treatment includes: making the thickness of the first part smaller than the thickness of the second part by etching.
  • the pre-layer for the active layer includes two sublayers with different carrier concentrations
  • the carrier concentration differential treatment further includes: removing the carrier concentration by wet etching. The sublayer of the two sublayers far from the substrate in the first part.
  • the carrier concentration differential treatment includes: annealing the first part in an oxidizing gas atmosphere, or performing an annealing treatment on the first part by using plasma excited by the oxidizing gas Processing so that the carrier concentration in the first part is smaller than the carrier concentration in the second part.
  • the step of etching the pre-layer for the active layer into a first part and a second part includes: on the side of the pre-layer for the active layer away from the substrate The surface is coated with photoresist; the photoresist is exposed and developed using a halftone mask to form a photoresist layer, and the photoresist layer includes: the first photoresist partially retained by the photoresist Layer and the second photoresist layer in which the photoresist is completely preserved; etching the pre-layer for the active layer to remove the pre-layer for the active layer that is not covered by the photoresist layer Layer is formed to form the first part and the second part; and the step of removing the first photoresist layer to expose the first part includes dry etching.
  • the present disclosure provides an array substrate.
  • the array substrate is prepared by the aforementioned method.
  • the present disclosure proposes an array substrate.
  • the array substrate includes a substrate; a driving transistor and a switching transistor located on the substrate, and the carrier concentration in the driving active layer of the driving transistor is smaller than that of the switching transistor. The carrier concentration in the active layer.
  • the thickness of the driving active layer is less than the thickness of the switching active layer; or at least one of the driving active layer and the switching active layer includes a plurality of sub-layers arranged in a stack. Layer, wherein the number of sublayers in the driving active layer is less than the number of sublayers in the switching active layer; or the concentration of doped carriers in the driving active layer is less than The concentration of the carrier doped in the source layer.
  • the switch active layer includes a first sublayer and a second sublayer, wherein the first sublayer is closer to the substrate than the second sublayer, and the switch has The surface of the source layer away from the substrate belongs to the second sublayer, and the driving active layer includes a third sublayer formed in the same layer as the first sublayer, and the driving active layer is far away from the The surface of the substrate belongs to the third sublayer.
  • the thickness of the first sublayer/third sublayer is 10-50 nm, and the first sublayer
  • the carrier concentration in the layer/third sublayer is 10 15 ⁇ 10 19 cm 2 V -1 s -1 ;
  • the material for forming the second sublayer includes indium zinc oxide, and the thickness of the second sublayer is 10-50 nm, the carrier concentration in the second sublayer is 10 18 -10 20 cm 2 V -1 s -1 .
  • the present disclosure proposes a display panel.
  • the display panel includes the aforementioned array substrate.
  • the present disclosure proposes a display device.
  • the display device includes: a housing; and the aforementioned display panel.
  • Fig. 1 shows a flowchart of a method for preparing an array substrate according to an embodiment of the present disclosure
  • FIG. 2 shows a flowchart of a method for preparing an array substrate according to another embodiment of the present disclosure
  • Fig. 3 shows a flow chart of a method for preparing an array substrate according to another embodiment of the present disclosure
  • Fig. 4 shows a flow chart of a method for preparing an array substrate according to another embodiment of the present disclosure
  • Fig. 5 shows a flow chart of a method for preparing an array substrate according to another embodiment of the present disclosure
  • FIG. 6 shows a flowchart of a method for preparing an array substrate according to another embodiment of the present disclosure
  • FIG. 7 shows a flowchart of a method for preparing an array substrate according to another embodiment of the present disclosure.
  • FIG. 8 shows a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the current array substrate often has the problem that the threshold voltages of the driving transistor and the switching transistor are inconsistent (usually, the threshold voltage of the switching transistor is greater than the threshold voltage of the driving transistor), thereby affecting the display quality of the display panel.
  • the inventor found that this is mainly due to:
  • a light shielding layer is usually formed between the drive transistor and the substrate to block external light from entering the drive from the substrate side.
  • the active layer of the transistor uses a preset layer to avoid the deterioration of the driving transistor characteristics caused by light.
  • no shading layer is provided.
  • the aforementioned problems such as the inconsistency of the threshold voltages of the driving transistor and the switching transistor are caused. Therefore, if a new array substrate and its preparation method can be proposed, it can make the driving transistor and the switching transistor have a light shielding layer between the driving transistor and the substrate, and there is no light shielding layer between the switching transistor and the substrate. The better consistency of the threshold voltage will improve the display quality of the display panel and solve the above problems to a large extent.
  • 100 substrate; 110: driving transistor area; 120: switching transistor area; 200: preset layer for active layer; 10: sublayer; 210: driving active layer; 220: switching active layer; 211: part one 221: the second part; 300: photoresist; 310: photoresist layer; 311: first photoresist layer; 312: second photoresist layer; 400: halftone mask; 500: light-shielding layer; 510: metal thin film; 600: buffer layer; 1000: array substrate.
  • the present disclosure proposes a method of manufacturing an array substrate.
  • a light shielding layer shield layer
  • the threshold voltage of the driving transistor and the switching transistor Inconsistent (usually the threshold voltage of the switching transistor is greater than the threshold voltage of the driving transistor), which further affects the display quality of the display panel using the array substrate.
  • the carrier concentration in the active layer Active layer
  • the threshold voltage has a greater impact on the threshold voltage.
  • the driving transistor and the substrate When there is a light-shielding layer between the bottom and no light-shielding layer between the switching transistor and the substrate, the carrier concentration in the driving active layer (that is, the pre-layer for the active layer in the driving transistor) is lower than that of the switching transistor.
  • the carrier concentration in the source layer (that is, the pre-layer for the active layer in the switching transistor) can increase the threshold voltage of the driving transistor, so that the threshold voltages of the switching transistor and the driving transistor in the prepared array substrate are more consistent. Furthermore, the display quality of the display panel using the array substrate is improved.
  • the method includes:
  • the substrate 100 may be glass or the like.
  • the substrate 100 has a driving transistor area 110 and a switching transistor area 120.
  • the driving transistor is formed in the driving transistor region 110, for example, directly above the driving transistor region 110
  • the switching transistor is formed in the switching transistor region 120, for example, directly above the switching transistor region 120.
  • S200 forming a pre-layer for the active layer, the pre-layer for the active layer includes at least two sub-layers arranged in a stack
  • a pre-layer for the active layer is formed on one side of the aforementioned substrate, and the pre-layer for the active layer includes at least two sub-layers arranged in a stack.
  • the active layer pre-layer 200 includes at least two sublayers 10 (for example, refer to the first sublayer 10A and the The second sub-layer 10B).
  • the pre-layer 200 for an active layer may be formed on one side of the substrate 100 by a deposition method. Specifically, an oxide semiconductor thin film may be deposited on one side of the substrate 100 to form a plurality of sublayers 10 respectively.
  • the material for forming the pre-layer 200 for the active layer is not particularly limited, and may include, for example, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and indium gallium tin oxide (IGTO). At least one of.
  • IZO indium zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin oxide
  • the formed pre-layer for the active layer includes at least two sub-layers arranged in a stack.
  • the material, thickness, and thickness of each sub-layer in the pre-layer for the active layer can be adjusted.
  • the carrier concentration, etc. can be set, and the number of sublayers and the combination of multiple sublayers can be set. Therefore, on the one hand, the final drive active layer and switching active layer can be made better.
  • the conductive channel of the thin film transistor is mainly the front channel (that is, the pre-layer for the active layer near the gate)
  • the In the array substrate of the pre-layer for dual active layers driving active layer and switching active layer
  • the carrier concentration of the front channel can be made lower.
  • the carrier concentration in different sublayers 10 may be different (for example, the first sublayer 10A and The carrier concentration in the second sublayer 10B may be different). Therefore, the performance of the driving active layer and the switching active layer can be further improved; and it is convenient to adjust the difference of the carrier concentration in the final driving active layer and the switching active layer, and further improve the prepared array substrate.
  • the consistency of the threshold voltages of the switching transistor and the driving transistor improves the display quality of the display panel using the array substrate.
  • the carrier concentration in the first sublayer 10A close to the substrate 100 may be less than the carrier concentration in the second sublayer 10B far from the substrate 100.
  • the carrier concentration in the first sublayer 10A may be 10 15 to 10 19 cm 2 V -1 s -1 , for example, it may be 10 16 cm 2 V -1 s -1 , or it may be 10 17 cm 2 V -1 s -1 , which can be 10 18 cm 2 V -1 s -1, etc.;
  • the carrier concentration in the second sublayer 10B can be 10 18 ⁇ 10 20 cm 2 V -1 s -1 , for example It can be 10 19 cm 2 V -1 s -1 and so on. Therefore, in the method according to the embodiment of the present disclosure, the carrier concentration in different sublayers is different.
  • the carrier concentration of the front channel can be made higher, which is beneficial to improve the mobility of the thin film transistor. , So that the carrier concentration in the back channel is lower, thereby reducing the power consumption of the thin film transistor and saving energy.
  • the carrier concentration in the first sublayer 10A is less than the carrier concentration in the second sublayer 10B, which can not only increase the mobility of the thin film transistor, but also save power consumption and further improve
  • the performance of the prepared array substrate is improved; and in the subsequent steps, only the second sub-layer 10B located in the driving transistor region 110 in the orthographic projection can be removed to reduce the load in the pre-layer for the active layer of the finally formed driving transistor.
  • the carrier concentration increases the threshold voltage of the pre-layer for the active layer of the finally formed drive transistor, and can make the difference of the carrier concentration in the finally formed switch active layer and the drive active layer within a certain range (The difference is the carrier concentration in the second sublayer 10B), which can better compensate for the decrease in the threshold voltage of the driving transistor due to the light shielding layer provided below, and improve the switching transistors and driving in the prepared array substrate.
  • the uniformity of the threshold voltage of the transistors improves the display quality of the display panel using the array substrate.
  • the materials in forming different sublayers 10 may be different (for example, the first sublayer 10A and the second sublayer 10A
  • the material of the sublayer 10B may be different).
  • the material of the first sub-layer may be indium gallium zinc oxide
  • the material of the second sub-layer may be indium zinc oxide. Therefore, a combination of multiple materials to form a pre-layer for the active layer not only improves the The performance of the prepared array substrate, and, in the subsequent preparation process, you can select appropriate etching reagents (for example, choose to only dissolve and etch the second sub-layer 10B, but not the first sub-layer 10A.
  • Etching reagent performs a wet etching process to simply remove the second sub-layer 10B in the drive transistor region 110 in the orthographic projection, and reduce the carrier concentration in the pre-layer for the active layer of the finally formed drive transistor. It will not cause damage to the first sublayer 10A, that is, it will not cause damage to the performance of the pre-layer for the active layer of the finally formed drive transistor.
  • the thickness of different sublayers 10 may be different (for example, the first sublayer 10A and the second sublayer The thickness of 10B can be different).
  • the thickness of the first sublayer 10A may be 10-50 nm, specifically, 15 nm, 20 nm, 25 nm, 28 nm, 30 nm, 35 nm, 40 nm, and 45 nm.
  • the thickness of the second sublayer 10B can be 10-50nm, specifically, it can be 15nm, can be 20nm, can be 25nm, can be 28nm, can be 30nm, can be 35nm, can be 40nm, can be 45nm, etc. . Therefore, the performance of the driving active layer and the switching active layer can be further improved; and it is convenient to adjust the difference of the carrier concentration in the final driving active layer and the switching active layer, and further improve the prepared array substrate The consistency of the threshold voltages of the switching transistor and the driving transistor improves the display quality of the display panel using the array substrate.
  • the active layer pre-layer 200 may be a first sub-layer 10A and a second sub-layer 10B that are stacked, and the first sub-layer 10A is close to the substrate 100 is set, the material for forming the first sub-layer 10A includes indium gallium zinc oxide, the thickness of the first sub-layer 10A is 10-50 nm, and the carrier concentration in the first sub-layer 10A is 10 15 -10 19 cm 2 V -1 s -1 ;
  • the material for forming the second sublayer 10B includes indium zinc oxide, the thickness of the second sublayer 10B is 10-50 nm, and the carrier concentration in the second sublayer 10B is 10 18 -10 20 cm 2 V -1 s -1 .
  • the performance of the driving active layer and the switching active layer can be further improved; and it is convenient to adjust the difference of the carrier concentration in the final driving active layer and the switching active layer, and further improve the prepared array substrate
  • the consistency of the threshold voltages of the switching transistor and the driving transistor improves the display quality of the display panel using the array substrate.
  • the active layer prepared in the previous step is patterned with a preset layer to form a driving active layer and a switching active layer, wherein the orthographic projection of the driving active layer on the substrate is located in the driving transistor area , The orthographic projection of the switching active layer on the substrate is located in the switching transistor region, and the carrier concentration in the driving active layer is less than the carrier concentration in the switching active layer.
  • the method further includes:
  • the active layer prepared in the previous step is etched into the first part and the second part with the pre-layer by the first patterning process.
  • etching the active layer into the first part and the second part by using the pre-layer can be achieved through the following steps:
  • the surface of the pre-layer for the active layer prepared in the previous step is coated with photoresist on the side away from the substrate.
  • the photoresist 300 is coated on the surface of the active layer pre-layer 200 on the side away from the substrate 100.
  • the halftone mask 400 may include a partially light-transmitting area III, a completely opaque area II, and a completely light-transmitting area I (in FIG. 4(d), The solid line represents completely opaque, the dashed line represents partial light transmission, and the unmarked area represents complete light transmission). Therefore, after the halftone mask 400 is used to expose and develop the photoresist 300, referring to (e) in FIG.
  • the formed photoresist layer 310 includes: a photoresist portion corresponding to the partially transparent region III The reserved area, namely the first photoresist layer 311; and the completely reserved area of photoresist corresponding to the completely opaque area II, namely the second photoresist layer 312; the photoresist in the area corresponding to the completely transparent area I Undeveloped, that is, no photoresist layer is formed, and the thickness of the first photoresist layer 311 formed is smaller than the thickness of the second photoresist layer 312.
  • the first etching process is performed on the pre-layer for the active layer on which the photoresist layer is set in the previous step, and the pre-layer for the active layer that is not covered by the photoresist layer is removed to form the first part And the second part.
  • the active layer pre-layer that is not covered by the photoresist layer 310 is removed.
  • the layer 200 (the pre-layer 200 for the active layer in the area covered by the photoresist layer 310 will not be etched) to form the first part 211 and the second part 221.
  • the orthographic projection of the first part 211 on the substrate 100 is located in the driving transistor area 110, the surface of the first part 211 far away from the substrate 100 has a first photoresist layer 311; the second part 221 is on the substrate 100
  • the orthographic projection is located in the switching transistor region 120, and the surface of the second portion 221 away from the substrate 100 has a second photoresist layer 312. Therefore, the pre-layer 200 for the active layer formed in the previous step can be etched into the first part 211 and the second part 221 easily.
  • the first etching process may be a wet etching process.
  • the first part of the surface covered with the first photoresist layer and the surface covered with the second photoresist formed in the previous step (as shown in FIG. 5(f), that is, as shown in FIG. 4(f))
  • the second part of the layer is subjected to a second etching treatment to remove the first photoresist layer on the surface of the first part, exposing the first part.
  • a second etching treatment to remove the first photoresist layer on the surface of the first part, exposing the first part.
  • the structure of the pre-layer for the active layer after the second etching process is referred to (g) in FIG. 5, the first part 211 is exposed, and a part of the second part 221 is still covered with Two photoresist layer 312.
  • the second etching process may be a dry etching process.
  • the carrier concentration difference treatment is performed on the pre-layer for the active layer after the second etching treatment in the previous step, so that the carrier concentration in the first part is less than the carrier concentration in the second part Sub-concentration to form a driving active layer and a switching active layer. Therefore, the driving active layer and the switching active layer can be easily formed by this method.
  • the carrier concentration differential treatment can only Work on the exposed first part without affecting the second part.
  • the carrier concentration in the first part can be reduced, so that the carrier concentration in the first part after the treatment is less than the carrier concentration in the second part, even if the final drive
  • the carrier concentration in the active layer is less than the carrier concentration in the switch active layer, which increases the threshold voltage of the driving transistor, so that the threshold voltages of the switching transistor and the driving transistor in the final prepared array substrate have better consistency , To improve the display quality of the display panel using the array substrate.
  • the carrier concentration differentiation treatment may further include: making the thickness of the first part smaller than the thickness of the second part through a third etching treatment. That is, the first part can be subjected to a third etching treatment to reduce the thickness of the first part, so that the thickness of the first part is smaller than the thickness of the second part, and the carrier concentration in the first part is smaller than the carrier concentration in the second part concentration. Therefore, this method can easily make the carrier concentration in the first part less than the carrier concentration in the second part, thereby improving the consistency of the threshold voltage of the switching transistor and the driving transistor in the prepared array substrate, and improving the use of the The display quality of the display panel of the array substrate.
  • the third etching process may be a wet etching process.
  • the conditions of the third etching treatment (such as etching time, etc.) can be adjusted so that the thickness difference between the first part and the second part finally formed is within a certain range, and the thickness difference causes the first part and the second part
  • the difference in the carrier concentration in the part that is, the increase in the threshold voltage of the driving transistor due to the decrease in the thickness of the first part, can better compensate for the decrease in the threshold voltage of the driving transistor due to the light shielding layer underneath, thereby making
  • the threshold voltages of the switching transistors and the driving transistors in the finally prepared array substrate have better consistency, which improves the display quality of the display panel using the array substrate.
  • the method can make the carrier concentration in the first part less than the carrier concentration in the second part, the operation is relatively simple, and the consistency of the threshold voltage of the switching transistor and the driving transistor in the prepared array substrate is improved. Improve the display quality of the display panel using the array substrate.
  • the pre-layer for the active layer prepared in the method according to the embodiments of the present disclosure includes a plurality of stacked sublayers, and the materials, thickness, The carrier concentration may be different.
  • the carrier concentration differential treatment may further include: wet etching treatment to remove at least one sublayer of the first part by etching. Floor.
  • the trimmer concentration difference treatment may be a wet etching treatment, that is, the etching reagent may only etch one sub-layer located far from the substrate, Without causing damage to other sublayers underneath it, this method can simply make the thickness of the first part finally formed smaller than the thickness of the second part.
  • the partial structure diagram of the array substrate after the wet etching process can be referred to (h) in FIG. 5, the second sub-layer 10B in the first part 211 is etched and removed, and only the first sub-layer 10A remains. , And the second part 221 still includes the first part 10A and the second part 10B that are stacked.
  • the thickness of the sub-layer removed by wet etching (ie, the second sub-layer 10B) can be designed in advance to make
  • the decrease in the carrier concentration of the first portion 221 after the sublayer (ie the second sublayer 10B) is etched and removed (ie the increase in the threshold voltage) can just make up for the threshold value of the driving transistor due to the light shielding layer provided below
  • the reduction in voltage further makes the threshold voltage of the switching transistor and the driving transistor in the finally prepared array substrate have better consistency, and improves the display quality of the display panel using the array substrate.
  • the method is easy to operate, and can better control the thickness difference between the first part and the second part, so as to better improve the consistency of the threshold voltage of the switching transistor and the driving transistor.
  • the carrier concentration differential treatment may further include: annealing the exposed first part in an oxidizing gas atmosphere, or using plasma excited by the oxidizing gas to treat the first part The treatment is performed so that the carrier concentration in the first part is smaller than the carrier concentration in the second part.
  • this method can be used in combination with the aforementioned method of reducing the thickness of the first part, or used alone, that is, in this method, there is no need to perform an etching treatment on the first part, that is, there is no need to adjust the thickness of the first part. Only the carrier concentration doped in the first part is adjusted.
  • this method can simply reduce the concentration of doped carriers in the first part, and make the carrier concentration in the first part less than that in the second part, thereby improving the switching transistors in the prepared array substrate.
  • the consistency with the threshold voltage of the driving transistor improves the display quality of the display panel using the array substrate.
  • the method may further include: removing the remaining photoresist layer.
  • the driving active layer 210 and the switching active layer 220 are formed for subsequent preparation, such as forming source and drain electrodes, gates, etc. Thin film transistor structure. Therefore, the driving active layer and the switching active layer can be easily prepared, and the threshold voltages of the switching transistor and the driving transistor in the prepared array substrate have better consistency, which improves the display quality of the display panel using the array substrate .
  • the method may further include:
  • the light shielding layer 500 may be formed by the following method: first deposit a whole layer of a metal film 510 on one side of the substrate 100 (see (a) in FIG. 7), and then the metal film 510 is patterned (for example, by setting a mask, etc.) to form a light-shielding layer 500 (refer to (b) in FIG. 7).
  • the orthographic projection of the light-shielding layer 500 on the substrate 100 is located in the driving transistor area 110 in.
  • the light shielding layer formed in the previous step forms a buffer layer on the side away from the substrate.
  • an insulating film may be deposited on the side of the light shielding layer away from the substrate, for example, silicon oxide, silicon nitride, etc., to form a buffer layer.
  • PECVD ion-enhanced chemical vapor deposition
  • the buffer layer 600 is formed on the side of the light shielding layer 500 away from the substrate 100.
  • the present disclosure provides an array substrate.
  • the array substrate is prepared by the aforementioned method. Therefore, the array substrate has all the features and advantages of the array substrate prepared by the method described above, and will not be repeated here.
  • the uniformity of the threshold voltage of the array substrate is good, which can improve the display quality of the display panel using the array substrate.
  • the present disclosure proposes an array substrate.
  • the array substrate can be prepared by the aforementioned method.
  • the array substrate also has all the features and advantages of the array substrate prepared by the method described above, which will not be repeated here. According to an embodiment of the present disclosure, referring to FIG.
  • the array substrate 1000 includes: a substrate 100 and a driving transistor and a switching transistor (not shown in the figure) on one side of the substrate 100, wherein the substrate 100 has a driving transistor
  • the area 110 and the switching transistor area 120, the driving transistor is located directly above the driving transistor area 110, the switching transistor is located directly above the switching transistor area 120, and the active layer of the driving transistor is a preset layer, which is the driving active layer shown in the figure. 210.
  • the active layer of the switching transistor uses a preset layer, that is, the switching active layer 220 shown in the figure.
  • the carrier concentration in the driving active layer 210 is less than the carrier concentration in the switching active layer 220, and at least one of the driving active layer 210 and the switching active layer 220 includes a plurality of stacked layers.
  • the driving active layer 210 and the switching active layer 220 may each include at least two sub-layers 10, and reference may also be made to FIG. 8.
  • the driving active layer 210 includes one sub-layer 10A, and the switching active layer 220 includes two sublayers 10A and 10B arranged one above the other.
  • the thickness of the driving active layer 210 is less than the thickness of the switching active layer 220.
  • the number of sublayers 10 in the driving active layer 210 is less than the number of sublayers in the switching active layer 220.
  • the driving active layer 210 may include One sublayer 10A
  • the switch active layer 220 may include two stacked sublayers 10A and 10B, thereby, the carrier concentration in the driving active layer can be easily made smaller than the carrier concentration in the switching active layer concentration.
  • the concentration of doped carriers in the driving active layer is less than the concentration of doped carriers in the switching active layer.
  • the carrier concentration in the driving active layer can be easily made smaller than the scavenging carrier concentration in the switching active layer.
  • the thickness of the driving active layer 210 and the thickness of the switching active layer 220 may be the same or different. That is to say, even if the thickness of the driving active layer 210 is the same as the thickness of the switching active layer 220, the doping process can be used to make the doped carrier concentration in the driving active layer less than the switching active layer. The carrier concentration in the doping.
  • the present disclosure proposes a display panel.
  • the display panel includes the aforementioned array substrate. Therefore, the display panel has all the features and advantages of the aforementioned array substrate, which will not be repeated here. In general, the display quality of the display panel is better.
  • the present disclosure proposes a display device.
  • the display device includes: a housing; and the aforementioned display panel. Therefore, the display device has all the features and advantages of the aforementioned display panel, which will not be repeated here. In general, the display quality of the display device is better.

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Abstract

本公开公开了阵列基板及其制备方法、显示面板、显示装置。具体地，本公开提出了一种制作阵列基板的方法，具有以下步骤：提供衬底，所述衬底上具有驱动晶体管区域以及开关晶体管区域；在所述衬底的一侧形成有源层用预置层；将所述有源层用预置层图案化，以形成驱动有源层以及开关有源层，其中，所述驱动有源层在所述衬底上的正投影位于所述驱动晶体管区域中，所述开关有源层在所述衬底上的正投影位于所述开关晶体管区域中，并且，所述驱动有源层中的载流子浓度小于所述开关有源层中的载流子浓度。

Description

阵列基板及其制备方法、显示面板、显示装置
相关申请的交叉引用
本申请要求2019年6月6日提交的题目为“阵列基板及其制备方法、显示面板、显示装置”的中国专利申请201910489759.3的优先权，其通过引用以其全部结合在此。
技术领域
本公开涉及显示领域，具体地，涉及阵列基板及其制备方法、显示面板、显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)是目前液晶显示面板以及有源矩阵驱动式有机发光显示面板中的主要驱动元件，薄膜晶体管的性能会直接影响显示面板的显示性能。目前，具有薄膜晶体管的显示面板中，阵列基板中的部分薄膜晶体管作为驱动晶体管(DR TFT)，部分薄膜晶体管作为开关晶体管(SW TFT)。驱动晶体管以及开关晶体管的阈值电压，对显示面板的显示质量具有重要影响。
然而，目前的薄膜晶体管及其制备方法、显示面板、显示装置等仍有待改进。
概述
在本公开的一个方面，本公开提出了一种制作阵列基板的方法。根据本公开的实施例，该方法包括：提供衬底，所述衬底上具有驱动晶体管区域以及开关晶体管区域；在所述衬底的一侧形成有源层用预置层；将所述有源层用预置层图案化，以形成驱动有源层以及开关有源层，其中，所述驱动有源层在所述衬底上的正投影位于所述驱动晶体管区域中，所述开关有源层在所述衬底上的正投影位于所述开关晶体管区域中，并且，所述驱动有源层中的载流子浓度小于所述开关有源层中的载流子浓度。
根据本公开的实施例，形成的所述有源层用预置层中包括两个其中载流子浓度不同的亚层，并且所述驱动有源层远离所述衬底的表面和所述开关有源层远离所述衬底的表面分别属于所述两个亚层。
根据本公开的实施例，所述两个亚层中靠近所述衬底的所述亚层中的载流子浓度小于远离所述衬底的所述亚层中的载流子浓度。
根据本公开的实施例，形成的所述有源层用预置层中，所述两个亚层是相邻的且材料不相同。
根据本公开的实施例，所述两个亚层为第一亚层和第二亚层，所述第一亚层比所述第二亚层更靠近所述衬底，形成所述第一亚层的材料包括铟镓锌氧化物，所述第一亚层的厚度为10～50nm，所述第一亚层中的载流子浓度为10 15～10 19cm 2V -1s -1；形成所述第二亚层的材料包括铟锌氧化物，所述第二亚层的厚度为10～50nm，所述第二亚层中的载流子浓度为10 18～10 20cm 2V -1s -1。
根据本公开的实施例，所述将所述有源层用预置层图案化包括以下步骤：通过使用光刻胶的构图工艺，将所述有源层用预置层刻蚀为第一部分以及第二部分，所述第一部分在所述衬底上的正投影位于所述驱动晶体管区域中，所述第一部分远离所述衬底一侧的表面保留第一光刻胶层；所述第二部分在所述衬底上的正投影位于所述开关晶体管区域中，所述第二部分远离所述衬底一侧的表面保留第二光刻胶层；并且所述第二光刻胶层的厚度大于所述第一光刻胶层的厚度；通过刻蚀，去除所述第一光刻胶层以暴露出所述第一部分，并且在第二部分远离所述衬底一侧的表面保留剩余厚度的第二光刻胶层；通过载流子浓度差异化处理，使所述第一部分中的载流子浓度小于所述第二部分中的载流子浓度；以及去除所述剩余厚度的第二光刻胶层，以使所述第一部分形成所述驱动有源层，使所述第二部分形成所述开关有源层。
根据本公开的实施例，所述载流子浓度差异化处理包括：通过刻蚀使所述第一部分的厚度小于所述第二部分的厚度。
根据本公开的实施例，所述有源层用预置层中包括两个其中载流子浓度不同的亚层，所述载流子浓度差异化处理进一步包括：通过湿法刻蚀除去所述第一部分中所述两个亚层中远离所述衬底的亚层。
根据本公开的实施例，所述载流子浓度差异化处理包括：在氧化性气体氛围中，对所述第一部分进行退火处理，或者利用氧化性气体所激发的等离子体对所述第一部分进行处理，以使所述第一部分中的载流子浓度小于所述第二部分中的载流子浓度。
根据本公开的实施例，所述将所述有源层用预置层刻蚀为第一部分以及第二部分的步骤包括：在所述有源层用预置层远离所述衬底一侧的表面涂布光刻胶；利用半色调掩模板对所述光刻胶进行曝光和显影，形成光刻胶层，所述光刻胶层包括：光刻胶部分保留的所述第一光刻胶层以及光刻胶完全保留的所述第二光刻胶层；对所述有源层用预置层进行刻蚀处理，去除未被所述光刻胶层覆盖的所述有源层用预置层，形成所述第一部分以及所述第二部分；并且所述去除所述第一光刻胶层以暴露出所述第一部分的步骤包括干法刻蚀。
在本公开的另一方面，本公开提出了一种阵列基板。根据本公开的实施例，所述阵列基板是由前面所述的方法制备的。
在本公开的又一方面，本公开提出了一种阵列基板。根据本公开的实施例，该阵列基板包括：衬底；位于所述衬底上的驱动晶体管以及开关晶体管，所述驱动晶体管的驱动有源层中的载流子浓度小于所述开关晶体管的开关有源层中的载流子浓度。
根据本公开的实施例，所述驱动有源层的厚度小于所述开关有源层的厚度；或者所述驱动有源层以及所述开关有源层的至少之一包括层叠设置的多个亚层，其中所述驱动有源层中的亚层的数目小于所述开关有源层中的亚层的数目；或者所述驱动有源层中掺杂的载流子的浓度小于所述开关有源层中掺杂的所述载流子的浓度。
根据本公开的实施例，所述开关有源层包括第一亚层和第二亚层，其中所述第一亚层比所述第二亚层更靠近所述衬底，并且所述开关有源层远离所述衬底的表面属于所述第二亚层，并且所述驱动有源层包括与所述第一亚层同层形成的第三亚层，并且所述驱动有源层远离所述衬底的表面属于所述第三亚层。
根据本公开的实施例，其中形成所述第一亚层/第三亚层的材料包括铟镓锌氧化物，所述第一亚层/第三亚层的厚度为10～50nm，所述第一亚层/第三亚层中的载流子浓度为10 15～10 19cm 2V -1s -1；形成所述第二亚层的材料包括铟锌氧化物，所述第二亚层的厚度为10～50nm，所述第二亚层中的载流子浓度为10 18～10 20cm 2V -1s -1。
在本公开的又一方面，本公开提出了一种显示面板。根据本公开的实施例，该显示面板包括前面所述阵列基板。
在本公开的又一方面，本公开提出了一种显示装置。根据本公开的实施例，该显示装置包括：壳体；以及前面所述的显示面板。
附图说明
本公开的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1显示了根据本公开一个实施例的制备阵列基板的方法流程图；
图2显示了根据本公开另一个实施例的制备阵列基板的方法流程图；
图3显示了根据本公开又一个实施例的制备阵列基板的方法流程图；
图4显示了根据本公开又一个实施例的制备阵列基板的方法流程图；
图5显示了根据本公开又一个实施例的制备阵列基板的方法流程图；
图6显示了根据本公开又一个实施例的制备阵列基板的方法流程图；
图7显示了根据本公开又一个实施例的制备阵列基板的方法流程图；以及
图8显示了根据本公开一个实施例的阵列基板的结构示意图。
具体实施方式
本公开是基于发明人对于以下事实和问题的发现和认识作出的：
目前的阵列基板常存在驱动晶体管和开关晶体管的阈值电压不一致(通常情况下开关晶体管的阈值电压大于驱动晶体管的阈值电压)，进而影响显示面板的显示质量的问题。发明人发现，这主要是由于：为了提高驱动晶体管(尤其是顶栅驱动晶体管)的稳定性，通常会在驱动晶体管与衬底之间形成遮光层，阻挡外界光线从衬底一侧入射到驱动晶体管的有源层用预置层，避免光照引起的驱动晶体管特性的劣化，而由于对开关晶体管的特性稳定性要求相对较低，且出于提高开口率的考虑，开关晶体管和衬底之间通常不设置遮光层。由此，导致了前面所述的驱动晶体管和开关晶体管的阈值电压不一致等问题。因此，如果能提出一种新的阵列基板及其制备方法，能够在驱动晶体管和衬底之间具有遮光层、开关晶体管和衬底之间没有遮光层的情况下，使驱动晶体管和开关晶体管的阈值电压的一致性较好，将能较好地提高显示面板的显示质量，将能在很大程度上解决上述问题。
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
附图标记说明如下：
100：衬底；110：驱动晶体管区域；120：开关晶体管区域；200：有源层用预置层；10：亚层；210：驱动有源层；220：开关有源层；211：第一部分；221：第二部分；300：光刻胶；310：光刻胶层；311：第一光刻胶层；312：第二光刻胶层；400：半色调掩模板；500：遮光层；510：金属薄膜；600：缓冲层；1000：阵列基板。
在本公开的一个方面，本公开提出了一种制作阵列基板的方法。如前所述，目前的阵列基板中，驱动晶体管和衬底之间具有遮光层(Shield层)，开关晶体管和衬底之间没有遮光层，这样会造成驱动晶体管和开关晶体管的阈值电压(Vth)不一致(通常情况下开关晶体管的阈值电压大于驱动晶体管的阈值电压)，进而影响使用该阵列基板的显示面板的显示质量。而本申请中，发明人发现，有源层用预置层(Active层)中的载流子浓度对阈值电压的影响较大，因而，根据本公开实施例的方法中，在驱动晶体管和衬底之间具有遮光层、开关晶体管和衬底之间没有遮光层的情况下，通过令驱动有源层(即驱动晶体管中的有源层用预置层)中的载流子浓度小于开关有源层(即开关晶体管中的有源层用预置层)中的载流子浓度，可以提高驱动晶体管中的阈值电压，从而使制备的阵列基板中开关晶体管和驱动晶体管的阈值电压较为一致，进而提高了使用该阵列基板的显示面板的显示质量。
根据本公开的实施例，参考图1，该方法包括：
S100：提供衬底
该步骤中，提供衬底。根据本公开的实施例，参考图4中的(a)，衬底100可以为玻璃等。具体地，衬底100上具有驱动晶体管区域110以及开关晶体管区域120。在后续制备过程中，驱动晶体管形成在该驱动晶体管区域110，例如驱动晶体管区域110的正上方，开关晶体管形成在该开关晶体管区域120，例如开关晶体管区域120的正上方。
S200：形成有源层用预置层，有源层用预置层包括层叠设置的至少两个亚层
在该步骤中，在前面所述的衬底的一侧形成有源层用预置层，该有源层用预置层包括层叠设置的至少两个亚层。根据本公开的实施例，参考图4中的(b)，有源层用预置层200包括层叠设置的至少两个亚层10(例如参考图中所示出的第一亚层10A和第二亚层10B)。根据本公开的实施例，可以通过沉积法在衬底100的一侧形成有源层用预置层200。具体地，可以在衬底100的一侧分别沉积氧化物半导体薄膜，以便分别形成多个亚层10。根据本公开的实施例，形成有源层用预置层200的材料不受特别限制，例如可以包括铟锌氧化物(IZO)铟镓锌氧化物(IGZO)、铟镓锡氧化物(IGTO)的至少之一。
根据本公开实施例的方法，形成的有源层用预置层包括至少两个层叠设置的亚层，该方法中可以对有源层用预置层中的每个亚层的材料、厚度、载流子浓度等进行设置，并且可以对亚层的数目以及多个亚层的组合方式等进行设置，由此，一方面，可以使最终形成的驱动有源层以及开关有源层具有较好的使用性能，具体地，由于薄膜晶体管的导电沟道主要为前沟道(即靠近栅极一侧的有源层用预置层)，因此，在根据本公开实施例的方法中，在具有双有源层用预置层(驱动有源层和开关有源层)的阵列基板中，利用多个亚层形成有源层用预置层时，可以令前沟道的载流子浓度较高，有利于提高该薄膜晶体管的迁移率，而令远离栅极一侧的有源层用预置层(后沟道)中的载流子浓度较低，进而可以降低该薄膜晶体管的功耗，节省能源；另一方面，有利于后续步骤中调节最终形成的驱动有源层以及开关有源层中的载流子浓度的差值，可以简化制造工艺，并进一步提高制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。
根据本公开的实施例，参考图4中的(b)，在形成的有源层用预置层200中，不同的亚层10中的载流子浓度可以不同(例如第一亚层10A和第二亚层10B中的载流子浓度可以不同)。由此，可以进一步提高驱动有源层以及开关有源层的使用性能；并且便于调节最终形成的驱动有源层以及开关有源层中的载流子浓度的差值，进一步提高制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。具体地，靠近衬底100的第一亚层10A中的载流子浓度，可以小于远离衬底100的第二亚层10B中的载流子浓度。由此，进一步提高了所制备的阵列基板的使用性能。具体地，第一亚层10A中的载流子浓度可以为10 15～10 19cm 2V -1s -1，例如可以为10 16cm 2V -1s -1， 可以为10 17cm 2V -1s -1，可以为10 18cm 2V -1s -1等；第二亚层10B中的载流子浓度可以为为10 18～10 20cm 2V -1s -1，例如可以为10 19cm 2V -1s -1等。由此，根据本公开实施例的方法中，不同亚层中的载流子浓度不同，如前所述，可以令前沟道的载流子浓度较高，有利于提高该薄膜晶体管的迁移率，而令后沟道中的载流子浓度较低，进而可以降低该薄膜晶体管的功耗，节省能源。具体地，在顶栅型的薄膜晶体管中，靠近衬底100的一侧即为远离栅极(图中未示出)的一侧，远离衬底100的一侧即为靠近栅极(图中未示出)的一侧，第一亚层10A中的载流子浓度小于第二亚层10B中的载流子浓度，不仅可以提高该薄膜晶体管的迁移率，还可以节省功耗，进一步提高了所制备的阵列基板的使用性能；并且，后续步骤中可以只去除正投影位于驱动晶体管区域110中的第二亚层10B，降低最终形成的驱动晶体管的有源层用预置层中的载流子浓度，提高最终形成的驱动晶体管的有源层用预置层的阈值电压，并且可以使得最终形成的开关有源层和驱动有源层中的载流子浓度的差值在一定范围内(该差值即为第二亚层10B中的载流子浓度)，可以较好地弥补驱动晶体管由于下方设置了遮光层而导致的阈值电压的降低，提高制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。
根据本公开的实施例，参考图4中的(b)，在形成的有源层用预置层200中，形成不同的亚层10中的材料可以不同(例如第一亚层10A和第二亚层10B的材料可以不同)。具体地，第一亚层的材料可以为铟镓锌氧化物，第二亚层的材料可以为铟锌氧化物，由此，多种材料组合形成有源层用预置层，不仅提高了所制备的阵列基板的使用性能，而且，后续制备工艺中，可以通过选择合适的刻蚀试剂(例如选择只能溶解刻蚀第二亚层10B，而不会溶解刻蚀第一亚层10A的刻蚀试剂)进行湿法刻蚀处理，简便地去除正投影位于驱动晶体管区域110中的第二亚层10B，降低最终形成的驱动晶体管的有源层用预置层中的载流子浓度，而不会对第一亚层10A造成损害，即不会对最终形成的驱动晶体管的有源层用预置层的使用性能造成损害。
根据本公开的实施例，参考图4中的(b)，在形成的有源层用预置层200中，不同的亚层10的厚度可以不同(例如第一亚层10A和第二亚层10B的厚度可以不同)。具体地，第一亚层10A的厚度可以为10～50nm，具体地，可以为15nm，可以为20nm，可以为25nm，可以为28nm，可以为30nm，可以为35nm，可以为40nm，可以为45nm等；第二亚层10B的厚度可以为10～50nm，具体地，可以为15nm，可以为20nm，可以为25nm，可以为28nm，可以为30nm，可以为35nm，可以为40nm，可以为45nm等。由此，可以进一步提高驱动有源层以及开关有源层的使用性能；并且便于调节最终形成的驱动有源层以及开关有源层中的载流子浓度的差值，进一步提高制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。
根据本公开的具体实施例，参考图4中的(b)，有源层用预置层200可以为层叠设置的第一亚层10A和第二亚层10B，第一亚层10A靠近衬底100设置，形成第一亚层10A的材料包括铟镓锌氧化物，第一亚层10A的厚度为10～50nm，第一亚层10A中的载流子浓度为10 15～10 19cm 2V -1s -1；形成第二亚层10B的材料包括铟锌氧化物，第二亚层10B的厚度为10～50nm，第二亚层10B中的载流子浓度为10 18～10 20cm 2V -1s -1。由此，可以进一步提高驱动有源层以及开关有源层的使用性能；并且便于调节最终形成的驱动有源层以及开关有源层中的载流子浓度的差值，进一步提高制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。
S300：将有源层用预置层图案化，形成驱动有源层以及开关有源层
该步骤中，将前面步骤中制备的有源层用预置层图案化，以形成驱动有源层以及开关有源层，其中，驱动有源层在衬底上的正投影位于驱动晶体管区域中，开关有源层在衬底上的正投影位于开关晶体管区域中，并且，驱动有源层中的载流子浓度，小于开关有源层中的载流子浓度。根据本公开的实施例，参考图2，该方法进一步包括：
S310：通过第一构图工艺，将有源层用预置层刻蚀为第一部分以及第二部分
在该步骤中，通过第一构图工艺，将前面步骤中制备的有源层用预置层刻蚀为第一部分以及第二部分。根据本公开的实施例，参考图3，将有源层用预置层刻蚀为第一部分以及第二部分可以是通过以下步骤实现的：
S10：涂布光刻胶
在该步骤中，在前面步骤中制备的有源层用预置层远离衬底一侧的表面涂布光刻胶。根据本公开的实施例，参考图4中的(c)，在有源层用预置层200远离衬底100一侧的表面涂布光刻胶300。
S20：形成光刻胶层
在该步骤中，利用半色调掩模板对前面步骤中涂布的光刻胶进行曝光和显影，形成光刻胶层。根据本公开的实施例，参考图4中的(d)，半色调掩膜板400可以包括部分透光区域III、完全不透光区域II以及完全透光区域I(图4(d)中，实线代表完全不透光，虚线代表部分透光，未划线区域代表完全透光)。因此，利用该半色调掩模板400对光刻胶300进行曝光和显影之后，参考图4中的(e)，形成的光刻胶层310包括：与部分透光区域III对应的光刻胶部分保留区域，即第一光刻胶层311；以及与完全不透光区域II对应的光刻胶完全保留区域，即第二光刻胶层312；与完全透光区域I对应区域的光刻胶未显影，即未形成光刻胶层，并且，形成的第一光刻胶层311的厚度小于第二光刻胶层312的厚度。
S30：对有源层用预置层进行第一刻蚀处理，形成第一部分以及第二部分
在该步骤中，对前面步骤中设置了光刻胶层的有源层用预置层进行第一刻蚀处理，去 除未被光刻胶层覆盖的有源层用预置层，形成第一部分以及第二部分。根据本公开的实施例，参考图4中的(f)，对有源层用预置层200进行第一刻蚀处理之后，去除了未被光刻胶层310覆盖的有源层用预置层200(被光刻胶层310覆盖区域的有源层用预置层200不会被刻蚀)，形成第一部分211以及第二部分221。其中，第一部分211在衬底100上的正投影位于驱动晶体管区域110中，第一部分211远离衬底100一侧的表面具有第一光刻胶层311；第二部分221在衬底100上的正投影位于开关晶体管区域120中，第二部分221远离衬底100一侧的表面具有第二光刻胶层312。由此，可以简便地将前面步骤中形成的有源层用预置层200刻蚀为第一部分211和第二部分221。具体地，第一刻蚀处理可以为湿法刻蚀处理。
S320：通过第二刻蚀处理，去除第一光刻胶层，暴露出第一部分
在该步骤中，对前面步骤中形成的(如图5(f)即图4(f)所示的)表面覆盖有第一光刻胶层的第一部分，以及表面覆盖有第二光刻胶层的第二部分进行第二刻蚀处理，去除第一部分表面的第一光刻胶层，暴露出第一部分。根据本公开的实施例，由于前面形成的第一光刻胶层的厚度小于第二光刻胶层的厚度，经过第二刻蚀处理后，当第一光刻胶层被完全刻蚀，暴露出第一部分时，第二光刻胶层仍然有部分保留。根据本公开的实施例，经过第二刻蚀处理后的有源层用预置层的结构参考图5中的(g)，第一部分211暴露在外，第二部分221的上方仍覆盖有部分第二光刻胶层312。具体地，第二刻蚀处理可以为干法刻蚀处理。
S330：通过载流子浓度差异化处理，形成驱动有源层以及开关有源层
在该步骤中，对前面步骤中经过第二刻蚀处理后的有源层用预置层进行载流子浓度差异化处理，令第一部分中的载流子浓度小于第二部分中的载流子浓度，以便形成驱动有源层以及开关有源层。由此，通过该方法可以简便地形成驱动有源层以及开关有源层。根据本公开的实施例，经过前面步骤中的第二刻蚀处理之后，第一部分暴露出来，第二部分仍然有部分第二光刻胶层覆盖，因此，该载流子浓度差异化处理可以仅对暴露出的第一部分进行，而不会影响第二部分。通过载流子浓度差异化处理，可以降低第一部分中的载流子浓度，从而使处理后的第一部分中的载流子浓度小于第二部分中的载流子浓度，即使最终制得的驱动有源层中的载流子浓度小于开关有源层中的载流子浓度，提高了驱动晶体管中的阈值电压，使得最终制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性较好，提高使用该阵列基板的显示面板的显示质量。
根据本公开的一些实施例，载流子浓度差异化处理可以进一步包括：通过第三刻蚀处理，令第一部分的厚度小于第二部分的厚度。即可以对第一部分进行第三刻蚀处理，减小第一部分的厚度，从而使第一部分的厚度小于第二部分的厚度，进而第一部分中的载流子 浓度小于第二部分中的载流子浓度。由此，该方法可以简便地令第一部分中的载流子浓度小于第二部分中的载流子浓度，从而提高制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。具体的，第三刻蚀处理可以为湿法刻蚀处理。具体地，可以对第三刻蚀处理的条件(例如刻蚀时间等)进行调节，使得最后形成的第一部分和第二部分的厚度差在一定范围内，该厚度差引起的第一部分和第二部分中的载流子浓度的差异，即第一部分的厚度的降低对驱动晶体管的阈值电压的提升量，可以较好地弥补驱动晶体管因下方设有遮光层而造成的阈值电压的降低，进而使得最终制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性较好，提高使用该阵列基板的显示面板的显示质量。由此，该方法可以令第一部分中的载流子浓度小于第二部分中的载流子浓度，操作较为简便，且提高了制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。
根据本公开的另一些实施例，如前所述，根据本公开实施例的方法中所制备的有源层用预置层包括多个层叠设置的亚层，多个亚层的材料、厚度、载流子浓度等可以不同，例如，相邻两个亚层的材料不同，此时，载流子浓度差异化处理可以进一步包括：通过湿法刻蚀处理，刻蚀除去第一部分的至少一个亚层。具体的，由于相邻两个亚层的材料不同，因此，该裁流子浓度差异化处理可以为湿法刻蚀处理，即刻蚀试剂可以仅对远离衬底设置的一个亚层进行刻蚀，而不会对其下方的其他亚层造成损害，由此，该方法可以简便地令最终形成的第一部分的厚度小于第二部分的厚度。具体地，经过湿法刻蚀处理后的阵列基板的部分结构示意图可以参考图5中的(h)，第一部分211中的第二亚层10B被刻蚀除去，仅保留了第一亚层10A，而第二部分221仍然包括层叠设置的第一部分10A以及第二部分10B。具体地，如前所述，在前面步骤中制备有源层用预置层时，就可以预先对该被湿法刻蚀去除的亚层(即第二亚层10B)的厚度进行设计，使该亚层(即第二亚层10B)被刻蚀去除后的第一部分221的载流子浓度的降低(即阈值电压的提升)，可以刚好弥补驱动晶体管因下方设有遮光层而造成的阈值电压的降低，进而使得最终制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性较好，提高使用该阵列基板的显示面板的显示质量。也即是说，该方法操作简便，且可以较好地对第一部分和第二部分的厚度差进行控制，以便更好地提高开关晶体管和驱动晶体管的阈值电压的一致性。
根据本公开的又一些实施例，载流子浓度差异化处理还可以进一步包括：在氧化性气体氛围中，对暴露的第一部分进行退火处理，或者利用氧化性气体所激发的等离子体对第一部分进行处理，以便令第一部分中的载流子浓度小于第二部分中的载流子浓度。具体的，该方法可以和前面所述的减小第一部分的厚度的方法结合使用，也可单独使用，即该方法中可以无需对第一部分进行刻蚀处理，即无需调节第一部分的厚度，而仅对第一部分中掺 杂的载流子浓度进行调节。由此，该方法可以简便地减少第一部分中掺杂的载流子的浓度，令第一部分中的载流子浓度小于第二部分中的载流子浓度，从而提高制备的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性，提高使用该阵列基板的显示面板的显示质量。
根据本公开的实施例，经过载流子浓度差异化处理之后，该方法可以进一步包括：去除剩余的光刻胶层。由此，可以暴露出第一部分和第二部分，参考图5中的(i)，形成了驱动有源层210以及开关有源层220，以便进行后续制备，例如形成源漏极、栅极等薄膜晶体管结构。由此，可以简便地制得驱动有源层和开关有源层，并且制得的阵列基板中开关晶体管和驱动晶体管的阈值电压的一致性较好，提高使用该阵列基板的显示面板的显示质量。
根据本公开的实施例，在前面所述的提供衬底之后，形成有源层用预置层之前，参考图6以及图7，该方法可以进一步包括：
S110：形成遮光层
在该步骤中，在衬底的驱动晶体管区域的一侧形成前面遮光层，该遮光层可以阻挡外界光线照射后续步骤中形成的驱动晶体管的有源层用预置层，避免光照引起的驱动晶体管特性的劣化。具体地，参考图7，遮光层500可以是通过下述方法形成的：先在衬底100的一侧沉积一整层金属薄膜510(参考图7中的(a))，然后对该金属薄膜510进行图案化(例如通过设置掩膜等方式进行图案化)，形成遮光层500(参考图7中的(b))，形成的遮光层500在衬底100上的正投影位于驱动晶体管区域110中。
S120：形成缓冲层
在该步骤中，在前面步骤中形成的遮光层远离衬底的一侧形成缓冲层。具体地，可以在遮光层远离衬底的一侧沉积一层绝缘薄膜，例如沉积氧化硅、氮化硅等材料，以便形成缓冲层。具体的，可以采用离子体增强化学的气相沉积法(PECVD)形成缓冲层。具体的，参考图7中的(c)，缓冲层600形成在遮光层500远离衬底100的一侧。
在本公开的另一方面，本公开提出了一种阵列基板。根据本公开的实施例，该阵列基板是由前面所述的方法制备的。由此，该阵列基板具有前面所述的方法所制备的阵列基板所具有的全部特征以及优点，在此不再赘述。总的来说，该阵列基板的阈值电压的均匀性较好，可以提高使用该阵列基板的显示面板的显示质量。
在本公开的又一方面，本公开提出了一种阵列基板。根据本公开的实施例，该阵列基板可以由前面所述的方法制备。在这种情况下，该阵列基板也具有前面所述的方法所制备的阵列基板所具有的全部特征以及优点，在此不再赘述。根据本公开的实施例，参考图8，该阵列基板1000包括：衬底100以及位于衬底100一侧的驱动晶体管以及开关晶体管(图中未示出)，其中，衬底100上具有驱动晶体管区域110以及开关晶体管区域120，驱动晶 体管位于驱动晶体管区域110的正上方，开关晶体管位于开关晶体管区域120的正上方，驱动晶体管的有源层用预置层即图中示出的驱动有源层210，开关晶体管的有源层用预置层即图中示出的开关有源层220。其中，驱动有源层210中的载流子浓度，小于开关有源层220中的载流子浓度，并且，驱动有源层210以及开关有源层220的至少之一包括层叠设置的多个亚层10。由此，该阵列基板的使用性能良好，且该阵列基板的阈值电压的均匀性较好，可以提高使用该阵列基板的显示面板的显示质量。具体的，驱动有源层210以及开关有源层220可以均包括至少两个亚层10，也可以参考图8中所示出的，驱动有源层210包括一个亚层10A，开关有源层220包括两个层叠设置的亚层10A和10B。
根据本公开的一些实施例，驱动有源层210的厚度小于开关有源层220的厚度。
根据本公开的另一些实施例，驱动有源层210中的亚层10的数目小于开关有源层220中的亚层的数目，例如参考图8所示出的，驱动有源层210可以包括一个亚层10A，开关有源层220可以包括两个层叠设置的亚层10A和10B，由此，可以简便地使驱动有源层中的载流子浓度小于开关有源层中的载流子浓度。
根据本公开的又一些实施例，驱动有源层中的掺杂的载流子的浓度小于开关有源层中掺杂的载流子的浓度。由此，可以简便地令驱动有源层中的载流子浓度小于开关有源层中的裁流子浓度。该情况下，驱动有源层210的厚度和开关有源层220的厚度可以相同，也可以不相同。也即是说，即使驱动有源层210的厚度和开关有源层220的厚度相同，也可以通过掺杂工艺等，令驱动有源层中的掺杂的载流子浓度小于开关有源层中掺杂的所述载流子浓度。
在本公开的又一方面，本公开提出了一种显示面板。根据本公开的实施例，该显示面板包括前面所述阵列基板。由此，该显示面板具有前面所述的阵列基板所具有的全部特征以及优点，在此不再赘述。总的来说，该显示面板的显示质量较好。
在本公开的又一方面，本公开提出了一种显示装置。根据本公开的实施例，该显示装置包括：壳体；以及前面所述的显示面板。由此，该显示装置具有前面所述的显示面板所具有的全部特征以及优点，在此不再赘述。总的来说，该显示装置的显示质量较好。
在本说明书的描述中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开而不是要求本公开必须以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此 外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (17)

  1. 一种制作阵列基板的方法，其特征在于，包括：
    提供衬底，所述衬底上具有驱动晶体管区域以及开关晶体管区域；
    在所述衬底的一侧形成有源层用预置层；
    将所述有源层用预置层图案化，以形成驱动有源层以及开关有源层，其中，所述驱动有源层在所述衬底上的正投影位于所述驱动晶体管区域中，所述开关有源层在所述衬底上的正投影位于所述开关晶体管区域中，并且，所述驱动有源层中的载流子浓度小于所述开关有源层中的载流子浓度。
  2. 根据权利要求1所述的方法，其特征在于，所述有源层用预置层中包括两个其中载流子浓度不同的亚层，并且所述驱动有源层远离所述衬底的表面和所述开关有源层远离所述衬底的表面分别属于所述两个亚层。
  3. 根据权利要求2所述的方法，其特征在于，所述两个亚层中靠近所述衬底的所述亚层中的载流子浓度小于远离所述衬底的所述亚层中的载流子浓度。
  4. 根据权利要求2所述的方法，其特征在于，形成的所述有源层用预置层中，所述两个亚层是相邻的且材料不相同。
  5. 根据权利要求2所述的方法，其特征在于，所述两个亚层为第一亚层和第二亚层，所述第一亚层比所述第二亚层更靠近所述衬底，
    形成所述第一亚层的材料包括铟镓锌氧化物，所述第一亚层的厚度为10～50nm，所述第一亚层中的载流子浓度为10 15～10 19cm 2V -1s -1；
    形成所述第二亚层的材料包括铟锌氧化物，所述第二亚层的厚度为10～50nm，所述第二亚层中的载流子浓度为10 18～10 20cm 2V -1s -1。
  6. 根据权利要求1所述的方法，其特征在于，所述将所述有源层用预置层图案化包括以下步骤：
    通过使用光刻胶的构图工艺，将所述有源层用预置层刻蚀为第一部分以及第二部分，其中所述第一部分在所述衬底上的正投影位于所述驱动晶体管区域中，所述第一部分远离所述衬底一侧的表面保留第一光刻胶层；所述第二部分在所述衬底上的正投影位于所述开关晶体管区域中，所述第二部分远离所述衬底一侧的表面保留第二光刻胶层；并且所述第二光刻胶层的厚度大于所述第一光刻胶层的厚度；
    通过刻蚀，去除所述第一光刻胶层以暴露出所述第一部分，并且在第二部分远离所述衬底一侧的表面保留剩余厚度的第二光刻胶层；
    通过载流子浓度差异化处理，使所述第一部分中的载流子浓度小于所述第二部分中的 载流子浓度；以及
    去除所述剩余厚度的第二光刻胶层，以使所述第一部分形成所述驱动有源层，使所述第二部分形成所述开关有源层。
  7. 根据权利要求6所述的方法，其特征在于，所述载流子浓度差异化处理包括：
    通过刻蚀使所述第一部分的厚度小于所述第二部分的厚度。
  8. 根据权利要求7所述的方法，其特征在于，所述有源层用预置层中包括两个其中载流子浓度不同的亚层，所述载流子浓度差异化处理进一步包括：
    通过湿法刻蚀除去所述第一部分中所述两个亚层中远离所述衬底的亚层。
  9. 根据权利要求6所述的方法，其特征在于，所述载流子浓度差异化处理包括：
    在氧化性气体氛围中，对所述第一部分进行退火处理，或者利用氧化性气体所激发的等离子体对所述第一部分进行处理，以使所述第一部分中的载流子浓度小于所述第二部分中的载流子浓度。
  10. 根据权利要求6所述的方法，其特征在于，
    所述将所述有源层用预置层刻蚀为第一部分以及第二部分的步骤包括：
    在所述有源层用预置层远离所述衬底一侧的表面涂布光刻胶；
    利用半色调掩模板对所述光刻胶进行曝光和显影，形成光刻胶层，所述光刻胶层包括：光刻胶部分保留的所述第一光刻胶层以及光刻胶完全保留的所述第二光刻胶层；
    对所述有源层用预置层进行刻蚀处理，去除未被所述光刻胶层覆盖的所述有源层用预置层，形成所述第一部分以及所述第二部分；并且
    所述去除所述第一光刻胶层以暴露出所述第一部分的步骤包括干法刻蚀。
  11. 一种阵列基板，其特征在于，所述阵列基板是由权利要求1-10任一项所述的方法制备的。
  12. 一种阵列基板，其特征在于，包括：
    衬底；
    位于所述衬底上的驱动晶体管以及开关晶体管，所述驱动晶体管的驱动有源层中的载流子浓度小于所述开关晶体管的开关有源层中的载流子浓度。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述驱动有源层的厚度小于所述开关有源层的厚度；或者
    所述驱动有源层以及所述开关有源层的至少之一包括层叠设置的多个亚层，其中所述驱动有源层中的亚层的数目小于所述开关有源层中的亚层的数目；或者
    所述驱动有源层中掺杂的载流子的浓度小于所述开关有源层中掺杂的所述载流子的浓度。
  14. 根据权利要求12所述的阵列基板，其特征在于，
    所述开关有源层包括第一亚层和第二亚层，其中所述第一亚层比所述第二亚层更靠近所述衬底，并且所述开关有源层远离所述衬底的表面属于所述第二亚层，并且
    所述驱动有源层包括与所述第一亚层同层形成的第三亚层，并且所述驱动有源层远离所述衬底的表面属于所述第三亚层。
  15. 根据权利要求14所述的阵列基板，其特征在于，
    其中形成所述第一亚层/第三亚层的材料包括铟镓锌氧化物，所述第一亚层/第三亚层的厚度为10～50nm，所述第一亚层/第三亚层中的载流子浓度为10 15～10 19cm 2V -1s -1；形成所述第二亚层的材料包括铟锌氧化物，所述第二亚层的厚度为10～50nm，所述第二亚层中的载流子浓度为10 18～10 20cm 2V -1s -1。
  16. 一种显示面板，其特征在于，包括：权利要求11-15任一项所述阵列基板。
  17. 一种显示装置，其特征在于，包括：壳体；以及权利要求16所述的显示面板。
PCT/CN2020/085107 2019-06-06 2020-04-16 阵列基板及其制备方法、显示面板、显示装置 WO2020244313A1 (zh)

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