WO2015113368A1 - 薄膜晶体管的制作方法及薄膜晶体管 - Google Patents

薄膜晶体管的制作方法及薄膜晶体管 Download PDF

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WO2015113368A1
WO2015113368A1 PCT/CN2014/080813 CN2014080813W WO2015113368A1 WO 2015113368 A1 WO2015113368 A1 WO 2015113368A1 CN 2014080813 W CN2014080813 W CN 2014080813W WO 2015113368 A1 WO2015113368 A1 WO 2015113368A1
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layer
photoresist
drain
source
photoresist layer
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PCT/CN2014/080813
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English (en)
French (fr)
Inventor
侯学成
吴涛
郭建
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/425,994 priority Critical patent/US9553170B2/en
Publication of WO2015113368A1 publication Critical patent/WO2015113368A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a method of fabricating a thin film transistor and a thin film transistor. Background technique
  • TFTs Thin Film Transistors
  • a thin film transistor includes at least a gate, a source and a drain (Source and Drain, or a source drain SD), and a channel layer (also referred to as an active layer).
  • a semiconductor layer for forming an active layer pattern and a conductive layer for patterning the source and drain patterns are first deposited, and then a gray tone mask (GTM) is used.
  • GTM gray tone mask
  • HTM halftone mask
  • a method for preparing a TFT includes:
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, which is capable of producing a thin film transistor having a high yield.
  • a method of fabricating a thin film transistor includes: forming a gate pattern and a gate insulating layer on a substrate, and forming a source, a drain, and an active layer pattern.
  • Forming source and drain The pole and active layer patterns include: sequentially forming a semiconductor layer covering the entire substrate and a conductive layer on the substrate; respectively forming a first photoresist layer on a region of the conductive layer where a source is to be formed and a region where a drain is to be formed Forming a second photoresist layer at least on the conductive layer to form a gap between the source and the drain; forming the first photoresist layer, the second photoresist layer, the semiconductor layer, and the conductive layer
  • the substrate of the layer is etched to form a pattern of the active layer, the source and the drain.
  • At least one embodiment of the present invention also provides a thin film transistor which is fabricated by the method of fabricating the above thin film transistor.
  • FIG. 1 is a schematic flowchart of fabricating a TFT according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a TFT structure including a gate and a gate insulating layer according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a TFT structure including a semiconductor layer for forming an active layer and a conductive layer for forming a source and a drain according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of a TFT including a first photoresist layer according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a TFT including a second photoresist layer according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a process of forming a source, a drain, and an active layer
  • FIG. 7 is a schematic structural diagram of a TFT including an active layer according to an embodiment of the present invention
  • FIG. 8 is a schematic structural diagram of a TFT for removing a second photoresist layer according to an embodiment of the present invention
  • FIG. 9 is a schematic structural diagram of a TFT including a source and a drain according to an embodiment of the present invention
  • the distance between the source and the drain is getting smaller and smaller.
  • the source and the drain are easily short-circuited due to incomplete etching (ie, formation).
  • GT Bridge is bad).
  • the active layer may also be damaged by over-etching, causing the active layer to be broken (i.e., forming a channel open defect).
  • the photoresist layer with different thicknesses of different regions is formed by the gray tone mask or the halftone mask. Due to the uniformity of the glue and the uniformity of the exposure, the incompletely exposed regions (ie, the regions corresponding to the channels) correspond to the produced light.
  • the thickness uniformity of the engraved layer is difficult to control accurately, and some areas are thinner and some areas are thicker.
  • the subsequent etching is performed under the condition of equal thickness, which results in incomplete etching of the photoresist in a thick region, poor MOSFET termination, and excessive etching of the photoresist in a thin region.
  • the channel open is poor, which seriously affects the working performance of the TFT or causes the TFT to be defective, so that the yield of the mass-produced TFT is lowered.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor and a thin film transistor, which are respectively formed on a film layer for forming a source, a drain, and an active layer pattern by two patterning processes.
  • the first photoresist layer ensures that the photoresist covers only the region where the source and the drain are to be formed, and exposes a region corresponding to the gap between the source and the drain to be formed; the second layer of photoresist ensures photolithography
  • the glue covers the area corresponding to the gap between the source and the drain to be formed.
  • the thickness of the second layer of photoresist disposed in the region corresponding to the gap between the source and the drain is uniform.
  • the active layer of the TFT is located under the source and the drain, and the portion of the active layer corresponding to the gap between the source and the drain is the channel region of the TFT when the TFT is turned on, and the channel is The length is approximately equal to the width of the gap between the source and the drain, and the width of the channel is approximately equal to the length of the gap between the source and the drain.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming a gate pattern and a gate insulating layer on a substrate, and forming source, drain, and active layer patterns.
  • the material of the active layer in the TFT provided by the present invention is not limited, and may be, for example, an amorphous silicon layer, a polysilicon layer or a metal oxide semiconductor layer; the structure of the TFT is not limited and may be a bottom gate type It can also be a top grid type.
  • the process of fabricating the source, drain and active layer patterns of one embodiment of the present invention will be specifically described below.
  • fabricating the source, drain, and active layer patterns includes the following steps:
  • a second photoresist layer of a set thickness at least on a region of the conductive layer corresponding to a gap between a source and a drain to be formed
  • forming the second photoresist layer further includes forming a second photoresist layer over the first photoresist layer.
  • the patterning process referred to in at least one embodiment of the present invention includes at least a step of photoresist coating or dripping, exposure, development, photolithography etching, and the like.
  • Step 1 Make the gate and gate insulation.
  • a conductive layer is deposited on the substrate 1, and a gate 2 pattern is formed by a patterning process; in this step, a gate pattern is formed using the first mask; the material of the gate is not limited.
  • one or more insulating layers are formed as the gate insulating layer 3 on the substrate 1 on which the gate electrode 2 is formed.
  • the method of forming the gate insulating layer is not limited, and the material of the gate insulating layer is not limited.
  • a gate pattern and a gate insulating layer on the gate pattern are formed on the substrate before forming the source, drain and active layer patterns;
  • a gate insulating layer is formed on the substrate after forming the source, drain and active layer patterns, and a gate pattern over the gate insulating layer.
  • Step 2 Make the source, drain and active layer patterns.
  • Step S11 sequentially forming a semiconductor layer and a conductive layer covering the entire substrate on the substrate.
  • a semiconductor layer 10 covering the entire substrate is deposited by a method such as thermal evaporation or the like; the semiconductor layer 10 may be a film layer of amorphous silicon, polysilicon or a metal oxide semiconductor; and the semiconductor layer 10 is used to form an active layer pattern.
  • a conductive layer 11 covering the entire substrate may be deposited by chemical vapor deposition or thermal evaporation, and the conductive layer 11 is used to form source and drain patterns.
  • the resulting structure is as shown in Fig. 3.
  • the TFT includes a semiconductor layer 10 on the gate insulating layer 3 and a conductive layer 11 on the semiconductor layer 10.
  • Step S12 forming a first photoresist layer of a predetermined thickness on a region of the conductive layer where a source is to be formed and a region where a drain is to be formed, respectively.
  • a photoresist layer of a set thickness is formed, at which time the photoresist layer covers the entire source for forming the source and the drain.
  • a conductive layer exposing and developing the photoresist layer through a second mask, leaving the photoresist directly above the source and the drain to be formed, and removing the photoresist at the remaining position, the source to be formed
  • the upper photoresist acts as a first photoresist layer together with the photoresist over the drain to be formed.
  • a first photoresist layer 4 is disposed directly above the source and drain to be formed.
  • a photoresist is used as a positive photoresist as an example.
  • the region outside the corresponding regions of the source and the drain is completely exposed through the second mask, and the photoresist in the exposed region is completely removed by, for example, a developer to effect development.
  • the photoresist corresponding to the gap between the source and the drain is completely exposed, and is completely developed during development to expose the conductive layer 11.
  • the photoresist can be formed on the conductive layer 11 by a coating method or a drip-rotation method.
  • the specific implementation method can be determined according to actual needs, and is not limited herein.
  • the thickness of the first photoresist layer 4 is not limited.
  • the thickness of the first photoresist layer 4 is about 1.5 to 2.5 ⁇ m (corresponding to 15000 25000 A).
  • the first photoresist layer 4 shown in Fig. 4 is a hydrophobic photoresist layer. Since the conductive layer 11 for forming the source and the drain over the semiconductor layer 10 is a hydrophilic film layer, and the first photoresist layer 4 is a hydrophobic photoresist layer, subsequent stripping of the photoresist (also It is easier to remove the photoresist completely during the process.
  • the first photoresist layer located above the source to be formed and located in the shape to be formed The distance L between the first photoresist layers above the formed drain is 2.0 to 4.5 ⁇ m, which is equal to the gap width between the source and the drain in the thin film transistor formed later.
  • the distance L is equal to the length of the channel on the active layer.
  • Step S13 forming a second photoresist layer of a predetermined thickness at least between the region on the conductive layer where the source is to be formed and the first photoresist layer on the region where the drain is to be formed.
  • a photoresist layer having a thickness h is formed over the first photoresist layer.
  • the photoresist layer is exposed and developed by a third mask to retain at least a photoresist corresponding to a gap between the source and the drain to be formed, and the remaining region of the photoresist is removed. This step ensures that the first photoresist layer is not removed.
  • the photoresist layer is exposed and developed through a third mask, and the photoresist corresponding to the gap between the source and the drain to be formed and the photoresist directly above the first photoresist layer are retained.
  • the remaining photoresist layer is a second photoresist layer. Whether or not to retain the photoresist directly above the first photoresist layer depends on specific process conditions or other factors.
  • the second photoresist layer 5 is disposed above the first photoresist layer 4.
  • the thickness of the second photoresist layer 5 is h, due to the conductive layer 11 under the second photoresist layer 5.
  • the surface is flat, so the thickness of the second photoresist layer 5 is uniform.
  • the step of forming the photoresist covering the entire substrate in the step S13 is similar to the process of forming the photoresist covering the entire substrate in the step S12, and may be performed by a method such as coating or drip rotation, and the specific implementation may be determined according to actual needs, Make restrictions.
  • the thickness of the second photoresist layer 5 is about 0.3 to 0.8 ⁇ m (corresponding to 3000-8000 ⁇ ).
  • the thickness of the second photoresist layer 5 is about 0.5 ⁇ m (corresponding to 5000 A).
  • the second photoresist layer is made of a hydrophobic photoresist.
  • the material of the second photoresist layer may be the same as or different from the material of the first photoresist layer.
  • the material of the second photoresist layer satisfies, for example, the following conditions: the adhesion of the second photoresist layer to the first photoresist layer is greater than the second photoresist layer and the conductive layer for forming the source and the drain The adhesion between.
  • the adhesion of the second photoresist layer to the first photoresist layer is greater than that of the first photoresist layer.
  • Two photoresist The adhesion between the layer and the conductive layer, the difference in adhesion between the two contributes to the execution of the subsequent steps.
  • Step S14 etching a substrate on which the first photoresist layer, the second photoresist layer, the semiconductor layer and the conductive layer are formed to form an active layer, a source and a drain.
  • an etching process is performed on the conductive layer 11 on which the source and the drain are to be formed. Referring to FIG. 6, the area covered by the first photoresist layer 4 and the second photoresist layer 5 on the conductive layer 11 is left exposed. The first photoresist layer 4 and the second photoresist layer 5 do not cover the semiconductor layer 10 of the region.
  • the etching process in this step uses, for example, wet etching.
  • the semiconductor layer 10 shown in FIG. 6 is subjected to an etching process to remove the semiconductor layer 10 of the uncovered region of the first photoresist layer 4 and the second photoresist layer 5, and the first photoresist layer 4 and the first photoresist layer are retained.
  • the second photoresist layer 5 covers the semiconductor layer 10 of the region.
  • the TFT structure to be formed is as shown in FIG. 7, and the semiconductor layer covering the first photoresist layer 4 and the second photoresist layer 5 serves as an active layer. 6 graphics.
  • the etching process in this step uses, for example, dry etching.
  • the second photoresist layer 5 is subjected to an ashing process according to the set thickness h of the second photoresist 5 shown in FIG. 7, and the second photoresist layer 5 is completely removed to expose the second photolithography layer.
  • the portion of the conductive layer 11 under the glue layer 5, that is, the portion of the gap between the source and the drain to be formed on the conductive layer 11 is exposed, see FIG.
  • the photoresist can be accurately ashed according to the thickness h of the ash photoresist, and excessive gray is not formed.
  • the photoresist or the ashing of the photoresist is insufficient, which causes a problem of defective TFT GT Bridge or poor channel open in the prepared TFT.
  • Ashing is a type of dry etching.
  • the second photoresist layer 5 is not limited to being processed by the ashing method.
  • the second photoresist can be etched by any method capable of accurately removing the second photoresist layer without excessive etching or etching. .
  • the conductive layer 11 is etched to remove the gap portion between the source and the drain to be formed on the conductive layer 11, and the mutually insulated source 7 and drain 8 patterns shown in Fig. 9 are formed.
  • the etching process in this step is, for example, dry etching.
  • the method further includes: stripping the first photoresist layer on the source and drain.
  • the first photoresist layer (RP strip ) is removed by dry etching, and the TFT to be formed is shown in FIG.
  • the TFT includes the gate electrode 2, the upper insulating layer 3, the active layer 6, the source electrode 7 and the drain electrode.
  • the above process is a detailed process for fabricating a bottom gate type TFT.
  • the process of fabricating the top gate type TFT is similar to the above process of fabricating the bottom gate type TFT, except that the active layer, the source and drain patterns are formed first, and the gate and gate insulating layer patterns are formed. Narration.
  • the method further includes fabricating an ohmic contact layer between the active layer and the source and the drain to reduce contact resistance between the semiconductor layer and the source and the drain, thereby improving The performance of the TFT.
  • a nitrogen-doped amorphous silicon layer may be formed between the active layer and the source and the drain (made) NVSi).
  • the fabrication method of the TFT provided by at least one embodiment of the present invention can replace any process including implementing a photoresist of different thickness by a halftone or gray tone mask, which is not only suitable for forming a source, a drain and an active layer, but also applicable.
  • the process of forming a large area of different thickness photoresist through a halftone or gray tone mask is not only suitable for forming a source, a drain and an active layer, but also applicable.
  • At least one embodiment of the present invention also provides a thin film transistor fabricated by the method of fabricating the thin film transistor provided by the above embodiment of the present invention.
  • the material type of the active layer in the thin film transistor is not limited.
  • the structure of the thin film transistor includes at least a gate electrode, a gate insulating layer, an active layer, a source and a drain, and may further include an etch barrier layer, an ohmic contact layer, a buffer layer in contact with the substrate, and passivation covering the entire TFT. Layers, etc. Not here - detailed.
  • the thin film transistor of the embodiment of the invention is used, for example, for a switching element or a driving element on an array substrate in a liquid crystal display panel or an organic light emitting diode (OLED) display panel, for example, for performing on/off of a sub-pixel unit in a liquid crystal panel.
  • Control in the OLED display panel for controlling or driving sub-pixel units.

Abstract

一种薄膜晶体管的制作方法及薄膜晶体管。在该制作方法中，形成源极（7）、漏极（8）和有源层（6）图形包括：在基板上依次形成覆盖整个基板的半导体层（10）和导电层（11）；分别在所述导电层（11）上待形成源极的区域和待形成漏极的区域形成第一光刻胶层（4）；至少在所述导电层（11）上待形成源极和漏极之间的间隙形成第二光刻胶层（5）；对形成有所述第一光刻胶层（4）、第二光刻胶层（5）、半导体层（10）和导电层（11）的基板进行刻蚀工艺形成有源层（6）、源极（7）和漏极（8）的图形。

Description

薄膜晶体管的制作方法及薄膜晶体管 技术领域
本发明的实施例涉及一种薄膜晶体管的制作方法及薄膜晶体管。 背景技术
薄膜晶体管（ Thin Film Transistor, TFT )作为开关器件在显示技术领域 发挥着重要的作用。
一般地，薄膜晶体管至少包括栅极（ Gate )、源极和漏极（ Source和 Drain, 或源漏极 SD ) 以及沟道层 ( Channel, 也称有源层）等。 近年来， 为了简化 工艺流程或减少掩模板的使用数量， 通过先沉积制作有源层图形的半导体层 和制作源极和漏极图形的导电层， 然后使用灰色调掩模板 ( gray tone mask, GTM )或半色调掩模板（halftone mask, HTM )技术形成不同厚度的光刻胶 图形， 最后经刻蚀工艺， 来制作出有源层、 源极和漏极图形等。
以底栅型 TFT为例， 一种制备 TFT的方法包括：
( 1 )在基板上制作栅极和栅极绝缘层；
( 2 )在形成有所述栅极和栅极绝缘层的基板上依次沉积半导体层和导电 层；
( 3 )通过灰色调掩模板或半色调掩模板在所述导电层上形成光刻胶图 形， 所述灰色调或半色调掩模板用以实现不同厚度的光刻胶层， 使得导电层 待形成源漏极的区域与源极和漏极之间的区域的光刻胶的厚度不等；
( 4 )先后对所述导电层和半导体层进行刻蚀工艺， 形成有源层、 源极和 漏极图形。 发明内容
本发明的至少一实施例提供一种薄膜晶体管的制作方法， 釆用该方法能 够生产良品率较高的薄膜晶体管。
本发明至少一实施例提供的薄膜晶体管的制作方法包括： 在基板上形成 栅极图形和栅极绝缘层， 以及形成源极、 漏极和有源层图形。 形成源极、 漏 极和有源层图形包括:在基板上依次形成覆盖整个基板的半导体层和导电层； 分别在所述导电层上待形成源极的区域和待形成漏极的区域形成第一光刻胶 层； 至少在所述导电层上待形成源极和漏极之间的间隙形成第二光刻胶层； 对形成有所述第一光刻胶层、 第二光刻胶层、 半导体层和导电层的基板进行 刻蚀工艺形成有源层、 源极和漏极的图形。
本发明的至少一实施例还提供一种薄膜晶体管， 釆用上述薄膜晶体管的 制作方法制作而成。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1本发明实施例提供的制作 TFT的流程示意图；
图 2为本发明实施例提供的包括有栅极和栅极绝缘层的 TFT结构示意 图；
图 3为本发明实施例提供的包括用于形成有源层的半导体层和用于形成 源极和漏极的导电层的 TFT结构示意图；
图 4为本发明实施例提供的包括第一光刻胶层的 TFT结构示意图； 图 5为本发明实施例提供的包括第二光刻胶层的 TFT结构示意图； 图 6为本发明实施例提供的形成源极、漏极和有源层过程的结构示意图； 图 7为本发明实施例提供的包括有源层的 TFT结构示意图；
图 8为本发明实施例提供的去除第二光刻胶层的 TFT结构示意图； 图 9为本发明实施例提供的包括源极和漏极的 TFT结构示意图； 图 10为本发明实施例提供的去除第一光刻胶层的 TFT结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
近年来， 随着图形线宽不断减小， 源极和漏极之间的距离越来越小， 一 般在几微米量级， 源极和漏极很容易由于刻蚀不完全而短路（即形成 GT Bridge不良） 。 此外， 有源层也可能因为过度刻蚀而被损坏， 造成有源层断 开（即形成 channel open不良） 。 通过灰色调掩模板或半色调掩模板形成不 同区域厚度不同的光刻胶层， 由于涂胶均一性和曝光均一性的限制， 不完全 曝光区域（即沟道对应的区域）对应制作出来的光刻胶层的厚度均一性难以 准确控制， 有些区域较薄而有些区域较厚。 后续刻蚀是按照等厚度的条件进 行的，这就导致较厚区域的光刻胶刻蚀不完全，产生源漏极短路（GT Bridge ) 不良， 较薄区域的光刻胶刻蚀过度造成 TFT通电时沟道开路（ channel open ) 不良，严重影响 TFT的工作性能，或造成 TFT的不良，使得批量生产的 TFT 的良品率下降。
本发明至少一个实施例提供一种薄膜晶体管的制作方法及薄膜晶体管， 通过两次构图工艺分别在用以形成源极、 漏极和有源层图形的膜层上制作两 层光刻胶层。 第一层光刻胶层保证光刻胶仅覆盖待形成的源极和漏极所在区 域， 露出待形成的源极和漏极之间的间隙对应的区域； 第二层光刻胶保证光 刻胶覆盖待形成的源极和漏极之间的间隙对应的区域。 源极和漏极之间的间 隙对应的区域设置的第二层光刻胶厚度均一。 后续刻蚀按照等厚度的条件进 行时， 由于第二层光刻胶厚度均一， 不会产生源漏极短路（GT Bridge )不良， 或者产生 TFT通电时沟道开路 ( channel open )不良的问题， 使得批量生产 的 TFT的良品率得以提高。
需要说明的是， TFT的有源层位于源极和漏极的下方， 源极和漏极之间 的间隙对应的有源层的部分在 TFT导通时为 TFT的沟道区域， 沟道的长度 约等于源极和漏极之间的间隙的宽度， 沟道的宽度约等于源极和漏极之间的 间隙的长度。
本发明的至少一实施例提供薄膜晶体管的制作方法， 包括： 在基板上形 成栅极图形和栅极绝缘层， 以及形成源极、 漏极和有源层图形。
需要说明的是， 本发明提供的 TFT中的有源层的材料不限， 例如可以为 非晶硅层、 多晶硅层或金属氧化物半导体层； 所述 TFT的结构不限， 可以为 底栅型也可以为顶栅型。 以下将具体说明本发明的一个实施例的制作源极、 漏极和有源层图形的 过程。
参见图 1 , 制作源极、 漏极和有源层图形包括以下步骤：
S 11、 在基板上依次形成覆盖整个基板的半导体层和导电层；
S12、 分别在所述导电层上待形成源极的区域和待形成漏极的区域形成 设定厚度的第一光刻胶层；
513、 至少在所述导电层上待形成源极和漏极之间的间隙对应的区域形 成设定厚度的第二光刻胶层；
514、 对形成有所述第一光刻胶层、 第二光刻胶层、 半导体层和导电层 的基板进行刻蚀工艺形成有源层、 源极和漏极图形。
在本发明的至少一实施例中， 在形成所述第二光刻胶层的同时还包括， 形成位于所述第一光刻胶层上方的第二光刻胶层。
本发明的至少一实施例提到的构图工艺至少包括光刻胶涂覆或滴注、 曝 光、 显影、 光刻刻蚀等步骤。
以下将以底栅型 TFT为例，具体说明本发明至少一实施例提供的薄膜晶 体管的制作方法。
步骤一： 制作栅极和栅极绝缘层。
参见图 2, 在基板 1上沉积一层导电层， 通过构图工艺形成栅极 2图形； 该步骤釆用第一掩模板制作栅极图形； 栅极的材料不限。
参见图 2, 在形成有栅极 2的基板 1上形成一层或多层绝缘层作为栅极 绝缘层 3。 形成栅极绝缘层的方法不限， 栅极绝缘层的材料不限。
针对底栅型 TFT, 在形成所述源极、 漏极和有源层图形之前， 在所述基 板上形成栅极图形以及位于所述栅极图形上的栅极绝缘层；
针对顶栅型 TFT, 在形成所述源极、 漏极和有源层图形之后在所述基板 上形成栅极绝缘层， 以及位于栅极绝缘层之上的栅极图形。
步骤二： 制作源极、 漏极和有源层图形。
以下将结合步骤一的描述具体说明图 1所示的制作源极、 漏极和有源层 图形的过程。
步骤 S11 : 在基板上依次形成覆盖整个基板的半导体层和导电层。
在所述形成有所述栅极和栅极绝缘层的基板上， 可以釆用化学气相沉积 法或热蒸镀等方法沉积一层覆盖整个基板的半导体层 10; 该半导体层 10可 以为非晶硅、多晶硅或金属氧化物半导体等膜层；该半导体层 10用于制作有 源层图形。
在形成有所述半导体层 10的基板上，可以釆用化学气相沉积法或热蒸镀 等方法沉积一层覆盖整个基板的导电层 11 , 该导电层 11用于制作源极和漏 极图形。
所形成的结构如图 3所示， TFT包括位于栅极绝缘层 3上的半导体层 10 和位于半导体层 10上的导电层 11。
步骤 S12: 分别在所述导电层上待形成源极的区域和待形成漏极的区域 形成设定厚度的第一光刻胶层。
在形成有所述半导体层 10和导电层 11的基板 1上， 形成一层设定厚度 的光刻胶（Photoresist, PR )层， 此时光刻胶层覆盖整个用于形成源极和漏 极的导电层； 通过第二掩模板对所述光刻胶层进行曝光和显影， 保留待形成 的源极和漏极正上方的光刻胶， 其余位置的光刻胶完全去除， 待形成的源极 上方的光刻胶和待形成的漏极上方的光刻胶一起作为第一光刻胶层。 如图 4 所示， 包括位于待形成的源极和漏极正上方的第一光刻胶层 4。 下面， 以光刻胶为正性光刻胶为例说明。 通过第二掩模板对所述源极和 漏极对应区域之外的区域完全曝光， 曝光区域的光刻胶被例如显影液完全去 除而实现显影。 当然， 源极和漏极之间的间隙对应区域的光刻胶完全曝光， 显影时完全被显影掉， 露出导电层 11。
在导电层 11上形成光刻胶可以通过涂覆或滴注旋转法等，具体实现方法 可以根据实际需求而定， 这里不做限制。
该第一光刻胶层 4 的厚度不限， 例如， 第一光刻胶层 4 的厚度约为 1.5~2.5μπι (对应 15000 25000A ) 。
例如， 图 4所示的第一光刻胶层 4为疏水性的光刻胶层。 由于半导体层 10上方用于形成源极和漏极的导电层 11为亲水性膜层， 第一光刻胶层 4为 疏水性的光刻胶层时， 后续在光刻胶的剥离 （也称去除）工艺过程中光刻胶 完全去除较容易。
例如， 如图 4所示， 位于待形成的源极上方的第一光刻胶层和位于待形 成的漏极上方的第一光刻胶层之间的距离 L为 2.0~4.5μπι, 该距离 L等于之 后形成的薄膜晶体管中的源极和漏极之间的间隙宽度。 TFT导通时， 该距离 L等于有源层上沟道的长度。 一个 TFT的源极和漏极之间间隙的宽度越小， 该 TFT导通时， 所产生的沟道的长度较短， TFT的开启电流 Ι。η越大， 有利 于提高 TFT的性能。
步骤 S13: 至少在所述导电层上待形成源极的区域和待形成漏极的区域 上的第一光刻胶层之间形成设定厚度的第二光刻胶层。
在第一光刻胶层上方形成一层设定厚度为 h的光刻胶层。 通过第三掩模 板对所述光刻胶层进行曝光显影， 至少保留待形成的源极和漏极之间的间隙 对应区域的光刻胶， 去除其余区域的光刻胶。 该步骤保证不去除第一光刻胶 层。
或者， 通过第三掩模板对所述光刻胶层进行曝光显影， 保留待形成的源 极和漏极之间的间隙对应区域的光刻胶以及第一光刻胶层正上方的光刻胶。 这里， 被保留下的光刻胶层为第二光刻胶层。 具体是否保留第一光刻胶层正 上方的光刻胶视具体工艺条件或其他因素决定。
如图 5所示， 包括位于第一光刻胶层 4上方的第二光刻胶层 5, 第二光 刻胶层 5的厚度为 h, 由于第二光刻胶层 5下方的导电层 11的表面平坦， 因 此第二光刻胶层 5的厚度均一。
步骤 S13中形成覆盖整个基板的光刻胶与步骤 S12中形成覆盖整个基板 的光刻胶过程类似， 可以通过涂覆或滴注旋转等方法进行， 具体实施时可以 根据实际需求而定， 这里不做限制。
例如， 第二光刻胶层 5的厚度约为 0.3~0.8μπι (对应 3000-8000Α ) 。 例如， 第二光刻胶层 5的厚度约为 0.5μπι (对应 5000 A ) 。
例如， 所述第二光刻胶层由疏水性的光刻胶制作而成。
例如，第二光刻胶层的材料与第一光刻胶层的材料可以相同也可以不同。 第二光刻胶层的材料例如满足以下条件： 第二光刻胶层与第一光刻胶层 的粘附性大于该第二光刻胶层与用于形成源极和漏极的导电层之间的粘附 性。
在至少一个实施例中， 由于光刻胶层均为疏水性材料， 源漏极导电层为 亲水性材料， 因此第二光刻胶层与第一光刻胶层的粘附性会大于第二光刻胶 层与导电层间的粘附性， 两者粘附性的差异有助于后续步骤的执行。
步骤 S14: 对形成有所述第一光刻胶层、 第二光刻胶层、 半导体层和导 电层的基板进行刻蚀工艺形成有源层、 源极和漏极的图形。
首先， 对所述待形成源极和漏极的导电层 11进行刻蚀工艺， 参见图 6, 保留导电层 11上第一光刻胶层 4和第二光刻胶层 5覆盖的区域，露出第一光 刻胶层 4和第二光刻胶层 5未覆盖区域的半导体层 10。该步骤中的刻蚀工艺 例如使用湿法刻蚀。
接着， 对图 6所示的半导体层 10进行刻蚀工艺， 去除第一光刻胶层 4 和第二光刻胶层 5未覆盖区域的半导体层 10,保留第一光刻胶层 4和第二光 刻胶层 5覆盖区域的半导体层 10, 此时待形成的 TFT结构如图 7所示， 第 一光刻胶层 4和第二光刻胶层 5覆盖区域的半导体层作为有源层 6的图形。 该步骤中的刻蚀工艺例如使用干法刻蚀。
接着， 按照图 7所示的第二光刻胶 5的设定厚度 h对第二光刻胶层 5进 行灰化 (ashing)处理， 完全去除第二光刻胶层 5, 露出第二光刻胶层 5下方的 导电层 11部分， 即露出导电层 11上待形成的源极和漏极之间的间隙部分， 参见图 8。 该过程由于第二光刻胶层 5的厚度均一， 对第二光刻胶层 5进行 灰化处理时， 可以根据灰化光刻胶的厚度 h准确灰化光刻胶， 不会形成过度 灰化光刻胶或对光刻胶灰化不足， 进而在制备的 TFT中引起 TFT GT Bridge 不良， 或者 channel open不良的问题。
灰化为干法刻蚀的一种。 当然这里的不限于通过灰化法处理第二光刻胶 层 5, 可以通过任何能够准确去除第二光刻胶层不会产生过度刻蚀或刻蚀不 到位的方法刻蚀第二光刻胶。
紧接着再次对导电层 11进行刻蚀， 去除导电层 11上待形成的源极和漏 极之间的间隙部分， 形成图 9所示的相互绝缘的源极 7和漏极 8图形。 该步 骤中的刻蚀过程例如干法刻蚀。
在步骤 S14的基础上， 所述方法还进一步包括： 剥离所述源极和漏极上 的第一光刻胶层。
例如， 通过干法刻蚀去除第一光刻胶层（RP strip ) , 待形成的 TFT参 见图 10所示。 此时 TFT包括栅极 2、 上级绝缘层 3 , 有源层 6、 源极 7和漏 上述过程为制作底栅型 TFT的详细过程。
制作顶栅型 TFT的过程与上述制作底栅型 TFT的过程类似， 不同之处 在于， 先制作有源层、 源极和漏极图形， 后制作栅极和栅极绝缘层图形， 这 里不再赘述。
上述制作 TFT的过程仅是针对解决本发明的技术问题而提出的，任何包 含本发明实施例提供的技术方案的 TFT制作过程均包含在本发明范围之内。 例如， 在本发明的至少一实施例中， 还包括制作位于有源层与源极和漏极之 间的欧姆接触层， 以减小半导体层与源极和漏极之间的接触电阻， 提高 TFT 的性能。 本发明的至少一实施例中， 针对非晶硅半导体层材料制作有源层的 情况， 可以在有源层与源极和漏极之间制作经氮离子掺杂过的非晶硅层（制 作 NVSi ) 。
本发明至少一实施例提供的 TFT 的制作方法可以取代任何包括通过半 色调或灰色调掩模板实现不同厚度的光刻胶的过程， 不仅适用于形成源极、 漏极和有源层， 同样适用于通过半色调或灰色调掩模板形成大面积不同厚度 光刻胶的过程。
本发明至少一实施例还提供一种薄膜晶体管， 釆用上述本发明实施例提 供的薄膜晶体管的制作方法制作而成。 薄膜晶体管中的有源层的材料类型不 限。 薄膜晶体管的结构至少包括栅极、 栅极绝缘层、 有源层、 源极和漏极， 还可以包括刻蚀阻挡层、 欧姆接触层， 与基板接触的緩冲层、 覆盖整个 TFT 的钝化层等。 这里就不——详述。
本发明实施例的薄膜晶体管例如用于液晶显示面板或有机发光二极管 ( OLED )显示面板中的阵列基板上的开关元件或驱动元件， 例如， 在液晶 面板中用于对亚像素单元的通断进行控制， 在 OLED显示面板用于控制或驱 动亚像素单元。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。
本申请要求于 2014年 1月 28日递交的中国专利申请第 201410042408.5 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种薄膜晶体管的制作方法， 包括： 在基板上形成栅极图形和栅极绝 缘层， 以及形成源极、 漏极和有源层图形； 其中，
所述形成源极、 漏极和有源层图形包括：
在所述基板上依次形成覆盖整个基板的半导体层和导电层；
分别在所述导电层上待形成源极的区域和待形成漏极的区域形成第一光 刻胶层；
至少在所述导电层上待形成源极和漏极之间的间隙形成第二光刻胶层； 对形成有所述第一光刻胶层、 第二光刻胶层、 半导体层和导电层的基板 进行刻蚀工艺形成有源层、 源极和漏极的图形。
2、根据权利要求 1所述的方法， 其中， 在形成所述第二光刻胶层的同时 还包括， 形成位于所述第一光刻胶层上方的第二光刻胶层。
3、 根据权利要求 1或 2所述的方法， 其中， 所述形成有源层、 源极和漏 极的图形还包括：
对所述导电层进行刻蚀工艺， 保留第一光刻胶层和第二光刻胶层覆盖区 域的导电层， 露出第一光刻胶层和第二光刻胶层未覆盖区域的半导体层； 对所述半导体层进行刻蚀工艺， 去除第一光刻胶层和第二光刻胶层未覆 盖区域的半导体层， 第一光刻胶层和第二光刻胶层覆盖区域的半导体层作为 有源层图形；
按照所述第二光刻胶的厚度对所述第二光刻胶层进行灰化处理， 露出待 形成的源极和漏极之间的间隙对应的导电层；
再次对所述导电层进行刻蚀， 去除待形成的源极和漏极之间的间隙对应 的导电层， 形成相互绝缘的源极漏极图形。
4、 根据权利要求 3所述的方法， 其中， 形成所述有源层、 源极和漏极的 图形之后还包括： 剥离所述源极和漏极上的第一光刻胶层。
5、 根据权利要求 1-4任一项所述的方法， 其中， 所述在基板上形成栅极 图形、 栅极绝缘层的过程， 包括：
在形成所述源极、 漏极和有源层图形之前， 在所述基板上形成栅极图形 以及位于所述栅极图形上的栅极绝缘层； 或者 在形成所述源极、漏极和有源层图形之后在所述基板上形成栅极绝缘层， 以及位于栅极绝缘层之上的栅极图形。
6、 根据权利要求 1-5任一项所述的方法， 其中， 所述第一光刻胶层的厚 度为 1.5~2.5μπι。
7、 根据权利要求 1-6任一项所述的方法， 其中， 所述第二光刻胶层为厚 度均一的膜层； 所述第二光刻胶层的厚度为 0.3 ~0.8μπι。
8、 根据权利要求 1-7任一项所述的方法， 其中， 所述待形成的源极和漏 极之间的 巨离为 2.5~4.55μπι。
9、 根据权利要求 1-8任一项所述的方法， 其中， 所述有源层由非晶硅、 多晶硅或金属氧化物半导体制作而成。
10、 一种薄膜晶体管， 釆用权利要求 1-9任一所述的方法制作而成。
PCT/CN2014/080813 2014-01-28 2014-06-26 薄膜晶体管的制作方法及薄膜晶体管 WO2015113368A1 (zh)

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