WO2015051677A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2015051677A1
WO2015051677A1 PCT/CN2014/085203 CN2014085203W WO2015051677A1 WO 2015051677 A1 WO2015051677 A1 WO 2015051677A1 CN 2014085203 W CN2014085203 W CN 2014085203W WO 2015051677 A1 WO2015051677 A1 WO 2015051677A1
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Prior art keywords
pattern
photoresist
ohmic contact
pixel electrode
contact layer
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PCT/CN2014/085203
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English (en)
French (fr)
Inventor
李田生
谢振宇
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/439,948 priority Critical patent/US9261744B2/en
Publication of WO2015051677A1 publication Critical patent/WO2015051677A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • the present disclosure relates to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • ADSDS Advanced Super Dimension Switch
  • TFT-LCD Thin Film Transistor
  • the Gate Driver on Array (GOA) technology of the array substrate integrates the TFTs forming the gate driving circuit on the array substrate, thereby eliminating the gate driving integrated circuit portion, from the material cost and the process steps. Reduce the cost of the product.
  • GAA Gate Driver on Array
  • the embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which can reduce the number of mask processes on the basis of the existing process, thereby reducing manufacturing cost and improving product yield.
  • Embodiments of the present invention provide an array substrate including a substrate substrate and a pattern of gate electrodes sequentially formed on the substrate substrate, a pattern of a gate insulating layer, a pattern of a pixel electrode, a pattern of an ohmic contact layer, and an active layer a pattern, a pattern of source and drain electrodes, wherein the pattern of the pixel electrode is located in the gate Between the pattern of the pole insulating layer and the pattern of the ohmic contact layer.
  • the pattern of the gate insulating layer is between the pattern of the gate and the pattern of the pixel electrode; the pattern of the ohmic contact layer is between the pattern of the active layer and the pattern of the pixel electrode.
  • the array substrate further includes: a pattern of a passivation layer sequentially formed over the pattern of the source and drain electrodes, and a pattern of the common electrode.
  • the embodiment of the invention further provides a method for fabricating an array substrate.
  • the array substrate may be the array substrate described above.
  • the method includes: sequentially forming a pattern of a gate, a pattern of a gate insulating layer, a pattern of a pixel electrode, a pattern of an ohmic contact layer, a pattern of an active layer, and a pattern of source and drain electrodes on a base substrate, wherein A masking process forms a pattern of pixel electrodes and a pattern of ohmic contact layers.
  • the pattern of the active layer and the pattern of the gate insulating layer are formed by one mask process.
  • the pattern of sequentially forming the gate on the base substrate, the pattern of the gate insulating layer, the pattern of the pixel electrode, the pattern of the ohmic contact layer, the pattern of the active layer, and the pattern of the source and drain electrodes include: a sub-mask process to form a pattern of gate electrodes on the base substrate; a pattern of the pixel electrode and a pattern of the ohmic contact layer are formed by a second mask process; a pattern and a gate of the active layer are formed by a third mask process a pattern of an insulating layer; and a pattern of source and drain electrodes formed by a fourth masking process.
  • the method further includes: forming a pattern of the passivation layer by a fifth masking process; and forming a pattern of the common electrode by the sixth masking process.
  • the second mask process includes: sequentially forming a pixel electrode film and an ohmic contact layer film on the structure obtained in the first mask process; applying a photoresist over the ohmic contact layer film, using a half exposure mask After exposure and development, a photoresist completely reserved region is formed in a region corresponding to the source drain electrode, a photoresist semi-reserved region is formed in a region corresponding to the pixel electrode, and a photoresist completely removed region is formed in the remaining region;
  • the etch process removes the pixel electrode film and the ohmic contact layer film in the completely removed region of the photoresist; the photoresist in the semi-reserved region of the photoresist is removed by an ashing process, and the semi-reserved region of the photoresist is removed by a second etching process An ohmic contact layer film; and a photoresist that removes a completely remaining region of the photoresist by a lift-off
  • a gate insulating film is formed over the pattern of the gate; and the third mask process includes: in the second mask process Thereafter, an active layer film is formed over the pattern of the ohmic contact layer; a photoresist is coated on the active layer film, and a photoresist is used to form a photoresist completely reserved region in the region corresponding to the gate after exposure and development using a half exposure mask.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • the array substrate includes a substrate and a pattern of a gate formed on the substrate, a pattern of a gate insulating layer, and a pattern of a pixel electrode. a pattern of the ohmic contact layer, a pattern of the active layer, and a pattern of the source and drain electrodes, wherein the pattern of the pixel electrode is between the pattern of the gate insulating layer and the pattern of the ohmic contact layer.
  • the method for fabricating the array substrate includes: forming a pattern of a gate, a pattern of a gate insulating layer, a pattern of a pixel electrode, a pattern of an ohmic contact layer, a pattern of an active layer, and a pattern of source and drain electrodes on the base substrate,
  • the pattern of the pixel electrode and the pattern of the ohmic contact layer are formed by one mask process.
  • the embodiment of the present invention reduces the mask process on the original seven mask processes, greatly reduces the production cost, improves the product yield, and can also achieve the etching-free formation of the channel, thereby avoiding the root cause.
  • the process produced by the channel is poor.
  • 1A is a schematic plan view of an array substrate known to the inventors
  • Figure 1B is a cross-sectional view taken along line B-B of Figure 1A;
  • FIGS. 1A and 1B are schematic views showing the structure formed after the first mask process in the method of fabricating the array substrate shown in FIGS. 1A and 1B;
  • FIGS. 1A and 1B are schematic structural views of the second mask process in the method of fabricating the array substrate shown in FIGS. 1A and 1B;
  • FIGS. 1A and 1B are schematic views showing the structure after the third mask process in the method of fabricating the array substrate shown in FIGS. 1A and 1B;
  • 2D is a schematic view showing the structure formed after the fourth mask process in the method of fabricating the array substrate shown in FIGS. 1A and 1B;
  • FIGS. 1A and 1B are schematic structural views of the fifth mask process in the method of fabricating the array substrate shown in FIGS. 1A and 1B;
  • 2F is a schematic structural view of the sixth mask process in the method of fabricating the array substrate shown in FIGS. 1A and 1B;
  • 3A is a schematic structural view of a first mask process in a method of fabricating an array substrate according to an embodiment of the invention;
  • 3B is a schematic structural view of a second masking process in a method of fabricating an array substrate according to an embodiment of the invention
  • 3C is a schematic structural view of a second step of a second masking process in a method of fabricating an array substrate according to an embodiment of the invention.
  • 3D is a schematic structural view of a second step of a second masking process in a method of fabricating an array substrate according to an embodiment of the invention
  • 3E is a schematic structural view of a third masking process in a method of fabricating an array substrate according to an embodiment of the invention.
  • 3F is a schematic structural view of a third step of a third masking process in a method of fabricating an array substrate according to an embodiment of the invention.
  • 3G is a schematic structural view of a third step of a third masking process in a method of fabricating an array substrate according to an embodiment of the invention.
  • 3H is a schematic structural view of a fourth mask process in a method of fabricating an array substrate according to an embodiment of the invention.
  • FIG. 31 is a schematic structural view of a fifth mask process in a method of fabricating an array substrate according to an embodiment of the present invention.
  • 3J is a schematic structural view of an array substrate according to an embodiment of the present invention. detailed description
  • the method for fabricating an array substrate is suitable for fabricating an array substrate with high PPI and containing GOA technology.
  • the method includes: forming a pattern of a gate, a pattern of a gate insulating layer, a pattern of a pixel electrode, a pattern of an ohmic contact layer, a pattern of an active layer, a pattern of source and drain electrodes on a base substrate, by a single mask process A pattern of the pixel electrode and a pattern of the ohmic contact layer are formed.
  • the array substrate of high PPI means: an array substrate having a PPI higher than 300 PPI.
  • the method further includes: forming a pattern of the active layer and a pattern of the gate insulating layer by a single mask process.
  • the pattern of forming the gate on the base substrate, the pattern of the gate insulating layer, the pattern of the pixel electrode, the pattern of the ohmic contact layer, the pattern of the active layer, and the pattern of the source and drain electrodes include: a mask process to form a pattern of gate electrodes on the base substrate; a pattern of the pixel electrode and a pattern of the ohmic contact layer are formed by the second mask process; a pattern of the active layer and a gate insulation are formed by the third mask process a pattern of layers; and a pattern of source and drain electrodes formed by a fourth mask process.
  • the method further includes: forming a pattern of the passivation layer by a fifth masking process; and forming a pattern of the common electrode by the sixth masking process.
  • the second masking process includes: sequentially forming a pixel electrode film and an ohmic contact layer film; coating a photoresist on the ohmic contact layer film, exposing and developing the half-tone mask to the corresponding source and drain electrode
  • the region forms a photoresist completely reserved region, a photoresist semi-reserved region is formed in a region corresponding to the pixel electrode, and a photoresist completely removed region is formed in the remaining region;
  • the photoresist completely removed region is removed by the first etching process a pixel electrode film and an ohmic contact layer film;
  • the photoresist in the semi-reserved region of the photoresist is removed by an ashing process, and the ohmic contact layer film of the semi-reserved region of the photoresist is removed by a second etching process to form an ohmic contact layer Pattern;
  • a photoresist that completely removes a region of the photoresist is removed
  • a gate insulating film is formed over the pattern of the gate.
  • the third masking process includes: after the second masking process, in the Forming an active layer film over the pattern of the ohmic contact layer; coating a photoresist on the active layer film, exposing and developing the halftone mask to form a photoresist completely reserved region in a region corresponding to the gate; Forming a photoresist completely removed region in a region corresponding to the gate line lead, and forming a photolithography film and a gate insulating layer film in the remaining region; removing the photoresist in the semi-reserved region of the photoresist by an ashing process, passing the second time An etching process removes an active layer film of a semi-reserved region of the photoresist; and a photoresist that removes a completely remaining region of the photoresist by a lift-off process.
  • An array substrate provided by an embodiment of the present invention includes a substrate substrate, a pattern of a gate formed on the substrate, a pattern of a gate insulating layer, a pattern of a pixel electrode, a pattern of an ohmic contact layer, and an active layer. a pattern, a pattern of source and drain electrodes, wherein a pattern of the pixel electrode is between the pattern of the gate insulating layer and the pattern of the ohmic contact layer.
  • the pattern of the gates in the embodiments of the present invention generally includes a gate of a display region formed by using a same layer of metal, a gate line, and a gate line of a non-display area; a pattern of source and drain electrodes, Generally, the source and drain electrodes of the display region formed by the same layer metal, the data lines, and the data line leads of the non-display area are included; the pattern of the pixel electrodes is usually a plate electrode formed in the display area; the pattern of the common electrode is usually a strip electrode formed in the display region; the pattern of the gate insulating layer is an insulating layer covering the pattern of the gate electrode, the pattern of the passivation layer is an insulating layer covering the pattern of the pixel electrode, the pattern of the gate insulating layer and the passivation layer The pattern is usually a transparent film covering the entire substrate, and a via is formed only in the area of the non-display area gate line for transmitting the gate driving signal to the gate line; the pattern of the o
  • the patterns of the layers formed on the array substrate in the embodiment of the present invention may also be other shapes or include other structures.
  • the pattern of the pixel electrodes may also be strips, patterns of gate electrodes or patterns of source and drain electrodes. It is also possible to include a common electrode line formed in the same layer, and the pattern of the source and drain electrodes and the pattern of the common electrode may further include connection electrodes formed in the same layer, and the like.
  • the array substrate includes a base substrate 11, a gate electrode 12, gate lines and gate line leads 13, a gate insulating layer 14, an ohmic contact layer 15, an active layer 16,
  • the array substrate shown in Figs. 1A and 1B is formed by the following fabrication method.
  • FIG. 2A is a schematic view showing the structure formed after the first masking process in the method for fabricating the array substrate.
  • a metal layer film is deposited on the substrate substrate 11, and the gate electrode 12, the gate line and the gate line lead 13 are formed by a first mask process, wherein the gate and the gate line are located on the display.
  • the gate line leads are located in the peripheral lead area.
  • FIG. 2B is a schematic view showing the structure formed after the second masking process in the method for fabricating the array substrate.
  • the gate insulating layer film 14 the active layer film and the ohmic contact layer film are sequentially deposited from bottom to top, after passing through the second mask process.
  • An ohmic contact layer 15 and an active layer 16 are formed in the display region.
  • FIG. 2C is a schematic view showing the structure formed after the third mask process in the method for fabricating the array substrate. As shown in Fig. 2C, on the basis of the structure formed after the second masking process, the pixel electrode 17 is formed in the display region by the third mask process after depositing the first transparent electrode layer film.
  • FIG. 2D is a schematic structural view of a conventional mask substrate fabrication method after the fourth mask process, as shown in FIG. 2D, on the basis of the structure formed after the third mask process, the film is directly deposited without depositing a film.
  • a gate insulating via hole 18 is formed on the gate insulating film 14 of the peripheral lead region.
  • FIG. 2E is a schematic view showing the structure formed after the fifth masking process in the method for fabricating the array substrate.
  • the source 19 and the drain 20 and the data line are formed in the display region by first depositing a metal layer film and then performing a fifth mask process ( Not shown in the drawing), a first connection electrode 21 is formed in the peripheral lead region, and the first connection electrode 21 is electrically connected to the gate line lead 13 through the gate insulating layer via 18 in the gate insulating film 14.
  • FIG. 2F is a schematic structural view of forming a passivation layer via hole after the sixth mask process in the method for fabricating the array substrate.
  • the passivation layer film 22 is first formed by deposition, and then blunt on the passivation layer film is formed in the peripheral lead region after the sixth mask process.
  • the via hole 24 is formed, and the second transparent electrode layer is further deposited.
  • the common electrode 23 is formed in the display region, and the second connection is formed in the peripheral lead region.
  • the electrode 25, the second connection electrode 25 is electrically connected to the gate line lead 13 through the passivation layer via 24 on the passivation layer film and the first connection electrode 21.
  • the mask process includes a process of photoresist coating, exposure, development, etching, photoresist stripping, and the like. Patterns of the above layers can also be formed by other processes such as printing.
  • FIG. 3A to 3J are schematic views showing the structure of each method of fabricating an array substrate according to an embodiment of the present invention. As shown in FIG. 3A to FIG. 3J, the method for fabricating the array substrate of the embodiment of the present invention includes the following steps.
  • a metal layer film is formed on the base substrate 111, and the gate electrode 112 is formed by a first mask process. At the same time, a gate line 113 of the display region and a gate line lead 113 of the peripheral lead region are formed. .
  • the first masking process in the method for fabricating the array substrate in the embodiment of the present invention is the same as that shown in FIG. 2A, and details are not described herein again.
  • a gate insulating layer film 114, a first transparent electrode layer film, and an ohmic contact layer film are formed by sequentially depositing, wherein the gate insulating layer film 114
  • the film may be a silicon nitride film or a silicon oxide film
  • the ohmic contact layer film may be an n+ doped silicon oxide film
  • the first transparent electrode layer film may be an indium tin oxide film.
  • a photoresist is coated on the ohmic contact layer film, and a halftone mask is used for exposure and development processing, a photoresist completely remaining region 201 is formed in a region corresponding to the source/drain electrode, and light is formed in a region corresponding to the pixel electrode.
  • the glue semi-reserved area 202 is formed, and a photoresist complete removal area 203 is formed in the remaining area.
  • the first transparent electrode layer film and the ohmic contact layer film under the photoresist completely removed region 203 are removed by an etching process; then, the photoresist semi-reserved region 202 is removed by an ashing process. Residual photoresist.
  • the ohmic contact layer film at the photoresist half-retaining region 202 is removed by a second etching process to form a pattern of the ohmic contact layer 115; the photoresist completely retained region 201 is removed by a lift-off process.
  • the photoresist forms a pattern of the pixel electrode 117.
  • the pattern of the active layer 116 and the pattern of the gate insulating layer 114 are formed by the third mask process.
  • an active layer film is deposited first, a photoresist is coated on the active layer film, and a halftone mask is used for exposure and development processing to form a photoresist completely reserved region 204 in a region corresponding to the gate 112. Forming a photoresist completely removed region 206 in a region corresponding to the gate line lead 113, and forming a photoresist half in the remaining region
  • the area 205 is reserved.
  • the active layer film and the gate insulating film under the photoresist completely removed region 206 are removed by an etching process, and a gate insulating layer above the gate line lead 13 is formed in the peripheral lead region.
  • a via 118, a gate insulating via 118 is used to input a gate drive signal to the gate line; the photoresist remaining at the photoresist semi-reserved region 205 is removed by an ashing process.
  • the active layer film under the photoresist semi-retained region 205 is removed by an etching process.
  • the photoresist of the photoresist completely remaining region 204 is removed by a lift-off process to form a pattern of the active layer 116 in the display region.
  • a metal thin film is deposited first, and a source electrode 119 and a drain electrode 120 and a data line are formed in the display region by a single mask process (in the figure). Not shown, the first connection electrode 121 is formed in the peripheral lead region.
  • a passivation layer film is first formed by deposition, and then a passivation layer via hole 124 is formed in the peripheral lead region through a fifth mask process, and then A second transparent electrode layer film is deposited.
  • the common electrode 123 is formed in the display region, and the second connection electrode 125 is formed in the peripheral lead region, the second connection electrode 125 passes through the passivation layer via 124 and the first connection
  • the electrode 121 and the gate line lead 113 are electrically connected.
  • the fifth and sixth mask processes of the array substrate of the present invention are the same as the sixth and seventh mask processes in the method shown in Figs. 1A-2F, respectively, and are not described herein again.
  • the pattern of the ohmic contact layer is generally located between the pattern of the active layer pattern and the source and drain electrodes, and the pattern of the ohmic contact layer is usually along with the pattern of the active layer.
  • the ohmic contact layer at the channel is simultaneously etched away.
  • the ohmic contact layer at the channel usually needs to be over-etched, that is, a part of the active layer under the ohmic contact layer is simultaneously etched, thereby causing a process defect at the channel of the thin film transistor.
  • the pattern of the ohmic contact layer 115 is located between the pattern of the pixel electrode 117 and the pattern of the active layer 116.
  • the pattern of the pixel electrode 117 is located between the pattern of the gate insulating layer 114 and the pattern of the ohmic contact layer 115.
  • the pattern of the ohmic contact layer 115 can be formed first, and then the pattern of the active layer 116 can be formed, thereby forming the channel without etching, thereby avoiding the trench from the root. The badness of the road.
  • the pattern of the pixel electrode 117 and the pattern of the ohmic contact layer 115 are formed by a single mask process
  • the pattern of the active layer 116 and the pattern of the gate insulating layer 114 are formed by a single mask process, which can be shown in 1A-2F.
  • Array substrate manufacturing method based on reducing the mask once The mold process realizes 6 mask processes to form an ADSDS type array substrate.
  • a lap of the source and drain electrodes is formed over the pattern 116 of the active layer by a single mask process by depositing a thin film of the metal layer, thereby forming a new TFT structure.
  • the pattern 115 of the ohmic contact layer, the pattern 116 of the active layer, and the pattern 117 of the pixel electrode in the embodiment of the present invention are different from those in the technical schemes shown in FIGS. 1A and 1B.
  • the different positions may allow the formation of the above array substrate by a six-mask process, and the etching-free formation of the channel may be achieved, which ensures the production yield.
  • An embodiment of the invention further provides an array substrate.
  • 3J is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • the array substrate provided by the embodiment of the present invention includes: a substrate substrate, a pattern of gates sequentially formed on the substrate, a pattern of a gate insulating layer, a pattern of a pixel electrode, and a pattern of an ohmic contact layer. , a pattern of the active layer and a pattern of source and drain electrodes.
  • the pattern of the pixel electrode is between the pattern of the gate insulating layer and the pattern of the ohmic contact layer, the pattern of the gate insulating layer is between the pattern of the gate and the pattern of the pixel electrode; the pattern of the active layer is located in the pattern of the ohmic contact layer Between the pattern of the source and drain electrodes.
  • the array substrate provided by the embodiment of the present invention further includes a pattern of a passivation layer sequentially formed over the pattern of the source and drain electrodes and a pattern of the common electrode.
  • the array substrate provided by the embodiment of the present invention includes: a pattern of gate lines 113, gate lines, and gate line leads 113 of the peripheral lead regions formed on the display region of the substrate substrate 111;
  • the pattern of the pixel electrode 117 and the pattern of the ohmic contact layer 115 are sequentially formed above the pattern of the gate line 113, wherein the pixel electrode 117 may be a plate electrode or a strip electrode, and the pattern of the ohmic contact layer 115 is located at the pixel electrode 117.
  • the ohmic contact layer 115 is formed only in a region corresponding to the source drain electrode, thereby forming a channel of the thin film transistor; a pattern of the active layer 116 formed over the pattern of the ohmic contact layer 115, and a peripheral lead a gate insulating layer via formed on the gate insulating layer 114 of the region, wherein the pattern of the ohmic contact layer 115 is formed before the pattern of the active layer 16 is formed, that is, it is not necessary to pass through the pattern of the active layer 116 Etching forms a channel of the thin film transistor, ensuring a production yield; a source electrode 119 and a drain electrode 120 formed over the pattern of the active layer 116, and a portion formed by the peripheral lead region a pattern of the connection electrode 121, wherein the drain electrode 120 overlaps the pixel electrode 117 located therebelow; a passivation layer 122 formed over the pattern of the source electrode 119 and the drain electrode 120 and the first connection electrode 121, wherein the peripheral lead
  • the pattern of the ohmic contact layer 115, the pattern of the active layer 116, and the pattern of the pixel electrode 117 in the array substrate of the embodiment of the present invention are different from those in the array substrate shown in Figs. 1A and 1B.
  • the pattern of the pixel electrode 117 is located between the pattern of the gate insulating layer 114 and the pattern of the ohmic contact layer 115, and the pattern of the gate insulating layer 114 is located between the pattern of the gate electrode 112 and the pattern of the pixel electrode 117; the ohmic contact layer 115
  • the pattern is located between the pattern of the active layer 116 and the pattern of the pixel electrode 117.
  • This structure constitutes a novel thin film transistor structure which allows the formation of the above array substrate by a six-mask process, which reduces the production cost. And can realize the etching-free formation of the channel to ensure the production yield.
  • the embodiment of the present invention further provides a display device, the display device includes an array substrate and a color filter substrate, wherein the array substrate includes: a substrate substrate and a gate electrode sequentially formed on the substrate substrate The pattern, the pattern of the gate insulating layer, the pattern of the pixel electrode, the pattern of the ohmic contact layer, the pattern of the active layer, and the pattern of the source and drain electrodes.
  • the color film may also be integrated in the array substrate, that is, the display device may further include an array substrate and an opposite substrate.
  • the display device may be: a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component. .

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Abstract

一种阵列基板及其制造方法、显示装置，所述阵列基板包括衬底基板（111）以及在衬底基板（111）上形成的栅极（112）的图案、栅极绝缘层（114）的图案、像素电极（117）的图案、欧姆接触层（115）的图案、有源层（116）的图案、源漏电极（119，120）的图案，其中，像素电极（117）的图案位于栅极绝缘层（114）的图案和欧姆接触层（115）的图案之间。采用本技术方案，能够减少一次掩模工艺，从而能降低制造成本和提高产品良品率。

Description

阵列基板及其制作方法、 显示装置 技术领域
本公开涉及一种阵列基板及其制作方法、 显示装置。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )具有体积小、 功耗低、 无辐射等特点， 在当前的平板显示器市场 占据了主导地位。 在 TFT-LCD行业中， 高级超维场转换（Advanced super Dimension Switch, ADSDS )型薄膜晶体管 （ Thin Film Transistor, TFT ) 面 内电场驱动模式的 TFT-LCD产品， 不但可提高 TFT-LCD产品的画面品质， 而且具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤 压水波纹（Push Mura )等优点， ADSDS型 TFT-LCD产品已经成为主流产 口口
阵列基板的栅极驱动（Gate Driver on Array, GOA )技术是将形成栅极 驱动电路的 TFT 集成于阵列基板上， 从而省掉栅极驱动集成电路部分， 从 材料成本和工艺步骤两个方面来降低产品的成本。
目前，在 TFT-LCD行业中，一方面为了使 TFT-LCD产品具有较好的视 觉效果， 即： 每英寸所拥有的像素（Pixels Per Inch, PPI )数目尽可能的高， 另一方面为了能够降低产品的成本而釆用 GOA技术， 因此， 当制备高 PPI 并且釆用 GOA技术的阵列基板时， 一般需要通过七次掩模工艺才能完成。 然而， 掩模工艺的成本和复杂度都很高， 掩模的应用次数越多其制造成本就 会越高， 而且产品质量也越难保证。 发明内容
有鉴于此， 本发明实施例提供一种阵列基板及其制作方法、 显示装置， 可在现有工艺基础上减少一次掩模工艺次数，从而能降低制造成本和提高产 品良品率。
本发明实施例提供了一种阵列基板，包括衬底基板以及在衬底基板上依 次形成的栅极的图案、 栅极绝缘层的图案、 像素电极的图案、 欧姆接触层的 图案、 有源层的图案、 源漏电极的图案， 其中， 所述像素电极的图案位于栅 极绝缘层的图案和欧姆接触层的图案之间。
例如， 所述栅极绝缘层的图案位于栅极的图案和像素电极的图案之间； 所述欧姆接触层的图案位于有源层的图案和像素电极的图案之间。
例如， 所述阵列基板还包括： 在源漏电极的图案上方依次形成的钝化层 的图案以及公共电极的图案。
本发明实施例还提供了一种阵列基板的制作方法。所述阵列基板可为上 述所述的阵列基板。 所述方法包括： 在衬底基板上依次制作栅极的图案、 栅 极绝缘层的图案、 像素电极的图案、 欧姆接触层的图案、 有源层的图案、 源 漏电极的图案， 其中， 通过一次掩模工艺形成像素电极的图案和欧姆接触层 的图案。
例如， 通过一次掩模工艺形成有源层的图案和栅极绝缘层的图案。 例如， 所述在衬底基板上依次制作栅极的图案、栅极绝缘层的图案、像 素电极的图案、 欧姆接触层的图案、 有源层的图案、 源漏电极的图案包括： 通过第一次掩模工艺在衬底基板上形成栅极的图案；通过第二次掩模工艺形 成像素电极的图案和欧姆接触层的图案；通过第三次掩模工艺形成有源层的 图案和栅极绝缘层的图案； 和通过第四次掩模工艺形成源漏电极的图案。
例如， 所述方法还包括： 通过第五次掩模工艺形成钝化层的图案； 和通 过第六次掩模工艺形成公共电极的图案。
例如， 所述第二次掩模工艺包括： 在第一次掩模工艺所得结构上依次形 成像素电极薄膜和欧姆接触层薄膜； 在欧姆接触层薄膜上方涂覆光刻胶， 利 用半曝光掩模板进行曝光、显影后在对应源漏电极的区域形成光刻胶完全保 留区域， 在对应像素电极的区域形成光刻胶半保留区域， 在其余区域形成光 刻胶完全去除区域；通过第一次刻蚀工艺去除光刻胶完全去除区域的像素电 极薄膜和欧姆接触层薄膜； 通过灰化工艺去除光刻胶半保留区域的光刻胶， 通过第二次刻蚀工艺去除光刻胶半保留区域的欧姆接触层薄膜；和通过剥离 工艺去除光刻胶完全保留区域的光刻胶。
例如，在第一次掩模工艺和第二次掩模工艺之间，在栅极的图案上方形 成栅极绝缘层薄膜； 且所述第三次掩模工艺包括： 在第二次掩模工艺之后， 在欧姆接触层的图案上方形成有源层薄膜； 在有源层薄膜上涂覆光刻胶， 利 用半曝光掩模板进行曝光、显影后在对应栅极的区域形成光刻胶完全保留区 域， 在对应栅线引线的区域形成光刻胶完全去除区域， 其余区域形成光刻胶 半保留区域；通过第一次刻蚀工艺去除光刻胶完全去除区域的有源层薄膜和 栅极绝缘层薄膜； 通过灰化工艺去除光刻胶半保留区域的光刻胶， 通过第二 次刻蚀工艺去除光刻胶半保留区域的有源层薄膜；通过剥离工艺去除光刻胶 完全保留区域的光刻胶。
本发明实施例又提供了一种显示装置， 包括上述的阵列基板。
本发明实施例提供的一种阵列基板及其制作方法、显示装置， 所述阵列 基板包括衬底基板以及在衬底基板上形成的栅极的图案、 栅极绝缘层的图 案、像素电极的图案、欧姆接触层的图案、有源层的图案、 源漏电极的图案， 其中， 所述像素电极的图案位于栅极绝缘层的图案和欧姆接触层的图案之 间。 所述阵列基板的制作方法包括： 在衬底基板上制作栅极的图案、 栅极绝 缘层的图案、 像素电极的图案、 欧姆接触层的图案、 有源层的图案、 源漏电 极的图案， 通过一次掩模工艺形成像素电极的图案和欧姆接触层的图案。 如 此， 本发明实施例在原有七次掩模制程之上减少一次掩模工艺， 大大降低了 生产成本， 提高产品良率， 且还能达到沟道的免刻蚀形成， 从而从根源上避 免了沟道产生的工艺不良。 附图说明
图 1A为发明人已知的阵列基板的平面示意图；
图 1B为沿图 1A中的线 B-B所取的剖视图；
图 2A为制造图 1A和 1B所示的阵列基板方法中的第一次掩模工艺后 形成的结构示意图；
图 2B为制造图 1 A和 1B所示的阵列基板方法中的第二次掩模工艺后形 成的结构示意图；
图 2C为制造图 1 A和 1B所示的阵列基板方法中的第三次掩模工艺后形 成的结构示意图；
图 2D为制造图 1A和 1B所示的阵列基板方法中的第四次掩模工艺后 形成的结构示意图；
图 2E为制造图 1A和 1B所示的阵列基板方法中的第五次掩模工艺后形 成的结构示意图；
图 2F为制造图 1A和 1B所示的阵列基板方法中的第六次掩模工艺后形 成的结构示意图； 图 3A为根据本发明实施例的制造阵列基板的方法中的第一次掩模工艺 后形成的结构示意图；
图 3B为根据本发明实施例的制造阵列基板的方法中的第二次掩模工艺 的第一步骤后形成的结构示意图；
图 3C为根据本发明实施例的制造阵列基板的方法中的第二次掩模工艺 的第二步骤后形成的结构示意图；
图 3D为根据本发明实施例的制造阵列基板的方法中的第二次掩模工艺 的第三步骤后形成的结构示意图；
图 3E为根据本发明实施例的制造阵列基板的方法中的第三次掩模工艺 的第一步骤后形成的结构示意图；
图 3F为根据本发明实施例的制造阵列基板的方法中的第三次掩模工艺 的第二步骤后形成的结构示意图；
图 3G为根据本发明实施例的制造阵列基板的方法中的第三次掩模工艺 的第三步骤后形成的结构示意图；
图 3H为根据本发明实施例的制造阵列基板的方法中的第四次掩模工艺 后形成的结构示意图；
图 31为根据本发明实施例的制造阵列基板的方法中的第五次掩模工艺 后形成的结构示意图； 和
图 3J为本发明实施例阵列基板的结构示意图。 具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本公开一部分实施例， 而 不是全部的实施例。基于本公开中的实施例， 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例， 都属于本公开保护的范围。 以下实施例用于说明本发明， 但不用来限制本发明的范围。 需要说明的是， 附图中所示的根据本发明实施例的掩膜板的大小、 形状、厚度等不是对掩膜 板结构的限定。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "连接" 或者 "相 连"等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电性的 连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右" 等仅用于表示 相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置关系也相应 地改变。
本发明实施例提供的一种阵列基板的制作方法，适用于制作高 PPI且包 含 GOA技术的阵列基板。 该方法包括： 在衬底基板上制作栅极的图案、 栅 极绝缘层的图案、 像素电极的图案、 欧姆接触层的图案、 有源层的图案、 源 漏电极的图案， 通过一次掩模工艺形成像素电极的图案和欧姆接触层的图 案。
这里， 所述高 PPI的阵列基板是指： PPI高于 300PPI的阵列基板。 例如， 所述方法还包括： 通过一次掩模工艺形成有源层的图案和栅极绝 缘层的图案。
例如， 所述在衬底基板上制作栅极的图案、栅极绝缘层的图案、像素电 极的图案、 欧姆接触层的图案、 有源层的图案、 源漏电极的图案包括： 通过 第一次掩模工艺在衬底基板上形成栅极的图案；通过第二次掩模工艺形成像 素电极的图案和欧姆接触层的图案；通过第三次掩模工艺形成有源层的图案 和栅极绝缘层的图案； 和通过第四次掩模工艺形成源漏电极的图案。
例如， 所述方法还包括： 通过第五次掩模工艺形成钝化层的图案； 和通 过第六次掩模工艺形成公共电极的图案。
例如， 所述第二次掩模工艺包括：依次形成像素电极薄膜和欧姆接触层 薄膜； 在欧姆接触层薄膜上方涂覆光刻胶， 利用半色调掩模板进行曝光、 显 影后在对应源漏电极的区域形成光刻胶完全保留区域，在对应像素电极的区 域形成光刻胶半保留区域， 在其余区域形成光刻胶完全去除区域； 通过第一 次刻蚀工艺去除光刻胶完全去除区域的像素电极薄膜和欧姆接触层薄膜；通 过灰化工艺去除光刻胶半保留区域的光刻胶，通过第二次刻蚀工艺去除光刻 胶半保留区域的欧姆接触层薄膜， 形成欧姆接触层的图案； 通过剥离工艺去 除光刻胶完全保留区域的光刻胶， 形成像素电极的图案。
例如，在第一次掩模工艺和第二次掩模工艺之间，在栅极的图案上方形 成栅极绝缘层薄膜。 第三次掩模工艺包括： 在第二次掩模工艺之后， 在所述 欧姆接触层的图案上方形成有源层薄膜； 在所述有源层薄膜上涂覆光刻胶， 利用半色调掩模板进行曝光、显影后在对应栅极的区域形成光刻胶完全保留 区域， 在对应栅线引线的区域形成光刻胶完全去除区域， 其余区域形成光刻 薄膜和栅极绝缘层薄膜； 通过灰化工艺去除所述光刻胶半保留区域的光刻 胶， 通过第二次刻蚀工艺去除光刻胶半保留区域的有源层薄膜； 以及通过剥 离工艺去除光刻胶完全保留区域的光刻胶。
本发明实施例提供的一种阵列基板，包括衬底基板以及在衬底基板上形 成的栅极的图案、栅极绝缘层的图案、像素电极的图案、欧姆接触层的图案、 有源层的图案、 源漏电极的图案， 其中， 像素电极的图案位于栅极绝缘层的 图案和欧姆接触层的图案之间。
需要说明的是，本发明实施例中所述的栅极的图案，通常包括釆用同层 金属形成的显示区的栅极、栅线以及非显示区的栅线引线；源漏电极的图案， 通常包括釆用同层金属形成的显示区的源漏电极、数据线以及非显示区的数 据线引线； 像素电极的图案， 通常为在显示区形成的板状电极； 公共电极的 图案， 通常为在显示区形成的条状电极； 栅极绝缘层的图案为覆盖栅极的图 案的绝缘层， 钝化层的图案为覆盖像素电极的图案的绝缘层， 栅极绝缘层的 图案和钝化层的图案通常均为覆盖整个衬底基板的透明薄膜，仅在非显示区 栅线引线的区域形成过孔， 用于将栅驱动信号传输到栅线； 欧姆接触层的图 案， 通常形成于对应源漏电极的区域， 用于降低接触电阻。 本发明实施例所 述的阵列基板上形成的各层的图案，还可以为其他的形状或者包括其他的结 构， 如像素电极的图案还可以为条状， 栅极的图案或者源漏电极的图案还可 以包括同层形成的公共电极线，源漏电极的图案和公共电极的图案还可以包 括同层形成的连接电极， 等等。
下面结合附图和具体实施例对本发明的技术方案进一步详细阐述。需要 说明的是， 图中各结构的形状、 大小等均只是示意说明本发明的实施例， 并 不是对结构的限定。 图中虚线将所述阵列基板分为显示区和周边引线区， 显 示区和周边引线区的图案同时形成。 为了示意的清楚简洁， 栅极绝缘层、 欧 姆接触层和钝化层在平面图中未示出， 各剖面图的剖面线均如图 1A中 B-B 线方向所示。
对于非晶硅薄膜晶体管阵列基板，通常需要用到欧姆接触层来降低接触 电阻，而欧姆接触层一般位于有源层与源漏电极之间，用于降低其接触电阻。 具体地， 如图 1A和图 1B所示， 所述阵列基板包括衬底基板 11、 栅极 12、 栅线和栅线引线 13、 栅极绝缘层 14、 欧姆接触层 15、 有源层 16、 像素电极 17、 源极 19、 漏极 20、 第一连接电极 21、 钝化层 22、 公共电极 23和第二 连接电极 25。
图 1A和图 1B所示的阵列基板是通过下述的制作方法来形成的。
图 2A为该阵列基板制作方法中第一次掩模工艺后形成的结构示意图。 如图 2A所示，在衬底基板 11上先沉积一层金属层薄膜，再通过第一次掩模 工艺形成栅极 12、 栅线和栅线引线 13， 其中， 栅极和栅线位于显示区， 栅 线引线位于周边引线区。
图 2B为该阵列基板制作方法中第二次掩模工艺后形成的结构示意图。 如图 2B所示， 在第一次掩模工艺后形成的结构基础上， 由下至上依次沉积 栅极绝缘层薄膜 14、 有源层薄膜和欧姆接触层薄膜， 通过第二次掩模工艺 后在显示区形成欧姆接触层 15和有源层 16。
图 2C为该阵列基板制作方法中第三次掩模工艺后形成的结构示意图。 如图 2C所示， 在第二次掩模工艺后形成的结构基础上， 通过沉积第一透明 电极层薄膜后， 利用第三次掩模工艺在显示区形成像素电极 17。
图 2D为现有的阵列基板制作方法中第四次掩模工艺后形成的结构示意 图， 如图 2D所示， 在第三次掩模工艺后形成的结构基础上， 不用沉积薄膜 而直接进行第四次掩模工艺， 在周边引线区的栅极绝缘层薄膜 14上形成栅 极绝缘层过孔 18。
图 2E为该阵列基板制作方法中第五次掩模工艺后形成的结构示意图。 如图 2E所示， 在第四次掩模工艺后形成的结构基础上， 通过先沉积金属层 薄膜，再通过第五次掩模工艺在显示区形成源极 19和漏极 20以及数据线（图 中未示出）， 在周边引线区形成第一连接电极 21， 第一连接电极 21通过栅 极绝缘层薄膜 14中的栅极绝缘层过孔 18与栅线引线 13电连接。
图 2F为该阵列基板制作方法中第六次掩模工艺后形成钝化层过孔的结 构示意图。 如图 2F所示， 在第五次掩模工艺后形成的结构基础上， 先通过 沉积形成钝化层薄膜 22， 然后经过第六次掩膜工艺在周边引线区形成钝化 层薄膜上的钝化层过孔 24， 再沉积第二透明电极层， 通过第七次掩模工艺， 如图 1A所示， 在显示区形成公共电极 23， 以及在周边引线区形成第二连接 电极 25， 第二连接电极 25通过钝化层薄膜上的钝化层过孔 24 以及第一连 接电极 21与栅线引线 13电连接。
所述掩模工艺包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。 也可以通过其他的工艺过程如打印来形成上述各层的图形。
图 3A至图 3J是根据本发明实施例的阵列基板的制作方法的各个步骤 完成后的结构示意图。如图 3A至图 3J所示， 本发明实施例的阵列基板的制 作方法包括以下步骤。
如图 3A所示， 先在衬底基板 111上形成金属层薄膜， 再通过第一次掩 模工艺形成栅极 112， 同时形成的还有显示区的栅线和周边引线区的栅线引 线 113。 本发明实施例中的阵列基板制作方法中第一次掩模工艺与图 2A所 示的相同， 这里不再赘述。
如图 3B所示， 在第一次掩模工艺后形成的结构基础上， 通过依次沉积 形成栅极绝缘层薄膜 114、 第一透明电极层薄膜和欧姆接触层薄膜， 其中栅 极绝缘层薄膜 114可以为氮化硅薄膜或氧化硅薄膜，欧姆接触层薄膜可以为 n+掺杂的氧化硅薄膜， 第一透明电极层薄膜可以为氧化铟锡薄膜。 然后， 通 过第二次掩模工艺形成欧姆接触层 115的图案和像素电极 117的图案。例如， 在欧姆接触层薄膜的上方涂覆光刻胶， 利用半色调掩模板进行曝光、 显影处 理， 在对应源漏电极的区域形成光刻胶完全保留区域 201， 在对应像素电极 的区域形成光刻胶半保留区域 202， 在其余区域形成光刻胶完全去除区域 203。
如图 3C所示， 通过釆用刻蚀工艺， 去除光刻胶完全去除区域 203下方 的第一透明电极层薄膜和欧姆接触层薄膜； 然后， 通过灰化工艺去除光刻胶 半保留区域 202处残留的光刻胶。
如图 3D所示， 通过第二次刻蚀工艺去除光刻胶半保留区域 202处的欧 姆接触层薄膜， 从而形成欧姆接触层 115的图案； 通过剥离工艺去除光刻胶 完全保留区域 201处的光刻胶， 形成像素电极 117的图案。
如图 3E所示， 在第二次掩模工艺后形成的结构基础上， 通过第三次掩 模工艺形成有源层 116的图案和栅极绝缘层 114的图案。 例如， 先沉积一层 有源层薄膜，在有源层薄膜的上方涂覆光刻胶，利用半色调掩模板进行曝光、 显影处理， 在对应栅极 112的区域形成光刻胶完全保留区域 204， 在对应栅 线引线 113的区域形成光刻胶完全去除区域 206， 在其余区域形成光刻胶半 保留区域 205。
如图 3F所示， 通过釆用刻蚀工艺， 去除光刻胶完全去除区域 206下方 的有源层薄膜和栅极绝缘层薄膜， 在周边引线区形成位于栅线引线 13上方 的栅极绝缘层过孔 118， 栅极绝缘层过孔 118用于将栅驱动信号输入栅线； 通过灰化工艺去除光刻胶半保留区域 205处残留的光刻胶。
如图 3G所示， 通过釆用刻蚀工艺， 去除光刻胶半保留区域 205下方的 有源层薄膜。 通过剥离工艺， 去除光刻胶完全保留区域 204的光刻胶， 在显 示区形成有源层 116的图案。
如图 3H所示， 在第三次掩模工艺后形成的结构基础上， 先沉积一层金 属薄膜，再通过一次掩模工艺在显示区形成源极 119和漏极 120以及数据线 (图中未示出）， 在周边引线区形成第一连接电极 121。
如图 31所示， 在第四次掩模工艺后形成的结构基础上， 先通过沉积形 成钝化层薄膜，然后经过第五次掩模工艺在周边引线区形成钝化层过孔 124， 再沉积第二透明电极层薄膜。 通过第六次掩模工艺， 如图 3J所示， 在显示 区形成公共电极 123， 以及在周边引线区形成第二连接电极 125， 第二连接 电极 125通过钝化层过孔 124以及第一连接电极 121和栅线引线 113电连接。 本发明阵列基板第五次和第六次掩模工艺分别与图 1A-2F 所示的方法中的 第六次和第七次掩模工艺相同， 这里不再赘述。
如前所述， 在图 1A-2F 所示的方法中， 欧姆接触层的图案一般位于有 源层图案和源漏电极的图案之间，欧姆接触层的图案通常是与有源层的图案 一起形成， 且在形成源漏电极的图案时， 同时刻蚀掉沟道处的欧姆接触层。 为了不影响薄膜晶体管的开关性能， 沟道处的欧姆接触层通常需要过刻， 即 同时刻蚀掉一部分位于欧姆接触层下方的有源层，进而导致薄膜晶体管沟道 处容易发生工艺不良。 而在本发明实施例中， 欧姆接触层 115的图案位于像 素电极 117的图案与有源层 116的图案之间。 换言之， 像素电极 117的图案 位于栅极绝缘层 114的图案和欧姆接触层 115的图案之间。 这样， 在本发明 实施例的阵列基板制作方法中， 可以先形成欧姆接触层 115的图案， 再形成 有源层 116的图案， 能够实现沟道的免刻蚀形成， 从而从根源上避免了沟道 产生的不良。 另外， 由于像素电极 117的图案和欧姆接触层 115的图案通过 一次掩模工艺形成，有源层 116的图案和栅极绝缘层 114的图案通过一次掩 模工艺形成，能够在 1A-2F所示的阵列基板的制作方法的基础上减少一次掩 模工艺， 实现 6次掩模工艺形成 ADSDS型阵列基板。
在形成有源层的图案 116后，通过沉积金属层薄膜， 通过一次掩模工艺 在有源层的图案 116的上方形成源漏电极的搭接， 从而形成了新的 TFT结 构。 本发明实施例中欧姆接触层的图案 115、 有源层的图案 116及像素电极 的图案 117与图 1A和 1B所示的技术方案中的位置不同。 所述位置不同可 以允许实现通过六次掩模工艺形成上述阵列基板，也可以实现沟道的免刻蚀 形成， 保证了生产良率。
本发明实施例还提供一种阵列基板。 图 3J为本发明实施例阵列基板的 结构示意图。 如图 3J所示， 本发明实施例提供的阵列基板包括： 衬底基板 以及在衬底基板上依次形成的栅极的图案、栅极绝缘层的图案、像素电极的 图案、 欧姆接触层的图案、 有源层的图案和源漏电极的图案。 像素电极的图 案位于栅极绝缘层的图案和欧姆接触层的图案之间，栅极绝缘层的图案位于 栅极的图案和像素电极的图案之间；有源层的图案位于欧姆接触层的图案和 源漏电极的图案之间。
本发明实施例提供的阵列基板还包括在源漏电极的图案上方依次形成 的钝化层的图案以及公共电极的图案。
具体的， 如图 3J所示， 本发明实施例提供的阵列基板包括： 在衬底基 板 111的显示区上形成的栅极 112、 栅线和周边引线区的栅线引线 113的图 案； 在栅极 112、 栅线 113的图案上方依次形成的像素电极 117的图案和欧 姆接触层 115的图案， 其中像素电极 117可以为板状电极或者条状电极， 欧 姆接触层 115的图案位于像素电极 117的图案的上方， 欧姆接触层 115仅在 对应源漏电极的区域形成，从而形成了薄膜晶体管的沟道；在欧姆接触层 115 的图案的上方， 形成的有源层 116的图案， 以及在周边引线区的栅极绝缘层 114上形成的栅极绝缘层过孔， 其中， 欧姆接触层 115的图案在形成有源层 16的图案之前形成，即无需在形成有源层 116的图案之后再通过刻蚀形成薄 膜晶体管的沟道， 保证了生产良率； 在有源层 116的图案的上方形成的源极 119和漏极 120， 以及周边引线区形成的第一连接电极 121的图案， 其中漏 极 120与位于其下方的像素电极 117搭接； 在源极 119和漏极 120以及第一 连接电极 121的图案的上方形成的钝化层 122， 其中在周边引线区中的钝化 层 122上形成有钝化层过孔；在钝化层 122的上方形成的公共电极 123的图 案； 以及在周边引线区中的通过钝化层过孔与第一连接电极 121连接的第二 连接电极 125的图案，其中第一连接电极 121和第二连接电极 125通过钝化 层过孔和栅极绝缘层过孔与栅线引线 113 电连接， 将栅驱动信号输入栅线 113。
本发明实施例的阵列基板中欧姆接触层 115的图案、有源层 116的图案 及像素电极 117的图案与图 1A和 1B所示的阵列基板中所处的位置不同。 像素电极 117的图案位于栅极绝缘层 114的图案和欧姆接触层 115的图案之 间，栅极绝缘层 114的图案位于栅极 112的图案和像素电极 117的图案之间； 欧姆接触层 115的图案位于有源层 116的图案和像素电极 117的图案之间， 此种结构构成了一种新型的薄膜晶体管结构，该结构可以允许实现通过六次 掩模工艺形成上述阵列基板， 降低了生产成本； 且可以实现沟道的免刻蚀形 成， 保证了生产良率。
基于上述阵列基板，本发明实施例还提供一种显示装置， 所述显示装置 包括阵列基板及彩膜基板， 其中所述阵列基板包括： 衬底基板以及在衬底基 板上依次形成的栅极的图案、 栅极绝缘层的图案、 像素电极的图案、 欧姆接 触层的图案、 有源层的图案和源漏电极的图案。 在显示装置中， 彩膜也可以 集成于阵列基板， 即所述显示装置还可以包括阵列基板及对向基板。
其中， 需要说明的是， 本发明实施例提供的显示装置， 其可以为： 液晶 面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪 等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本公开， 而并非对本公开的限制，有关技术领 域的普通技术人员， 在不脱离本公开的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本公开的范畴， 本公开的专 利保护范围应由权利要求限定。
本申请要求于 2013 年 10 月 12 日递交的中国专利申请第 201310476473.4号的优先权，在此全文引用上述中国专利申请公开的内容以 作为本申请的一部分。

Claims

权利要求书
1、 一种阵列基板， 包括衬底基板以及在衬底基板上依次形成的栅极的 图案、 栅极绝缘层的图案、 像素电极的图案、 欧姆接触层的图案、 有源层的 图案和源漏电极的图案， 其中，
所述像素电极的图案位于栅极绝缘层的图案和欧姆接触层的图案之间。
2、 根据权利要求 1所述的阵列基板， 其中所述栅极绝缘层的图案位于 所述栅极的图案和所述像素电极的图案之间；
所述欧姆接触层的图案位于所述有源层的图案和所述像素电极的图案 之间。
3、 根据权利要求 1或 2所述的阵列基板， 还包括： 在所述源漏电极的 图案上方依次形成的钝化层的图案以及公共电极的图案。
4、 一种阵列基板的制作方法， 包括： 在衬底基板上依次制作栅极的图 案、 栅极绝缘层的图案、 像素电极的图案、 欧姆接触层的图案、 有源层的图 案、 源漏电极的图案， 其特征在于， 通过一次掩模工艺形成所述像素电极的 图案和所述欧姆接触层的图案。
5、 根据权利要求 4所述的方法， 其中通过一次掩模工艺形成所述有源 层的图案和所述栅极绝缘层的图案。
6、 根据权利要求 5所述的方法， 其中所述在衬底基板上依次制作栅极 的图案、 栅极绝缘层的图案、 像素电极的图案、 欧姆接触层的图案、 有源层 的图案、 源漏电极的图案包括：
通过第一次掩模工艺在所述衬底基板上形成所述栅极的图案； 通过第二次掩模工艺形成所述像素电极的图案和所述欧姆接触层的图 案；
通过第三次掩模工艺形成所述有源层的图案和所述栅极绝缘层的图案； 和
通过第四次掩模工艺形成所述源漏电极的图案。
7、 根据权利要求 6所述的方法， 还包括：
通过第五次掩模工艺形成钝化层的图案； 和
通过第六次掩模工艺形成公共电极的图案。
8、 根据权利要求 6所述的方法， 其中所述第二次掩模工艺包括： 在第一次掩模工艺所得结构上依次形成像素电极薄膜和欧姆接触层薄 膜；
在所述欧姆接触层薄膜上方涂覆光刻胶， 利用半色调掩模板进行曝光、 显影后在对应源漏电极的区域形成光刻胶完全保留区域，在对应所述像素电 极的区域形成光刻胶半保留区域， 在其余区域形成光刻胶完全去除区域； 通过第一次刻蚀工艺去除所述光刻胶完全去除区域的所述像素电极薄 膜和所述欧姆接触层薄膜；
通过灰化工艺去除所述光刻胶半保留区域的光刻胶，通过第二次刻蚀工 艺去除所述光刻胶半保留区域的欧姆接触层薄膜； 以及
通过剥离工艺去除所述光刻胶完全保留区域的光刻胶。
9、 根据权利要求 6所述的方法， 其中，
在第一次掩模工艺和第二次掩模工艺之间，在栅极的图案上方形成栅极 绝缘层薄膜； 且
所述第三次掩模工艺包括：
在第二次掩模工艺之后， 在所述欧姆接触层的图案上方形成有源层薄 膜；
在所述有源层薄膜上涂覆光刻胶， 利用半色调掩模板进行曝光、显影后 在对应栅极的区域形成光刻胶完全保留区域，在对应栅线引线的区域形成光 刻胶完全去除区域， 其余区域形成光刻胶半保留区域；
通过第一次刻蚀工艺去除所述光刻胶完全去除区域的有源层薄膜和栅 极绝缘层薄膜；
通过灰化工艺去除所述光刻胶半保留区域的光刻胶，通过第二次刻蚀工 艺去除光刻胶半保留区域的有源层薄膜； 以及
通过剥离工艺去除光刻胶完全保留区域的光刻胶。
10、 一种显示装置， 其特征在于， 包括如权利要求 1-3任一项所述的阵 列基板。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080049208A (ko) * 2006-11-30 2008-06-04 삼성전자주식회사 박막 트랜지스터 기판 및 이의 제조 방법
CN102646713A (zh) * 2011-05-13 2012-08-22 京东方科技集团股份有限公司 一种薄膜晶体管液晶显示器的像素结构及其制造方法
KR101294691B1 (ko) * 2006-06-30 2013-08-08 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조방법
CN203561812U (zh) * 2013-10-12 2014-04-23 北京京东方光电科技有限公司 一种阵列基板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101198907B1 (ko) * 2006-07-28 2012-11-08 삼성디스플레이 주식회사 유기 박막 트랜지스터 기판 및 그 제조 방법
CN101561604B (zh) * 2008-04-17 2011-07-06 北京京东方光电科技有限公司 薄膜晶体管液晶显示器阵列基板结构及制造方法
CN102446925B (zh) * 2010-09-30 2015-05-20 京东方科技集团股份有限公司 阵列基板、液晶显示器及阵列基板的制造方法
US9496287B2 (en) * 2012-08-02 2016-11-15 Sharp Kabushiki Kaisha Semiconductor device and production method therefor
CN102832254B (zh) * 2012-09-10 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示面板
CN103219284B (zh) * 2013-03-19 2015-04-08 北京京东方光电科技有限公司 Tft阵列基板、tft阵列基板的制作方法及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101294691B1 (ko) * 2006-06-30 2013-08-08 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조방법
KR20080049208A (ko) * 2006-11-30 2008-06-04 삼성전자주식회사 박막 트랜지스터 기판 및 이의 제조 방법
CN102646713A (zh) * 2011-05-13 2012-08-22 京东方科技集团股份有限公司 一种薄膜晶体管液晶显示器的像素结构及其制造方法
CN203561812U (zh) * 2013-10-12 2014-04-23 北京京东方光电科技有限公司 一种阵列基板及显示装置

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