WO2014146349A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2014146349A1
WO2014146349A1 PCT/CN2013/076283 CN2013076283W WO2014146349A1 WO 2014146349 A1 WO2014146349 A1 WO 2014146349A1 CN 2013076283 W CN2013076283 W CN 2013076283W WO 2014146349 A1 WO2014146349 A1 WO 2014146349A1
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WIPO (PCT)
Prior art keywords
pixel
electrode
array substrate
display
pixel unit
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PCT/CN2013/076283
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English (en)
French (fr)
Inventor
刘金良
田广彦
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合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Publication of WO2014146349A1 publication Critical patent/WO2014146349A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134381—Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates

Definitions

  • Embodiments of the present invention relate to an array substrate and a display device. Background technique
  • the advanced super-dimensional field switching type liquid crystal display device is a horizontal electric field driving type liquid crystal display device in which a common electrode and a pixel electrode are disposed on an array substrate to form a horizontal electric field.
  • the high aperture ratio advanced super-dimensional field switching type liquid crystal display device has the common electrode 5 on the array substrate disposed on the pixel electrode 4, and the common electrode is integrated, and is disposed in the corresponding pixel region. There are slits.
  • a passivation layer 8 is provided between the common electrode 5 and the pixel electrode 4 for electrically insulating the common electrode 5 and the pixel electrode 4 to form a storage capacitor.
  • the array substrate of the high aperture ratio advanced super-dimensional field switching type liquid crystal display device includes: a gate line 1, a data line 2, a driving thin film transistor 3, a pixel electrode 4, a common electrode 5, and a pixel electrode 4 and a common electrode 5; a passivation layer 8; wherein the driving thin film transistor 3 includes a gate 31, a source 32 and a drain 33, wherein the gate 31 is connected to the gate line 1, the source 32 is connected to the data line 2, and the drain 33 is The pixel electrodes 4 are connected.
  • the array substrate 100 of the conventional high aperture ratio advanced super-dimensional field switching liquid crystal display device includes a display pixel region 101, a peripheral non-display pixel region 102, and a trace region 103.
  • the display pixel area 101 and the peripheral non-display pixel area 102 respectively include a plurality of pixel units formed by staggered gate lines and data lines, as shown in FIG. 1, and each pixel unit corresponds to one driving thin film transistor 3.
  • the display pixel area is mainly used for image display, and the surrounding non-display pixel area does not display an image.
  • the common electrode of the array substrate of the high-opening rate advanced super-dimensional field-switching liquid crystal display device is located on the surface of the substrate, the display pixel region has no common electrode line, and the common electrode is electrically connected to the common electrode line at the trace region 103 through the contact hole, so that Increase the aperture ratio of the pixels of the display pixel area.
  • the array substrate is further provided with a test area 104 in a peripheral region of the substrate during production, and the test area 104 is provided with a driving thin film transistor for detecting characteristics of a driving thin film transistor on the substrate. When the array substrate is bonded to the color filter substrate to form a display panel, the region is generally cut off.
  • test area is disposed on the periphery of the substrate display pixel area, although the structure and shape parameters of the driving thin film transistor of the test area and the driving thin film transistor of the display area are the same, The difference in microenvironment may cause a large difference between the characteristics of the driving thin film transistor in the test area and the characteristics of the driving thin film transistor in the display pixel area.
  • Embodiments of the present invention provide an array substrate and a display device.
  • the array substrate can detect characteristics of a driving thin film transistor after the test area around the pixel is cut off, and the detection result is more than the test result of the peripheral test area. The actual condition of driving the thin film transistor close to the display pixel region.
  • An embodiment of the present invention provides an array substrate, including: a transparent substrate including a display pixel region and a peripheral non-display pixel region; and a gate line and a data line disposed on the transparent substrate and intersecting each other
  • the gate line and the data line divide each of the display pixel area and the peripheral non-display pixel area into a plurality of pixel units, wherein each of the pixel units includes: a driving thin film transistor including a gate connected to the gate line a pole, a source connected to the data line, and a drain; a pixel electrode; and a common electrode disposed above the pixel electrode via a passivation layer, wherein the pixel electrodes of each of the pixel units are not electrically connected to each other
  • the common electrodes of the display pixel region are electrically connected to each other, and the common electrode of the peripheral non-display pixel region and the common electrode of the display pixel region are electrically insulated from each other, wherein each of the peripheral non-display pixel regions a via
  • the common electrodes of the respective pixel units of the peripheral non-display pixel area are electrically insulated from each other.
  • a via hole is disposed in the passivation layer of each of the pixel units of the peripheral non-display pixel region, so that a common corresponding to each of the pixel units of the peripheral non-display pixel region is
  • the electrode is electrically connected to the drain of the driving thin film transistor corresponding to the pixel unit through the via.
  • the pixel electrode position Above the drain At a position where the pixel electrode is connected to the drain, the pixel electrode position Above the drain.
  • the pixel electrode is located below the drain.
  • the via is disposed at a position of a corresponding drain of the pixel unit, and the common electrode corresponding to the pixel unit is directly electrically connected to the drain of the pixel unit through the via.
  • a color filter layer is further disposed between the pixel electrode and the common electrode, and the via hole penetrates through the color filter layer.
  • the gate lines and the data lines of the peripheral non-display pixel area are respectively provided with gate line test points and data line test points for applying the gate line signals and the data line signals.
  • the gate line test point and the data line test point are disposed in a peripheral area of the array substrate.
  • the embodiment of the present invention further provides a display device, including any of the array substrates provided by the embodiments of the present invention.
  • FIG. 1 is a schematic top plan view of a pixel unit of a peripheral non-display pixel area in the prior art
  • FIG. 2 is a cross-sectional view of the pixel unit of the prior art non-display pixel area shown in FIG. 1 along a-a;
  • FIG. 3 is a schematic top plan view of an array substrate in the prior art
  • FIG. 4 is a schematic plan view showing a pixel unit of a peripheral non-display pixel area according to an embodiment of the present invention
  • FIG. 5 is a cross-sectional view of a pixel unit of the peripheral non-display pixel area shown in FIG. 4 along a-a, in accordance with one embodiment of the present invention
  • FIG. 6 is a cross-sectional view of a pixel unit of the peripheral non-display pixel region shown in FIG. 4 along a-a, in accordance with another embodiment of the present invention. detailed description
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 4, FIG. 5 and FIG. 6, comprising: a transparent substrate 6 and gate lines 1 and data lines 2 arranged to intersect each other, the transparent substrate further including a display pixel area And the peripheral non-display pixel area, the gate line 1 and the data line 2 divide the display pixel area and the peripheral non-display pixel area into a plurality of pixel units, each of the pixel units further comprising a driving thin film transistor 3 and a pixel electrode And a common electrode disposed above the pixel electrode via a passivation layer, wherein the driving thin film transistor 3 includes a gate 31 connected to the gate line 1, a source 32 connected to the data line 2, and The drain electrodes 33 connected to the pixel electrodes are not in contact with each other.
  • the common electrodes included in each pixel unit of the display pixel region are connected to each other, and the common electrodes included in each pixel unit of the peripheral non-display pixel region are not connected to each other and are located in a common area of the peripheral non-display pixel region.
  • the electrodes are not electrically connected to the common electrode located in the display pixel region, that is, the common electrode located in the peripheral non-display pixel region is electrically insulated from the common electrode located in the display pixel region.
  • a via hole is provided in the passivation layer 8 of each pixel unit of the peripheral non-display pixel region, so that the common electrode corresponding to the pixel unit passes through the via hole and the drain of the driving thin film transistor 3 of the pixel unit
  • the pole 33 is electrically connected.
  • the common electrode is disposed on the top of the pixel electrode, wherein the "upper” and “lower” are based on the order of making each electrode film, for example, “below”
  • the pixel electrode is a relatively fabricated electrode
  • the "upper” common electrode is an electrode fabricated later.
  • the array substrate further includes other thin film or layer structures. As shown in FIG. 5 and FIG. 6, the array substrate further includes a gate insulating layer 7 on the gate 31, an active layer 11 and an ohmic contact layer, etc., in the present invention.
  • materials, thicknesses, formation methods, and the like of the gate insulating layer 7, the active layer 11, and the ohmic contact layer may employ parameters and methods commonly used in the art, for example, the active layer 11 is formed by a mask patterning process, where , do not give a detailed description.
  • the liquid crystal display device is divided into a horizontal electric field drive type liquid crystal display device and a vertical electric field drive type liquid crystal display device according to a method of driving liquid crystal, wherein the horizontal electric field drive type liquid crystal display device has a common electrode and a pixel formed on the array substrate. Electrode, through common electrode and pixel The pole forms a horizontal electric field to drive the liquid crystal.
  • an ADS (Advanced-Super Dimensional Switching) type liquid crystal display device an ADS (Advanced-Super Dimensional Switching) type liquid crystal display device.
  • the liquid crystal display device in which the common electrode on the array substrate is disposed on the upper surface of the pixel electrode is referred to as a HADS (High aperture Advanced-Super Dimensional Switching) type liquid crystal display device.
  • the array substrate provided by the embodiment of the invention can be applied to the HADS type liquid crystal display device described above.
  • a via hole is disposed in the passivation layer 8 of each pixel unit of the peripheral non-display pixel region, such that a common electrode corresponding to the pixel unit passes through the via hole and a drain of the driving thin film transistor of the pixel unit
  • the pole is electrically connected, that is, when the common electrode and the pixel electrode corresponding to the pixel unit of the peripheral non-display pixel area are separated by a passivation layer, a via hole is disposed in the passivation layer. If another layer structure is further disposed between the common electrode and the pixel electrode corresponding to the pixel unit, the via hole is simultaneously disposed in each layer structure between the first common electrode and the pixel electrode.
  • the common electrode corresponding to each pixel unit of the peripheral non-display pixel area is electrically connected to the drain of the pixel unit through the via hole, and the common electrode corresponding to the pixel unit may pass through the via hole and the pixel.
  • the drain of the cell is directly electrically connected, and a common electrode corresponding to the pixel cell may be electrically connected to the drain of the pixel cell through the via hole and other conductive layers.
  • the common electrode corresponding to the pixel unit can be electrically connected to the pixel electrode of the pixel unit through the via hole, thereby achieving electrical connection with the drain of the pixel unit.
  • the driving film is generally evaluated by detecting a drain by applying a gate line signal and a data line signal through a probe on a gate line and a data line corresponding to the driving thin film transistor, respectively.
  • the characteristics of the transistor are generally evaluated by detecting a drain by applying a gate line signal and a data line signal through a probe on a gate line and a data line corresponding to the driving thin film transistor, respectively. The characteristics of the transistor.
  • An embodiment of the present invention provides an array substrate, wherein a via hole is disposed in the passivation layer of each pixel unit of the peripheral non-display pixel region, so that a common electrode corresponding to the pixel unit passes through the via hole and the pixel
  • the drain of the driving thin film transistor of the cell is electrically connected.
  • the common electrode of each pixel unit of the peripheral non-display pixel area is electrically insulated from the common electrode located in the display pixel area.
  • the common electrode of the peripheral non-display pixel region on the array substrate is electrically connected to the drain, and the characteristics of the driving thin film transistor can be detected by the common electrode.
  • the shape and structure of the driving thin film transistor of the peripheral non-display pixel area and the driving thin film transistor of the display pixel area are the same, and the detection result is closer to the display pixel area driving thin film transistor characteristic with respect to the driving thin film transistor of the detecting test area.
  • the peripheral non-display pixel area of the array substrate is not cut off, and the characteristics of the driving thin film transistor of the display pixel area can be conveniently evaluated.
  • the respective common electrodes of the respective pixel units of the peripheral non-display pixel area are electrically insulated from each other.
  • Each pixel unit of the peripheral non-display pixel area respectively corresponds to one common electrode, that is, each of the pixel units respectively corresponds to a common electrode located at a position of the pixel unit thereof, and then each of the first common electrode and the second The common electrode is electrically insulated.
  • a via hole is disposed in the passivation layer of each pixel unit of the peripheral non-display pixel region, so that the common electrode corresponding to each pixel unit is electrically connected to the drain corresponding to the pixel unit through the via hole.
  • the peripheral non-display pixel area includes a plurality of pixel units, each of the pixel units respectively corresponding to one common electrode, and each of the pixel units has a via hole in the passivation layer, and each common electrode and the corresponding pixel respectively The drain of the unit is electrically connected.
  • the characteristic detection of the driving thin film transistor at a fixed position can be performed as needed. It is also possible to detect characteristics of a plurality of driving thin film transistors, and to evaluate overall whether the characteristics of the driving thin film transistors on the array substrate are good.
  • the pixel electrode is located below the drain. Specifically, as shown in FIG. 5, the pixel electrode 4 is located below the drain 33.
  • a passivation layer 8 is disposed between the drain and the common electrode 51, and a via hole is disposed in the passivation layer 8, so that the common electrode 51 is electrically connected to the drain electrode 33 through the via hole.
  • the via is disposed at a position of a corresponding drain of the pixel unit, and the common electrode corresponding to the pixel unit is directly electrically connected to the drain of the pixel unit through the via.
  • the passivation layer is provided with via holes in a region corresponding to the drain.
  • the pixel electrode is located above the drain. Specifically, as shown in Fig. 6, the pixel electrode 4 is located above the drain electrode 33 and under the common electrode 51. If a via hole is provided in the passivation layer, a corresponding common electrode can be electrically connected to the pixel electrode, and further electrically connected to the drain through the pixel electrode.
  • the via is disposed at a position of a corresponding drain of the pixel unit, and the common electrode corresponding to the pixel unit is directly electrically connected to the drain of the pixel unit through the via.
  • the passivation layer and the pixel electrode corresponding to the region above the drain are each provided with a via, and the common electrode is directly electrically connected to the drain through the via. Due to the same via size, the common electrode is directly electrically connected to the drain through the via hole in the pixel electrode and the passivation layer, and the contact resistance is reduced by electrically connecting the drain electrode through the pixel electrode, thereby driving the thin film transistor. Feature detection is more accurate.
  • a color filter layer is further disposed between the pixel electrode and the common electrode, and the via hole penetrates through the color filter layer.
  • the array substrate is provided with a passivation layer and a color filter layer between the common electrode and the pixel electrode, and then a via hole is disposed in the passivation layer and the color filter layer to make the common electrode and the drain electrode connection.
  • the gate lines and the data lines of the peripheral non-display pixel area are respectively provided with gate line test points and data line test points for inputting the gate line signal and the data line signal.
  • a voltage signal is generally applied to the gate and source of the driving thin film transistor, and the characteristics of the driving thin film transistor are evaluated by detecting the drain signal. Further, since the gate and the gate line are connected, and the source and the data line are connected, the gate line signal and the data line signal are respectively applied to the gate line and the data line corresponding to the driving thin film transistor by the probe.
  • the portions of the corresponding probe that are in contact with the gate and data lines are gate test points and data line test points.
  • a gate line test point and a data line test point are respectively disposed on the corresponding gate line and the data line of the driving thin film transistor.
  • the gate line test point and the data line test point may be a portion electrically connected to the gate line or the data line, or may be a fixedly disposed lead.
  • the gate line test point and the data line test point may be directly a portion where the gate line and the data line leak on the surface of the substrate.
  • the gate line test point and the data line test point may be separately disposed in a peripheral area of the array substrate.
  • the gate line test point and the data line test point may be disposed in the trace area 103 of the array substrate to facilitate detection of characteristics of the driving thin film transistor.
  • An embodiment of the present invention also provides a display device comprising the array substrate of any of the above embodiments.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color film substrate.
  • the pixel electrode of each pixel unit of the display pixel region of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display further includes a backlight that provides backlighting for the array substrate.
  • the liquid crystal display device may be a liquid crystal display and any display product or component such as a television, a digital camera, a mobile phone, a tablet computer, or the like including a liquid crystal display.
  • Another example of the display device is an organic electroluminescence display device in which a pixel electrode of each pixel unit of a display pixel region of an array substrate is used as an anode or a cathode for driving organic light emission The material is illuminated for display operation.
  • a via hole is disposed in the passivation layer of each pixel unit of the peripheral non-display pixel region so as to correspond to the pixel unit of the peripheral non-display pixel region.
  • the common electrode is electrically connected to the drain of the driving thin film transistor of the pixel unit through the via.
  • the common electrode of the peripheral non-display pixel area is electrically insulated from the common electrode of the display pixel area. The characteristics of the driving thin film transistor can be detected by the common electrode of the peripheral non-display pixel area, and the detection result is closer to the actual condition of the driving thin film transistor of the display pixel area than the prior art, and can be conveniently located around the array substrate.
  • the test area is cut off and tested.

Abstract

提供了一种阵列基板及显示装置；该阵列基板包括：透明基板（6），包括显示像素区域和周边非显示像素区域；栅线（1）和数据线（2）相互交叉设置在透明基板（6）上，彼此交叉设置的栅线（1）和数据线（2）将显示像素区域和周边非显示像素区域的每一个划分为多个像素单元；其中每个像素单元包括：驱动薄膜晶体管（3），包括与栅线（1）相连的栅极（31）、与数据线（2）相连的源极（32）以及漏极（33）；像素电极；公共电极，隔着钝化层设置于像素电极上方；每个像素单元的像素电极互不电连接，显示像素区域的公共电极彼此电连接，周边非显示像素区域的公共电极与显示像素区域的公共电极彼此电绝缘；其中周边非显示像素区域的每个像素单元的钝化层（8）中设置有过孔，使得与周边非显示区域的每个像素单元对应的公共电极通过过孔与对应像素单元的驱动薄膜晶体管（3）的漏极（33）电连接。

Description

阵列基板及显示装置 技术领域
本发明的实施例涉及一种阵列基板及显示装置。 背景技术
高级超维场开关型液晶显示装置是一种水平电场驱动型液晶显示装置， 其是在阵列基板上设置公共电极和像素电极以形成水平电场。 如图 1、 图 2 所示， 高开口率高级超维场开关型液晶显示装置是将阵列基板上的公共电极 5设置在像素电极 4的上面， 公共电极为一个整体， 在对应像素区域内设置 有狭缝。在公共电极 5和像素电极 4之间设置有钝化层 8,用于使公共电极 5 和像素电极 4电绝缘， 形成存储电容。 具体地， 高开口率高级超维场开关型 液晶显示装置的阵列基板包括： 栅线 1、 数据线 2、 驱动薄膜晶体管 3、 像素 电极 4、公共电极 5以及位于像素电极 4和公共电极 5之间的钝化层 8;其中， 驱动薄膜晶体管 3包括栅极 31、 源极 32和漏极 33, 其中， 栅极 31和栅线 1 相连， 源极 32和数据线 2相连， 漏极 33和像素电极 4相连。
如图 3所示， 现有的高开口率高级超维场开关型液晶显示装置的阵列基 板 100, 包括显示像素区域 101、 周边非显示像素区域 102和走线区域 103。 显示像素区域 101和周边非显示像素区域 102分别包括多个由交错设置的栅 线和数据线形成的像素单元， 如图 1所示， 且每一像素单元对应一个驱动薄 膜晶体管 3。 显示像素区域主要用于图像显示， 周边非显示像素区域不显示 图像。 高开口率高级超维场开关型液晶显示装置的阵列基板的公共电极位于 基板表面，显示像素区域无公共电极线，公共电极通过接触孔与走线区域 103 处的公共电极线电连接， 这样可以提高显示像素区域的像素的开口率。 阵列 基板在生产过程中在所述基板的周边区域还设置有测试区 104, 所述测试区 104设置有驱动薄膜晶体管， 用于检测基板上驱动薄膜晶体管的特性。 当阵 列基板与彩膜基板贴合， 形成显示面板后， 该区域一般会被切掉。 然而， 由 于测试区设置在基板显示像素区域的外围， 尽管测试区的驱动薄膜晶体管与 显示区域的驱动薄膜晶体管的结构和形状参数相同， 但由于工艺制作过程中 微观环境的差异可能会使测试区的驱动薄膜晶体管特性与显示像素区域的驱 动薄膜晶体管特性存在较大差异。 另外， 在产品画质检查过程中出现残像或 对比度不足等不良而需要检测驱动薄膜晶体管的特性时， 由于周边测试区已 被切掉， 而显示像素区域和周边非显示像素区域的驱动薄膜晶体管均被钝化 层覆盖， 阵列基板上驱动薄膜晶体管的特性无法检测， 会对后期的产品解析 造成困扰。 发明内容
本发明的实施例提供一种阵列基板及显示装置， 所述阵列基板可在像素 周边的测试区域被切掉后对驱动薄膜晶体管的特性进行检测， 且检测结果相 比周边测试区的测试结果更接近显示像素区驱动薄膜晶体管的实际状况。
本发明的实施例提供了一种阵列基板， 包括： 透明基板， 包括显示像素 区域和周边非显示像素区域； 以及栅线和数据线， 相互交叉设置在所述透明 基板上， 彼此交叉设置的所述栅线和数据线将所述显示像素区域和周边非显 示像素区域的每一个划分为多个像素单元， 其中每个所述像素单元包括： 驱 动薄膜晶体管， 包括与所述栅线相连的栅极、 与所述数据线相连的源极、 以 及漏极； 像素电极； 以及公共电极， 隔着钝化层设置于所述像素电极上方， 其中每个所述像素单元的像素电极互不电连接， 所述显示像素区域的公共电 极彼此电连接， 且所述周边非显示像素区域的公共电极与所述显示像素区域 的公共电极彼此电绝缘， 其中所述周边非显示像素区域的每个所述像素单元 的所述钝化层中设置有过孔， 使得与所述周边非显示像素区域的每个所述像 的漏极电连接。
可选的， 周边非显示像素区域的各像素单元分别对应的公共电极彼此电 绝缘。
可选的， 所述周边非显示像素区域的每个所述像素单元的所述钝化层中 均设置有过孔， 使得与所述周边非显示像素区域的每个所述像素单元对应的 公共电极通过所述过孔与对应所述像素单元的驱动薄膜晶体管的漏极电连 接。
可选的， 在所述像素电极与所述漏极相连接的位置处， 所述像素电极位 于所述漏极上方。
可选的， 在所述像素电极与所述漏极相连接的位置处， 所述像素电极位 于所述漏极下方。
可选的， 所述过孔设置在像素单元的对应漏极的位置处， 该像素单元对 应的公共电极通过所述过孔与该像素单元的漏极直接电连接。
可选的， 所述像素电极与所述公共电极之间还设置有彩色滤光层， 所述 过孔贯穿所述彩色滤光层。
可选的， 周边非显示像素区域的栅线和数据线分别设置有用于施加栅线 信号和数据线信号的栅线测试点和数据线测试点。
可选的， 所述栅线测试点和数据线测试点设置在阵列基板的周边区域。 本发明实施例还提供了一种显示装置， 包括本发明实施例提供的任一所 述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中周边非显示像素区域的像素单元俯视结构示意图； 图 2为图 1所示的现有技术的周边非显示像素区域的像素单元沿 a-a，剖 面示意图；
图 3为现有技术中阵列基板的俯视结构示意图；
图 4为本发明实施例提供的周边非显示像素区域的像素单元俯视结构示 意图；
图 5为根据本发明一个实施例的图 4所示的周边非显示像素区域的像素 单元沿 a-a，的剖面示意图；
图 6为根据本发明另一实施例的图 4所示的周边非显示像素区域的像素 单元沿 a-a，的剖面示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供了一种阵列基板， 如图 4、 图 5和图 6所示包括： 透明基板 6和相互交叉设置的栅线 1和数据线 2, 所述透明基板进一步包括 显示像素区域和周边非显示像素区域， 所述栅线 1和数据线 2将所述显示像 素区域和周边非显示像素区域划分为多个像素单元， 每个所述像素单元进一 步包括驱动薄膜晶体管 3、 像素电极以及隔着钝化层设置于所述像素电极上 方的公共电极， 其中， 所述驱动薄膜晶体管 3包括与所述栅线 1相连的栅极 31、 与所述数据线 2相连的源极 32和与所述像素电极相连的漏极 33, 各像 素单元的像素电极互不接触。
在本发明的实施例中， 显示像素区域的各像素单元所包括的公共电极彼 此相连， 而周边非显示像素区域的各像素单元所包括的公共电极彼此不相连 且位于周边非显示像素区域的公共电极与位于显示像素区域的公共电极未电 连接， 也就是， 位于周边非显示像素区域的公共电极与位于显示像素区域的 公共电极电绝缘。 而且， 在周边非显示像素区域的每个像素单元的钝化层 8 中设置有过孔， 使得与所述像素单元对应的公共电极通过所述过孔与该像素 单元的驱动薄膜晶体管 3的漏极 33电连接。
需要说明的是， 本发明的实施例中所述公共电极设置在所述像素电极的 上面， 其中， 所述 "上" 、 "下" 以制作各电极薄膜的顺序为依据， 例如在 "下" 的像素电极为相对在先制作的电极， 在 "上" 的公共电极为相对在后 制作的电极。 且阵列基板上还包括其他薄膜或层结构， 如图 5、 图 6所示， 阵列基板还包括位于栅极 31上面的栅绝缘层 7、 有源层 11以及欧姆接触层 等，在本发明的实施例中，栅绝缘层 7、有源层 11以及欧姆接触层等的材料、 厚度、 形成方法等可采用本领域常用的参数及方法， 例如， 通过掩模构图工 艺形成有源层 11 , 这里， 对其不做具体描述。
需要说明的是， 液晶显示装置按照驱动液晶的方式分为水平电场驱动型 液晶显示装置和垂直电场驱动型液晶显示装置， 其中， 水平电场驱动型液晶 显示装置在阵列基板上形成有公共电极和像素电极， 通过公共电极和像素电 极形成水平电场以驱动液晶。 例如 ADS ( Advanced-Super Dimensional Switching, 高级超维场开关）型液晶显示装置。 其中， 阵列基板上公共电极 设置在像素电极的上面的液晶显示装置称之为 HADS ( High aperture Advanced-Super Dimensional Switching, 高开口率高级超维场开关）型液晶显 示装置。本发明实施例提供的阵列基板可适用于上述 HADS型液晶显示装置。
具体地， 在周边非显示像素区域的每个像素单元的钝化层 8中设置有过 孔， 使得与所述像素单元对应的公共电极通过所述过孔与该像素单元的驱动 薄膜晶体管的漏极电连接， 即当周边非显示像素区域的所述像素单元对应的 公共电极和像素电极之间隔着钝化层， 则在所述钝化层中设置过孔。 若在所 述像素单元对应的公共电极和像素电极之间还设置有其他层结构， 则所述过 孔同时设置在第一公共电极和像素电极之间的各层结构中。
需要说明的是， 与周边非显示像素区域的每个像素单元对应的公共电极 通过过孔与该像素单元的漏极电连接， 可以是与像素单元对应的公共电极通 过所述过孔与该像素单元的漏极直接电连接， 还可以是与像素单元对应的公 共电极通过所述过孔以及其他导电层与该像素单元的漏极电连接。 例如， 由 于漏极与像素电极电连接， 与像素单元对应的公共电极可以通过所述过孔与 该像素单元的像素电极电连接， 进而实现与该像素单元的漏极的电连接。
另外， 在对驱动薄膜晶体管进行特性检测时， 一般通过在与该驱动薄膜 晶体管对应的栅线和数据线上分别通过探针施加栅线信号和数据线信号， 通 过检测漏极来评估该驱动薄膜晶体管的特性。
本发明实施例提供了一种阵列基板， 在周边非显示像素区域的每个像素 单元的所述钝化层中设置有过孔， 使得与像素单元对应的公共电极通过所述 过孔与该像素单元的驱动薄膜晶体管的漏极电连接。 而且， 周边非显示像素 区域的每个像素单元的公共电极与位于显示像素区域的公共电极电绝缘。 所 述阵列基板上的周边非显示像素区域的公共电极与漏极电连接， 可通过所述 公共电极来检测所述驱动薄膜晶体管的特性。 而且， 周边非显示像素区域的 驱动薄膜晶体管和显示像素区域的驱动薄膜晶体管的形状和结构相同， 相对 于检测测试区的驱动薄膜晶体管， 其检测结果更接近显示像素区驱动薄膜晶 体管特性。 且所述阵列基板的周边非显示像素区域不会被切掉， 可方便对显 示像素区域的驱动薄膜晶体管的特性进行评估。 备选地， 周边非显示像素区域的各像素单元分别对应的公共电极彼此电 绝缘。 周边非显示像素区域的各像素单元分别对应一个公共电极， 即每一所 述像素单元分别与位于其像素单元位置处的公共电极——对应， 则各所述第 一公共电极和所述第二公共电极电绝缘。
进一步的， 在周边非显示像素区域的每个像素单元的所述钝化层中均设 置有过孔， 使得各像素单元对应的公共电极通过所述过孔与该像素单元对应 的漏极电连接。 具体地， 周边非显示像素区域包括多个像素单元， 每一像素 单元分别对应一个公共电极,每一个像素单元中的所述钝化层中均设置过孔， 则各公共电极分别与对应的像素单元的漏极电连接。 则可根据需要对固定位 置的驱动薄膜晶体管进行特性检测。还可以检测多个驱动薄膜晶体管的特性， 整体评估阵列基板上驱动薄膜晶体管的特性是否良好。
可选的， 在所述像素电极与所述漏极相连接的位置处， 所述像素电极位 于所述漏极下方。 具体地， 如图 5所示， 像素电极 4位于漏极 33的下面。 在 漏极和公共电极 51之间设置有钝化层 8, 则所述钝化层 8中设置过孔， 使得 公共电极 51通过所述过孔与漏极 33电连接。
备选地， 所述过孔设置在像素单元的对应漏极的位置处， 该像素单元对 应的公共电极通过所述过孔与该像素单元的漏极直接电连接。 如图 5所示， 钝化层在对应漏极的区域设置有过孔。 这样， 相同过孔尺寸条件下， 公共电 极通过所述过孔直接与所述漏极电连接，相对于通过像素电极与漏极电连接， 减小了接触电阻， 使驱动薄膜晶体管的特性检测结果相对更加准确。
可选的， 在所述像素电极与所述漏极相连接的位置处， 所述像素电极位 于所述漏极上方。 具体地， 如图 6所示， 像素电极 4位于漏极 33的上面， 且 位于公共电极 51的下面。若在所述钝化层中设置有过孔，可以使得对应的公 共电极与所述像素电极电连接， 进而通过所述像素电极与所述漏极电连接。
可选地， 所述过孔设置在像素单元的对应漏极的位置处， 该像素单元对 应的公共电极通过所述过孔与该像素单元的漏极直接电连接。 如图 6所示， 钝化层和像素电极对应漏极上方的区域均设置有过孔， 所述公共电极通过所 述过孔直接与所述漏极电连接。 由于相同过孔尺寸条件下， 公共电极通过所 述像素电极和钝化层中的过孔直接与漏极电连接相对于通过像素电极与漏极 电连接减小了接触电阻， 使得驱动薄膜晶体管的特性检测更加准确。 可选的， 所述像素电极与所述公共电极之间还设置有彩色滤光层， 所述 过孔贯穿所述彩色滤光层。 具体地， 阵列基板在公共电极和像素电极之间设 置有钝化层以及彩色滤光层， 则在所述钝化层和彩色滤光层中均设置过孔， 以使得公共电极与漏极电连接。
可选的， 周边非显示像素区域的栅线和数据线分别设置有用于输入栅线 信号和数据线信号的栅线测试点和数据线测试点。
需要说明的是， 在对驱动薄膜晶体管进行特性检测时， 一般是在驱动薄 膜晶体管的栅极和源极添加电压信号， 通过检测漏极信号评估该驱动薄膜晶 体管的特性是否良好。 又由于栅极和栅线相连、 源极和数据线相连， 因此一 般通过利用探针向与该驱动薄膜晶体管对应的栅线和数据线分别施加栅线信 号和数据线信号。 对应的探针与栅线和数据线接触的部分为栅线测试点和数 据线测试点。 且为了更方便的对驱动薄膜晶体管的特性进行测试， 在所述驱 动薄膜晶体管对应的栅线和数据线上分别设置一个栅线测试点和数据线测试 点。 所述栅线测试点和数据线测试点可以是与栅线或数据线电连接的部分， 也可以是固定设置的引线。 例如， 所述栅线测试点和数据线测试点可以直接 是栅线和数据线棵漏在基板表面上的部分。
可选的， 所述栅线测试点和数据线测试点可单独设置在阵列基板的周边 区域。 具体地， 如图 3所示， 所述栅线测试点和数据线测试点可以设置在阵 列基板的走线区域 103, 方便对驱动薄膜晶体管的特性进行检测。
本发明的实施例还提供了一种显示装置， 其包括上述任一实施例的阵列 基板。
该显示装置的一个示例为液晶显示装置， 其中， 阵列基板与对置基板彼 此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为彩膜 基板。 阵列基板的显示像素区域的每个像素单元的像素电极用于施加电场对 液晶材料的旋转的程度进行控制从而进行显示操作。 在一些示例中， 该液晶 显示器还包括为阵列基板提供背光的背光源。
所述液晶显示装置可以为液晶显示器以及包括液晶显示器的电视、 数码 相机、 手机、 平板电脑等任何具有显示功能的产品或者部件。
该显示装置的另一个示例为有机电致发光显示装置， 其中， 阵列基板的 显示像素区域的每个像素单元的像素电极作为阳极或阴极用于驱动有机发光 材料发光以进行显示操作。
本发明实施例提供的阵列基板及显示装置， 在周边非显示像素区域的每 个像素单元的所述钝化层中均设置有过孔， 使得与周边非显示像素区域的所 述像素单元对应的公共电极通过所述过孔与该像素单元的驱动薄膜晶体管的 漏极电连接。 而且， 周边非显示像素区域的公共电极与显示像素区域的公共 电极电绝缘。 可通过所述周边非显示像素区域的公共电极来检测所述驱动薄 膜晶体管的特性， 相对于现有技术其检测结果更加接近显示像素区域的驱动 薄膜晶体管的实际状况， 且可方便在阵列基板周边测试区域被切掉后进行检 测。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保 护范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种阵列基板， 包括：
透明基板， 包括显示像素区域和周边非显示像素区域； 以及
栅线和数据线， 相互交叉设置在所述透明基板上， 彼此交叉设置的所述 栅线和数据线将所述显示像素区域和周边非显示像素区域的每一个划分为多 个像素单元， 其中每个所述像素单元包括：
驱动薄膜晶体管， 包括与所述栅线相连的栅极、 与所述数据线相连 的源极、 以及漏极；
像素电极； 以及
公共电极， 隔着钝化层设置于所述像素电极上方，
其中每个所述像素单元的像素电极互不电连接， 所述显示像素区域的公 共电极彼此电连接， 且所述周边非显示像素区域的公共电极与所述显示像素 区域的公共电极彼此电绝缘，
其中所述周边非显示像素区域的每个所述像素单元的所述钝化层中设置 有过孔， 使得与所述周边非显示像素区域的每个所述像素单元对应的公共电 极通过所述过孔与对应所述像素单元的驱动薄膜晶体管的漏极电连接。
2、根据权利要求 1所述的阵列基板，其中所述周边非显示像素区域的各 像素单元分别对应的公共电极彼此电绝缘。
3、根据权利要求 1所述的阵列基板，其中在所述像素电极与所述漏极相 连接的位置处， 所述像素电极位于所述漏极上方。
4、根据权利要求 1所述的阵列基板，其中在所述像素电极与所述漏极相 连接的位置处， 所述像素电极位于所述漏极下方。
5、 根据权利要求 4 所述的阵列基板， 其中在每个所述像素单元中， 每 个所述像素单元对应的公共电极通过在对应于漏极的位置处设置在所述钝化 层中的所述过孔与该像素单元的漏极直接电连接。
6、 根据权利要求 3 所述的阵列基板， 其中在每个所述像素单元中， 每 个所述像素单元对应的公共电极通过在对应于漏极的位置处设置在所述钝化 层中的所述过孔以及设置在所述像素电极中的过孔与该像素单元的漏极直接 电连接。
7、根据权利要求 3所述的阵列基板， 其中在每个所述像素单元中， 所述 每个所述像素单元对应的公共电极通过在对应于漏极的位置处设置在所述钝 化层中的所述过孔与该像素单元的像素电极电连接， 从而与该像素单元的漏 极电连接。
8、根据权利要求 1所述的阵列基板，其中所述像素电极与所述公共电极 之间还设置有彩色滤光层， 所述过孔贯穿所述彩色滤光层。
9、根据权利要求 1所述的阵列基板，其中所述周边非显示像素区域的栅 线和数据线分别设置有用于施加栅线信号和数据线信号的栅线测试点和数据 线测试点。
10、 根据权利要求 9所述的阵列基板， 其中所述栅线测试点和数据线测 试点设置在阵列基板的周边区域。
11、 一种显示装置， 包括：
权利要求 1-10任一项所述的阵列基板； 以及
对置基板， 与所述阵列基板对盒而形成所述显示装置。
12、 根据权利要求 11 所述的显示装置， 其中所述显示装置为液晶显示 装置。
13、根据权利要求 12所述的显示装置，其中所述液晶显示装置还包括位 于所述阵列基板与所述对置基板直接的液晶层，且所述对置基板是彩膜基板。
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