WO2018214637A1 - 薄膜晶体管测试装置、测试方法及阵列基板 - Google Patents

薄膜晶体管测试装置、测试方法及阵列基板 Download PDF

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Publication number
WO2018214637A1
WO2018214637A1 PCT/CN2018/080708 CN2018080708W WO2018214637A1 WO 2018214637 A1 WO2018214637 A1 WO 2018214637A1 CN 2018080708 W CN2018080708 W CN 2018080708W WO 2018214637 A1 WO2018214637 A1 WO 2018214637A1
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Prior art keywords
thin film
film transistor
substrate
drain
source
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PCT/CN2018/080708
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English (en)
French (fr)
Inventor
马彬
崔子巍
尹岩岩
田鹏程
李鑫
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/099,345 priority Critical patent/US20210041491A1/en
Publication of WO2018214637A1 publication Critical patent/WO2018214637A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to the field of display, and in particular to a thin film transistor test device, a test method, and an array substrate.
  • a display screen such as a liquid crystal panel has a sufficiently high pixel density and a wide color gamut to satisfy the requirements for image quality and picture saturation.
  • a higher pixel density Pixels Per Inch, PPI
  • PPI Pixel Per Inch
  • many defects are related to the switching characteristics of a thin film transistor (TFT) on an array substrate. Therefore, if the electrical characteristics of the TFT (especially the TFT in the display area) switch can be accurately monitored, the accurate monitoring of the defect can be accurately performed, which is advantageous for further improvement.
  • a thin film transistor testing apparatus includes: a substrate; a thin film transistor disposed on the substrate, the thin film transistor including an active layer, a source and a drain, a gate electrode and a gate insulating layer; a light shielding layer disposed on a side of the active layer away from the substrate to shield at least an exposed portion of the active layer; a first electrode layer a first electrode layer connected to one of the drain and the source; and a second electrode layer disposed on the first electrode layer away from the substrate via an intermediate insulating layer Surfacely, the second electrode layer is connected to at least one of the drain and the source.
  • the thin film transistor testing device further includes: a first resistor, two ends of the first resistor being respectively connected to one of the drain and the source and the second electrode layer.
  • the thin film transistor testing device further includes: a second resistor, two ends of the second resistor being respectively connected to the other of the drain and the source and the second electrode layer .
  • the substrate is an array substrate.
  • the thin film transistor further includes: an insulating layer covering at least the source, the drain, and a surface of the first electrode layer away from the substrate, the light shielding A layer is formed on a surface of the insulating layer remote from the substrate.
  • the thin film transistor further includes: an insulating layer covering at least the source, the drain, and a surface of the first electrode layer away from the substrate, the light shielding The layer is at least a portion of the insulating layer, and at least a portion of the insulating layer is added with a light blocking material.
  • the light shielding layer is formed of a black resin.
  • the thin film transistor test apparatus is for use with an array substrate, wherein the substrate acts as a substrate for the array substrate.
  • the first electrode layer and the second electrode layer are formed of a light transmissive conductive material.
  • the source and drain are separated from each other, respectively in contact with the active layer, and a portion of the active layer is exposed.
  • the thin film transistor test apparatus further includes a plurality of terminals connected to the source, the drain, and the first electrode layer, respectively, for electrical connection to the outside.
  • an array substrate comprising: the thin film transistor testing device according to any of the embodiments.
  • the array substrate further includes: an array formed of other thin film transistors formed on the substrate; and a common electrode.
  • a thin film transistor testing method including: providing a thin film transistor testing device, the thin film transistor testing device comprising: a substrate; a thin film transistor on the substrate, the thin film transistor including an active layer a source, a drain, a gate, and a gate insulating layer; a light shielding layer disposed on a side of the active layer away from the substrate to shield at least an exposed portion of the active layer a first electrode layer, the first electrode layer being connected to one of the drain and the source; and a second electrode layer disposed on the first electrode layer via an intermediate insulating layer On a surface away from the substrate, the second electrode layer is connected to at least one of the drain and the source, and to the source, the drain of the thin film transistor, and One or more of the gates apply a voltage and detect corresponding electrical parameters.
  • the substrate includes a substrate for an array substrate.
  • providing a thin film transistor test device includes disposing a thin film transistor test device in a non-display area of an array substrate.
  • the thin film transistor in the thin film transistor test device may be configured to simulate a thin film transistor in a display region of the array substrate.
  • the thin film transistor testing device further includes: a first resistor, two ends of the first resistor being respectively connected to the second electrode layer and one of the drain and the source, The first resistor is configured such that a divided voltage on the second electrode layer can simulate a voltage of a common electrode of the array substrate.
  • the thin film transistor testing device further includes: a second resistor, two ends of the second resistor being respectively connected to the second electrode layer and the other of the drain and the source
  • the second resistor is configured such that a divided voltage on the second electrode layer is capable of simulating a voltage of a common electrode on the array substrate.
  • the thin film transistor further includes: an insulating layer covering at least the source, the drain, and a surface of the first electrode layer away from the substrate, the light shielding A layer is formed on a surface of the insulating layer remote from the substrate.
  • the thin film transistor further includes: an insulating layer covering at least the source, the drain, and a surface of the first electrode layer away from the substrate, the light shielding The layer is at least a portion of the insulating layer, and at least a portion of the insulating layer is added with a light blocking material.
  • the first electrode layer and the second electrode layer are formed of a light transmissive conductive material.
  • the source and drain are separated from each other, respectively in contact with the active layer, and a portion of the active layer is exposed.
  • the accuracy of detection can be improved, and substrate yield and performance can be improved.
  • FIG. 1A is a schematic cross-sectional view showing the structure of a thin film transistor test apparatus according to an embodiment of the present disclosure
  • FIG. 1B is a schematic cross-sectional view showing the structure of a thin film transistor testing device according to another embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a portion of a conventional thin film transistor test apparatus
  • FIG. 3 shows a schematic top view of a portion of a thin film transistor testing device in accordance with an embodiment of the present disclosure
  • FIG. 4 is a flow chart showing a test method according to an embodiment of the present disclosure.
  • FIG. 5 is a flow chart showing a test method according to another embodiment of the present disclosure.
  • FIG. 6 shows a schematic flow chart of a test method according to still another embodiment of the present disclosure.
  • Figure 7 is a view showing a test result of the prior art thin film transistor test device before the box is placed;
  • FIG. 8 is a view showing a test result of the conventional thin film transistor test apparatus after the counter box is placed.
  • a thin film transistor test group device (also commonly referred to as a test teg) is usually disposed in a non-display area of an array substrate of a thin film transistor liquid crystal display (TFT-LCD).
  • TFT-LCD thin film transistor liquid crystal display
  • the thin film transistor in the thin film transistor test device is used to simulate the thin film transistor of the display region, thereby realizing the detection of the TFT switching characteristics of the display region.
  • the inventors have found that in the current test group apparatus, it is ubiquitous that the test result is difficult to accurately reflect the switching characteristics of the TFT in the actual display area.
  • the inventors have conducted in-depth research and a large number of experiments and found that this possible reason is: for the thin film transistor disposed in the test group device in the non-display area, the working environment and the work of the thin film transistor disposed in the display area There are differences in the environment. Therefore, in the prior art, when testing with the test set device, the influence of the actual environment in the display area on the switching characteristics of the thin film transistor is not considered, thereby causing the switching characteristics of the thin film transistor obtained by the test set device, and The actual switching characteristics of the TFTs in the display area do not match.
  • the present disclosure proposes a thin film transistor testing device.
  • the thin film transistor test device can be adapted to be disposed in a non-display area of the array substrate.
  • the switching characteristics of the thin film transistor in the display region of the array substrate can be evaluated by testing the thin film transistor test device, for example, before the array substrate and the substrate (e.g., pixel substrate, etc.) mated with the array substrate.
  • FIG. 1A shows a schematic cross-sectional view of a structure of a thin film transistor test apparatus according to an embodiment of the present disclosure.
  • the thin film transistor test apparatus may include a substrate 100 and a thin film transistor 200 disposed on the substrate 100.
  • the thin film transistor 200 may include an active layer 220, a source 230 and a drain 240, a gate 210, and a gate insulating layer 215.
  • a gate 210 is disposed over a substrate 100, and a gate insulating layer 215 is shown formed over the substrate on which the gate 210 is formed, overlying the gate 210.
  • the active layer 220 is formed on the gate insulating layer 215.
  • the active layer 220 may be formed of a semiconductor material.
  • the source 230 and the drain 240 are formed in contact with the active layer 220. Although in FIG. 1A, the source 230 and the drain 240 are each shown as being partially formed on the active layer 220 and another portion covering the side of the active layer 220, it is apparent that the present disclosure is not limited thereto.
  • the source 230 and the drain 240 are separated from each other such that a portion of the active layer 220 is exposed.
  • Source 230 and drain 240 may each be formed of a conductive material such as, but not limited to, metal or polysilicon or the like.
  • the thin film transistor 200 may have substantially the same structure as the thin film transistor disposed in the display region of the array substrate.
  • the thin film transistor disposed in the display region of the array substrate may have substantially the same gate, gate insulating layer, active layer, source, and drain as the thin film transistor 200 disposed in the non-display region.
  • the gate, the gate insulating layer, the active layer, the source and the drain of the thin film transistor disposed in the display region of the array substrate may be formed as gates respectively in the thin film transistor 200 disposed in the non-display region
  • the gate insulating layer, the active layer, the source and the drain have substantially the same size and are formed from substantially the same material using substantially the same process.
  • the thin film transistor test device may further include a light shielding layer 250.
  • the light shielding layer 250 may be disposed on a side of the active layer 220 away from the substrate 100 as shown in FIG. 1A.
  • the light shielding layer 250 may be disposed corresponding to the active layer 220.
  • a light shielding layer may be used to shield at least the exposed portion of the active layer.
  • a light shielding layer can be used to shield at least a portion of the active layer 220 that is exposed through the source and source.
  • the light shielding layer 250 may be formed using a black resin.
  • the light shielding layer 250 may also be at least a portion of a certain insulating layer to which at least a portion of the light shielding material is added.
  • the influence of irradiation for example, ultraviolet (UV)
  • UV ultraviolet
  • the thin film transistor testing device may further include a first electrode layer 300 and a second electrode layer 400.
  • the first electrode layer 300 may be connected to one of a source and a drain (eg, the drain 240).
  • the second electrode layer 400 may be disposed on a surface of the first electrode layer 300 remote from the substrate 100 via the insulating layer 10.
  • the second electrode layer 400 may be connected to at least one of the drain 240 and the source 230.
  • Each of the first electrode layer 300 and the second electrode layer 400 may be formed of a transparent conductive material such as, but not limited to, ITO, IZO, or the like.
  • the first electrode layer 300 may be used to simulate a pixel ITO electrode or wiring connected to the TFT in the display region; and the second electrode 400 may be used to simulate effects of, for example, a common electrode of the array substrate on the pixel ITO electrode or wiring (eg, due to parasitic capacitance) , effects caused by capacitive coupling, etc.).
  • the light shielding layer and/or the first and second electrode layers can be utilized to simulate the electrical environment during operation of the TFT in the display region, thereby improving the accuracy of the data of the thin film transistor test device during testing.
  • the structure shown in FIG. 1A is merely exemplary; the present disclosure is not limited to the configuration shown in FIG. 1A.
  • the gate insulating layer 215 may be shown such that the thickness of a portion on both sides of the gate electrode 210 is thicker than the thickness of a portion thereof on the gate electrode 210 such that its upper surface is substantially flat; In other embodiments, the gate insulating layer 215 may be formed such that its thickness on both sides of the gate 210 substantially coincides with its thickness on the gate 210.
  • FIG. 1A the gate insulating layer 215 may be shown such that the thickness of a portion on both sides of the gate electrode 210 is thicker than the thickness of a portion thereof on the gate electrode 210 such that its upper surface is substantially flat; In other embodiments, the gate insulating layer 215 may be formed such that its thickness on both sides of the gate 210 substantially coincides with its thickness on the gate 210.
  • FIG. 1A the gate insulating layer 215 may be shown such that the thickness of a portion on both sides
  • source 230 and drain 240 are shown with their outer sidewalls substantially vertical, the disclosure is not limited thereto, for example, in other embodiments, source 230 and drain Each of 240 may also include an extension (not shown) extending further outward from the respective outer sidewalls on the gate insulating layer 215.
  • the source 230 and the drain 240 may also not cover the ends of the active layer 220.
  • the light shielding layer shields all exposed portions of the active layer, that is, The exposed ends of the active layer 220 are also covered.
  • a fixed voltage can be applied to the source and the drain, the gate voltage can be scanned within a certain range, and the drain current can be detected, thereby determining the switching characteristics of the thin film transistor. .
  • the gate voltage can be scanned within a certain range, and the drain current can be detected, thereby determining the switching characteristics of the thin film transistor.
  • the accuracy of the test result of the thin film transistor test device is determined by whether the thin film transistor 200 in the thin film transistor test device can truly reflect the thin film transistor in the display region.
  • the thin film transistor 200 should have the same structure and composition as the TFT in the display area, and the electrical environment in which it is placed should also be It is advantageous to be as close as possible to the electrical environment in which the TFTs in the display area are located.
  • Figure 2 shows a schematic top view of a portion of a prior art thin film transistor test device. It will be understood that for clarity and conciseness of the description, the top view of FIG. 2 omits certain layers, and that some of the occluded or partially occluded layers are not explicitly shown, but only the portions of the description are shown.
  • Floor Referring to FIG. 2, in a conventional thin film transistor test apparatus, a source 230, a drain 240, a gate 210, and an active layer 220 forming a thin film transistor, and a first electrode layer 300 connected to the drain 240 may be provided.
  • the active layer 220 is formed over the gate 210 via a gate insulating layer (not shown).
  • a drain (which may also be referred to as a drain electrode) 230 and a source (which may also be referred to as a source electrode) 240 are formed over the active layer 220.
  • the first electrode layer 300, the source electrode 230, the drain electrode 240, and the like are connected to terminals corresponding to connections to the outside, such as pads, through a connection line 20 formed of a conductive material such as metal.
  • a gate pad 211 connected to the gate, a drain pad 231 connected to the drain, and a source pad 241 connected to the source (through the first electrode layer 300) are shown in FIG.
  • the first electrode layer 300 may be formed of a transparent conductive material.
  • the test apparatus having the above structure has a significant difference in the test results before and after the box.
  • the drain current (Photo Avg) and the pixel are not lit in the state in which the thin film transistor test device is lit.
  • the relationship between the drain current leakage current and the gate voltage (Vg) in the state is as shown in FIG.
  • the array substrate and the color filter substrate are paired (MDL Out)
  • the relationship between the drain current (Photo Avg) and the gate voltage (Vg) in a state where the pixel is lit is as shown in FIG. 8.
  • the switching characteristics of the thin film transistor detected by the test device before and after the box were significantly changed.
  • the purpose of testing through the thin film transistor test device before the box is to find out whether the switching characteristics of the thin film transistor on the array substrate meet the predetermined standard as early as possible before the box is placed, so as to reduce the probability of product failure and save liquid crystal molecules and The cost of the color film substrate assembled with it. If the thin film transistor test device itself has a large difference in the switching characteristics detected before and after the box, the accuracy of the detection result is lowered.
  • the inventors have conducted in-depth research and a large number of experiments and found that one of the main causes of the above problems is that, in the structural design as shown in FIG. 2, only the electrical characteristics at the switching channel are considered, and the actual pixel area pixel lighting is not considered.
  • the environment behind the box is the environment in which the thin film transistor is actually operated.
  • the thin film transistor test device since the thin film transistor test device has only one first electrode layer, the effect of the electric field generated by the pixel electrode on the thin film transistor can only be simulated by the electrode layer.
  • the thin film transistor in the display region operates, the electric field generated between the common electrode and the pixel electrode also has an influence on the TFT switching characteristics.
  • the liquid crystal module is illuminated, and the illumination of the light also has a non-negligible influence on the TFT switching characteristics at the channel.
  • the prior art thin film transistor test apparatus as shown in FIG. 2 fails to recognize or take into account the influence of the above factors.
  • FIG. 3 shows a schematic top view of a portion of a thin film transistor testing device in accordance with an embodiment of the present disclosure.
  • An improvement to the scheme shown in Fig. 2 is schematically illustrated in Fig. 3.
  • the same reference numerals are used to denote the same or corresponding components as those in FIG. 2, and the description thereof will not be repeated here.
  • the thin film transistor test apparatus may include a source 230 forming a thin film transistor, a drain 240, a gate 210, and an active layer 220, and a first electrode layer 300 connected to the drain 240.
  • the first electrode layer 300, the source electrode 230, the drain electrode 240, and the like are connected to terminals corresponding to connections to the outside, such as pads, through a connection line 20 formed of a conductive material such as metal.
  • a gate pad 211 connected to the gate, a drain pad 231 connected to the drain, and a source pad 241 connected to the source (through the first electrode layer 300) are shown in FIG.
  • a second electrode layer 400 is further provided in accordance with some embodiments of the present disclosure.
  • the second electrode layer 400 is disposed insulatively from the first electrode layer 300 on a side of the first electrode layer 300 away from the substrate.
  • the thin film transistor test apparatus according to an embodiment of the present disclosure has two electrode layers, so that the common electrode and the pixel electrode can be simulated, and the influence of the common electrode and the pixel electrode on the switching characteristics of the thin film transistor 200 is simulated at the time of testing.
  • the insulating layer 10 therebetween is not shown in FIG.
  • a thin film transistor test device is generally disposed in a non-display area of an array substrate. That is, the substrate 100 may be a substrate of an array substrate. Due to the narrow frame and the like, the non-display area of the array substrate generally does not have enough lead terminals.
  • the second electrode layer 400 may be connected to at least one of the source 230 and the drain 240, thereby being applied to the source 230 by means of testing during testing And the voltage on the drain 240, so that the second electrode layer 400 has a certain voltage, thereby achieving the effect of simulating the common electrode.
  • the thin film transistor testing device may further include a first resistor 600.
  • the first resistor 600 is disposed between one of the source and the drain (here, the drain 240) and the second electrode layer 400. Both ends of the first resistor 600 are connected to one of a source and a drain (here, a drain 240) and a second electrode layer 400, respectively.
  • the voltage applied to the drain can be supplied to the second electrode layer 400 by using the first resistor (here, an appropriate voltage drop can be formed on the resistor 500), so that an appropriate voltage can be supplied to the second
  • the electrode layer 400 is used to simulate the influence of the common electrode in the display region on the thin film transistor by the second electrode layer 400.
  • the thin film transistor testing device may further include a second resistor 500.
  • the second resistor 500 may be disposed between the other of the source and the drain (here, the source 230) and the second electrode layer 400. Both ends of the second resistor 500 are connected to the source 230 and the second electrode layer 400, respectively. Thereby, the voltage applied to the source 230 can be divided (for example, a voltage drop is formed on the resistor 500) by the second resistor 500 and supplied to the second electrode layer 400.
  • a second resistor 500 may be disposed between the source 230 and the second electrode layer 400, and a first resistor 600 may be disposed between the drain 240 and the second electrode layer 400, such as Figure 3 shows.
  • an appropriate voltage can be supplied to the second electrode layer 400 by the partial pressure of the first resistor and the second resistor.
  • a voltage having a fixed value may be applied to the source 230 and the drain 240, respectively, and the voltage applied to the gate 210 may be scanned within a certain range. The current value of the drain current at different gate voltages is detected.
  • the term “connected” may include, but is not limited to, at least one of the following: a physical connection and/or an electrical connection. Additionally, the term “connected” can include both direct and indirect connections. Accordingly, it should be understood that although in FIG. 3, the resistors are shown as being connected to respective terminals, they pass through the respective terminals and corresponding connecting lines or other components (eg, the first electrode layer, as needed) ) Connect to the corresponding electrode. In general, since the connecting wires or other components are basically formed of a material used as an electrode, their electrical resistance is relatively low, and may even be neglected in some cases.
  • the specific values of the voltages applied to the source, the drain, and the gate are not particularly limited, and those skilled in the art can set them according to actual conditions. For example, when testing multiple batches of products, the same settings can be used for testing to facilitate product performance comparisons.
  • the specific values of the first resistor 600 and the second resistor 500 may be determined according to the voltages of the source and the drain, and the value of the voltage actually required to be applied to the common electrode layer on the array substrate corresponding to the product.
  • the second electrode layer 400 can be made to have a desired partial pressure. Thereby, the simulation of the influence of the common electrode and the common electrode on the TFT can be realized without additionally providing additional pads or terminals.
  • the thin film transistor may further include a light shielding layer such as a light shielding layer 250.
  • a light shielding layer such as a light shielding layer 250.
  • the light shielding layer 250 covers the exposed portion of the active layer 220 (that is, a portion not covered by the source 230 and the drain 240), and also covers the source 230.
  • the drain 240 covers the outline of the active region covered by the source 230 and the drain 240 and the light shielding layer 250 is shown by a dash-line, and is shown by a dash-dot-line.
  • first electrode 300 is illustrated as being in direct contact with the drain (or drain line) 240 in FIGS. 1A and 1B, the present disclosure is not limited thereto, for example, in the exemplary embodiment shown in FIG.
  • the first electrode 300 can also be connected to the drain 240 through additional leads.
  • the active layer in the thin film transistor is in an environment different from that in the state after being turned on and illuminated (ie, the display device The environment under working conditions). Since the active layer is mostly made of a light-sensitive polysilicon material (for example, a high-resistance polysilicon material), this influencing factor also has an important influence on the switching characteristics of the thin film transistor. Therefore, the measurement results of the prior art thin film transistor test apparatus may deviate from the actual parameters of the TFT device in the display area. According to the thin film transistor test apparatus of the embodiment of the present disclosure, the above problem can be largely alleviated, thereby making the test result more accurate and reliable.
  • the specific arrangement, materials, and structure of the light shielding layer 250 are not particularly limited, and those skilled in the art can design according to actual conditions.
  • an insulating layer may be provided in the thin film transistor 200, and the insulating layer may be disposed on a surface of the source, the drain, and the first electrode layer away from the substrate; At least a portion of the layer is added with a light-shielding material, such as a black dye, to form the light-shielding layer 250 to achieve a light-shielding effect.
  • the at least a portion may correspond to an exposed portion of the active layer.
  • the light shielding layer 250 may also be provided separately or additionally.
  • the light shielding layer 250 may be separately formed, for example, using a black resin.
  • FIG. 1B shows a schematic cross-sectional view of a structure of a thin film transistor test apparatus according to another embodiment of the present disclosure.
  • a light shielding layer 250 may be additionally formed over the insulating layer 260 disposed on the surface of the source, the drain, and the first electrode layer away from the substrate.
  • the same components in FIG. 1B as those in FIG. 1A are denoted by the same reference numerals, and the same components will not be described here.
  • the insulating layer 260 and the insulating layer 10 may be formed of the same layer of insulating material.
  • the light shielding layer may be formed of a material used to form the black matrix.
  • a light shielding layer can be utilized that acts as a structure for the black matrix. According to the embodiment of the present disclosure, the working environment of the thin film transistor in the display region in the lighting state of the display region can be more accurately and reliably simulated, so that a more accurate and reliable detection structure can be obtained.
  • an array substrate can include a thin film transistor test device according to any of the embodiments of the present disclosure and any other embodiments that can be readily obtained in accordance with the present disclosure.
  • the array substrate may further include an array formed of other thin film transistors formed on the substrate thereof; and a common electrode.
  • the array substrate has all of the features and advantages of the previously described thin film transistor test apparatus.
  • the test result of the thin film transistor test device is closer to the actual situation of the thin film transistor in the display region, thereby facilitating more accurate discovery of potential defects (if any) in the substrate, which can be reduced. Costs in mass production (for example, avoiding the preparation of poor display panels, and avoiding unnecessary waste, etc.).
  • the improvement of the array substrate is made possible, and the improvement is more targeted, thereby directly or indirectly improving the production efficiency and the yield, and reducing the display. The manufacturing cost of the panel.
  • the present disclosure proposes a thin film transistor test device test method.
  • the test method may be suitably or adaptively used with a thin film transistor test apparatus according to any of the embodiments of the present disclosure and any other embodiment that can be apparently obtained according to the present disclosure.
  • 4 shows a flow diagram of a test method in accordance with one embodiment of the present disclosure.
  • the method includes:
  • a voltage is applied to the source, the drain, and the gate, respectively.
  • the voltage applied to the source and the drain may be a fixed voltage.
  • a voltage of 0 V may be applied to the source and a voltage of 15 V may be applied to the drain; and the gate voltage may be scanned within a range of -20 to 20 V. .
  • the current of the drain is detected while the gate voltage is being scanned.
  • the test method according to an embodiment of the present disclosure can better simulate the environment in which the thin film transistor of the display region is actually operated, so that the accuracy of the test result can be improved.
  • FIG. 5 shows a flow chart of a test method according to another embodiment of the present disclosure.
  • the testing method may further include:
  • a thin film transistor test device suitable for the method may include a first resistor and/or a second resistor.
  • the first resistor and/or the second resistor may be utilized such that the second electrode layer has a certain partial pressure.
  • the voltage applied to the source and the drain may also be integrated, and the resistance of the first resistor and/or the second resistor may be designed to provide a suitable voltage to the second electrode layer, thereby It is possible to simulate the influence of the common electrode on the array substrate on the TFT in the display region under the operating state. Thereby, the accuracy of the test performed by the method can be further improved.
  • FIG. 6 shows a flow chart of a test method according to still another embodiment of the present disclosure.
  • the thin film transistor testing method may include: providing a thin film transistor testing device in step S610.
  • the thin film transistor test device can be a thin film transistor test device according to any of the embodiments of the present disclosure and any other embodiment that can be apparently obtained in accordance with the present disclosure.
  • the thin film transistor testing device may include: a substrate; a thin film transistor on the substrate, the thin film transistor including an active layer, a source, a drain, a gate, and a gate insulating layer a light shielding layer disposed on a side of the active layer away from the substrate to shield at least an exposed portion of the active layer; a first electrode layer, the first electrode layer and Connected to one of the drain and the source; and a second electrode layer disposed on the surface of the first electrode layer away from the substrate via an intermediate insulating layer, the second An electrode layer is coupled to at least one of the drain and the source.
  • the method may further include: applying a voltage to one or more of a source, a drain, and a gate of the thin film transistor, and detecting a corresponding electrical parameter, in step S610.
  • the electrical parameter can include any suitable parameter of the transistor, such as, but not limited to, detecting current/voltage/capacitance of one or more electrodes of the thin film transistor; various characteristic curves of the transistor; .
  • the substrate includes a substrate for an array substrate.
  • the thin film transistor testing apparatus may further include: a first resistor, two ends of the first resistor being respectively connected to the second electrode layer and the drain and source respectively And the first resistor is configured such that a partial voltage on the second electrode layer can simulate a voltage of a common electrode of the array substrate.
  • the thin film transistor testing device may further include: a second resistor, two ends of the second resistor being respectively connected to the second electrode layer and the other of the drain and the source One, the second resistor is configured such that a partial voltage on the second electrode layer can simulate a voltage of a common electrode on the array substrate.
  • the thin film transistor may further include: an insulating layer covering at least the source, the drain, and a surface of the first electrode layer away from the substrate, A light shielding layer is formed on a surface of the insulating layer remote from the substrate.
  • the thin film transistor further includes: an insulating layer covering at least the source, the drain, and a surface of the first electrode layer away from the substrate, the light shielding The layer is at least a portion of the insulating layer, and at least a portion of the insulating layer is added with a light blocking material.
  • the first electrode layer and the second electrode layer are formed of a light transmissive conductive material.
  • the source and drain are separated from each other and are respectively in contact with the active layer and expose a portion of the active layer.
  • the method has at least one of the following advantages: improved test accuracy, and simple test method.
  • the description of the terms “one embodiment”, “another embodiment” or the like means that the specific features, structures, materials or characteristics described in connection with the embodiments are included in at least one embodiment of the present disclosure. .
  • the schematic representation of the above terms is not necessarily directed to the same embodiment or example.
  • the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.
  • various embodiments or examples described in the specification, as well as features of various embodiments or examples may be combined and combined.

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Abstract

本公开涉及薄膜晶体管测试装置、测试方法及阵列基板。一种薄膜晶体管测试装置，包括：衬底；薄膜晶体管，所述薄膜晶体管设置在所述衬底上，所述薄膜晶体管包括有源层、源极和漏极、栅极以及栅极绝缘层；遮光层，所述遮光层设置在所述有源层远离所述衬底的一侧，以至少遮蔽所述有源层的露出的部分；第一电极层，所述第一电极层与所述漏极和源极中的一个相连；以及第二电极层，所述第二电极层隔着中间绝缘层设置在所述第一电极层的远离所述衬底的表面上，所述第二电极层与所述漏极和所述源极中的至少之一相连。

Description

薄膜晶体管测试装置、测试方法及阵列基板
相关申请的交叉引用
本申请要求于2017年5月26日提交的中国申请No.201710385385.1的优先权，通过引用将其全文并入在此。
技术领域
本公开涉及显示领域，具体地，涉及薄膜晶体管测试装置、测试方法及阵列基板。
背景技术
随着显示技术以及半导体技术的发展，人们对显示屏幕的画质要求也越来越高。期望液晶屏等显示屏幕具有足够高的像素密度以及较宽的色域，以满足对画质的清晰度以及画面饱和度的要求。而对于诸如液晶显示器件而言，越来越高的像素密度(Pixels Per Inch，PPI)却使得液晶屏的不良更容易产生。另一方面，在高像素密度的显示器件中，很多的不良与阵列基板上薄膜晶体管(TFT)的开关特性相关。因此，若能准确监测TFT(特别是显示区中的TFT)开关的电学特性，就能准确的对不良进行合理监控，有利于进而提出改善方案。
发明内容
根据本公开一个方面，提供了一种薄膜晶体管测试装置，包括：衬底；薄膜晶体管，所述薄膜晶体管设置在所述衬底上，所述薄膜晶体管包括有源层、源极和漏极、栅极以及栅极绝缘层；遮光层，所述遮光层设置在所述有源层远离所述衬底的一侧，以至少遮蔽所述有源层的露出的部分；第一电极层，所述第一电极层与所述漏极和源极中的一个相连；以及第二电极层，所述第二电极层隔着中间绝缘层设置在所述第一电极层的远离所述衬底的表面上，所述第二电极层与所述漏极和所述源极中的至少之一相连。
在一个实施例中，所述薄膜晶体管测试装置进一步包括：第一电阻器，所述第一电阻器的两端分别连接到所述漏极和源极中的一个以及所述第二电极层。
在一个实施例中，所述薄膜晶体管测试装置进一步包括：第二电阻器，所述第二电阻器的两端分别连接到所述漏极和源极中的另一个以及所述第二电极层。
在一个实施例中，所述衬底为阵列基板衬底。
在一个实施例中，所述薄膜晶体管进一步包括：绝缘层，所述绝缘层至少覆盖所述源 极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层形成在所述绝缘层的远离所述衬底的表面上。
在一个实施例中，所述薄膜晶体管进一步包括：绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层是所述绝缘层的至少一部分，所述至少一部分添加有遮光材料。
在一个实施例中，所述遮光层是由黑色树脂形成的。
在一个实施例中，所述薄膜晶体管测试装置用于与阵列基板一起使用，其中所述衬底作为阵列基板的衬底。
在一个实施例中，所述第一电极层和所述第二电极层由透光导电材料形成。
在一个实施例中，所述源极和漏极彼此分离，分别与所述有源层接触，并使得所述有源层的一部分露出。
在一个实施例中，所述薄膜晶体管测试装置还包括：多个端子，分别与源极、漏极和第一电极层相连，以用于到外部的电连接。
根据本公开另一方面，提供了一种阵列基板，包括：根据任一实施例所述的薄膜晶体管测试装置。
在一个实施例中，所述阵列基板还包括：由形成在所述衬底上的其他薄膜晶体管形成的阵列；以及公共电极。
根据本公开再一方面，提供了一种薄膜晶体管测试方法，包括：提供薄膜晶体管测试装置，所述薄膜晶体管测试装置包括：衬底；衬底上的薄膜晶体管，所述薄膜晶体管包括有源层、源极、漏极、栅极以及栅极绝缘层；遮光层，所述遮光层设置在所述有源层远离所述衬底的一侧，以至少遮蔽所述有源层的露出的部分；第一电极层，所述第一电极层与所述漏极和源极中的一个相连；以及第二电极层，所述第二电极层隔着中间绝缘层设置在所述第一电极层的远离所述衬底的表面上，所述第二电极层与所述漏极和所述源极中的至少之一相连，以及对所述薄膜晶体管的所述源极、所述漏极以及所述栅极中的一个或多个施加电压，并检测相应的电参数。
在一个实施例中，所述衬底包括用于阵列基板的衬底。在一个实施例中，提供薄膜晶体管测试装置包括：将薄膜晶体管测试装置设置在阵列基板的非显示区中。所述薄膜晶体管测试装置中的薄膜晶体管可以被配置用于模拟所述阵列基板的显示区中的薄膜晶体管。
在一个实施例中，所述薄膜晶体管测试装置进一步包括：第一电阻器，所述第一电阻器的两端分别连接到所述第二电极层以及所述漏极和源极中的一个，所述第一电阻器被配置为使得所述第二电极层上的分压能够模拟阵列基板的公共电极的电压。
在一个实施例中，所述薄膜晶体管测试装置进一步包括：第二电阻器，所述第二电阻 器的两端分别连接到所述第二电极层以及所述漏极和源极中的另一个，所述第二电阻器被配置为使得所述第二电极层上的分压能够模拟阵列基板上公共电极的电压。
在一个实施例中，所述薄膜晶体管进一步包括：绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层形成在所述绝缘层的远离所述衬底的表面上。
在一个实施例中，所述薄膜晶体管进一步包括：绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层是所述绝缘层的至少一部分，所述至少一部分添加有遮光材料。
在一个实施例中，所述第一电极层和所述第二电极层由透光导电材料形成。
在一个实施例中，所述源极和漏极彼此分离，分别与所述有源层接触，并使得所述有源层的一部分露出。
根据本公开的各种方面和实施例，可以提高检测的准确性，提高基板良率和性能。
附图说明
本公开的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1A示出了根据本公开一个实施例的薄膜晶体管测试装置的结构的示意截面图；
图1B示出了根据本公开另一个实施例的薄膜晶体管测试装置的结构的示意截面图；
图2示出了现有的薄膜晶体管测试装置的部分的示意俯视图；
图3示出了根据本公开一个实施例的薄膜晶体管测试装置的部分的示意俯视图；
图4示出了根据本公开一个实施例的测试方法的流程示意图；
图5示出了根据本公开另一个实施例的测试方法的流程示意图；
图6示出了根据本公开又一个实施例的测试方法的流程示意图；
图7示出了现有的薄膜晶体管测试装置在对盒前的测试结果图；以及
图8示出了现有的薄膜晶体管测试装置在对盒后的测试结果图。
注意，在以下说明的实施方式中，有时在不同的附图之间共同使用同一附图标记来表示相同部分或具有相同功能的部分，而省略其重复说明。在本说明书中，使用相似的标号和字母表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图的说明中不需要对其进行进一步讨论。
附图标记说明：
100：衬底；200：薄膜晶体管；210：栅极；220：有源层；230：源极；240：漏极； 250：遮光层；300：第一电极层；400：第二电极层；10：绝缘层；20：连接线；500：第二电阻器；600：第一电阻器。
具体实施方式
下面参考附图详细描述本公开的一些示例实施例。在附图中，使用相同或类似的标号来表示相同或类似的元件、步骤或项或者具有相同或类似功能的元件、步骤或项。下面描述的实施例是示例性的，仅用于解释本公开的原理，而不应理解为对如权利要求所限定的发明的限制。
为了方便检测显示区薄膜晶体管的电学特性，通常在薄膜晶体管液晶显示器(TFT-LCD)的阵列基板的非显示区，设置薄膜晶体管测试组装置(也常称作测试teg)。利薄膜晶体管测试装置中的薄膜晶体管来模拟显示区的薄膜晶体管，从而实现对显示区TFT开关特性的检测。然而，发明人发现，目前的测试组装置，普遍存在测试结果难以准确反应实际的显示区中TFT的开关特性的情况。
发明人经过深入研究以及大量实验发现，这一个可能的原因是：对于设置在非显示区的测试组装置中的薄膜晶体管，其所处的工作环境与设置在显示区的薄膜晶体管所处的工作环境存在差异。因此，在现有技术中，在利用测试组装置进行测试时，并未考虑显示区中的实际环境对薄膜晶体管的开关特性造成的影响，从而导致通过测试组装置获得的薄膜晶体管开关特性，与显示区中TFT的实际开关特性不相符。
在本公开的一个方面，本公开提出了一种薄膜晶体管测试装置。该薄膜晶体管测试装置可以适于设置在阵列基板的非显示区中。可以例如在阵列基板和与之配合的基板(如，像素基板等)对盒之前，通过对该薄膜晶体管测试装置进行测试，来评估阵列基板的显示区中的薄膜晶体管的开关特性。
图1A示出了根据本公开一个实施例的薄膜晶体管测试装置的结构的示意截面图。参考图1A，该薄膜晶体管测试装置可以包括：衬底100以及设置在衬底100上的薄膜晶体管200。薄膜晶体管200可以包括有源层220、源极230和漏极240、栅极210、以及栅极绝缘层215。在图1A所示的实施例中，栅极210设置在衬底100上，栅极绝缘层215被示出为形成在其上形成了栅极210的衬底上，覆盖栅极210。有源层220形成在栅极绝缘层215上。有源层220可以由半导体材料形成。源极230和漏极240被形成为与有源层220接触。尽管在图1A中，源极230和漏极240各自被示出为一部分形成在有源层220上，另一部分覆盖有源层220的侧面，但显然，本公开不限于此。源极230和漏极240彼此分离，从而使得有 源层220的一部分露出。源极230和漏极240各自可以由导电材料形成，例如但不限于，金属或多晶硅等。
需要说明的是，该薄膜晶体管200可以具有与设置在阵列基板显示区中的薄膜晶体管基本相同的结构。在一些实施例中，设置在阵列基板显示区中的薄膜晶体管可以具有与设置在非显示区中的薄膜晶体管200基本相同的栅极、栅极绝缘层、有源层、源极和漏极。例如，设置在阵列基板显示区中的薄膜晶体管的栅极、栅极绝缘层、有源层、源极和漏极可以被形成为分别与设置在非显示区中的薄膜晶体管200中的栅极、栅极绝缘层、有源层、源极和漏极具有基本相同的尺寸，由基本相同的材料利用基本相同的工艺形成。
还应该理解的是，图中仅仅示出了用于描述本公开的示例实施例所可能涉及的部件，而并未示出这些实施例可能不涉及或不关注的特征。
该薄膜晶体管测试装置还可以包括遮光层250。遮光层250可以设置在有源层220的远离衬底100的一侧，如图1A中所示。遮光层250可以与有源层220对应设置。遮光层可以用于至少遮蔽所述有源层的露出的部分。例如，遮光层可以用于至少遮蔽有源层220的通过源极和源极露出的部分。遮光层250可以利用黑色树脂形成。遮光层250也可以是某个绝缘层的至少一部分，所述至少一部分添加有遮光材料。通过遮光层250，可以减少后续工艺步骤中的辐照(例如紫外线(UV))等对薄膜晶体管220的有源区的影响，从而使得薄膜晶体管200的电学性质与显示区中的TFT更加接近或一致。
该薄膜晶体管测试装置还可以包括第一电极层300以及第二电极层400。第一电极层300可以与源极和漏极中的一个(例如，漏极240)相连。第二电极层400可以隔着绝缘层10设置在第一电极层300的远离衬底100的表面上。第二电极层400可以与漏极240和源极230中的至少之一相连。第一电极层300和第二电极层400中的每一个可以由透明导电材料形成，例如但不限于，ITO、IZO等。第一电极层300可以用于模拟显示区中与TFT连接的像素ITO电极或布线；而第二电极400可以用于模拟例如阵列基板的公共电极对像素ITO电极或布线的影响(例如由于寄生电容、电容性耦合等导致的影响等)。
由此，可以利用遮光层和/或第一和第二电极层，模拟显示区TFT工作时的电学环境，从而提高该薄膜晶体管测试装置在进行测试时数据的准确性。
这里，应理解，图1A所示的结构仅仅是示例性的；本公开并不限于图1A所示的配置。例如，尽管在图1A中，栅极绝缘层215可以被示出为其在栅极210两侧的部分的厚度比其在栅极210上的部分的厚度厚，使得其上表面基本平坦；然而，在其他实施例中，栅极绝缘层215可以被形成为：其在栅极210两侧的部分的厚度与其在栅极210上的部分厚度基本一致。另外，尽管在图1A中，源极230和漏极240被示出为其两侧的外侧壁基本竖直，然而本公开不限于此，例如，在其他实施例中，源极230和漏极240各自还可以包括在栅 极绝缘层215上从各自外侧壁向外进一步延伸的延伸部分(图中未示出)。在某些实施例中，源极230和漏极240也可能不覆盖有源层220的端部，在这种情况下，优选地，遮光层遮蔽有源层的所有露出部分，也就是说，也覆盖有源层220的露出的端部。
下面首先对薄膜晶体管测试装置的操作和原理进行简单说明。
在利用薄膜晶体管测试装置进行测试时，例如，可以对源极以及漏极施加固定值的电压，在一定范围内扫描栅极电压，同时检测漏极电流，由此可以确定该薄膜晶体管的开关特性。本领域技术人员将容易明了，可以通过不同的测试方法或步骤来检测薄膜晶体管的多种多样的参数。然而，由于薄膜晶体管测试装置往往设置在非显示区中，薄膜晶体管测试装置测试结果的准确程度，由该薄膜晶体管测试装置中的薄膜晶体管200是否能够真实反应显示区中的薄膜晶体管而决定。也即是说，为了使薄膜晶体管测试装置能够获得更准确的测试结果，则在使薄膜晶体管200具有与显示区中的TFT相同的结构以及组成等之外，使其所处的电学环境也应尽量与显示区TFT所处的电学环境一致是有利的。
图2示出了现有的薄膜晶体管测试装置的部分的示意俯视图。应理解，为了说明的清楚和简明器件，图2的俯视图省略了某些层，以及某些被遮挡的或者部分被遮挡的层也并未明确示出，而仅示出了说明所涉及的部分层。参考图2，在现有的薄膜晶体管测试装置中，可以具有形成薄膜晶体管的源极230、漏极240、栅极210以及有源层220，以及与漏极240相连的第一电极层300。
参见图2，有源层220隔着栅极绝缘层(图中未示出)形成在栅极210之上。漏极(也可称作漏电极)230和源极(也可称作源电极)240形成在有源层220之上。第一电极层300、源极230、漏极240等通过由金属等导电材料形成的连接线20连接到相应用于到外部的连接的端子，例如焊盘(pad)。例如，图2中示出了与栅极相连的栅极焊盘211、与漏极相连的漏极焊盘231、以及与源极(通过第一电极层300)相连的源极焊盘241。第一电极层300可以由透明导电材料形成。在测试时，通过焊盘(pad)将不同电压施加到TFT开关的三个电极(源极230、漏极240、栅极210)，来监测TFT开关的电学特性。
然而，具有上述结构的测试装置，在对盒前后的测试结果具有显著差异。当该薄膜晶体管测试装置设置在阵列基板上，且阵列基板未与彩膜基板进行对盒时，该薄膜晶体管测试装置在像素点亮的状态下的漏极电流(Photo Avg)以及像素未点亮的状态下的漏极电流漏电流以及栅电压(Vg)之间的关系如图7所示。当该阵列基板与彩膜基板进行对盒之后(MDL Out)，像素点亮的状态下的漏极电流(Photo Avg)以及栅电压(Vg)之间的关系如图8所示。对比可知，在对盒前后，通过测试装置检测的薄膜晶体管的开关特性出现了显著的改变。
在对盒之前通过薄膜晶体管测试装置进行测试的目的是：希望能够在对盒之前，尽早 发现阵列基板上薄膜晶体管的开关特性是否符合预定标准，以降低产品出现不良的概率，并节省液晶分子以及与之组装的彩膜基板的成本。而如果薄膜晶体管测试装置自身在对盒前后检测的开关特性即存在较大差异，则会使得检测结果的准确性降低。
发明人经过深入研究以及大量实验发现，造成上述问题的一个主要原因是，在如图2所示出的结构设计，只考虑了开关沟道处的电学特性，未考虑到实际像素区像素点亮时，薄膜晶体管所处的全部电学环境。对于阵列基板上显示区的薄膜晶体管而言，对盒后的环境才是该薄膜晶体管在实际工作中所处的环境。另一方面，由于该薄膜晶体管测试装置中仅具有一个第一电极层，因此，只能由该电极层模拟像素电极产生的电场对薄膜晶体管的影响。而实际上，在显示区的薄膜晶体管工作时，公共电极与像素电极之间产生的电场，对TFT开关特性也具有一定影响。另外，对盒后在该液晶模组点亮状态，光的照射时对沟道处TFT开关特性也具有不可忽视的影响。如图2所示出的现有技术的薄膜晶体管测试装置未能认识或考虑到上述因素的影响。
图3示出了根据本公开一个实施例的薄膜晶体管测试装置的部分的示意俯视图。图3中示意性地示出了对图2所示的方案的改进。在图3中，使用相同的附图标记来表示与图2中相同或相应的部件，并且这里，不再重复对其进行说明。根据本公开实施例的薄膜晶体管测试装置可以包括：形成薄膜晶体管的源极230、漏极240、栅极210以及有源层220，以及与漏极240相连的第一电极层300。第一电极层300、源极230、漏极240等通过由金属等导电材料形成的连接线20连接到相应用于到外部的连接的端子，例如焊盘(pad)。图3中示出了与栅极相连的栅极焊盘211、与漏极相连的漏极焊盘231、以及与源极(通过第一电极层300)相连的源极焊盘241。
与图2所示的薄膜晶体管测试装置相比，根据本公开的一些实施例，进一步提供了第二电极层400。第二电极层400被与第一电极层300绝缘地设置在第一电极层300远离衬底的一侧。由此，根据本公开实施例的薄膜晶体管测试装置具有两个电极层，从而可以模拟公共电极以及像素电极，并在测试时模拟公共电极、像素电极对薄膜晶体管200的开关特性的影响。这里，二者间的绝缘层10未在图3中示出。
根据本公开的一些实施例，薄膜晶体管测试装置一般设置在阵列基板的非显示区。也即是说，衬底100可以为阵列基板的衬底。出于窄边框化等考虑，阵列基板的非显示区一般不会设置足够多的引线端子。考虑到此，在根据本公开的一些实施例中，可以将第二电极层400与源极230以及漏极240的至少之一相连，由此，可以借助在测试过程中，施加在源极230以及漏极240上的电压，使得第二电极层400具有一定的电压，从而实现模拟公共电极的效果。
根据本公开的实施例，参考图3，该薄膜晶体管测试装置可以进一步包括第一电阻器 600。第一电阻器600设置在源极和漏极之一(这里，漏极240)与第二电极层400之间。第一电阻器600的两端分别连接到源极和漏极之一(这里，漏极240)以及第二电极层400。由此，可以利用第一电阻器，将施加在漏极的电压提供至第二电极层400(这里，可以在电阻器500上形成适当的电压降)，从而可以将适当的电压提供到第二电极层400，以便利用第二电极层400模拟显示区中公共电极对薄膜晶体管的影响。
根据本公开的一些实施例，薄膜晶体管测试装置可以进一步包括第二电阻器500。第二电阻器500可以设置在源极和漏极中的另一个(这里，源极230)以及第二电极层400之间。第二电阻器500的两端分别连接到源极230以及第二电极层400。由此，可以利用第二电阻器500，将施加在源极230的电压分压(例如，在电阻器500上形成电压降)并提供至第二电极层400。
根据本公开的一些具体实施例，可以在源极230以及第二电极层400之间设置第二电阻器500，并在漏极240以及第二电极层400之间设置第一电阻器600，如图3所示。从而可以通过第一电阻器和第二电阻器的分压，提供适当的电压到第二电极层400。在一种利用该薄膜晶体管测试装置进行测试的具体示例中，可以对源极230以及漏极240分别施加具有固定值的电压，并使施加在栅极210上的电压在一定范围内扫描，来检测不同栅极电压下漏极电流的电流值。
需要说明的是，在本公开的上下文中，术语“连接”可以包括但不限于下列中的至少一种：物理连接和/或电连接。另外，术语“连接”可以包括直接连接和间接连接。因此，应理解，尽管在图3中，电阻器被示出为连接到相应的端子，然而其通过该相应的端子以及相应的连接线或其他部件(如第一电极层，在需要的情况下)连接到相应的电极。一般地，由于连接线或其他部件基本都是由用作电极的材料形成，因此其电阻相对较低，甚至在某些情况下可以忽略。
另外，还应理解，为了图示的清楚，在图2和图3中未示出不同导电的层之间的可能的连接部件(例如，通孔(via)等)。
对于在源极、漏极以及栅极上施加的电压的具体数值没有特别限制，本领域技术人员可以根据实际情况进行设置。例如，在对多批次的产品进行测试时，可以采用相同设置来进行测试，从而有利于产品性能的比对。第一电阻器600以及第二电阻器500的具体数值，可以根据源极、漏极的电压，以及与该产品对应的阵列基板上公共电极层实际需要施加的电压的数值而确定。
在如图3所示的实施例中，由于施加在源极230以及漏极240上的电压不同，且源漏极之间的电压差经过第二电阻器以及第一电阻器分压，因此，可以使得第二电极层400具有期望的分压。从而，可以实现对公共电极以及公共电极对TFT影响的模拟，而无需多设 置额外的焊盘或端子。
根据本公开的一些实施例，如图3所示，薄膜晶体管还可以包括遮光层，例如遮光层250。由此，可以模拟在实现对盒之后显示区点亮状态下有源层240所处的环境。这里，如图1A和图3中所示，遮光层250覆盖了有源层220的露出的部分(也即，未被源极230和漏极240覆盖的部分)，并且还覆盖了源极230和漏极240。因此，在图3中，以虚线(dash-line)示出了被源极230和漏极240以及遮光层250覆盖的有源区的轮廓，并以点画线(dash-dot-line)示出了被源极230和漏极240被遮光层250覆盖的部分的轮廓。
另外，尽管在图1A和1B中，第一电极300被示出为与漏极(或漏极线)240直接接触，然而本公开不限于此，例如在图3所示的示例性实施例中，第一电极300也可以通过额外的引线与漏极240连接。
由于如图2所示的薄膜晶体管测试装置未设置遮光层，因此，其薄膜晶体管中的有源层所处的环境，不同于在对盒后且点亮的状态下(也即，显示器件的工作状态下)的环境。由于有源层多采用光敏感的多晶硅材料(例如，高阻多晶硅材料)制备，因此，这一影响因素也对薄膜晶体管的开关特性具有重要影响。因此，现有技术的薄膜晶体管测试装置的测量结果可能与显示区中的TFT器件的实际参数有偏差。而根据本公开实施例的薄膜晶体管测试装置，可以在很大程度上减轻上述问题，从而使得测试结果更加准确可靠。
根据本公开的一些实施例，对于遮光层250的具体设置方式、材料以及结构没有特别限制，本领域技术人员可以根据实际情况进行设计。例如，根据本公开的一个实施例，可以在薄膜晶体管200中提供一绝缘层，该绝缘层可以设置在源极、漏极以及第一电极层远离衬底的表面上；之后可以通过对该绝缘层的至少一部分添加遮光材料，例如黑色染料，来形成遮光层250，以实现遮光作用。例如，所述至少一部分可以与有源层的暴露部分对应。或者，根据本公开的另一些实施例，也可以单独设置或者额外添加遮光层250。例如可以采用黑色树脂，单独形成遮光层250。
图1B示出了根据本公开另一个实施例的薄膜晶体管测试装置的结构的示意截面图。如图1B所示，可以在设置在源极、漏极以及第一电极层远离衬底的表面上的绝缘层260之上，额外形成遮光层250。图1B所示的实施例中与图1A相同的部件被标示以相同的附图标记，并且这里不再对相同部件进行说明。另外，在图1B所示的实施例中，绝缘层260与绝缘层10可以由同一层绝缘材料形成。
在另外的实施例中，遮光层可以由用于形成黑矩阵的材料形成。在一些实施例中，可以利用遮光层，充当黑矩阵的结构。根据本公开的实施例，可以更准确可靠地模拟显示区中的薄膜晶体管在显示区点亮状态下的工作环境，从而可以得到更准确可靠的检测结构。
在本公开的另一方面，提供了一种阵列基板，其可以包括根据本公开任意实施例以及 可以根据本公开显而易见地得到任何其他实施例的薄膜晶体管测试装置。阵列基板还可以包括由形成在其衬底上的其他薄膜晶体管形成的阵列；以及公共电极。由此，该阵列基板具有前面描述的薄膜晶体管测试装置所具有的全部特征以及优点。具体地，根据本公开的阵列基板，薄膜晶体管测试装置的测试结果更加接近显示区中的薄膜晶体管的实际情况，从而有利于更准确地发现基板中的潜在缺陷(如果有的话)，可以降低大批量生产中的成本(例如，避免不良的显示面板的制备，以及避免不必要的浪费等)。另外，由于能够更准确地发现基板中的潜在缺陷，使得对该阵列基板的改进成为可能，并使得这样的改进更有针对性，从而直接或间接地提高了生产效率和良品率，降低了显示面板的制造成本。
在本公开的又一方面，本公开提出了一种薄膜晶体管测试装置测试方法。根据本公开的一些实施例，该测试方法可以适当地或适应性地与根据本公开任意实施例以及可以根据本公开显而易见地得到任何其他实施例的薄膜晶体管测试装置一起使用。图4示出了根据本公开一个实施例的测试方法的流程示意图。
参考图4，该方法包括：
S100：在源极、漏极以及栅极上施加电压
根据本公开的一些实施例，在该步骤中，分别在源极、漏极以及栅极上施加电压。作为一个示例，施加在源极、漏极上的电压可以为固定电压，例如，可以在源极施加0V电压，在漏极施加15V电压；而栅极电压可以在-20～20V范围内进行扫描。
S200：检测漏极电流
在该步骤中，在对栅极电压进行扫描的同时，检测漏极的电流。根据本公开的实施例的测试方法可以更好地模拟显示区薄膜晶体管在实际工作中的环境，从而可以提高测试结果的准确性。
图5示出了根据本公开另一个实施例的测试方法的流程示意图。参考图5，根据本公开的另一些实施例，测试方法可以进一步包括：
S10：在第二电极层上分压，以模拟公共电极
适于该方法的薄膜晶体管测试装置可以可以包括第一电阻器和/或第二电阻器。关于第一电阻器、第二电阻器的设置位置以及作用原理，前面已经进行了详细的描述，在此不再赘述。根据本公开的一些实施例，在该步骤中，在可以利用第一电阻器和/或第二电阻器，使得第二电极层具有一定的分压。在一些实施例中，还可以综合施加在源极、漏极的电压，对第一电阻器和/或第二电阻器的阻值进行设计，以对第二电极层提供合适的电压，从而使得能够模拟阵列基板上公共电极在工作状态下对显示区中的TFT的影响。由此，可以进一步提高该方法进行测试的准确性。
图6示出了根据本公开又一个实施例的测试方法的流程示意图。如图6所示，该薄膜 晶体管测试方法可以包括：在步骤S610，提供薄膜晶体管测试装置。所述薄膜晶体管测试装置可以为根据本公开任意实施例以及可以根据本公开显而易见地得到任何其他实施例的薄膜晶体管测试装置。例如，在一些具体实现方式中，所述薄膜晶体管测试装置可以包括：衬底；衬底上的薄膜晶体管，所述薄膜晶体管包括有源层、源极、漏极、栅极以及栅极绝缘层；遮光层，所述遮光层设置在所述有源层远离所述衬底的一侧，以至少遮蔽所述有源层的露出的部分；第一电极层，所述第一电极层与所述漏极和源极中的一个相连；以及第二电极层，所述第二电极层隔着中间绝缘层设置在所述第一电极层的远离所述衬底的表面上，所述第二电极层与所述漏极和所述源极中的至少之一相连。
所述方法还可以包括：在步骤S610，对薄膜晶体管的源极、漏极以及栅极中的一个或多个施加电压，并检测相应的电参数。在一些实现方式中，所述电参数可以包括晶体管的任意适合的参数，例如但不限于：检测所述薄膜晶体管的一个或多个电极的电流/电压/电容；晶体管各种特性曲线；等等。
在一些实施例中，所述衬底包括用于阵列基板的衬底。在一些实施例中，所述薄膜晶体管测试装置可以进一步包括：第一电阻器，所述第一电阻器的两端分别连接到所述第二电极层以及所述漏极和源极中所述的一个，所述第一电阻器被配置为使得所述第二电极层上的分压能够模拟阵列基板的公共电极的电压。在一些实施例中，所述薄膜晶体管测试装置可以进一步包括：第二电阻器，所述第二电阻器的两端分别连接到所述第二电极层以及所述漏极和源极中的另一个，所述第二电阻器被配置为使得所述第二电极层上的分压能够模拟阵列基板上公共电极的电压。
在一些实施例中，所述薄膜晶体管可以进一步包括：绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层形成在所述绝缘层的远离所述衬底的表面上。在一些实施例中，所述薄膜晶体管进一步包括：绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层是所述绝缘层的至少一部分，所述至少一部分添加有遮光材料。
在一些实施例中，所述第一电极层和所述第二电极层由透光导电材料形成。在一些实施例中，所述源极和漏极彼此分离并分别与所述有源层接触且使得所述有源层的一部分露出。
总的来说，该方法具有以下优点中的至少之一：提高的测试准确性、测试方法简单。
在本公开的描述中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开而不是要求本公开必须以特定的方位构造和操作，因此不能理解为对本公开的限制。本公开的实施例可以在与图中所示的不同的取向 (orientation)上来实现。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的一些实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (21)

  1. 一种薄膜晶体管测试装置，包括：
    衬底；
    薄膜晶体管，所述薄膜晶体管设置在所述衬底上，所述薄膜晶体管包括有源层、源极和漏极、栅极以及栅极绝缘层；
    遮光层，所述遮光层设置在所述有源层远离所述衬底的一侧，以至少遮蔽所述有源层的露出的部分；
    第一电极层，所述第一电极层与所述漏极和源极中的一个相连；以及
    第二电极层，所述第二电极层隔着中间绝缘层设置在所述第一电极层的远离所述衬底的表面上，所述第二电极层与所述漏极和所述源极中的至少之一相连。
  2. 根据权利要求1所述的薄膜晶体管测试装置，进一步包括：第一电阻器，所述第一电阻器的两端分别连接到所述漏极和源极中的一个以及所述第二电极层。
  3. 根据权利要求2所述的薄膜晶体管测试装置，进一步包括：第二电阻器，所述第二电阻器的两端分别连接到所述漏极和源极中的另一个以及所述第二电极层。
  4. 根据权利要求1所述的薄膜晶体管测试装置，其中，所述衬底为阵列基板衬底。
  5. 根据权利要求1所述的薄膜晶体管测试装置，其中，所述薄膜晶体管进一步包括：
    绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层形成在所述绝缘层的远离所述衬底的表面上。
  6. 根据权利要求1所述的薄膜晶体管测试装置，其中，所述薄膜晶体管进一步包括：
    绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层是所述绝缘层的至少一部分，所述至少一部分添加有遮光材料。
  7. 根据权利要求1所述的薄膜晶体管测试装置，其中，所述遮光层是由黑色树脂形成的。
  8. 根据权利要求1所述的薄膜晶体管测试装置，其中，所述薄膜晶体管测试装置用于与阵列基板一起使用，其中所述衬底作为阵列基板的衬底。
  9. 根据权利要求1所述的薄膜晶体管测试装置，其中，所述第一电极层和所述第二电极层由透光导电材料形成。
  10. 根据权利要求1所述的薄膜晶体管测试装置，其中，所述源极和漏极彼此分离，分别与所述有源层接触，并使得所述有源层的一部分露出。
  11. 根据权利要求1所述的薄膜晶体管测试装置，还包括：
    多个端子，分别与源极、漏极和第一电极层相连，以用于到外部的电连接。
  12. 一种阵列基板，包括：
    权利要求1-11中任一项所述的薄膜晶体管测试装置。
  13. 如权利要求12所述阵列基板，还包括：
    由形成在所述衬底上的其他薄膜晶体管形成的阵列；以及
    公共电极。
  14. 一种薄膜晶体管测试方法，包括：
    提供薄膜晶体管测试装置，所述薄膜晶体管测试装置包括：
    衬底；
    衬底上的薄膜晶体管，所述薄膜晶体管包括有源层、源极、漏极、栅极以及栅极绝缘层；
    遮光层，所述遮光层设置在所述有源层远离所述衬底的一侧，以至少遮蔽所述有源层的露出的部分；
    第一电极层，所述第一电极层与所述漏极和源极中的一个相连；以及
    第二电极层，所述第二电极层隔着中间绝缘层设置在所述第一电极层的远离所述衬底的表面上，所述第二电极层与所述漏极和所述源极中的至少之一相连，以及
    对所述薄膜晶体管的所述源极、所述漏极以及所述栅极中的一个或多个施加电压，并检测相应的电参数。
  15. 根据权利要求14所述的方法，
    其中，所述衬底包括用于阵列基板的衬底；
    其中，提供薄膜晶体管测试装置包括：将薄膜晶体管测试装置设置在阵列基板的非显示区中，
    其中，所述薄膜晶体管测试装置中的薄膜晶体管被配置用于模拟所述阵列基板的显示区中的薄膜晶体管。
  16. 根据权利要求15所述的方法，其中，所述薄膜晶体管测试装置进一步包括：
    第一电阻器，所述第一电阻器的两端分别连接到所述第二电极层以及所述漏极和源极中的一个，所述第一电阻器被配置为使得所述第二电极层上的分压能够模拟阵列基板的公共电极的电压。
  17. 根据权利要求16所述的方法，其中，所述薄膜晶体管测试装置进一步包括：
    第二电阻器，所述第二电阻器的两端分别连接到所述第二电极层以及所述漏极和源极中的另一个，所述第二电阻器被配置为使得所述第二电极层上的分压能够模拟阵列基板上公共电极的电压。
  18. 根据权利要求14所述的方法，其中，所述薄膜晶体管进一步包括：
    绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层形成在所述绝缘层的远离所述衬底的表面上。
  19. 根据权利要求14所述的方法，其中，所述薄膜晶体管进一步包括：
    绝缘层，所述绝缘层至少覆盖所述源极、所述漏极以及所述第一电极层的远离所述衬底的表面，所述遮光层是所述绝缘层的至少一部分，所述至少一部分添加有遮光材料。
  20. 根据权利要求14所述的方法，其中，所述第一电极层和所述第二电极层由透光导电材料形成。
  21. 根据权利要求14所述的方法，其中，所述源极和漏极彼此分离，分别与所述有源层接触，并使得所述有源层的一部分露出。
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