WO2016106881A1 - 一种阵列基板的制备方法 - Google Patents

一种阵列基板的制备方法 Download PDF

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WO2016106881A1
WO2016106881A1 PCT/CN2015/071059 CN2015071059W WO2016106881A1 WO 2016106881 A1 WO2016106881 A1 WO 2016106881A1 CN 2015071059 W CN2015071059 W CN 2015071059W WO 2016106881 A1 WO2016106881 A1 WO 2016106881A1
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transparent conductive
conductive film
address electrode
metal
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PCT/CN2015/071059
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French (fr)
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薛景峰
陈归
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深圳市华星光电技术有限公司
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Publication of WO2016106881A1 publication Critical patent/WO2016106881A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.
  • capacitive touch screens are widely used in various electronic products such as mobile phones and tablet computers.
  • the more common capacitive touch screens are OGS (One Glass Solution), on-cell and in-cell.
  • OGS One Glass Solution
  • on-cell and in-cell are the more common capacitive touch screens.
  • in-cell technology has the advantages of lighter weight, better light transmission and more stable structure than OGS technology and on-cell technology due to its manufacturing process advantages.
  • the inventors have found that in order to reduce the resistance of the address electrodes, in the touch panel using the in-cell technology, it is necessary to match the address electrodes with a metal structure.
  • the appearance of the metal structure will increase the process complexity of preparing the array substrate and reduce the yield of the array substrate.
  • the object of the present invention is to provide a method for preparing an array substrate to solve the technical problem that the preparation process of the array substrate is complicated in the touch panel using the in-cell technology.
  • the invention provides a method for preparing an array substrate, the method comprising:
  • the transparent conductive film is formed into an address electrode by using a mask process, and the metal film is formed into a metal structure matched with the address electrode, including:
  • the metal thin film corresponding to the partially reserved region is removed by an etching process and the residual photoresist is stripped to form a metal structure in combination with the address electrode.
  • the transparent conductive film and the metal film corresponding to the completely removed region are removed by an etching process, and the forming the address electrode includes:
  • the transparent conductive film corresponding to the completely removed region is removed by a wet etching process to form an address electrode.
  • the address electrode comprises a driving electrode and a sensing electrode.
  • the halftone mask or the gray dimming cover comprises an opaque region, a semi-transmissive region and a fully transparent region, and the semi-transmissive region has a light transmittance of 30% to 50%.
  • the thickness is deposited by sputtering or thermal evaporation.
  • Transparent conductive film is deposited by sputtering or thermal evaporation.
  • the material of the transparent conductive film is indium tin oxide, indium zinc oxide or indium gallium zinc oxide.
  • the thickness of the transparent conductive film is deposited by sputtering or thermal evaporation. Metal film.
  • the predetermined thickness of the photoresist layer is
  • the thickness ratio of the completely reserved region and the partially retained region is 4:1.
  • a halftone mask process or a gray dimmer process can be used to form an address electrode and a metal structure matched with the address electrode in the same mask process.
  • the patterning electrode and the metal structure are separately patterned without two mask processes, which is advantageous for reducing the complexity of the fabrication process of the array substrate, reducing the cost of the fabrication process of the array substrate, and improving the yield of the array substrate.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 are flowcharts showing a method of fabricating an array substrate according to an embodiment of the present invention
  • FIG. 4 to FIG. 11 are schematic diagrams showing a process of preparing an array substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural view of an address electrode in an embodiment of the present invention.
  • Embodiments of the present invention provide a method of fabricating an array substrate.
  • the array substrate includes a plurality of pixel units, and each of the pixel units is provided with a thin film transistor 2 and a pixel electrode 7.
  • the thin film transistor 2 in the embodiment of the present invention is a top gate type thin film transistor using Low Temperature Poly-Silicon (LTPS).
  • LTPS 21 is located on the bottom layer
  • the gate electrode 22 is located above the LTPS 21
  • a gate insulating layer 23 is disposed between the gate electrode 22 and the LTPS 21.
  • a first insulating layer 3 is disposed above the gate electrode 22, a source electrode 24 and a drain electrode 25 are disposed over the first insulating layer 3, and the source electrode 24 and the drain electrode 25 are connected to the LTPS 21 through the via hole 6 and remain with the gate electrode 22. insulation.
  • a second insulating layer 4 and a third insulating layer 5 are further disposed over the source electrode 24 and the drain electrode 25.
  • the pixel electrode 7 is connected to the drain electrode 25 through a via 6 penetrating through the second insulating layer 4 and the third insulating layer 5.
  • a light shielding layer 8 for shielding the LTPS 21 from light is provided on the base substrate 1 below the LTPS 21.
  • the array substrate is driven by a Fringe Field Switching (FFS) type.
  • FFS Fringe Field Switching
  • the core technical characteristics of the FFS can be simply described as: the electric field generated by the edge of the slit-shaped pixel electrode 7 in the same plane enables the plane-rotation of all the aligned liquid crystal molecules between the slit-shaped electrodes and directly above the electrode, thereby improving The light transmission efficiency of the liquid crystal layer.
  • FFS technology can improve the picture quality of liquid crystal display, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no squeeze water ripple.
  • the array substrate is further provided with a common electrode 9 which is located between the third insulating layer 5 and the second insulating layer 4 and has a plate-like structure.
  • the pixel electrode 7 that is fitted to the common electrode 9 is a stripe structure having slits.
  • the common electrode 9 can be used as the address electrode 10 of the array substrate.
  • the array substrate can adopt a driving mode of display and touch time-sharing scanning. Specifically, when displaying an image, the common electrode 9 supplies a common voltage to the corresponding pixel unit, so that a common electrode 9 and the pixel electrode 7 are formed. An electric field, and one common electrode 9 may correspond to one or more pixel units; at the time of touch scanning, the common electrode 9 serves as an address electrode 10, for transmitting a touch signal, for processing chip analysis on the edge of the array substrate, determining the occurrence of the touch signal, so that the array substrate or even the entire display device can respond according to the touch signal.
  • Each of the address electrodes 10 is provided with a metal structure 11 short-circuited with the address electrodes 10, so that the resistance of the address electrodes 10 can be lowered, and the sensing sensitivity of the address electrodes 10 can be improved.
  • the method for preparing the array substrate may include:
  • Step S101 sequentially forming a transparent conductive film and a metal film.
  • the thickness can be deposited by sputtering or thermal evaporation.
  • the transparent conductive film 12 may be made of indium tin oxide, indium zinc oxide or indium gallium zinc oxide.
  • a thickness deposited on the transparent conductive film 12 by sputtering or thermal evaporation may be employed.
  • Step S102 using a photomask process, forming a transparent conductive film into the address electrodes, and simultaneously forming the metal film into a metal structure matched with the address electrodes, and the photomask process is a halftone mask process or a gray dimming process.
  • the address electrode 10 and the metal structure 11 matched with the address electrode 10 can be formed in the same mask process by using a halftone mask process or a gray dimmer process.
  • the address electrode 10 and the metal structure 11 are separately patterned without two mask processes, which is advantageous for reducing the complexity of the fabrication process of the array substrate, reducing the cost of the fabrication process of the array substrate, and improving the fabrication of the array substrate. rate.
  • step S102 may include the following steps:
  • Step S1021 forming a photoresist layer of a predetermined thickness over the metal thin film.
  • a photoresist layer 15 is formed by a coating method or the like, and the predetermined thickness of the photoresist layer 15 is about.
  • step S1022 the photoresist layer is exposed and developed by using a halftone mask or a gray dimming cover, and the photoresist layer forms a completely reserved area, a partially reserved area, and a completely removed area.
  • the structure shown in Fig. 8 can be obtained.
  • the photoresist layer 15 forms a completely remaining region 151, a partially reserved region 152, and a completely removed region.
  • the photoresist layer 15 having a thickness ratio of the completely remaining region 151 and the partially remaining region 152 of about 4:1 is obtained.
  • the halftone mask 14 or the gray dimming cover 14 includes an opaque region 141, a semi-transmissive region 142, and a fully transparent region 143, and the light transmittance of the semi-transmissive region 142 is 30. % ⁇ 50%.
  • Step S1023 removing the transparent conductive film and the metal film corresponding to the completely removed region by an etching process to form an address electrode.
  • the metal thin film 13 covers the transparent conductive film 12, it can be removed first by a dry etching process.
  • the metal film 13 corresponding to the region; the transparent conductive film 12 corresponding to the completely removed region is removed by a wet etching process to form the address electrode 10, as shown in FIG.
  • Step S1024 using a ashing process to remove a portion of the photoresist in the remaining area.
  • Step S1025 removing a metal thin film corresponding to a portion of the remaining region by an etching process and stripping the residual photoresist to form a metal structure 11 matched with the address electrode.
  • the remaining metal film 13 is the metal structure 11 matched with the address electrode 10, as shown in FIG.
  • the address electrodes 10 of the array substrate are crisscrossed.
  • the address electrodes 10 are connected via the via holes 6 to the first trace 16 which is in the same layer as the source 24 and the drain 25 of the thin film transistor 2.
  • the first trace 16 is connected via the via 6 to the second trace 17 of the same layer as the gate 22, and the second trace 17 of the address electrode 10 of the same row or column is connected. It is ensured that the address electrodes 10 located in different rows or columns are insulated from each other, and the touch function of the array substrate is ensured.
  • the address electrodes 10 on the array substrate include a driving electrode and a sensing electrode.
  • the driving electrode and the sensing electrode are both square and located on the same plane, so that the driving electrode and the sensing electrode can completely cover the display area of the array substrate, and the touch signal applied to the display area is prevented from being ignored.
  • the drive electrodes located in the same row and the drive electrodes in the same row are connected to each other by a cross-layer method. Therefore, a capacitance is formed at the intersection of the sensing electrode and the driving electrode, and adjacent sensing electrodes and driving electrodes can form a capacitance.

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Abstract

一种阵列基板的制备方法，包括依次形成透明导电薄膜（12）和金属薄膜（13）（S101）；采用光罩工艺，将透明导电薄膜形成寻址电极（10），同时将金属薄膜形成与寻址电极搭配的金属结构（11），光罩工艺为半色调光罩工艺或灰色调光罩工艺（S102）。

Description

一种阵列基板的制备方法
本申请要求享有2014年12月31日提交的名称为“一种阵列基板的制备方法”的中国专利申请CN201410855378.X的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板的制备方法。
背景技术
随着智能电子产品的普及，电容式触控屏被广泛的应用于手机、平板电脑等各种电子产品中。目前较为多见的电容式触控屏有OGS(One Glass Solution)、on-cell和in-cell三种技术。其中，in-cell技术由于其制作工艺上的优势，相比OGS技术和on-cell技术，具有更加轻薄、透光性更好、结构更加稳定等优点。
发明人发现，为了减小寻址电极的阻值，采用in-cell技术的触控屏中，需要对寻址电极搭配一金属结构。但该金属结构的出现将增加制备阵列基板的工艺复杂程度，降低阵列基板的良品率。
发明内容
本发明的目的在于提供一种阵列基板的制备方法，以解决采用in-cell技术的触控屏中，阵列基板的制备工艺复杂的技术问题。
本发明提供了一种阵列基板的制备方法，该方法包括：
依次形成透明导电薄膜和金属薄膜；
采用光罩工艺，将所述透明导电薄膜形成寻址电极，同时将所述金属薄膜形成与所述寻址电极搭配的金属结构，所述光罩工艺为半色调光罩工艺或灰色调光罩工艺。
其中，采用光罩工艺，将所述透明导电薄膜形成寻址电极，同时将所述金属薄膜形成与所述寻址电极搭配的金属结构包括：
在所述金属薄膜之上形成预定厚度的光刻胶层；
采用半色调光罩或灰色调光罩，对所述光刻胶层进行曝光和显影，所述光刻胶层形成完全保留区域、部分保留区域以及完全去除区域；
通过刻蚀工艺去除所述完全去除区域对应的透明导电薄膜和金属薄膜，形成所述寻址电极；
利用灰化工艺，去除所述部分保留区域的光刻胶；
通过刻蚀工艺去除所述部分保留区域对应的金属薄膜并剥离残留的光刻胶，形成与所述寻址电极搭配的金属结构。
其中，通过刻蚀工艺去除完全去除区域对应的透明导电薄膜和金属薄膜，形成寻址电极包括：
通过干刻工艺，去除所述完全去除区域对应的金属薄膜；
通过湿刻工艺，去除所述完全去除区域对应的透明导电薄膜，形成寻址电极。
其中，所述寻址电极包括驱动电极和感应电极。
其中，所述半色调光罩或所述灰色调光罩包括不透光区域、半透光区域和全透光区域，所述半透光区域的光强透过率为30％～50％。
其中，采用溅射或热蒸发的方式沉积形成厚度为
Figure PCTCN2015071059-appb-000001
的透明导电薄膜。
其中，所述透明导电薄膜的材质为氧化铟锡、氧化铟锌或氧化铟镓锌。
其中，采用溅射或热蒸发的方式在所述透明导电薄膜之上沉积厚度为
Figure PCTCN2015071059-appb-000002
的金属薄膜。
其中，所述光刻胶层的预定厚度为
Figure PCTCN2015071059-appb-000003
其中，所述完全保留区域和所述部分保留区域的厚度比为4∶1。
本发明带来了以下有益效果：在本发明实施例中，采用半色调光罩工艺或灰色调光罩工艺，可在同一次光罩工艺中形成寻址电极以及与寻址电极搭配的金属结构。无需经过两次光罩工艺分别图案化寻址电极和金属结构，有利于降低该阵列基板的制备工艺的复杂程度，降低该阵列基板的制备工艺的成本，同时提高阵列基板的制成良品率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1为本发明实施例中的阵列基板的结构示意图；
图2至图3为本发明实施例中的阵列基板的制备方法的流程图；
图4至图11为本发明实施例中的阵列基板的制备过程示意图；
图12为本发明实施例中的寻址电极的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明实施例提供了一种阵列基板的制备方法。如图1所示，该阵列基板包括多个像素单元，每个像素单元中设置有薄膜晶体管2和像素电极7。本发明实施例中的薄膜晶体管2为采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)的顶栅型薄膜晶体管。在该薄膜晶体管2中，LTPS21位于底层，栅极22位于LTPS21之上，且栅极22与LTPS21之间设置有栅极绝缘层23。栅极22上方设置有第一绝缘层3，源极24和漏极25设置于第一绝缘层3之上，并且源极24和漏极25通过过孔6与LTPS21连接且保持与栅极22绝缘。源极24和漏极25之上还设置有第二绝缘层4和第三绝缘层5，像素电极7通过贯穿第二绝缘层4和第三绝缘层5的过孔6连接至漏极25。
为了防止来自背光源的光照射至LTPS21的导电沟道，使得导电沟道在光照情况下出现光生电流、影响该薄膜晶体管2的性能。如图1所示，可在衬底基板1之上、LTPS21之下设置有遮光层8，该遮光层8用于为LTPS21遮光。
该阵列基板优选采用边缘场开关型(Fringe Field Switching，简称FFS)的驱动方式。FFS的核心技术特性可简单描述为：通过同一平面内狭缝状像素电极7电极边缘所产生的电场，使狭缝状电极间以及电极正上方的所有取向液晶分子都能够产生平面旋转，从而提高了液晶层的透光效率。FFS技术可以提高液晶显示器的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹等优点。
因此，如图1所示，该阵列基板还设置有公共电极9，公共电极9位于第三绝缘层5和第二绝缘层4之间，为板状结构。与该公共电极9配合的像素电极7则为具有狭缝的条状结构。
进一步的，为了实现触控功能，公共电极9可作为阵列基板的寻址电极10使用。该阵列基板在应用中可采用显示与触控分时扫描的驱动方式，具体的：在显示图像时，公共电极9为相应的像素单元提供公共电压，使公共电极9与像素电极7之间形成电场，并且一个公共电极9可以对应一个或多个像素单元；在触控扫描时，公共电极9作为寻址电极 10，用于传输触控信号，供位于阵列基板的边缘的处理芯片分析、判断触控信号发生处，使得阵列基板甚至整个显示装置可以根据该触控信号进行响应。
每一寻址电极10上设置有与寻址电极10短接的金属结构11，从而可降低寻址电极10的电阻，提高寻址电极10的感应灵敏度。为了制备寻址电极10及位于其上的金属结构11，如图2所示，该阵列基板的制备方法可包括：
步骤S101、依次形成透明导电薄膜和金属薄膜。
其中，可采用溅射或热蒸发的方式沉积形成厚度为
Figure PCTCN2015071059-appb-000004
的透明导电薄膜12，该透明导电薄膜12的材质可为氧化铟锡、氧化铟锌或氧化铟镓锌等。对于金属薄膜13，可采用溅射或热蒸发的方式在透明导电薄膜12之上沉积厚度为
Figure PCTCN2015071059-appb-000005
的金属薄膜13。
步骤S102、采用光罩工艺，将透明导电薄膜形成寻址电极，同时将金属薄膜形成与寻址电极搭配的金属结构，光罩工艺为半色调光罩工艺或灰色调光罩工艺。
在本发明实施例中，采用半色调光罩工艺或灰色调光罩工艺，可在同一次光罩工艺中形成寻址电极10以及与寻址电极10搭配的金属结构11。无需经过两次光罩工艺分别图案化寻址电极10和金属结构11，有利于降低该阵列基板的制备工艺的复杂程度，降低该阵列基板的制备工艺的成本，同时提高阵列基板的制成良品率。
具体的，如图3所示，步骤S102可包括如下步骤：
步骤S1021、在金属薄膜之上形成预定厚度的光刻胶层。
具体的，如图5所示，在图4形成了金属薄膜13的阵列基板之上，通过涂覆等方法形成光刻胶层15，该光刻胶层15的预定厚度为
Figure PCTCN2015071059-appb-000006
左右。
步骤S1022、采用半色调光罩或灰色调光罩，对光刻胶层进行曝光和显影，光刻胶层形成完全保留区域、部分保留区域以及完全去除区域。
采用半色调光罩14(图6)或灰色调光罩14(图7)，对图5所示的结构进行曝光显影之后，可得到如图8所示的结构。此时该光刻胶层15形成完全保留区域151、部分保留区域152和完全去除区域。通过控制光的强度和照射时长，得到完全保留区域151和部分保留区域152的厚度比为4∶1左右的光刻胶层15。
在本发明实施例中，半色调光罩14或灰色调光罩14包括不透光区域141、半透光区域142和全透光区域143，半透光区域142的光强透过率为30％～50％。
步骤S1023、通过刻蚀工艺去除完全去除区域对应的透明导电薄膜和金属薄膜，形成寻址电极。
由于金属薄膜13覆盖透明导电薄膜12，因此，可首先通过干刻工艺，去除完全去除 区域对应的金属薄膜13；之后通过湿刻工艺，去除完全去除区域对应的透明导电薄膜12，形成寻址电极10，如图9所示。
步骤S1024、利用灰化工艺，去除部分保留区域的光刻胶。
图9所示的结构去除光刻胶层15的部分保留区域152后，将部分保留区域152对应的金属薄膜13暴露出来，形成如图10所示的结构。
步骤S1025、通过刻蚀工艺去除部分保留区域对应的金属薄膜并剥离残留的光刻胶，形成与寻址电极搭配的金属结构11。
最后，通过干刻工艺去除部分保留区域152对应的金属薄膜13后，剩余的金属薄膜13即为与寻址电极10搭配的金属结构11，如图11所示。
在本发明实施例中，如图12所示，该阵列基板的寻址电极10纵横交错。如图1所示，为了使得同一列或同一行的寻址电极10彼此连接，寻址电极10通过过孔6连接与薄膜晶体管2的源极24和漏极25同层的第一走线16；第一走线16通过过孔6连接与栅极22同一图层的第二走线17，同一行或同一列的寻址电极10的第二走线17相连。保证了位于不同行或不同列的寻址电极10彼此绝缘，保证了阵列基板的触控功能。
若是将该阵列基板运用在互电容式触控屏中，阵列基板上的寻址电极10包括驱动电极和感应电极。驱动电极和感应电极均呈方形且位于同一平面，以使得驱动电极和感应电极可共同完整覆盖阵列基板的显示区域，防止加诸于显示区域上的触摸信号被忽略。如图1所示，通过跨层的方式，使得位于同一列的感应电极彼此连接、位于同一行的驱动电极彼此连接。因此，感应电极和驱动电极的交叠处形成电容，同时相邻的感应电极和驱动电极可形成电容。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。
附图标记说明：
1-衬底基板；2-薄膜晶体管；21-LTPS；22-栅极；23-栅极绝缘层；24-源极；25-漏极；3-第一绝缘层；4-第二绝缘层；5-第三绝缘层；6-过孔；7-像素电极；8-遮光层；9-公共电极；10-寻址电极；11-金属结构；12-透明导电薄膜；13-金属薄膜；14-光罩；141-不透光区域；142-半透光区域；143-全透光区域；15-光刻胶层；151-完全保留区域；152-部分保留区域；16-第一走线；17-第二走线。

Claims (10)

  1. 一种阵列基板的制备方法，其中，包括：
    依次形成透明导电薄膜和金属薄膜；
    采用光罩工艺，将所述透明导电薄膜形成寻址电极，同时将所述金属薄膜形成与所述寻址电极搭配的金属结构，所述光罩工艺为半色调光罩工艺或灰色调光罩工艺。
  2. 根据权利要求1所述的方法，其中，采用光罩工艺，将所述透明导电薄膜形成寻址电极，同时将所述金属薄膜形成与所述寻址电极搭配的金属结构包括：
    在所述金属薄膜之上形成预定厚度的光刻胶层；
    采用半色调光罩或灰色调光罩，对所述光刻胶层进行曝光和显影，所述光刻胶层形成完全保留区域、部分保留区域以及完全去除区域；
    通过刻蚀工艺去除所述完全去除区域对应的透明导电薄膜和金属薄膜，形成所述寻址电极；
    利用灰化工艺，去除所述部分保留区域的光刻胶；
    通过刻蚀工艺去除所述部分保留区域对应的金属薄膜并剥离残留的光刻胶，形成与所述寻址电极搭配的金属结构。
  3. 根据权利要求2所述的方法，其中，通过刻蚀工艺去除完全去除区域对应的透明导电薄膜和金属薄膜，形成寻址电极包括：
    通过干刻工艺，去除所述完全去除区域对应的金属薄膜；
    通过湿刻工艺，去除所述完全去除区域对应的透明导电薄膜，形成寻址电极。
  4. 根据权利要求1所述的方法，其中，所述寻址电极包括驱动电极和感应电极。
  5. 根据权利要求2所述的方法，其中，所述半色调光罩或所述灰色调光罩包括不透光区域、半透光区域和全透光区域，所述半透光区域的光强透过率为30％～50％。
  6. 根据权利要求1所述的方法，其中，采用溅射或热蒸发的方式沉积形成厚度为
    Figure PCTCN2015071059-appb-100001
    的透明导电薄膜。
  7. 根据权利要求1所述的方法，其中，所述透明导电薄膜的材质为氧化铟锡、氧化铟锌或氧化铟镓锌。
  8. 根据权利要求1所述的方法，其中，采用溅射或热蒸发的方式在所述透明导电薄膜之上沉积厚度为
    Figure PCTCN2015071059-appb-100002
    的金属薄膜。
  9. 根据权利要求2所述的方法，其中，所述光刻胶层的预定厚度为
    Figure PCTCN2015071059-appb-100003
  10. 根据权利要求2所述的方法，其中，所述完全保留区域和所述部分保留区域的厚度比为4∶1。
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