WO2016106880A1 - 阵列基板的制备方法 - Google Patents

阵列基板的制备方法 Download PDF

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WO2016106880A1
WO2016106880A1 PCT/CN2015/071046 CN2015071046W WO2016106880A1 WO 2016106880 A1 WO2016106880 A1 WO 2016106880A1 CN 2015071046 W CN2015071046 W CN 2015071046W WO 2016106880 A1 WO2016106880 A1 WO 2016106880A1
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insulating layer
layer
transparent region
conductive layer
partially transparent
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PCT/CN2015/071046
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English (en)
French (fr)
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杜海波
申智渊
明星
虞晓江
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深圳市华星光电技术有限公司
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Publication of WO2016106880A1 publication Critical patent/WO2016106880A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.
  • the thickness and excessive slope of the photoresist layer remaining after the half exposure technique are generally difficult to control, which may cause undesirable phenomena such as voiding in a portion of the photoresist layer.
  • the masking property of the photoresist layer to the underlying material to be processed is reduced, so that the structure formed by the material to be processed after the etching process does not conform to the preset.
  • the success rate of the semi-exposure technology is reduced, the yield of the array substrate is lowered, and the production cost of the array substrate is improved.
  • the invention provides a method for preparing an array substrate, comprising:
  • the remaining photoresist layer and the insulating layer corresponding to the partially transparent region are removed.
  • removing the insulating layer corresponding to the completely transparent region of the reticle, and removing the lithography corresponding to the partially transparent region are:
  • the insulating layer corresponding to the completely transparent region of the reticle is removed by a dry etching process, and the photoresist layer corresponding to the partially transparent region is removed, and the thickness of the insulating layer corresponding to the partially transparent region is reduced.
  • removing the conductive layer of the uncovered region of the insulating layer, and forming the conductive layer comprises:
  • the conductive layer of the uncovered region of the insulating layer is removed by a wet etching process to form a structure of the conductive layer.
  • the material of the conductive layer is indium tin oxide, indium zinc oxide or indium gallium zinc oxide.
  • the driving of the array substrate adopts a fringe field switching technology, and the conductive layer is a common electrode layer on the array substrate.
  • the material of the insulating layer is silicon, silicon nitride or silicon oxide.
  • the material of the conductive layer is metal or metal oxide.
  • the light transmittance of the partially transparent region is 30% to 50%.
  • the embodiment of the invention provides a method for preparing an array substrate, wherein the insulating layer is used as a mask for etching the conductive layer, and the light formed by the half exposure technique is reduced.
  • the quality requirements of the partially retained area of the engraved layer At this time, even if a part of the photoresist layer has a defect such as voiding, it does not easily affect the masking property of the insulating layer to the conductive layer to be etched, and the conductive layer can be formed to conform to the preset after etching.
  • the structure ensures the success rate of the half exposure technology and improves the yield of the array substrate.
  • FIG. 1 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present invention
  • FIGS. 2 to 7 are schematic structural views of an array substrate in an embodiment of the present invention.
  • the present invention provides a method for fabricating an array substrate.
  • an array substrate driven by Fringe Field Switching (FFS) is taken as an example for description.
  • FFS Fringe Field Switching
  • the core technical characteristics of FFS can be simply described as: the electric field generated by the edge of the slit-shaped pixel electrode in the same plane enables the plane-rotation of all the aligned liquid crystal molecules between the slit-shaped electrodes and directly above the electrode, thereby improving the liquid crystal.
  • FFS technology can improve the picture quality of liquid crystal display, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no squeeze water ripple.
  • the method for preparing the array substrate will be described by taking a pattern of a common electrode layer constituting the array substrate and the insulating layer 2 located thereon. As shown in FIG. 1, the method for preparing the array substrate includes:
  • Step S101 forming a conductive layer to be etched.
  • the conductive layer 1 is a common electrode layer of the array substrate. Therefore, the conductive layer 1 may be made of a transparent conductive material such as indium tin oxide, indium zinc oxide or indium gallium zinc oxide.
  • a gate electrode including a thin film transistor (TFT) and a gate insulating layer are formed on the substrate structure of the array substrate.
  • the underlying structure 3 of the source layer or the like is formed, and then the source 4 and the drain 5 of the thin film transistor are formed on the underlying structure 3. Since the drain 5 needs to be electrically connected to the pixel electrode of the array substrate, the organic layer 6 above the drain 5 is formed with a via corresponding to the drain 5.
  • the conductive layer 1 to be etched as the common electrode layer in this embodiment is formed.
  • Step S102 forming an insulating layer on the conductive layer, and forming a photoresist layer on the insulating layer.
  • the conductive layer 1 and the insulating layer 2 located thereon may be patterned in the same halftone mask process or gray dimmer process. Therefore, as shown in FIG. 3, after the insulating layer 2 is formed over the conductive layer 1, a photoresist layer 7 covering the insulating layer 2 is formed.
  • Step S103 performing a halftone mask process or a gray dimmer process, removing the insulating layer corresponding to the completely transparent region of the mask, removing the photoresist layer corresponding to the partially transparent region, and reducing the corresponding portion of the transparent region.
  • the thickness of the insulating layer is the thickness of the insulating layer.
  • the conductive layer 1 and the insulating layer 2 of the array substrate may be patterned by a halftone mask process or a gray dimmer process.
  • the array substrate is developed, and the photoresist layer 7 forms a non-retained area corresponding to the completely transparent region 81 of the mask 8.
  • the light transmittance of the partially transparent region 82 of the photomask 8 is about 30% to 50%, and the thickness ratio of the completely retained region and the partially retained region of the formed photoresist may be about 4:1.
  • the insulating layer 2 corresponding to the completely transparent region 81 of the photomask 8 can be removed by a dry etching process, and the removing portion can be removed.
  • the photoresist layer 7 corresponding to the light-transmitting region 82 is divided, and the thickness of the insulating layer 2 corresponding to the partial light-transmitting region 82 is reduced. Wherein, since the materials of the photoresist layer 7 and the insulating layer 2 are different, the photoresist layer 7 and the insulating layer 2 need to be dry-etched by using different gases.
  • the insulating layer 2 corresponding to the completely transparent region 81 may be first subjected to a dry etching process. Thereafter, the dry etching gas is replaced, and the photoresist layer 7 is etched.
  • the remaining thickness is smaller than the thickness of the photoresist layer 7 corresponding to the opaque region 83; therefore, by controlling the concentration of the dry etching gas and The entire photoresist layer 7 is etched by the parameters such as the velocity of circulation, and the photoresist layer 7 corresponding to the partially transparent region 82 is completely removed, and at the same time, the photoresist layer 7 remains in the opaque region 83.
  • the dry etching gas can be replaced again, and the exposed insulating layer 2 is etched to reduce the thickness of the portion of the insulating layer 2.
  • the dry etching gas corresponding to the photoresist and the dry etching gas corresponding to the insulating layer 2 may be doped, and the photoresist layer 7 and the insulating layer 2 on the array substrate are simultaneously performed by using the doping gas. Dry engraving.
  • Step S104 removing the conductive layer of the uncovered region of the insulating layer to form a structure of the conductive layer.
  • the insulating layer 2 can be used as a mask to treat the conductive layer 1 under the insulating layer 2.
  • the conductive layer 1 of the uncovered region of the insulating layer 2 is removed by a wet etching process to form the structure of the conductive layer 1.
  • the patterning process of the conductive layer 1 as the common electrode layer is completed.
  • the quality requirement of the partially reserved region of the photoresist layer 7 generated after the half exposure technique is reduced (for example, film thickness uniformity, etc.) .
  • the quality requirement of the partially reserved region of the photoresist layer 7 generated after the half exposure technique is reduced (for example, film thickness uniformity, etc.) .
  • it does not easily affect the masking property of the insulating layer 2 to the conductive layer 1 to be etched, thereby ensuring that the conductive layer 1 after etching can be formed.
  • Presetting the matching structure ensures the success rate of the half exposure technology and improves the yield of the array substrate.
  • Step S105 removing the remaining photoresist layer and the insulating layer corresponding to the partially transparent region.
  • the remaining photoresist layer 7 and the partial light-transmitting region 82 of the reticle 8 are successively or simultaneously removed by dry etching. Insulation layer 2.
  • the thickness of the insulating layer 2 corresponding to the partially transparent region 82 has been previously reduced. Therefore, if it is improperly handled in this step, the remaining light is caused before the insulating layer 2 corresponding to the partially transparent region 82 is removed.
  • the engraved layer 7 has been completely removed, and the insulating layer 2 can be further subjected to dry etching to form a pattern of the insulating layer 2 required, and the thickness of the insulating layer 2 after the dry etching can still ensure the insulating effect.
  • the parameters such as the concentration of the dry gas and the circulation speed should be controlled during the dry etching process. Moreover, after the insulating layer 2 corresponding to the partially transparent region 82 is completely removed, the dry etching process is stopped immediately, so as to prevent the insulating layer 2 that does not need to be removed from being excessively etched and affecting the insulating effect thereof.
  • a multilayer structure such as a flat layer 9 and a pixel electrode layer 10 is sequentially formed, and the preparation process of the array substrate can be completed.
  • capacitive touch screens are widely used in various electronic products such as mobile phones and tablet computers.
  • the more common capacitive touch screens are OGS (One Glass Solution), on-cell and in-cell.
  • OGS One Glass Solution
  • on-cell and in-cell are the more common capacitive touch screens.
  • in-cell technology has the advantages of lighter weight, better light transmission and more stable structure than OGS technology and on-cell technology due to its manufacturing process advantages.
  • the array substrate in the embodiment of the present invention further includes a touch layer metal line 11 on the common electrode layer and providing a touch signal, and adopts a driving mode of display and touch time-sharing scanning, that is, The touch function of the array substrate can be realized by using a common electrode layer.
  • the common electrode layer when displaying an image, provides a common voltage for the corresponding pixel unit, an electric field is formed between the common electrode layer and the pixel electrode layer 10, and one common electrode layer may correspond to one or more pixel units;
  • the common electrode layer serves as an address electrode for transmitting the touch signal, and the processing chip located at the edge of the array substrate analyzes and determines the occurrence of the touch signal, so that the array substrate or even the entire display device can perform the touch signal according to the touch signal. response.
  • the preparation method provided by the embodiments of the present invention is not only applicable to the patterning process of the common electrode layer and the insulating layer 2 located thereon, as long as the same halftone mask process or gray dimming can be utilized.
  • the two-layer structure of the mask process and the different etching processes are applicable to the method for preparing the array substrate provided by the embodiments of the present invention.
  • the material of the insulating layer 2 in the embodiment of the present invention is an insulating material suitable for a dry etching process such as silicon, silicon nitride or silicon oxide; in addition, the conductive layer 1 is made of indium tin oxide or indium zinc oxide. In addition to a metal oxide such as indium gallium zinc oxide, it may be a metal commonly used on an array substrate.

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Abstract

一种阵列基板的制备方法，包括：进行半色调光罩工艺或灰色调光罩工艺，去除光罩（8）的完全透光区域（81）对应的绝缘层（2），并去除部分透光区域（82）对应的光刻胶层（7）、减小所述部分透光区域（82）对应的绝缘层（2）的厚度；去除所述绝缘层（2）未覆盖区域的导电层（1），形成所述导电层（1）的结构；去除剩余的光刻胶层（7）以及所述部分透光区域（82）对应的绝缘层（2）。

Description

一种阵列基板的制备方法
本申请要求享有2014年12月31日提交的名称为“一种阵列基板的制备方法”的中国专利申请CN201410856151.7的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板的制备方法。
背景技术
在阵列基板的制作过程中，为了减少曝光次数，工程人员常使用半曝光技术。利用半曝光技术，可仅通过一道光罩(Mask)、同时对两层以上的待处理材料进行图案化处理，从而提高生产效率，降低生产成本。
但是受到材料和曝光工艺的制约，半曝光技术后残留的光刻胶层的厚度及过度坡度通常不易控制，这样可能造成光刻胶层的部分保留区域出现镂空等不良现象。进而降低了光刻胶层对下层待处理材料的掩蔽性，使得待处理材料经过刻蚀工艺后形成的结构与预设定的不符。降低了半曝光技术的成功率，降低了阵列基板的良品率，提高了阵列基板的生产成本。
发明内容
本发明的目的在于提供一种阵列基板的制备方法，提高了半曝光技术的成功率，并且提高了阵列基板的良品率。
本发明提供了一种阵列基板的制备方法，包括：
形成待刻蚀的导电层；
在所述导电层之上形成绝缘层，在所述绝缘层之上形成光刻胶层；
进行半色调光罩工艺或灰色调光罩工艺，去除所述光罩的完全透光区域对应的绝缘层，并去除部分透光区域对应的光刻胶层、减小所述部分透光区域对应的绝缘层的厚度；
去除所述绝缘层未覆盖区域的导电层，形成所述导电层的结构；
去除剩余的光刻胶层以及所述部分透光区域对应的绝缘层。
其中，去除所述光罩的完全透光区域对应的绝缘层，并去除部分透光区域对应的光刻 胶层、减小所述部分透光区域对应的绝缘层的厚度包括：
通过干刻工艺，去除所述光罩的完全透光区域对应的绝缘层，并去除部分透光区域对应的光刻胶层、减小所述部分透光区域对应的绝缘层的厚度。
其中，去除所述绝缘层未覆盖区域的导电层，形成所述导电层的结构包括：
通过湿刻工艺，去除所述绝缘层未覆盖区域的导电层，形成所述导电层的结构。
其中，所述导电层的材质为氧化铟锡、氧化铟锌或氧化铟镓锌。
其中，所述阵列基板的驱动采用边缘场开关技术，所述导电层为所述阵列基板上的公共电极层。
其中，所述绝缘层的材质为硅、硅的氮化物或硅的氧化物。
其中，所述导电层的材质为金属或金属氧化物。
其中，所述部分透光区域的光强透过率为30％～50％。
本发明带来了以下有益效果：本发明实施例提供了一种阵列基板的制备方法，该制备方法中采用绝缘层作为刻蚀导电层的掩膜，降低了对半曝光技术后所形成的光刻胶层的部分保留区域的质量要求。此时即使光刻胶层的部分保留区域出现镂空等不良现象，也不易影响到绝缘层对下层待刻蚀的导电层的掩蔽性，保证了刻蚀后导电层可以形成与预设定相符的结构，保证了半曝光技术的成功率，提高了阵列基板的良品率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是本发明实施例中的阵列基板的制备方法的流程示意图；
图2至图7是本发明实施例中的阵列基板的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明提供了一种阵列基板的制备方法，本发明实施例中以采用边缘场开关技术(Fringe Field Switching，简称FFS)进行驱动的阵列基板为例进行说明。FFS的核心技术特性可简单描述为：通过同一平面内狭缝状像素电极边缘所产生的电场，使狭缝状电极间以及电极正上方的所有取向液晶分子都能够产生平面旋转，从而提高了液晶层的透光效率。FFS技术可以提高液晶显示器的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹等优点。
具体的，本阵列基板的制备方法以构成该阵列基板的公共电极层及位于其上的绝缘层2的图案为例进行说明。如图1所示，该阵列基板的制备方法包括：
步骤S101、形成待刻蚀的导电层。
本发明实施例的技术方案中，该导电层1为该阵列基板的公共电极层，因此该导电层1的材质可选为氧化铟锡、氧化铟锌或氧化铟镓锌等透明导电材质。
在形成该待刻蚀的导电层1之前，如图2所示，需在该阵列基板的衬底结构上形成包括薄膜晶体管(Thin Film Transistor，简称TFT)的栅极、栅极绝缘层、有源层等结构的下层结构3，之后在该下层结构3上形成该薄膜晶体管的源极4和漏极5。由于漏极5需要电连接至阵列基板的像素电极，因此在漏极5之上的有机层6形成有对应漏极5的过孔。
之后，在所形成的有机层6之上，形成本实施例中的作为公共电极层的、待刻蚀的导电层1。可通过采用溅射或热蒸发的方式沉积形成厚度大致为
Figure PCTCN2015071046-appb-000001
的导电层1。
步骤S102、在导电层之上形成绝缘层，在绝缘层之上形成光刻胶层。
本发明实施例中，导电层1及位于其之上的绝缘层2可在同一次半色调光罩工艺或灰色调光罩工艺中进行图案化处理。因此，如图3所示，在导电层1之上形成绝缘层2之后，形成覆盖绝缘层2的光刻胶层7。
步骤S103、进行半色调光罩工艺或灰色调光罩工艺，去除光罩的完全透光区域对应的绝缘层，并去除部分透光区域对应的光刻胶层、减小部分透光区域对应的绝缘层的厚度。
形成光刻胶层7之后，可利用半色调光罩工艺或灰色调光罩工艺，同时对该阵列基板的导电层1和绝缘层2进行图案化处理。
如图4所示，在经过半色调光罩工艺或灰色调光罩工艺后，对阵列基板进行显影处理，光刻胶层7会形成对应光罩8的完全透光区域81的不保留区、对应部分透光区域82的部分保留区、对应不透光区域83的完全保留区。其中，光罩8的部分透光区域82的光强透过率大约为30％～50％，所形成的光刻胶的完全保留区域和部分保留区域的厚度比可为4∶1左右。
之后，可通过干刻工艺，去除光罩8的完全透光区域81对应的绝缘层2，并去除部 分透光区域82对应的光刻胶层7、减小部分透光区域82对应的绝缘层2的厚度。其中，由于光刻胶层7和绝缘层2的材质不同，因此光刻胶层7和绝缘层2需要利用不同的气体进行干刻处理。
在本发明实施例中，由于此时光罩8的完全透光区域81对应的光刻胶层7已通过显影处理去除，可首先对完全透光区域81对应的绝缘层2进行干刻工艺。之后，更换干刻气体，对光刻胶层7进行刻蚀工艺。
由于部分透光区域82对应的光刻胶层7的厚度经过显影处理之后，剩余的厚度小于不透光区域83对应的光刻胶层7的厚度；因此，可通过控制干刻气体的浓度和流通速度等参数，对整个光刻胶层7进行刻蚀工艺，完全去除部分透光区域82对应的光刻胶层7，同时保证不透光区域83仍存留有光刻胶层7。
部分透光区域82对应的光刻胶层7去除后，暴露出部分绝缘层2。此时，可再次更换干刻气体，对所暴露出的绝缘层2进行刻蚀处理、减小这部分绝缘层2的厚度。
或者，也可将对应于光刻胶的干刻气体和对应于绝缘层2的干刻气体掺杂，利用该掺杂气体，同时对该阵列基板上的光刻胶层7和绝缘层2进行干刻处理。
需要说明的是，对光刻胶层7的部分透光区域82对应的绝缘层2进行干刻处理后，应保证这部分被干刻处理之后的绝缘层2仍然能够完全覆盖其所对应的导电层1。
步骤S104、去除绝缘层未覆盖区域的导电层，形成导电层的结构。
如图5所示，对绝缘层2进行干刻处理、形成绝缘层2的图案后，可以绝缘层2作为掩膜，对位于绝缘层2之下的导电层1进行处理。通过湿刻工艺，去除绝缘层2未覆盖区域的导电层1，形成导电层1的结构。此时，作为公共电极层的导电层1的图案化处理完毕。
由于本发明实施例中采用绝缘层2作为刻蚀导电层1的掩膜，降低了对半曝光技术后所生成的光刻胶层7的部分保留区域的质量要求(例如膜厚均匀性等)。此时即使光刻胶层7的部分保留区域出现镂空等不良现象，也不易影响到绝缘层2对下层待刻蚀的导电层1的掩蔽性，保证了刻蚀后的导电层1可以形成与预设定相符的结构，保证了半曝光技术的成功率，提高了阵列基板的良品率。
步骤S105、去除剩余的光刻胶层以及部分透光区域对应的绝缘层。
如图6所示，在图5所示的阵列基板的结构的基础上，再次通过干刻处理，先后或同时去除剩余的光刻胶层7、以及光罩8的部分透光区域82对应的绝缘层2。
由于在本发明中，已预先将部分透光区域82对应的绝缘层2的厚度减小。因此，若是在此步骤中处理不当，导致在将部分透光区域82对应的绝缘层2去除之前、剩余的光 刻胶层7已被完全去除，仍可继续对绝缘层2进行干刻处理、形成所需要的绝缘层2的图形，且干刻处理后的绝缘层2的厚度仍然可以保证绝缘效果。
需要注意的是，在进行干刻处理时，应当控制干刻气体的浓度、流通速度等参数。并且需要在部分透光区域82对应的绝缘层2被完全去除后，立刻停止干刻处理，以免不需去除的绝缘层2遭到过度刻蚀、影响其的绝缘效果。
之后，在图6所示的结构的基础上，如图7所示，先后制作形成平坦层9、像素电极层10等多层结构，即可完成该阵列基板的制备工艺。
进一步的，随着智能电子产品的普及，电容式触控屏被广泛的应用于手机、平板电脑等各种电子产品中。目前较为多见的电容式触控屏有OGS(One Glass Solution)、on-cell和in-cell三种技术。其中，in-cell技术由于其制作工艺上的优势，相比OGS技术和on-cell技术，具有更加轻薄、透光性更好、结构更加稳定等优点。
因此，如图7所示，本发明实施例中的阵列基板还包括位于公共电极层上的、提供触控信号的触控层金属线11，采用显示与触控分时扫描的驱动方式，即可利用公共电极层实现该阵列基板的触控功能。具体的：在显示图像时，公共电极层为相应的像素单元提供公共电压，使公共电极层与像素电极层10之间形成电场，并且一个公共电极层可以对应一个或多个像素单元；在触控扫描时，公共电极层作为寻址电极，用于传输触控信号，供位于阵列基板边缘的处理芯片分析、判断触控信号发生处，使得阵列基板甚至整个显示装置可以根据该触控信号进行响应。
需要说明的是，本发明实施例所提供的制备方法并不仅仅适用于对公共电极层及位于其之上的绝缘层2进行构图工艺，只要可利用同一道半色调光罩工艺或灰色调光罩工艺、且采用不同的刻蚀工艺的两层结构均适用于本发明实施例所提供的阵列基板的制备方法。
因此，本发明实施例中的绝缘层2的材质为硅、硅的氮化物或硅的氧化物等适用干刻工艺的绝缘材质；另外，导电层1的材质除了为氧化铟锡、氧化铟锌或氧化铟镓锌等金属氧化物之外，还可为阵列基板上常用的金属。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (8)

  1. 一种阵列基板的制备方法，其中，包括：
    形成待刻蚀的导电层；
    在所述导电层之上形成绝缘层，在所述绝缘层之上形成光刻胶层；
    进行半色调光罩工艺或灰色调光罩工艺，去除光罩的完全透光区域对应的绝缘层，并去除部分透光区域对应的光刻胶层、减小所述部分透光区域对应的绝缘层的厚度；
    去除所述绝缘层未覆盖区域的导电层，形成所述导电层的结构；
    去除剩余的光刻胶层以及所述部分透光区域对应的绝缘层。
  2. 根据权利要求1所述的方法，其中，去除光罩的完全透光区域对应的绝缘层，并去除部分透光区域对应的光刻胶层、减小所述部分透光区域对应的绝缘层的厚度包括：
    通过干刻工艺，去除所述光罩的完全透光区域对应的绝缘层，并去除部分透光区域对应的光刻胶层、减小所述部分透光区域对应的绝缘层的厚度。
  3. 根据权利要求1所述的方法，其中，去除所述绝缘层未覆盖区域的导电层，形成所述导电层的结构包括：
    通过湿刻工艺，去除所述绝缘层未覆盖区域的导电层，形成所述导电层的结构。
  4. 根据权利要求1所述的方法，其中，所述导电层的材质为氧化铟锡、氧化铟锌或氧化铟镓锌。
  5. 根据权利要求4所述的方法，其中，所述阵列基板的驱动采用边缘场开关技术，所述导电层为所述阵列基板上的公共电极层。
  6. 根据权利要求1所述的方法，其中，
    所述绝缘层的材质为硅、硅的氮化物或硅的氧化物。
  7. 根据权利要求1所述的方法，其中，
    所述导电层的材质为金属。
  8. 根据权利要求1所述的方法，其中，
    所述部分透光区域的光强透过率为30％～50％。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112270891A (zh) * 2020-11-03 2021-01-26 上海天马有机发光显示技术有限公司 显示面板及其制备方法、显示装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105677123B (zh) 2016-01-11 2018-09-11 京东方科技集团股份有限公司 一种触控面板及其制作方法、显示装置
CN107154405B (zh) * 2017-05-09 2019-10-22 北京理工大学 金属自容触控基板的过孔刻蚀方法
CN112542471A (zh) * 2020-12-04 2021-03-23 武汉华星光电半导体显示技术有限公司 阵列基板的制备方法、阵列基板及显示面板
CN114023275B (zh) * 2021-11-29 2022-09-27 Tcl华星光电技术有限公司 背光模组的驱动方法及驱动装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429058B1 (en) * 2000-06-02 2002-08-06 International Business Machines Corporation Method of forming fully self-aligned TFT improved process window
CN1645224A (zh) * 2005-01-26 2005-07-27 广辉电子股份有限公司 薄膜晶体管液晶显示器的像素电极接触点的制造方法
CN101034262A (zh) * 2006-03-09 2007-09-12 京东方科技集团股份有限公司 一种薄膜晶体管液晶显示器的阵列基板的制作方法
CN101728333A (zh) * 2008-10-10 2010-06-09 华映视讯（吴江）有限公司 阵列基板的制造方法
CN102681714A (zh) * 2011-10-10 2012-09-19 京东方科技集团股份有限公司 触摸感应器的制造方法及显示设备
CN102723279A (zh) * 2012-06-12 2012-10-10 华南理工大学 一种金属氧化物薄膜晶体管的制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04282831A (ja) * 1991-03-12 1992-10-07 Fujitsu Ltd 半導体装置の製造方法
JP4282831B2 (ja) * 1999-06-17 2009-06-24 旭化成ケミカルズ株式会社 ジオール類の製法
JP2005108912A (ja) * 2003-09-29 2005-04-21 Quanta Display Japan Inc 液晶表示装置とその製造方法
KR101117725B1 (ko) * 2009-11-11 2012-03-07 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 이의 제조 방법
CN102654807A (zh) * 2011-10-10 2012-09-05 京东方科技集团股份有限公司 触控面板的制备方法
CN102543867A (zh) * 2012-03-08 2012-07-04 南京中电熊猫液晶显示科技有限公司 一种金属氧化物薄膜晶体管阵列基板的制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429058B1 (en) * 2000-06-02 2002-08-06 International Business Machines Corporation Method of forming fully self-aligned TFT improved process window
CN1645224A (zh) * 2005-01-26 2005-07-27 广辉电子股份有限公司 薄膜晶体管液晶显示器的像素电极接触点的制造方法
CN101034262A (zh) * 2006-03-09 2007-09-12 京东方科技集团股份有限公司 一种薄膜晶体管液晶显示器的阵列基板的制作方法
CN101728333A (zh) * 2008-10-10 2010-06-09 华映视讯（吴江）有限公司 阵列基板的制造方法
CN102681714A (zh) * 2011-10-10 2012-09-19 京东方科技集团股份有限公司 触摸感应器的制造方法及显示设备
CN102723279A (zh) * 2012-06-12 2012-10-10 华南理工大学 一种金属氧化物薄膜晶体管的制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112270891A (zh) * 2020-11-03 2021-01-26 上海天马有机发光显示技术有限公司 显示面板及其制备方法、显示装置

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