WO2013135125A1 - Tft阵列基板及其制造方法和显示装置 - Google Patents

Tft阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2013135125A1
WO2013135125A1 PCT/CN2013/071544 CN2013071544W WO2013135125A1 WO 2013135125 A1 WO2013135125 A1 WO 2013135125A1 CN 2013071544 W CN2013071544 W CN 2013071544W WO 2013135125 A1 WO2013135125 A1 WO 2013135125A1
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Prior art keywords
common electrode
spare
electrode line
shielding strip
line
Prior art date
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PCT/CN2013/071544
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English (en)
French (fr)
Inventor
张弥
Original Assignee
京东方科技集团股份有限公司
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Priority to US14/112,331 priority Critical patent/US9240422B2/en
Publication of WO2013135125A1 publication Critical patent/WO2013135125A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • TFT array substrate manufacturing method thereof and display device
  • the present invention relates to the field of liquid crystal display, and in particular to a TFT array substrate, a method of manufacturing the same, and a display device. Background technique
  • TFT-LCD Thin film transistor liquid crystal display
  • the TFT array substrate is the main component of TFT-LCD.
  • a TFT array substrate in the prior art includes: a gate line 19, a data line 20, and a pixel unit defined by the gate line 19 and the data line 20;
  • FIG. 1 takes one pixel unit as an example, and simultaneously Referring to the cross-sectional view of the pixel unit shown in FIG. 2 along the line AA, it can be seen that the pixel unit includes: a common electrode line 11, a gate electrode 13 of the thin film transistor, a source electrode 14 and a drain electrode 15, and a gate insulating layer 16, The semiconductor active layer, the passivation layer 17, the pixel electrode 12, and the like; wherein the pixel electrode 12 is connected to the drain 15 through a passivation layer via between the passivation layer 17 and the drain 15.
  • a gate insulating layer 16 and a passivation layer 17 are provided between the common electrode line 11 and the pixel electrode 12 as shown in FIG. 2, when a passivation layer via hole is formed under the etching process of the prior art, once There is a manufacturing error. Because the passivation layer is the same or similar to the material of the gate insulating layer, the passivation layer may be broken and the resulting gate insulating layer may be eroded at the same position (for example, etching solution) to be broken. In this case, if the position is the position of the common electrode line, the pixel electrode and the common electrode line are short-circuited, thereby causing bright spots or bright lines on the liquid crystal display panel (display screen). Summary of the invention
  • the embodiment of the present invention provides a TFT array substrate, a method of manufacturing the same, and a display device.
  • a TFT array substrate comprising: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units defined by the gate lines and the data lines, wherein each pixel unit
  • the method includes: a common electrode line and a pixel electrode, and sequentially formed on the common electrode line and the image a gate insulating layer and a passivation layer between the pixel electrodes; wherein in each pixel unit, a spare common electrode is disposed at a position between the gate insulating layer and the passivation layer and opposite to the common electrode line And; the spare common electrode line is electrically insulated from the data line.
  • a display device comprising the above TFT array substrate.
  • a method of fabricating a TFT array substrate includes: forming a plurality of gate lines, a plurality of data lines on a substrate, and in an area defined by the gate lines and the data lines Forming a plurality of pixel units, wherein the forming of each of the pixel units comprises:
  • a passivation layer and a pixel electrode are formed over the alternate common electrode line.
  • FIG. 1 is a top plan view of a TFT array substrate in the prior art
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • FIG. 3 is a top view of a TFT array substrate according to an embodiment of the present invention.
  • Figure 4 is a cross-sectional view taken along line A-A of Figure 3;
  • Figure 5 is a cross-sectional view of the passivation layer of Figure 4 when it is broken;
  • FIG. 6 is a top plan view of another TFT array substrate according to an embodiment of the present invention.
  • Figure 7 is a cross-sectional view taken along line B-B of Figure 6.
  • an embodiment of the present invention provides a TFT array substrate, including: a plurality of gate lines 19, a plurality of data lines 20, and a plurality of pixel units defined by the gate lines 19 and the data lines 20, wherein each The pixel unit includes: a common electrode line 11 and a pixel electrode 12, and a gate insulating layer 16 and a passivation layer 17 formed between the common electrode line 11 and the pixel electrode 12; in each pixel unit, the gate insulating layer 16 and the blunt layer A spare common electrode line 41 is disposed between the layers 17 and opposite to the common electrode line 11; and, the spare common electrode line 41 is electrically connected to the data line 20, that is, electrically insulated.
  • the spare common electrode line 41 may be made of the same material as the common electrode line 11, for example, copper, molybdenum or the like.
  • the common electrode lines of all the pixel units in the same row may be connected together, usually in a unitary structure; it should be noted that the spare common electrode added in this embodiment Line 41 is set in each pixel unit At the position where the common electrode line 11 is facing, and although the spare common electrode line 41 and the data line 20 are both provided between the gate insulating layer 16 and the passivation layer 17, the spare common electrode line 41 and the data line 20 are referred to FIG. There is no electrical connection.
  • FIG. 4 is a cross-sectional view of the TFT array substrate shown in FIG. 3 taken along line AA.
  • a gate insulating layer 16, a passivation layer 17, and a gate electrode 12 are disposed between the pixel electrode 12 and the common electrode line 11.
  • a backup common electrode line 41 disposed between the gate insulating layer 16 and the passivation layer 17 at a position directly opposite to the common electrode line 11.
  • the spare common electrode line 41 can be made of the same material as the common electrode line 11, so that the etching of the films of the two materials is different.
  • etching which can be performed by etching with an etching solution or by dry etching with a gas
  • the failure causes the passivation layer 17 above the common electrode line 11 to be eroded and broken, since the gate insulating layer 16 under the position of the common electrode line 41 of the passivation layer 17 does not break, thereby avoiding the pixel electrode to some extent. 12 is shorted to the common electrode line 11, thereby preventing the appearance of bright or bright lines on the display.
  • the common electrode line 11 in the pixel unit can be connected to the spare common electrode line 41 by laser, 1: early connection, etc., thereby ensuring publicity. Normal transmission of electrical signals on electrode line 11.
  • the spare common electrode line 41 is disposed in the same layer as the data line 20.
  • “same layer” means that a plurality of patterns or structures are formed in the same process (i.e., a patterning process) using the same material.
  • the standby common electrode line 41 is disposed in the same layer as the data line 20 in such a manner that a metal thin film is formed by using a metal material such as molybdenum or copper, and the metal thin film is patterned by a patterning process to form the data line 20 and the spare common electrode.
  • the pattern of the source and drain of the thin film transistor can also be formed using the metal film of the layer. Since the same layer setting can simplify the manufacturing process, it is a preferred method.
  • the spare common electrode line 41 and the data line 20 may be disposed in different layers, so that two layers of thin films are needed to separately form the data line 20 and the spare common electrode line 41, and the preparation method may have Various types are not limited in the embodiment of the present invention.
  • the pixel unit further includes a light blocking strip 42, as shown in FIGS.
  • the light shielding strip 42 and the common electrode line 11 may have an integrated structure (the two may also be non-integrated according to actual conditions). Structure).
  • the light-shielding strip 42 is disposed adjacent the opposite edge of the pixel unit 12 and in the same layer as the common electrode line 11 for improving light leakage in the pixel unit.
  • a replacement light-shielding strip 43 is further disposed in each pixel unit of the TFT array substrate provided by the present invention, which is disposed on the gate insulating layer 16 and The passivation layer 17 is at a position opposite to the light shielding strip 42; and, the spare light shielding strip 43 is not electrically connected to the data line 20.
  • the light-shielding strip 42 and the spare light-shielding strip 43 are simultaneously shown in FIG. 6 , and their relative positions are slightly misaligned. In fact, the light-shielding strip 42 is opposite to the spare light-shielding strip 43 , and in FIG. 7 , it can be clearly seen The positional relationship (overlap each other) of the light-shielding strip 42 and the spare light-shielding strip 43. It should be noted that although the additional light-shielding strip 43 and the data line 20 added in the present invention are disposed between the gate insulating layer 16 and the passivation layer 17, the spare light-shielding strip 43 is not electrically connected to the data line 20 with reference to FIG.
  • the pixel electrode 12 and the light shielding strip 42 are electrically connected, in the case where the light shielding strip 42 and the common electrode line 11 are integrated.
  • the pixel electrode 12 is short-circuited with the common electrode line 11; the present invention prevents the pixel electrode 12 from being short-circuited with the light-shielding strip 42 by providing a spare light-shielding strip 43 between the gate insulating layer 16 and the passivation layer 17.
  • the etching process is performed when a via hole is formed on the passivation layer 17 (in the etching process, the etching process may be performed) Etching with an etching solution, or dry etching with a gas) does not cause damage to the spare light-shielding strips 43 so that the gate insulating layer 16 under the spare light-shielding strips 43 does not break, and the spare light-shielding strips are used.
  • the pixel electrode 12 In the region where 43 is located, the pixel electrode 12 is prevented from being short-circuited with the light-shielding strip 42; or in the case where the passivation layer 17 is pressed or doped with impurities, etc., when the passivation layer 17 is broken, there is a spare light-shielding strip 43, The lower gate insulating layer 16 is not broken, and the pixel electrode 12 is prevented from being short-circuited with the light-shielding strip 42 in the region where the spare light-shielding strip 43 is located, thereby preventing the pixel electrode 12 from being short-circuited with the light-shielding strip 42, thereby preventing the pixel from being blocked.
  • the electrode 12 is shorted to the common electrode line 11.
  • the spare light-shielding strip 43 and the spare common electrode line 41 may not be a unitary structure, but in the present invention, as shown in FIG. 6, the spare light-shielding strip 43 and the spare common electrode line 41 are integrally formed; In the pixel unit, the spare light-shielding strip 43 and the spare common electrode line 41 of the unitary structure are completely corresponding to the light-shielding strip 42 and the common electrode line 44 of the integral structure as a whole, which prevents Shorted by 12.
  • the pattern of the spare common electrode lines 41 completely covers the pattern of the common electrode lines 11.
  • the passivation layer 17 is eroded and broken, a passivation layer 17 is formed. 16 No breakage occurs.
  • the pattern of the common common electrode line 41 completely covers the pattern of the common electrode line 11, the area where the common electrode line 11 is located can completely avoid short-circuiting with the pixel electrode 12.
  • the pattern of the spare light-shielding strips 43 completely covers the pattern of the light-shielding strips 42.
  • the etching method for forming the passivation layer 17 through the via hole does not cause damage to the dummy light-shielding strip 43, so that the gate insulating layer 16 is not broken. Since the pattern of the spare light-shielding strip 43 completely covers the pattern of the light-shielding strips 42, the area where the light-shielding strips 42 are located can completely avoid short-circuiting with the pixel electrodes 12, thereby preventing the common electrode lines 11 from being short-circuited with the pixel electrodes 12.
  • the pattern of the common electrode lines 11 in one pixel unit is based on the pattern in which the common electrode lines 11 and the pixel electrodes 12 overlap in the pixel unit.
  • the above complete coverage means that the upper layer pattern completely obscures the lower layer pattern from a top view; of course, the complete coverage includes a special case of complete coincidence.
  • the spare light shielding strips 43 are disposed in the same layer as the data lines 20.
  • the spare common electrode line 41 and the spare light-shielding strip 43 are disposed in the same layer as the data line 20.
  • three patterns of the spare common electrode line 41, the spare light-shielding strip 43, and the data line 20 are formed on a film made of the same material by a patterning process.
  • the standby common electrode line 41, the spare light-shielding strip 43 and the data line 20 are disposed in the same layer.
  • the formation process of the structure is: using a material such as molybdenum or copper to form a source-drain metal film, and the source-drain metal film is formed into a data line 20 by a patterning process. a pattern of the standby common electrode line 41, the spare light-shielding strip 43, and the source and drain of the thin film transistor. Since the same layer arrangement can simplify the fabrication process, it is a preferred method. Of course, in other embodiments of the present invention, the spare light bar 43 and the spare common electrode line 41 and the data line 20 may be disposed in different layers.
  • Embodiments of the present invention also provide a method of fabricating a TFT array substrate, comprising: forming a gate line 19, a data line 20 on a substrate, and forming a plurality of pixel units in a region defined by the gate line 19 and the data line 20, wherein each The formation of one pixel unit includes:
  • a spare common electrode line 41 is formed over the gate insulating layer 16, and the spare common electrode line 41 is located at a position directly opposite to the common electrode line 11 and is electrically insulated from the data line 21;
  • a passivation layer 17 and a pixel electrode 12 are formed over the spare common electrode line 41.
  • the spare common electrode line 41 and the data line 20 are preferably formed in the same layer, which simplifies the fabrication process.
  • the standby common electrode line 41 and the data line 20 are formed by forming a metal thin film using a metal material such as molybdenum or copper, and patterning the metal thin film by a patterning process to form the data line 20 and the spare common electrode line 41. pattern.
  • the pattern of the source and drain of the thin film transistor can also be formed using the metal film of the layer.
  • the pattern of the spare common electrode line 41 is preferably configured to completely cover the pattern of the common electrode line 11.
  • the forming of the pixel unit may further include:
  • a spare light-shielding strip 43 is formed between the gate insulating layer 16 and the passivation layer 17, and the spare light-shielding strip 43 is located at a position directly opposite to the light-shielding strip 42 and is electrically insulated from the data line 20 to prevent the pixel electrode 12 and the light-shielding strip Short circuit of 42.
  • the spare light-shielding strips 43 and the data lines 20 are preferably formed in the same layer, and more preferably, the spare common electrode lines 41, the spare light-shielding strips 43 and the data lines 20 are formed in the same layer to simplify the fabrication process.
  • the pattern of the spare light-shielding strips 43 is preferably configured to completely cover the pattern of the light-shielding strips 42.
  • the spare light shielding strip 43 and the spare common electrode line 41 are preferably of a unitary structure.
  • the embodiment of the invention further provides a display device comprising any of the above TFT array substrates.
  • the TFT array substrate includes: a plurality of gate lines 19, a plurality of data lines 20, and a plurality of pixel units defined by the gate lines 19 and the data lines 20, wherein each of the pixel units includes: a common electrode line 11 and a pixel electrode 12, and a gate insulating layer 16 and a passivation layer 17 formed between the common electrode line 11 and the pixel electrode 12; in each pixel unit, between the gate insulating layer 16 and the passivation layer 17 and with the common electrode line 11
  • the standby common electrode line 41 is disposed at a position opposite to each other; and the spare common electrode line 41 is electrically insulated from the data line 20.
  • An example of the display device is a liquid crystal display device in which a TFT array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the TFT array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the TFT array substrate.
  • Another example of the display device is an organic electroluminescence display device (OLED) in which a stack of organic light-emitting materials is formed on a TFT array substrate, and a pixel electrode of each pixel unit is another example of the display device.
  • OLED organic electroluminescence display device
  • a paper display device in which an electronic ink layer is formed on a TFT array substrate, and a pixel electrode of each pixel unit serves as a voltage for applying a charged microparticle moving in

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Abstract

一种TFT阵列基板及其制造方法和显示装置。TFT阵列基板包括：栅线（19）、数据线（20）、以及多个像素单元，每一个像素单元依次包括公共电极线（11）、栅绝缘层（16）、钝化层（17）和像素电极（12），其中在栅绝缘层（16）和钝化层（17）之间且与公共电极线（11）正相对的位置上设置有备用公共电极线（41），备用公共电极线（41）与数据线（20）无电连接。具有这样的结构的TFT阵列基板能避免像素电极（12）与公共电极线（11）之间的短接。

Description

TFT阵列基板及其制造方法和显示装置 技术领域
本发明涉及液晶显示领域，尤其涉及一种 TFT阵列基板及其制造方法和 显示装置。 背景技术
薄膜晶体管液晶显示器（TFT-LCD )具有体积小、 功耗低、 无辐射等特 点，现已成为平板显示器市场中的主导产品，其中 TFT阵列基板为 TFT-LCD 的主要组成部分。
现有技术中一种 TFT阵列基板， 如图 1所示， 包括： 栅线 19、 数据线 20、 以及由栅线 19和数据线 20限定的像素单元； 图 1以一个像素单元作为 示例， 同时， 参考图 2所示的该像素单元在沿 A-A线的剖视图， 可以看到该 像素单元包括： 公共电极线 11 , 薄膜晶体管的栅极 13、 源极 14和漏极 15, 栅绝缘层 16, 半导体有源层， 钝化层 17, 像素电极 12等； 其中， 像素电极 12通过钝化层 17与漏极 15之间的钝化层过孔与漏极 15相连。
虽然如图 2所示，在公共电极线 11和像素电极 12之间设有栅绝缘层 16 和钝化层 17, 但在现有技术的刻蚀工艺条件下制作钝化层过孔时， 一旦出现 制作上的失误， 因钝化层与栅绝缘层的材料相同或相近， 会出现钝化层断裂 和由此引发的栅绝缘层在同一位置受到侵蚀（例如刻蚀液的侵蝕） 而断裂的 情况， 若这一位置是公共电极线所在位置， 则会导致了像素电极与公共电极 线短接， 进而造成在液晶显示面板（显示屏）上会产生亮点或亮线。 发明内容
因此， 为了解决像素电极与公共电极线短接的问题， 本发明的实施例提 供一种 TFT阵列基板及其制造方法和显示装置。
根据本发明的第一方面， 提供一种 TFT阵列基板， 包括： 多条栅线、 多 条数据线、 以及由所述栅线和所述数据线限定的多个像素单元， 其中每个像 素单元包括： 公共电极线和像素电极， 以及依次形成在所述公共电极线和像 素电极之间的栅绝缘层、 钝化层； 其中在每个像素单元内， 所述栅绝缘层与 钝化层之间且与所述公共电极线正相对的位置上， 设置有备用公共电极线； 并且， 所述备用公共电极线与所述数据线为电绝缘。
根据本发明的第二方面，提供一种显示装置，包括上述的 TFT阵列基板。 根据本发明的第三方面， 提供一种 TFT阵列基板的制造方法， 包括： 在 基板上形成多条栅线、 多条数据线、 以及在由所述栅线和所述数据线限定的 区域中形成多个像素单元， 其中每一个像素单元的形成包括：
依次形成公共电极线和栅绝缘层；
在栅绝缘层上方形成备用公共电极线， 该备用公共电极线位于与所述公 共电极线正相对的位置上并与所述数据线为电绝缘； 以及
在该备用公共电极线上方形成钝化层和像素电极。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中 TFT阵列基板的俯视图；
图 2为图 1沿 A-A线的截面图；
图 3为本发明实施例提供的一种 TFT阵列基板的俯视图；
图 4为沿图 3中 A-A线的截面图；
图 5为图 4中的钝化层断裂时的截面图；
图 6为本发明实施例提供的另一 TFT阵列基板的俯视图；
图 7为沿图 6中 B-B线的截面图。
附图标记：
11-公共电极线； 12-像素电极； 13-栅极、 14-源极； 15-漏极；
16-栅绝缘层； 17-钝化层； 19-栅线； 20-数据线；
41-备用公共电极线； 42-遮光条； 43-备用遮光条。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
如图 3所示， 本发明实施例提供一种 TFT阵列基板， 包括： 多条栅线 19、 多条数据线 20、 以及由栅线 19和数据线 20限定的多个像素单元， 其中 每个像素单元包括： 公共电极线 11和像素电极 12, 以及形成在公共电极线 11和像素电极 12之间的栅绝缘层 16、 钝化层 17; 在每个像素单元内， 栅绝 缘层 16与钝化层 17之间且与公共电极线 11正相对的位置上，设置有备用公 共电极线 41 ; 并且， 备用公共电极线 41与数据线 20无电连接， 即为电绝缘 的。
其中，备用公共电极线 41可以釆用与公共电极线 11相同的材料，例如： 铜、 钼等金属制作而成。
需要说明的是， 为了将公共电极线 11和备用公共电极线 41同时表示在 图 3所示的俯视图中， 图 3中两者的位置略有错位， 但实际上备用公共电极 线 41设置在公共电极线 11正对的位置（即相互重叠的位置）上， 这一正对 的位置关系可以通过图 4清楚的看到。 另外， 现有技术中， 在同一行（与栅 线平行）的所有像素单元的公共电极线可以是连在一起的，通常是一体结构； 需要注意的是,本实施例中增设的备用公共电极线 41在每个像素单元内设置 在公共电极线 11正对的位置上，且虽然备用公共电极线 41和数据线 20都设 在栅绝缘层 16与钝化层 17之间， 但参考图 3备用公共电极线 41和数据线 20并无电连接。
图 4为图 3所示的 TFT阵列基板沿 A-A线的剖视图， 参考图 4可以清 楚看到， 在像素电极 12与公共电极线 11之间设有栅绝缘层 16、 钝化层 17、 以及在栅绝缘层 16与钝化层 17之间且与公共电极线 11正相对的位置上设置 的备用公共电极线 41。
这样， 由于钝化层 17—般釆用氮化硅的材料， 备用公共电极线 41可以 釆用与公共电极线 11相同的材料，故刻蚀这两种材料的薄膜所使用的刻蚀方 式不同； 在通过刻蚀 （可以釆用刻蚀溶液进行刻蚀， 也可釆用气体进行干法 刻蚀）制作钝化层 17的过孔的过程中，如图 5所示， 即使出现制造中的失误 而造成公共电极线 11上方的钝化层 17受到侵蝕而断裂， 由于在钝化层 17 公共电极线 41位置下方的栅绝缘层 16也不会发生断裂， 从而在一定程度上 避免了像素电极 12与公共电极线 11短接， 进而防止了显示屏上亮点或亮线 的出现。
另外， 当某一像素单元内的公共电极线 11上出现断裂时，通过激光； 1：早接 等方法可以将该像素单元中的公共电极线 11与备用公共电极线 41连接， 从 而保证了公共电极线 11上的电信号的正常传输。
优选的， 备用公共电极线 41与数据线 20同层设置。 在本发明所有实施 例中， "同层"是指多个图案或结构利用同种材料在同一工序（即构图工艺） 中形成。 备用公共电极线 41与数据线 20同层设置这种结构的形成过程是， 利用钼、 铜等金属材料制作一层金属薄膜， 通过构图工艺图案化该金属薄膜 以形成数据线 20和备用公共电极线 41。 薄膜晶体管的源极和漏极的图案也 可利用该层金属薄膜形成。 由于同层设置可以简化制作工艺， 故而作为一优 选方法。 当然， 在本发明实施例中备用公共电极线 41与数据线 20可以不同 层设置，那么就需要制作两层薄膜用以分别图案化形成数据线 20和备用公共 电极线 41 , 其制备方法可以有多种， 在本发明实施例中不做限定。
在另一个实施例， 像素单元还包括遮光条 42, 如图 6、 7所示。 遮光条 42与公共电极线 11可以为一体结构 （根据实际情况， 二者也可以为非一体 结构） 。 如图所示， 该遮光条 42设置在像素单元 12的相对边缘附近并与公 共电极线 11位于同一层中， 用于改善像素单元中的漏光现象。
参考图 6和图 7 , 为了进一步防止像素电极 12和遮光条 42的短接， 在 本发明提供的 TFT阵列基板的每个像素单元内进一步包括备用遮光条 43 , 其设置在栅绝缘层 16与钝化层 17之间且与遮光条 42相对的位置上； 并且， 备用遮光条 43与数据线 20无电连接。
需要说明的是， 将遮光条 42与备用遮光条 43同时表示在图 6中， 其相 对位置略有错位， 实际上遮光条 42与备用遮光条 43正对， 在图 7中， 可以 清楚看到遮光条 42与备用遮光条 43的正对位置关系 （相互重叠） 。 需要注 意的是， 虽然本发明中增设的备用遮光条 43和数据线 20都设置在栅绝缘层 16与钝化层 17之间， 但参考图 6备用遮光条 43与数据线 20无电连接。
当钝化层 17和栅绝缘层 16在遮光条 42所在区域的同一位置发生断裂 时， 像素电极 12与遮光条 42会发生电连接， 在遮光条 42与公共电极线 11 为一体结构的情况下， 就会导致像素电极 12与公共电极线 11短接； 本发明 通过在栅绝缘层 16与钝化层 17之间设置备用遮光条 43来防止像素电极 12 与遮光条 42短接。
具体的， 在设置备用遮光条 43的情况下， 当钝化层 17受到侵蝕而断裂 时， 因在钝化层 17上形成过孔时所进行的刻蚀过程 (在该刻蚀过程中可以釆 用刻蚀溶液进行刻蚀， 也可釆用气体进行干法刻蚀） 不会对备用遮光条 43 造成损害， 使得备用遮光条 43下方的栅绝缘层 16不会发生断裂， 则在备用 遮光条 43所在的区域内， 防止了像素电极 12与遮光条 42短接；或者在钝化 层 17受到挤压或掺入杂质等情况下， 导致钝化层 17断裂时， 因存在备用遮 光条 43 , 下方的栅绝缘层 16不会发生断裂， 则在备用遮光条 43所在的区域 内， 防止了像素电极 12与遮光条 42短接， 防止了像素电极 12与遮光条 42 短接， 进而防止了像素电极 12与公共电极线 11短接。
其中， 备用遮光条 43和备用公共电极线 41可以不是一体结构， 但在本 发明中优选的， 如图 6所示， 备用遮光条 43和备用公共电极线 41为一体结 构； 此时，在一个像素单元内，使得一体结构的备用遮光条 43和备用公共电 极线 41与一体结构的遮光条 42和公共电极线 44整体上完全对应 ,这就防止 12的短接。
优选的，在每个像素单元内，备用公共电极线 41的图案完全覆盖公共电 极线 11的图案。 在这种情况下， 当钝化层 17受到侵蝕而断裂， 因形成钝化 层 17
Figure imgf000008_0001
16 未发生断裂， 此时， 因备用公共电极线 41的图案完全覆盖公共电极线 11图 案， 则公共电极线 11所在的区域能够完全避免与像素电极 12的短接。
又优选的， 在每个像素单元内， 备用遮光条 43 的图案完全覆盖遮光条 42的图案。 在这种情况下， 当钝化层 17受到侵蝕而断裂， 因形成钝化层 17 过孔釆用的刻蚀方式对备用遮光条 43未造成损害， 使得栅绝缘层 16未发生 断裂， 此时， 因备用遮光条 43的图案完全覆盖遮光条 42的图案， 则遮光条 42所在的区域能够完全避免与像素电极 12的短接， 进而避免了公共电极线 11与像素电极 12短接。
需要说明的是，上述在一个像素单元中的公共电极线 11的图案，以在该 像素单元内公共电极线 11和像素电极 12重合的图案为准。 上述完全覆盖是 指从俯视的角度来看， 上层图案将下层图案完全遮住； 当然， 完全覆盖包括 完全重合的特殊情况。
优选的，备用遮光条 43与数据线 20同层设置。在备用遮光条 43和备用 公共电极线 41为一体结构的情况下， 优选的， 备用公共电极线 41、 备用遮 光条 43与数据线 20同层设置。 具体的， 通过构图工艺在同种材料制成的一 层薄膜上形成备用公共电极线 41、 备用遮光条 43、 和数据线 20三种图案。 备用公共电极线 41、备用遮光条 43与数据线 20同层设置这种结构的形成过 程是： 利用钼、 铜等材料制作源漏金属薄膜， 通过构图工艺将该源漏金属薄 膜形成数据线 20、 备用公共电极线 41、 备用遮光条 43、 以及薄膜晶体管的 源极和漏极的图案。 由于同层设置可以简化制作工艺，故而作为一优选方法。 当然， 在本发明的其他实施例中， 备用遮光条 43、 备用公共电极线 41与数 据线 20可以不同层设置。
本发明的实施例还提供一种制造 TFT阵列基板的方法， 包括： 在基板上 形成栅线 19、 数据线 20以及在栅线 19和数据线 20限定的区域中形成多个 像素单元， 其中每一个像素单元的形成包括：
* 在栅绝缘层 16上方形成备用公共电极线 41 ,该备用公共电极线 41位于 与公共电极线 11正相对的位置上并与数据线 21为电绝缘； 以及
在该备用公共电极线 41上方形成钝化层 17和像素电极 12。
在一个示例中， 备用公共电极线 41与数据线 20优选为在同层中形成， 这样可以简化制作工艺。 具体地， 备用公共电极线 41与数据线 20的形成过 程是， 利用钼、 铜等金属材料制作一层金属薄膜， 通过构图工艺图案化该金 属薄膜， 以形成数据线 20和备用公共电极线 41图案。 薄膜晶体管的源极和 漏极的图案也可利用该层金属薄膜形成。另夕卜，备用公共电极线 41的图案优 选构造为完全覆盖公共电极线 11的图案。
在另一个示例中， 像素单元的形成还可包括：
形成遮光条 42, 以及
在栅绝缘层 16和钝化层 17之间形成备用遮光条 43 , 该备用遮光条 43 位于与遮光条 42正相对的位置上并与数据线 20为电绝缘， 以防止像素电极 12和遮光条 42的短接。
备用遮光条 43与数据线 20优选为在同层中形成， 更优选地， 备用公共 电极线 41、备用遮光条 43与数据线 20在同层中形成以简化制作工艺。另夕卜， 备用遮光条 43的图案优选构造为完全覆盖遮光条 42的图案。备用遮光条 43 和备用公共电极线 41优选为一体结构。
本发明实施例还提供一种显示装置，包括上述任一 TFT阵列基板。例如， 该 TFT阵列基板包括： 多条栅线 19、 多条数据线 20、 以及由栅线 19和数据 线 20限定的多个像素单元， 其中每个像素单元包括： 公共电极线 11和像素 电极 12, 以及形成在公共电极线 11和像素电极 12之间的栅绝缘层 16、钝化 层 17;在每个像素单元内，栅绝缘层 16与钝化层 17之间且与公共电极线 11 正相对的位置上， 设置有备用公共电极线 41 ; 并且， 备用公共电极线 41与 数据线 20为电绝缘的。
该显示装置的一个示例为液晶显示装置， 其中， TFT阵列基板与对置基 板彼此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为 彩膜基板。 TFT阵列基板的每个像素单元的像素电极用于施加电场对液晶材 料的旋转的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示装 置还包括为 TFT阵列基板提供背光的背光源。 该显示装置的另一个示例为有机电致发光显示装置 （OLED ) , 其中， TFT阵列基板上形成有有机发光材料叠层， 每个像素单元的像素电极作为阳 该显示装置的再一个示例为电子纸显示装置， 其中， TFT阵列基板上形 成有电子墨水层， 每个像素单元的像素电极作为用于施加驱动电子墨水中的 带电微颗粒移动以进行显示操作的电压。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种 TFT阵列基板， 包括： 多条栅线、 多条数据线、 以及由所述栅 线和所述数据线限定的多个像素单元， 其中每个像素单元包括： 公共电极线 和像素电极， 以及依次形成在所述公共电极线和像素电极之间的栅绝缘层、 钝化层； 其中在每个像素单元内， 所述栅绝缘层与钝化层之间且与所述公共 电极线正相对的位置上， 设置有备用公共电极线； 并且， 所述备用公共电极 线与所述数据线为电绝缘。
2、 根据权利要求 1所述的 TFT阵列基板， 其中在每个像素单元内， 所 述备用公共电极线的图案完全覆盖所述公共电极线的图案。
3、 根据权利要求 1所述的 TFT阵列基板， 其中所述备用公共电极线与 所述数据线同层设置。
4、 根据权利要求 1所述的 TFT阵列基板， 其中， 所述像素单元还包括 遮光条， 并且
在每个像素单元内， 所述栅绝缘层与钝化层之间且与所述遮光条相对的 位置上， 设置有备用遮光条； 所述备用遮光条与所述数据线为电绝缘。
5、 根据权利要求 4所述的 TFT阵列基板， 其中所述备用遮光条和所述 备用公共电极线为一体结构。
6、 根据权利要求 4所述的 TFT阵列基板， 其中在每个像素单元内， 所 述备用遮光条的图案完全覆盖所述遮光条的图案。
7、 根据权利要求 4所述的 TFT阵列基板， 其中所述备用遮光条与所述 数据线同层设置。
8、 根据权利要求 4所述的 TFT阵列基板， 其中所述备用公共电极线、 所述备用遮光条与所述数据线同层设置。
9、 一种显示装置， 包括权利要求 1所述的 TFT阵列基板。
10、 一种 TFT阵列基板的制造方法， 包括： 在基板上形成多条栅线、 多 条数据线、以及在由所述栅线和所述数据线限定的区域中形成多个像素单元， 其中每一个像素单元的形成包括：
依次形成公共电极线和栅绝缘层；
在栅绝缘层上方形成备用公共电极线， 该备用公共电极线位于与所述公 共电极线正相对的位置上并与所述数据线为电绝缘； 以及
在该备用公共电极线上方形成钝化层和像素电极。
11、根据权利要求 10所述的制造方法， 其中在每个像素单元内， 所述备 用公共电极线的图案完全覆盖所述公共电极线的图案。
12、根据权利要求 10所述的制造方法，其中所述备用公共电极线与所述 数据线在同层中形成。
13、根据权利要求 10所述的制造方法， 其中， 所述像素单元的形成还包 括：
形成遮光条， 以及
在栅绝缘层和钝化层之间形成备用遮光条， 该备用遮光条位于与所述遮 光条正相对的位置上并与所述数据线为电绝缘。
14、根据权利要求 13所述的制造方法，其中所述备用遮光条和所述备用 公共电极线为一体结构。
15、根据权利要求 13所述的制造方法， 其中在每个像素单元内， 所述备 用遮光条的图案完全覆盖所述遮光条的图案。
16、根据权利要求 13所述的制造方法，其中所述备用遮光条与所述数据 线在同层中形成。
17、根据权利要求 13所述的制造方法， 其中所述备用公共电极线、所述 备用遮光条与所述数据线在同层中形成。
PCT/CN2013/071544 2012-03-16 2013-02-07 Tft阵列基板及其制造方法和显示装置 WO2013135125A1 (zh)

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