WO2017177764A1 - 显示基板及液晶显示装置 - Google Patents

显示基板及液晶显示装置 Download PDF

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WO2017177764A1
WO2017177764A1 PCT/CN2017/073859 CN2017073859W WO2017177764A1 WO 2017177764 A1 WO2017177764 A1 WO 2017177764A1 CN 2017073859 W CN2017073859 W CN 2017073859W WO 2017177764 A1 WO2017177764 A1 WO 2017177764A1
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sub
pixel
pixel electrodes
display substrate
pixel unit
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PCT/CN2017/073859
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English (en)
French (fr)
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方正
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京东方科技集团股份有限公司
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Priority to US15/562,975 priority Critical patent/US20180196321A1/en
Publication of WO2017177764A1 publication Critical patent/WO2017177764A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133742—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers for homeotropic alignment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133753—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a display substrate and a liquid crystal display device.
  • At least one embodiment of the present disclosure is directed to a display substrate and a display device that can solve a flicker phenomenon of a display screen.
  • An aspect of the present disclosure provides a display substrate including a plurality of data lines and a plurality of gate lines, a plurality of pixel units; at least one of the plurality of pixel units includes at least two sub-pixel electrodes insulated from each other And two thin film transistors; the two sub-pixel electrodes are respectively connected to different ones of the two thin film transistors, and the sources of the two thin film transistors are respectively connected to two different data lines.
  • the two different data lines are configured to apply voltages of opposite polarity.
  • the two sub-pixel electrodes are respectively located in two different regions of the pixel unit.
  • the two sub-pixel electrodes are sequentially arranged in a direction in which the gate lines extend.
  • the two sub-pixel electrodes are sequentially arranged in a direction in which the data lines extend.
  • the gates of the two thin film transistors are connected to the same gate line or respectively connected to two different gate lines.
  • the distance between the two sub-pixel electrodes is 8-10 ⁇ m.
  • the two sub-pixel electrodes include a plate electrode or a strip electrode.
  • the at least one pixel unit includes three sub-pixel electrodes that are not in contact with each other and three thin film transistors respectively connected to the three sub-pixel electrodes; the sources of the three thin film transistors are respectively connected to different data lines .
  • the at least one pixel unit includes four sub-pixel electrodes that are not in contact with each other and arranged side by side, and four thin film transistors respectively connected to the four sub-pixel electrodes; the sources of the four thin film transistors are respectively connected differently Data line.
  • the two different data lines are configured to apply a voltage of the same absolute value.
  • Another aspect of the present disclosure provides a liquid crystal display device including the above display substrate.
  • the liquid crystal display device further includes a color filter substrate disposed opposite to the display substrate, the color filter substrate including pixel units corresponding to the plurality of pixel units of the display substrate, each of the color filter substrates
  • the pixel unit includes a color filter of one color.
  • Another aspect of the present disclosure also provides a driving method of the above liquid crystal display device, comprising: applying a voltage to different sub-pixel electrodes of each pixel unit on the display substrate, wherein different sub-pixels are applied to each pixel unit The voltages of the pixel electrodes are opposite in polarity and the absolute values are equal.
  • 1 is a top plan view showing a structure of a pixel unit
  • FIG. 2a is two sub-arrays arranged along a direction in which a gate line extends in a pixel unit according to an embodiment of the present disclosure
  • 2b is a schematic diagram of connecting two sub-pixel electrodes arranged along a direction of a gate line in a pixel unit according to an embodiment of the present disclosure to connect different gate lines;
  • FIG. 3 is a schematic diagram of a source and drain of a TFT disposed above a gate line according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of connecting two sub-pixel electrodes arranged along a direction in which a data line extends in a pixel unit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a gate line driving a sub-pixel electrode located on both sides of the gate line and adjacent to the gate line in a portion of the display area according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of distance between two sub-pixel electrodes in a pixel unit according to an embodiment of the present disclosure.
  • a display substrate for a liquid crystal display device includes a plurality of gate lines and a plurality of data lines disposed to cross each other.
  • the gate lines and data lines define a plurality of pixel cells arranged in an array on the display substrate.
  • Each pixel unit includes a pixel electrode and a corresponding Thin Film Transistor (TFT) or the like.
  • TFT Thin Film Transistor
  • FIG. 1 is a top plan view of a pixel unit of a display substrate.
  • a gate line 102 and a data line 108 define a pixel unit.
  • a TFT 110 is disposed adjacent to an intersection of the gate line 102 and the data line 108.
  • the TFT includes a gate 112, a source 118, a drain 119, and a gate.
  • An active layer 116 over the pole 112 and for providing a path for the source 118 and drain 119.
  • the gate line 102 is connected to the gate 112 to provide a gate line scan signal; the source 118 is connected to the data line 108 to provide a data signal; the drain 119 is connected to the pixel electrode 109 as an output electrode of the TFT, and is the pixel electrode 109.
  • An aspect of the present disclosure provides a display substrate including a plurality of data lines and a plurality of gate lines, a plurality of pixel units; at least one of the plurality of pixel units includes at least two insulation layers from each other a sub-pixel electrode and two thin film transistors; the two sub-pixel electrodes are respectively connected to different thin film transistors, and the sources of the two thin film transistors are respectively connected to two different data lines.
  • the pixel electrode structure can ensure that positive and negative voltage driving are simultaneously present in the same pixel unit, thereby ensuring that there is no difference even if the polarity of the driving voltage is reversed to the brightness of the same pixel unit, thereby reducing the flicker of the display device.
  • the present disclosure realizes positive and negative voltage driving in one pixel unit by providing two or more sub-pixel electrodes insulated from each other in one pixel unit and one TFT for each sub-pixel electrode.
  • the two data lines connected by the two sub-pixel electrodes have opposite voltage polarities.
  • Such a structure of a sub-pixel electrode driven by positive and negative voltages in one pixel unit can eliminate the phenomenon of picture flicker generated when driven by a positive voltage or a negative voltage alone.
  • the source and the drain of the TFT are not strictly distinguished, and the source and drain names are also interchanged when the source and drain are interchanged with the data line and the pixel electrode. Those skilled in the art are not allowed to explain this limitation.
  • the pixel unit does not necessarily correspond to a lattice in which a plurality of gate lines and a plurality of data lines cross each other. As long as the pixel unit is located in the display area, those skilled in the art may not limit the explanation.
  • two sub-pixel electrodes in a pixel unit of an embodiment of the present disclosure are located in different regions of the pixel unit, such as two regions juxtaposed in the pixel unit.
  • the two sub-pixel electrodes may have no intersection with each other.
  • connection relationship between the TFTs of the sub-pixel electrodes and the gate lines and the data lines in the pixel unit of the present disclosure will be further described by taking one pixel unit and two sub-pixel electrodes and two TFTs in the pixel unit as an example.
  • the number of sub-pixel electrodes in the pixel unit of the present disclosure is not limited to two.
  • the sub-pixel electrodes in one pixel unit are, for example, two, and the two sub-pixel electrodes are located in two different regions in the pixel unit.
  • the two sub-pixel electrodes are arranged side by side in the direction in which the gate lines extend.
  • the sub-pixel electrode 130 and the sub-pixel electrode 140 are disposed in order along the extending direction of the gate line 102, and are juxtaposed to each other.
  • Each of the sub-pixel electrodes is driven by one TFT, respectively.
  • the gates 112 of the two TFTs are connected to the same gate line 102.
  • the sources 118 of the two TFTs are respectively connected to two data lines 108 (i.e., the data lines 108 on the left and right sides of the pixel unit in the figure) that define the pixel unit and are adjacent to each other.
  • the drains 119 of the two TFTs are connected to the sub-pixel electrode 130 and the sub-pixel electrode 140, respectively.
  • the sub-pixel electrode 130 and the sub-pixel electrode 140 are respectively configured to apply positive and negative data voltages by the two TFTs, the screen flicker of the display device driven by the positive and negative voltages can be eliminated.
  • the absolute values of the data voltages applied thereto are equal, but are positive and negative, respectively.
  • the sub-pixel electrode 130 and the gate 112 of the TFT of the sub-pixel electrode 140 may be respectively connected to two adjacent gate lines 102 defining the pixel unit.
  • the sources 118 of the two TFTs are respectively connected to two data lines 108 that define the pixel unit and are adjacent to each other.
  • the drains 119 of the two TFTs are connected to the sub-pixel electrode 130 and the sub-pixel electrode 140, respectively.
  • the gates 112 of the two TFTs are respectively connected to the adjacent two gate lines 102 (ie, the gate lines 102 on the upper side and the lower side of the pixel unit in the figure).
  • the flexibility of TFT control can be improved, and the complete destruction of the pixel electrodes when a single gate line is damaged can be prevented, that is, the pixel unit is given a certain redundancy capability.
  • the two gate lines 102 are synchronously applied with an on and off signal.
  • the source and the drain of the TFT may both be disposed above the gate line.
  • the source 118 and the drain 119 of both TFTs are disposed over the gate line 102, that is, a portion of the gate line 102 serves as a gate of the TFT, and accordingly the active layer of the TFT also serves as a gate. Partial overlap. That is, the orthographic projection of the source 118 and the drain 119 of the two TFTs on one main surface (for example, the upper surface or the lower surface) of the substrate is at least partially located on the main surface of the substrate to which the gate line 102 connected to the TFT is projected.
  • the orthographic projection of the source 118 and the drain 119 of the two TFTs on one main surface of the substrate is completely within the orthographic projection of the gate line 102 to which the TFT is connected on the main surface of the substrate to lift the pixel electrode
  • the aperture ratio increases the display brightness.
  • the sources 118 of the two TFTs are respectively connected to two data lines 108 that define the pixel unit and are adjacent to each other.
  • the drains 119 of the two TFTs are connected to the sub-pixel electrode 130 and the sub-pixel electrode 140, respectively.
  • the gates 112 of the two TFTs are respectively connected to the same gate line 102.
  • the gate of the TFT for two sub-pixel electrodes may also be disposed on the gate line connected to the TFT to increase the aperture ratio of the pixel electrode and improve the display brightness.
  • the sub-pixel electrodes are, for example, two, and the two sub-pixel electrodes are disposed to be juxtaposed in the extending direction of the data line.
  • FIG. 4 it is shown that the sub-pixel electrodes 130 and 140 in the pixel unit (shown by the broken line in the figure) are sequentially arranged in the direction in which the data line 108 extends, juxtaposed to each other.
  • the sub-pixel electrode 130 and the sub-pixel electrode 140 are respectively driven by one TFT.
  • the gates of the TFTs of the two sub-pixel electrodes are respectively connected to the adjacent gate lines 102 (ie, the sub-pixel electrode 130 is connected to the gate line on the upper side thereof, and the sub-pixel electrode 140 is connected to the gate line on the lower side thereof) .
  • the sources 118 of the two TFTs are respectively connected to two data lines 108 adjacent to each other and defining the pixel unit (i.e., the data lines 108 on the left and right sides of the pixel unit in the figure).
  • the drains 119 of the two TFTs are connected to the sub-pixel electrode 130 and the sub-pixel electrode 140, respectively.
  • the screen flicker of the liquid crystal display device can be eliminated.
  • Using different gate lines to provide gate signals for different sub-pixel electrodes can improve the flexibility of TFT control and prevent complete destruction of pixel electrodes in one pixel unit when a single gate line is damaged, that is, give a certain redundancy to the pixel unit. ability.
  • the sub-pixel electrode 130 and the sub-pixel electrode 140 correspond to the same pixel in the same displayed image, the absolute values of the data voltages applied thereto are equal, but are positive and negative, respectively; and for example, The bar lines 102 are synchronously applied with an on and off signal.
  • the source and the drain of the TFT are both disposed over the gate line, whereby a portion of the gate line serves as the gate of the TFT, and accordingly the active layer of the TFT also acts as a gate. Partial overlap. That is, the orthographic projection of the source and drain of the TFT on one major surface (e.g., the upper or lower surface) of the substrate is at least partially within the orthographic projection of the gate line to which the TFT is connected on the major surface of the substrate. For example, the orthographic projection of the source and drain of the TFT on one major surface of the substrate is entirely within the orthographic projection of the gate line to which the TFT is connected, on the major surface of the substrate.
  • the structure in which the source and the drain of the TFT are disposed on the gate line can increase the aperture ratio of the pixel electrode and improve the display brightness.
  • the same gate line drives the TFTs of all of the sub-pixel electrodes within the pixel cells on either side thereof.
  • the gates of the TFTs of the sub-pixel electrodes on both sides of the gate line may be connected to the gate line. That is, by using the same gate line to drive all the sub-pixel electrodes in the pixel unit on both sides and adjacent thereto, the energy consumption is reduced and the material is saved.
  • the same gate line only drives sub-pixel electrodes on both sides and adjacent thereto.
  • a plurality of gate lines 102 crossing each other and a plurality of data lines 108 collectively define a display area (only a portion of the display area is shown), the display area including a plurality of pixel units.
  • the sub-pixel electrodes are juxtaposed in the direction in which the data lines 108 extend.
  • the same gate line 102 drives only the TFTs of the sub-pixel electrodes on both sides thereof and close thereto.
  • the gate line 102 drives the sub-pixel electrode 130 and the other sub-pixel electrode 140 in one pixel unit. That is, the same gate line 102 simultaneously drives the sub-pixel electrodes located on both sides of the gate line.
  • the same gate line drives only the sub-pixel electrodes on one side thereof and adjacent thereto.
  • the two sub-pixel electrodes are sequentially arranged, for example, in the direction in which the data lines extend, and are juxtaposed to each other.
  • one gate line drives only the sub-pixel electrodes on one side thereof and close thereto. That is, the gate of the TFT of the sub-pixel electrode in one pixel unit is connected to one gate line, and the gate of the TFT of the other sub-pixel electrode is connected to the other gate line adjacent to the gate line.
  • the number of sub-pixel electrodes is, for example, two.
  • the display effect is affected, for example, the separation distance between the two sub-pixel electrodes is set to 8-10 ⁇ m. This can effectively prevent the screen from flickering without causing display errors.
  • the separation distance between two sub-pixels refers to the distance between the edges of two pixels close to each other, that is, d indicated in FIG. 6 .
  • the two sub-pixel electrodes are plate electrodes or strip electrodes.
  • the two sub-pixel electrodes can, for example, also have other regular or irregular shapes.
  • the number of sub-pixel electrodes in one pixel unit of the present disclosure is not limited to two, and may be plural, for example, three or four.
  • Each of the sub-pixel electrodes is provided with one TFT. It can be known to those skilled in the art that in the case where there are a plurality of sub-pixel electrodes, the TFT sources of each sub-pixel electrode need to be connected with different data lines, that is, the sub-pixel electrodes need to be disposed. The corresponding data line. As described above, the gates of the TFTs of the plurality of sub-pixel electrodes may be connected to, for example, the same gate line or respectively connected to different gate lines.
  • one pixel unit includes three sub-pixel electrodes arranged side by side and three TFTs respectively connected to the three sub-pixel electrodes, and the sources of the three TFTs are connected to different data lines.
  • two of the three sub-pixel electrodes are driven by a positive voltage, and the other sub-pixel electrode is driven by a negative voltage; or two sub-pixel electrodes are driven by a negative voltage, and the other sub-pixel electrode is driven by a positive voltage drive.
  • one pixel unit includes four sub-pixel electrodes arranged side by side and four TFTs respectively connected to the four sub-pixel electrodes, and the sources of the four TFTs are connected to different data lines.
  • two of the four sub-pixel electrodes are driven by a positive voltage
  • the other two sub-pixel electrodes are driven by a negative voltage.
  • a plurality of sub-pixel electrodes may also be disposed in the same pixel unit, and the sub-pixel electrodes are configured to have both positive voltage driving and negative voltage driving.
  • sub-pixel electrodes driven by positive and negative voltages are alternately arranged.
  • the display substrate described above may be, for example, an array substrate, but the display substrate of the present disclosure is not limited thereto.
  • the method for preparing the display substrate of the present disclosure is described below by taking only two sub-pixel electrodes in one pixel unit and the two sub-pixel electrodes are arranged along the direction in which the data lines extend. For example, the following is as follows:
  • a metal layer is formed on the substrate by, for example, sputtering, and then etched using a first mask to obtain a gate line and a gate connected to the gate line.
  • the metal layer may, for example, comprise aluminum, an aluminum alloy, and copper or other suitable material. After the first masking process is performed to pattern, the gate lines and the gate electrodes are formed on the display substrate.
  • TFTs are disposed in one pixel unit of the present disclosure, and correspondingly, the gate and the source and the drain corresponding to the gate are two; the source of each TFT is connected with two different data.
  • One of the lines; the pattern on the mask should correspond to this structure of the present disclosure.
  • an insulating layer is formed as a gate insulating layer.
  • the material for the insulating layer includes, for example, SiNx or SiOx; then a layer of half is formed over the insulating layer. a conductor layer and a patterning process to form an active layer of the TFT, the active layer being disposed over the insulating layer and corresponding to the gate.
  • the active layer can be prepared, for example, by photolithography, by designing the mask as a pattern of the corresponding active layer, and removing the active layer in other regions by, for example, photolithography, to obtain an active layer corresponding to the gate.
  • the material for forming the active layer may be, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor (for example, IGZO), or other suitable materials.
  • a metal layer is further formed on the substrate on which the active layer is formed.
  • the material of the metal layer can be, for example, aluminum, aluminum alloy, copper or other suitable material.
  • the method of forming the metal layer may be, for example, CVD or sputtering. And performing a photolithography process using a mask having a source, a drain, and a data line pattern to pattern the metal layer, thereby forming a data line crossing the gate line, a source and a drain spaced apart from each other over the active layer. .
  • the mask pattern used in this step should correspond to this.
  • a structure in which a passivation layer, a passivation layer via, or the like is further formed on the source, the drain, and the data line may be formed.
  • a transparent conductive layer e.g., ITO
  • photolithography is performed by a mask having a mask corresponding to the pixel electrode structure of the present disclosure to obtain a display substrate structure of one embodiment of the present disclosure.
  • the mask includes at least a pattern corresponding to two sub-pixel electrodes spaced apart from each other in the first pixel unit, after the lithographic exposure of the mask, for example, the two spaced-apart sub-pixel electrodes formed along the The direction in which the data lines extend is arranged in order.
  • the two sub-pixel electrodes are respectively connected to the drains of one of the two TFTs through via holes.
  • the mask pattern can be changed correspondingly for lithography, and details are not described herein again.
  • the display substrate preparation method of the present disclosure is not limited to the method described above.
  • the present disclosure provides a liquid crystal display device including the above display substrate.
  • the display substrate is an array substrate.
  • the display device further includes a counter substrate, such as a color filter substrate, and one pixel of the color filter substrate corresponds to two sub-pixel electrodes in the same pixel unit of the display substrate.
  • the liquid crystal display device can effectively reduce the flicker of the display screen.
  • a pixel unit corresponding to a plurality of pixel units on the array substrate is included on the color filter substrate.
  • the pixel unit on the color filter substrate and the corresponding pixel unit on the array substrate are opposed to each other in a direction perpendicular to the color filter substrate or the array substrate.
  • Each pixel on the color film substrate The element includes a color filter such that light passing through the two sub-pixel electrodes of the corresponding pixel unit on the array substrate passes through the color filter.
  • An embodiment of the present disclosure further provides a driving method of the above liquid crystal display device, comprising: applying a voltage to different sub-pixel electrodes of each pixel unit on the display substrate, wherein different sub-pixels are applied to each pixel unit
  • the electrodes have opposite voltage polarities and equal absolute values.
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.
  • Embodiments of the present disclosure have, for example, at least one of the following technical effects:
  • the present disclosure can effectively reduce picture flicker and improve display effect by providing at least two sub-pixel electrodes in one pixel unit.
  • connection of two thin film transistors in one pixel unit to one or two gate lines respectively can achieve the purpose of reducing power consumption or improving driving flexibility.
  • the embodiment of the present disclosure can further improve the display effect by setting the interval between the two sub-pixel electrodes.
  • Embodiments of the present disclosure can further reduce picture flicker and improve display effect by providing three or four sub-pixel electrodes in one pixel unit.

Abstract

一种显示基板及液晶显示装置。该显示基板包括多条数据线(108)和多条栅线(102)，多个像素单元；所述多个像素单元中的至少一个像素单元至少包括两个彼此绝缘的子像素电极(130,140)和两个薄膜晶体管(110)；两个子像素电极(130,140)分别连接到不同的薄膜晶体管(110)，两个薄膜晶体管(110)的源极(118)分别连接两条不同数据线(108)。该显示基板的显示装置可减轻画面闪烁，具有较好的显示效果。

Description

显示基板及液晶显示装置 技术领域
本公开的实施例涉及显示技术领域，特别是一种显示基板及液晶显示装置。
背景技术
目前，提高显示装置的显示效果的方法包括多畴垂直取向技术(MVA)、面内切换技术(IPS)以及边缘切换技术(FFS)等。近年来，FFS模式凭借其在穿透率、驱动电压、宽视角和可触控性等方面的优势而被广泛应用于具有高分辨率的高端产品上，并逐渐成为一种主流趋势。
然而，采用FFS模式常常会发生显示画面的闪烁。当公共电极上的参考电极电压发生偏移时，像素电极和参考电极间的电场强度发生变化，造成液晶分子偏转差异，影响光线透过率。这种由像素电极和参考电极之间的电压差变化所导致的光线透过率的变化，会使显示画面发生闪烁，影响显示效果。同时，因为饶曲电效应的存在，像素电极被施加正负极性电压时，显示画面的亮度会存在差异。因为正负极性电压驱动下，像素点的亮度不同，随着极性的反转，画面也就会一亮一暗的闪烁。
发明内容
本公开的至少一个实施例涉及一种显示基板及显示装置，可解决显示画面的闪烁现象。
本公开的一个方面提供了一种显示基板，包括多条数据线和多条栅线，多个像素单元；所述多个像素单元中的至少一个像素单元至少包括两个彼此绝缘的子像素电极和两个薄膜晶体管；所述两个子像素电极分别连接到所述两个薄膜晶体管中的不同的薄膜晶体管，所述两个薄膜晶体管的源极分别连接两条不同数据线。
例如，所述两条不同数据线被配置为施加极性相反的电压。
例如，所述两个子像素电极分别位于所述像素单元中不同的两个区域。
例如，所述两个子像素电极在所述栅线延伸的方向依次布置。
例如，所述两个子像素电极在所述数据线延伸的方向依次布置。
例如，所述两个薄膜晶体管的栅极连接同一条栅线或分别连接两条不同的栅线。
例如，所述两个子像素电极的间隔距离为8-10μm。
例如，所述两个子像素电极包括板状电极或条形电极。
例如，所述至少一个像素单元包括彼此互不接触的三个子像素电极以及包括分别与所述三个子像素电极连接的三个薄膜晶体管；所述三个薄膜晶体管的源极分别连接不同的数据线。
例如，所述至少一个像素单元包括彼此互不接触且并列布置的四个子像素电极以及包括分别与所述四个子像素电极连接的四个薄膜晶体管；所述四个薄膜晶体管的源极分别连接不同的数据线。
例如，所述两条不同数据线被配置为施加绝对值相同的电压。
本公开的另一个方面提供了一种包括上述显示基板的液晶显示装置。
例如，液晶显示装置还包括与所述显示基板相对设置的彩膜基板，所述彩膜基板包括与所述显示基板的多个像素单元一一对应的像素单元，所述彩膜基板的每个像素单元包括一种颜色的滤色器。
本公开的另一个方面还提供一种上述液晶显示装置的驱动方法，包括：对所述显示基板上的每个像素单元的不同子像素电极施加电压，其中，施加到每个像素单元的不同子像素电极的电压极性相反且绝对值相等。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种像素单元结构的俯视示意图；
图2a为本公开实施例的一个像素单元中沿栅线延伸方向排列的两个子 像素电极连接同一条栅线的示意图；
图2b为本公开实施例的一个像素单元中沿栅线延伸方向排列的两个子像素电极连接不同栅线的示意图；
图3为本公开实施例的TFT的源漏极设置于栅线之上的示意图；
图4为本公开实施例的一个像素单元中沿数据线延伸方向排列的两个子像素电极连接不同栅线的示意图；
图5为本公开实施例的部分显示区域内栅线驱动位于该栅线两侧且靠近该栅线的子像素电极的示意图；
图6为本公开实施例的像素单元中两个子像素电极之间距离示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
例如用于液晶显示装置的显示基板上包括彼此交叉设置的多条栅线和多条数据线。这些栅线和数据线在显示基板上限定出按阵列布置的多个像素单元。每个像素单元包括像素电极以及相应的薄膜晶体管(Thin Film Transistor，TFT)等。通过控制每个像素单元中的像素电极与公共电极之间压差的变化，可以控制该液晶显示装置中的液晶分子以不同角度的偏转，进而控制光线透过率，完成画面显示。
图1是一种显示基板的像素单元的俯视示意图。参照图1，栅线102和数据线108限定一个像素单元，在栅线102与数据线108的交叉区域附近设置TFT 110，该TFT包括栅极112、源极118、漏极119以及设置于栅极112之上且用于为源极118和漏极119提供通道的有源层116。栅线102与栅极112连接，以提供栅线扫描信号；源极118与数据线108连接，以提供数据信号；漏极119与像素电极109连接，作为TFT的输出电极，且为像素电极109充电。在这种像素结构中，在采用正、负电压驱动时，如果公共电极上设置的参考电压发生偏移，会发生显示画面的闪烁现象，影响显示效果。另 外，即使参考电压未发生偏移，这种正负电压极性反转的驱动也会导致画面的闪烁。
本公开的一个方面提供了一种显示基板，该显示基板包括多条数据线和多条栅线，多个像素单元；所述多个像素单元中的至少一个像素单元至少包括两个彼此绝缘的子像素电极和两个薄膜晶体管；所述两个子像素电极分别连接到不同的薄膜晶体管，所述两个薄膜晶体管的源极分别连接两条不同数据线。这种像素电极结构可以保证同一像素单元内同时存在正、负电压驱动，进而保证即使驱动电压的极性反转同一像素单元的亮度也不会存在差异，以降低显示装置的闪烁。
本公开通过在一个像素单元内设置彼此绝缘的两个或多个子像素电极以及分别为每一个子像素电极配备一个TFT，来实现一个像素单元内有正、负电压驱动。例如两个子像素电极连接的两个数据线的电压极性相反。这种在一个像素单元内由正、负电压驱动的子像素电极的结构，可以消除单独由正电压或负电压驱动时产生的画面闪烁现象。
需要说明的是，TFT的源极和漏极并不严格区分，源漏极与数据线和像素电极的连接方式互换时，源漏极的名称也随之互换。本领域技术人员不得对此作限制解释。
另外，像素单元并不一定对应于多条栅线与多条数据线彼此交叉形成的格子。像素单元只要位于显示区域即可，本领域技术人员不得对此作限制解释。
在一个实施例中，本公开实施例的像素单元中的两个子像素电极位于像素单元中不同的区域，例如该像素单元中并列的两个区域。例如这两个子像素电极彼此之间可以无交叉部分。防止在对这两个子像素电极进行正负电压驱动时，两个子像素电极之间产生电场，影响显示效果。
以下以一个像素单元且该像素单元内设置两个子像素电极和两个TFT为例，进一步说明本公开的像素单元内的子像素电极的TFT与栅线、数据线的连接关系。但本公开的像素单元内子像素电极的个数不限于两个。
在本公开的一个实施例中，一个像素单元内的子像素电极例如为两个，两个子像素电极位于像素单元中不同的两个区域。例如，两个子像素电极沿栅线延伸的方向并列排列。参照图2a，在像素单元(如图中的虚线所示意的) 内，子像素电极130和子像素电极140设置为沿栅线102的延伸方向依次排列，彼此并列。每一个子像素电极分别由一个TFT驱动。两个TFT的栅极112连接同一条栅线102。两个TFT的源极118分别连接限定该像素单元且彼此相邻的两根数据线108(即图中像素单元左侧和右侧的数据线108)。两个TFT的漏极119分别连接子像素电极130和子像素电极140。例如，当子像素电极130和子像素电极140分别配置为由两个TFT施加正、负数据电压时，可消除正、负电压驱动下显示装置的画面闪烁。例如，在子像素电极130和子像素电极140对应于同一个被显示图像中的同一个像素点，二者上施加的数据电压的绝对值相等，但是分别为正值和负值。通过采用一条栅线驱动该像素单元内的两个TFT，可降低能耗，提高开口率。
在该实施例中，子像素电极130和子像素电极140的TFT的栅极112可以分别连接限定该像素单元的两条彼此相邻的栅线102。参照图2b，如前所述，在像素单元(如图中的虚线所示意的)内，两个TFT的源极118分别连接限定该像素单元且彼此相邻的两根数据线108。两个TFT的漏极119分别连接子像素电极130和子像素电极140。而两个TFT的栅极112分别连接相邻的两根栅线102(即图中像素单元上侧和下侧的栅线102)。通过采用不同的栅线为不同子像素电极提供栅信号，可以提高TFT控制的灵活性，并能够防止在单条栅线损坏时像素电极的完全损坏，即赋予该像素单元一定的冗余能力。例如，这两条栅线102被同步地施加开启和关闭信号。
在该实施例中，例如，TFT的源极和漏极可以均设置于栅线之上。参照图3，两个TFT的源极118和漏极119均设置于栅线102之上，也即栅线102的一部分充当TFT的栅极，相应地该TFT的有源层也与充当栅极的部分重叠。即两个TFT的源极118和漏极119在基板一个主表面(例如上表面或下表面)的正投影至少部分位于该TFT所连接的栅线102在基板的该主表面上的正投影之内，例如两个TFT的源极118和漏极119在基板的一个主表面的正投影完全位于该TFT所连接的栅线102在基板的该主表面上的正投影之内，以提升像素电极的开口率，提高显示亮度。继续参照图3。如前所述，两个TFT的源极118分别连接限定该像素单元且彼此相邻的两根数据线108。两个TFT的漏极119分别连接子像素电极130和子像素电极140。两个TFT的栅极112分别连接同一条栅线102。例如，对于两个子像素电极的TFT的栅 极连接不同的栅线的结构，TFT的源极和漏极也可以设置于与该TFT连接的栅线之上，以提升像素电极的开口率，提高显示亮度。
在本公开的一个实施例中，子像素电极例如为两个，这两个子像素电极设置为沿数据线延伸方向并列排列。参照图4，其示出了像素单元(如图中虚线所示意的)内的子像素电极130和140沿数据线108延伸的方向依次排列，彼此并列。如前所述，子像素电极130和子像素电极140分别由一个TFT驱动。两个子像素电极的TFT的栅极分别与各自邻近的栅线102连接(即图中子像素电极130与位于其上侧的栅线连接，子像素电极140与位于其下侧的栅线连接)。继续参照图4，这两个TFT的源极118分别连接彼此相邻且限定该像素单元的两条数据线108(即图中像素单元左侧和右侧的数据线108)。这两个TFT的漏极119分别连接子像素电极130和子像素电极140。例如，当子像素电极130和子像素电极140可以配置为分别通过这两个TFT施加正、负电压数据时，可消除液晶显示装置的画面闪烁。采用不同的栅线为不同子像素电极提供栅信号，可以提高TFT控制的灵活性，并能够防止在单个栅线损坏时一个像素单元内的像素电极完全损坏，即赋予该像素单元一定的冗余能力。例如在子像素电极130和子像素电极140对应于同一个被显示图像中的同一个像素点，二者上施加的数据电压的绝对值相等，但是分别为正值和负值；而且例如，这两条栅线102被同步地施加开启和关闭信号。
在该实施例中，例如，TFT的源极和漏极均设置于栅线之上，由此栅线的一部分作为该TFT的栅极，相应地该TFT的有源层也与充当栅极的部分重叠。即TFT的源极和漏极在基板的一个主表面(例如上表面或下表面)的正投影至少部分位于该TFT所连接的栅线在基板的该主表面上的正投影之内。例如TFT的源极和漏极在基板一个主表面的正投影完全位于该TFT所连接的栅线在基板的该主表面上的正投影之内。采用TFT的源极和漏极设置于栅线上的结构，可以提升像素电极的开口率，提高显示亮度。
在一个实施例中，同一条栅线驱动在其两侧的像素单元内的所有子像素电极的TFT。例如，图5所示，当栅线102两侧的子像素电极均沿栅线102的延伸方向依次排列时，栅线两侧的这些子像素电极的TFT的栅极均可连接该栅线。即通过采用同一条栅线驱动位于其两侧且与其邻近的像素单元内所有子像素电极，以降低能耗，节省材料。
在一个实施例中，同一条栅线仅驱动位于其两侧且与其邻近的子像素电极。参照图5，彼此交叉的多条栅线102与多条数据线108共同限定显示区域(图中仅示出显示区域的一部分)，该显示区域包括多个像素单元。在每一个像素单元(如图中虚线所示意的)内，子像素电极沿数据线108延伸的方向并列排列。同一条栅线102仅驱动位于其两侧且与其靠近的子像素电极的TFT。如图5所示，栅线102驱动一个像素单元内的子像素电极130与另一个子像素电极140。即同一条栅线102同时驱动位于该栅线两侧的子像素电极。
在一个实施例中，同一条栅线仅驱动位于其一侧且与其邻近的子像素电极。基板显示区域内的每一个像素单元内，两个子像素电极例如沿数据线延伸的方向依次排列，且彼此并列。如上所述，一条栅线仅驱动位于其一侧且与其靠近的子像素电极。即，一个像素单元内的子像素电极的TFT的栅极连接一条栅线，而另一个子像素电极的TFT的栅极连接与该栅线相邻的另一条栅线。采用这种栅线连接方式，不仅可实现同一行像素单元的子像素电极的分别由不同栅线控制，也可以实现不同行的像素单元分别由不同栅线控制。这既避免了在一条栅线损坏时，同一行的像素单元出现故障；也避免了在一条栅线损坏时，同时影响位于栅线两侧的像素单元，进一步提高了像素结构的稳定性。
在一个实施例中，子像素电极的个数例如为两个。为了避免彼此间隔的两个子像素电极之间产生强电场，影响显示效果，例如将两个子像素电极之间的间隔距离设置为8-10μm。这样既能有效防止画面闪烁，又不会产生显示错误。
需要说明的是，两个子像素的间隔距离是指两个像素彼此靠近的边缘之间的距离，即图6中所标示的d。
在一个实施例中，两个子像素电极为板状电极或条形电极。例如两个子像素电极例如也可以为其它规则或不规则的形状。
本领域技术人员应当了解的是，本公开的一个像素单元中的子像素电极个数并不限于两个，也可以为多个，例如三个或四个。每个子像素电极分别设置一个TFT。本领域技术人员可知，在子像素电极为多个的情况下，每个子像素电极的TFT源极需要连接不同的数据线，即需要针对子像素电极布设 相应的数据线。如前文所述，多个子像素电极的TFT的栅极例如可以连接同一条栅线或分别连接不同栅线。
例如一个像素单元包括并列布置的三个子像素电极和与这三个子像素电极分别连接的三个TFT，且这三个TFT的源极连接不同数据线。例如，在同一时刻，这三个子像素电极中有两个子像素电极由正电压驱动，另一个子像素电极由负电压驱动；或者两个子像素电极由负电压驱动，另一个子像素电极由正电压驱动。
例如一个像素单元包括并列布置的四个子像素电极和与这四个子像素电极分别连接的四个TFT，且这四个TFT的源极连接不同数据线。例如，在同一个时刻，这四个子像素电极中的两个子像素电极由正电压驱动，另外两个子像素电极由负电压驱动。当然，也可以在同一个像素单元内设置多个子像素电极，且这些子像素电极配置为既有正电压驱动，又有负电压驱动。而且，例如，由正负电压驱动的子像素电极交替布置。这些显而易见的变形都不超出本公开的范围。
需要说明的是，通过增加子像素电极的个数，在这些子像素电极同时由正负电压驱动时，可进一步降低显示画面的闪烁。
以上所述的显示基板例如可以为阵列基板，但本公开的显示基板不限于此。
下面仅以一个像素单元内包括两个子像素电极且两个子像素电极沿数据线延伸的方向间隔排列为例说明本公开的显示基板的制备方法，例如具体如下：
在基板上通过例如溅射的方法形成一层金属层，然后采用第一掩模进行蚀刻得到栅线和与所述栅线连接的栅极。该金属层例如可以包括铝、铝合金，以及铜或其它适合材料。进行第一次掩模工艺以进行构图后，显示基板上即形成有栅线以及栅极。
需要说明的是，本公开的一个像素单元内设置两个TFT，相应地，栅极以及与该栅极对应的源极和漏极均为两个；每一个TFT的源极连接两条不同数据线之一；掩模上的图案应当与本公开的这种结构对应。
在形成有栅线和栅极的显示基板上，形成一层绝缘层以作为栅绝缘层。用于该绝缘层的材料例如包括SiNx或SiOx；随后在绝缘层之上形成一层半 导体层，并通过构图工艺以形成TFT的有源层，该有源层设置于绝缘层之上，且与栅极对应。制备有源层例如可以采用光刻法，将掩模设计为对应的有源层的图案，并通过例如光刻方法去除其它区域中的有源层，获得与栅极对应的有源层。用于形成有源层的材料例如可以为非晶硅、多晶硅、氧化物半导体(例如IGZO)或其它适合的材料。
此后，在形成有有源层的基板上，进一步形成一层金属层。该金属层的材料例如可以为铝、铝合金、铜或其它适合材料。形成金属层的方法例如可以为CVD或溅射法。并采用具有源极、漏极以及数据线图案的掩模进行光刻工艺以对该金属层构图，进而在有源层的上方形成与栅线交叉的数据线、彼此间隔的源极、漏极。如上所述，在一个像素单元包括两个TFT，且两个TFT的源极分别连接两条不同的数据线，该步骤中所采用的掩模图案应与此对应。
之后，还可以形成进一步在源极、漏极、数据线之上形成钝化层、钝化层过孔等结构。
随后，在钝化层上方继续覆盖一层透明导电层(例如ITO)，并通过具有与本公开像素电极结构对应的掩模进行光刻，获得本公开的一个实施例的显示基板结构。该掩模上至少包括对应于第一像素单元中具有彼此间隔的两个子像素电极的图案，在对该掩模进行光刻曝光后，例如所形成的这两个彼此间隔的子像素电极沿上述数据线延伸的方向依次排列。这两个子像素电极分别通过过孔连接到两个TFT之一的漏极。
对于本公开上述其它的实施例，可相应的改变掩模图案进行光刻，在此不再赘述。
本公开的显示基板制备方法不限于上述描述的方法。
本公开提供了一种包括上述显示基板的液晶显示装置。例如，该显示基板为阵列基板。该显示装置还包括对置基板，该对置基板例如为彩膜基板，彩膜基板的一个像素对应显示基板的同一个像素单元内的两个子像素电极。该液晶显示装置可有效降低显示画面闪烁。
例如，在该彩膜基板上包括与该阵列基板上的多个像素单元一一对应的像素单元。例如，在该彩膜基板上的像素单元与阵列基板上对应的像素单元在垂直于彩膜基板或阵列基板的方向上彼此相对。彩膜基板上的每个像素单 元包括一种颜色的滤色器，以使得通过阵列基板上的对应像素单元的两个子像素电极的光均透过该滤色器。
本公开的实施例还提供一种上述液晶显示装置的驱动方法，包括：对所述显示基板上的每个像素单元的不同子像素电极施加电压，其中，施加到每个像素单元的不同子像素电极的电压极性相反且绝对值相等。
在本文中，诸如“第一”、“第二”等术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不要求或者暗示这些实体或操作之间存在任何关系或者顺序。术语“包括”、“包含”这些表述为开放式的，并不排除所包括的过程、方法、物品，还存在其他要素。还需要说明的是，“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
本公开的实施例例如具有如下技术效果至少之一：
(1)本公开通过在一个像素单元内设置至少两个子像素电极，可以有效降低画面闪烁，提高显示效果。
(2)本公开的实施例一个像素单元内的两个薄膜晶体管连接一个或分别连接两个栅线，可以实现降低能耗或提高驱动灵活性的目的。
(3)本公开的实施例通过设置两个子像素电极的间隔，可以进一步提高显示效果。
(4)本公开的实施例通过在一个像素单元内设置三个或四个子像素电极，可以进一步降低画面闪烁，提高显示效果。
以上具体实施例之间可相互组合，并不超出本公开公开的范围，且能够带来更好的组合效果。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年4月15日递交的中国专利申请第201620320070.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种显示基板，包括多条数据线、多条栅线和多个像素单元，其中，
    所述多个像素单元中的至少一个像素单元至少包括两个彼此绝缘的子像素电极和两个薄膜晶体管；所述两个子像素电极分别连接到所述两个薄膜晶体管中的不同薄膜晶体管，所述两个薄膜晶体管的源极分别连接两条不同数据线。
  2. 根据权利要求1所述的显示基板，其中，所述两条不同数据线被配置为施加极性相反的电压。
  3. 根据权利要求1或2所述的显示基板，其中，所述两个子像素电极分别位于所述像素单元中不同的两个区域。
  4. 根据权利要求3所述的显示基板，其中，所述两个子像素电极在所述栅线延伸的方向依次布置。
  5. 根据权利要求3所述的显示基板，其中，所述两个子像素电极在所述数据线延伸的方向依次布置。
  6. 根据权利要求1-5任意一项所述的显示基板，其中，所述两个薄膜晶体管的栅极连接同一条栅线或分别连接两条不同的栅线。
  7. 根据权利要求1-6任意一项所述的显示基板，其中，所述两个子像素电极的间隔距离为8-10μm。
  8. 根据权利要求1-7任意一项所述的显示基板，其中，所述两个子像素电极包括板状电极或条形电极。
  9. 根据权利要求1-8任意一项所述的显示基板，其中，所述至少一个像素单元包括彼此互不接触的三个子像素电极以及包括分别与所述三个子像素电极连接的三个薄膜晶体管；所述三个薄膜晶体管的源极分别连接不同的数据线。
  10. 根据权利要求1-8任意一项所述的显示基板，其中，所述至少一个像素单元包括彼此互不接触的四个子像素电极以及包括分别与所述四个子像素电极连接的四个薄膜晶体管；所述四个薄膜晶体管的源极分别连接不同的数据线。
  11. 根据权利要求2所述的显示基板，其中，所述两条不同数据线被配 置为施加绝对值相同的电压。
  12. 一种液晶显示装置，包括如权利要求1-11任意一项所述的显示基板。
  13. 根据权利要求12所述的液晶显示装置，还包括与所述显示基板相对设置的彩膜基板，所述彩膜基板包括与所述显示基板的多个像素单元一一对应的像素单元，所述彩膜基板的每个像素单元包括一种颜色的滤色器。
  14. 一种根据权利要求12或13所述的液晶显示装置的驱动方法，包括：
    对所述显示基板上的每个像素单元的不同子像素电极施加电压，其中，施加到每个像素单元的不同子像素电极的电压极性相反且绝对值相等。
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CN106873264A (zh) * 2017-04-27 2017-06-20 厦门天马微电子有限公司 阵列基板、液晶显示面板、显示装置和像素充电方法
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