WO2016106894A1 - 薄膜晶体管阵列基板及显示面板 - Google Patents

薄膜晶体管阵列基板及显示面板 Download PDF

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Publication number
WO2016106894A1
WO2016106894A1 PCT/CN2015/071176 CN2015071176W WO2016106894A1 WO 2016106894 A1 WO2016106894 A1 WO 2016106894A1 CN 2015071176 W CN2015071176 W CN 2015071176W WO 2016106894 A1 WO2016106894 A1 WO 2016106894A1
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Prior art keywords
thin film
film transistor
sub
pixel
region
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PCT/CN2015/071176
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English (en)
French (fr)
Inventor
杜鹏
施明宏
康志聪
许哲豪
吕启标
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深圳市华星光电技术有限公司
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Priority to US14/436,056 priority Critical patent/US10013929B2/en
Publication of WO2016106894A1 publication Critical patent/WO2016106894A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]

Definitions

  • the present invention relates to the field of display, and in particular to a thin film transistor array substrate and a display panel.
  • Liquid crystal display is a commonly used electronic device, which is favored by users because of its low power consumption, small size and light weight.
  • the current liquid crystal display is mainly a thin film transistor (TFT) liquid crystal display.
  • TFT thin film transistor
  • the present invention provides a thin film transistor array substrate having a plurality of pixels arranged in an array, each of which includes a first sub-pixel, a second sub-pixel, and a third sub-array arranged in a first direction.
  • a pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected to a same scan line, and the first data line arranged in the first direction is further disposed on the thin film transistor array substrate, a second data line for driving the first sub-pixel, the second data line for driving the second sub-pixel, and the third data line for Driving the third sub-pixel
  • the first sub-pixel includes a first region and a second region arranged in a second direction
  • the second sub-pixel includes a third region and a fourth region arranged in a second direction
  • the third sub-pixel includes a fifth region and a sixth region arranged in a second direction, and a voltage difference between the sub-pixel electrode and the common electrode in the sixth region is different from a sub-pixel electrode in
  • the first thin film transistor is disposed in the first region, and the second thin film is disposed in the second region a thin film transistor, a third thin film transistor is disposed in the third region, a fourth thin film transistor is disposed in the fourth region, a fifth thin film transistor is disposed in the fifth region, and a sixth thin film transistor is disposed in the sixth region
  • a seventh thin film transistor, the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the a gate of the seventh thin film transistor is connected to the same scan line, a drain of the first thin film transistor and the second thin film transistor is connected to the first data line, and a source of the first thin film transistor is sequentially connected to the first a main sub-pixel electrode, a first capacitor to the common electrode, a source of the second thin film transistor sequentially connecting the first sub-pixel electrode, the second capacitor to the common electrode, and the third thin film transistor and the fourth thin film transistor The drain is connected to the second
  • the voltage difference between the sub-pixel electrode and the common electrode in the fourth region is different from the voltage difference between the sub-pixel electrode and the common electrode in the third region.
  • An eighth thin film transistor is disposed in the fourth region, a gate of the eighth thin film transistor is connected to the scan line, and a drain of the eighth thin film transistor is connected to the second sub-pixel electrode, A source of the eighth thin film transistor is connected to the common electrode.
  • the fourth data line is further disposed on the thin film transistor array substrate, the third data line drives a fifth area of the third sub-pixel, and the fourth data line drives the third sub-pixel
  • the driving voltage loaded on the third data line is different from the driving voltage loaded on the fourth data line.
  • the first thin film transistor is disposed in the first region
  • the second thin film transistor is disposed in the second region
  • the fourth thin film transistor is disposed in the third region
  • the fifth thin film transistor is disposed in the fifth region.
  • a sixth thin film transistor, the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, and the fifth thin film are disposed in the sixth region a gate of the transistor and the sixth thin film transistor are connected to a same scan line, and drains of the first thin film transistor and the second thin film transistor are connected to the first data line, a source of the first thin film transistor Connecting the first main sub-pixel electrode and the first capacitor to the common electrode, the source of the second thin film transistor sequentially connecting the first sub-pixel electrode and the second capacitor to the common electrode, the third thin film transistor and the The drain of the fourth thin film transistor is connected to the second data line
  • the source of the third thin film transistor is sequentially connected to the second main sub-pixel electrode and the third capacitor to the common electrode
  • the fifth data line is further disposed on the thin film transistor array substrate, the second data line drives a third area of the second sub-pixel, and the fifth data line drives a fourth of the second sub-pixel
  • the driving voltage applied to the second data line is different from the driving voltage loaded on the fifth data line.
  • a first thin film transistor is disposed in the first region, a second thin film transistor is disposed in the second region, a third thin film transistor is disposed in the third region, and a fourth thin film transistor is disposed in the fourth region.
  • a fifth thin film transistor is disposed in the fifth region, and a sixth thin film transistor is disposed in the sixth region, the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film a gate of the transistor, the fifth thin film transistor, and the sixth thin film transistor is connected to a same scan line, and drains of the first thin film transistor and the second thin film transistor are connected to the first data line,
  • the source of the first thin film transistor is sequentially connected to the first main sub-pixel electrode, the first capacitor to the common electrode, and the source of the second thin film transistor is sequentially connected to the first sub-pixel electrode and the second capacitor to the common electrode
  • the source of the third thin film transistor is sequentially connected to the second main sub-pixel electrode and the third capacitor to the common electrode, and the
  • the first sub-pixel is a red sub-pixel
  • the second sub-pixel is a green sub-pixel
  • the third sub-pixel is a blue sub-pixel.
  • the present invention also provides a display panel comprising the thin film transistor array substrate of any one of the above embodiments.
  • FIG. 1 is a schematic view of a thin film transistor array substrate according to a first preferred embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a pixel in a thin film transistor array substrate in a first preferred embodiment of the present invention.
  • FIG 3 is a schematic view of a thin film transistor array substrate according to a second preferred embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a pixel in a thin film transistor array substrate in a second preferred embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a thin film transistor array substrate according to a third preferred embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a pixel in a thin film transistor array substrate in a third preferred embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a thin film transistor array substrate according to a fourth preferred embodiment of the present invention.
  • FIG. 8 is a schematic structural view of a pixel in a thin film transistor array substrate in a third preferred embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a thin film transistor array substrate according to a first preferred embodiment of the present invention
  • FIG. 2 is a schematic structural view of a pixel in a thin film transistor array substrate according to a first preferred embodiment of the present invention.
  • a plurality of pixels 100 arranged in an array are disposed on the thin film transistor array substrate 10, and each of the pixels 100 includes a first sub-pixel 110, a second sub-pixel 120, and a third sub-pixel 130 arranged in a first direction.
  • One sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 are connected to the same scan line GL.
  • the thin film transistor array substrate 10 is further provided with a first data line D1, a second data line D2, and a third data line D3 which are sequentially arranged in the first direction.
  • the first data line D1 is used to drive the first sub-pixel 110
  • the second data line D2 is used to drive the second sub-pixel 120
  • the third data line D3 is used to drive the third sub-pixel 130.
  • the first sub-pixel 110 includes a first region 111 and a second region 112 arranged in a second direction
  • the second sub-pixel 120 includes a third region 121 and a fourth region 122 arranged in a second direction
  • the third sub-pixel 130 includes a fifth region 131 and a sixth region 132 arranged in the second direction.
  • the voltage difference between the sub-pixel electrode and the common electrode in the sixth region 132 is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 131.
  • the first direction is a horizontal direction
  • the second direction is a vertical direction.
  • a first thin film transistor Q1 is disposed in the first region 111
  • a second thin film transistor Q2 is disposed in the second region 112
  • a third thin film transistor Q3 is disposed in the third region 121
  • the fourth region 122 is disposed in the fourth region 122.
  • a fifth thin film transistor Q5 is disposed in the fifth region 131
  • a sixth thin film transistor Q6 and a seventh thin film transistor Q7 are disposed in the sixth region 132.
  • the seventh thin film transistors Q7 each include a gate, a source, and a drain.
  • the first region 111, the second region 112, the third region 121, the fourth region 122, the fifth region 131, and the sixth region 132 respectively correspond to one sub-pixel electrode
  • the corresponding sub-pixel electrode in the first region 111 is named as the first main sub-pixel electrode 113
  • the corresponding sub-pixel electrode in the second region 112 is named as the first sub-pixel electrode 114
  • the corresponding sub-pixel electrode in the area 121 is named as the second main sub-pixel electrode 123
  • the corresponding sub-pixel electrode in the fourth area 122 is named as the second sub-pixel electrode 124, and the corresponding sub-pixel in the fifth area 131.
  • the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, the sixth thin film transistor Q6, and the The gate of the seventh thin film transistor Q7 is connected to the same scanning line GL.
  • the drains of the first thin film transistor Q1 and the second thin film transistor Q2 are connected to the first data line D1, and the source of the first thin film transistor Q1 is sequentially connected to the first main sub-pixel electrode 113 and the first capacitor C1.
  • the source of the second thin film transistor Q2 sequentially connects the first sub-pixel electrode 114 and the second capacitor C2 to the common electrode Cm.
  • the drains of the third thin film transistor Q3 and the fourth thin film transistor Q4 are connected to the second data line D2, and the source of the third thin film transistor Q3 is sequentially connected to the second main sub-pixel electrode 123 and the third capacitor C3.
  • the source of the fourth thin film transistor Q4 sequentially connects the second sub-pixel electrode 124 and the fourth capacitor C4 to the common electrode Cm.
  • the drains of the fifth thin film transistor Q5 and the sixth thin film transistor Q6 are connected to the third data line D3, and the source of the fifth thin film transistor Q5 is sequentially connected to the third main sub-pixel electrode 133 and the fifth capacitor C5.
  • the source of the sixth thin film transistor Q6 sequentially connects the third sub-pixel electrode 134 and the sixth capacitor C6 to the common electrode Cm.
  • the drain of the seventh thin film transistor Q7 is connected to the third sub-pixel electrode 134, and the source of the seventh thin film transistor Q7 is connected to the common electrode Cm.
  • the fifth thin film transistor Q5 of the fifth region 131 and the drain of the sixth thin film transistor Q6 of the sixth region 132 are simultaneously connected to the third data line D3, the fifth film.
  • the source of the transistor Q5 is sequentially connected to the third main sub-pixel electrode 133 and the fifth capacitor C5 to the common electrode Cm
  • the source of the sixth thin film transistor Q6 is sequentially connected to the third sub-pixel electrode 134 and the sixth capacitor.
  • the drain of the seventh thin film transistor Q7 is connected to the third sub-pixel electrode 134
  • the source of the seventh thin film transistor Q7 is connected to the common electrode Cm.
  • the voltage of the third sub-pixel electrode 134 and the fifth region 131 are loaded in the sixth region 132 through the voltage division of the seventh thin film transistor Q7.
  • the voltage applied to the third main sub-pixel electrode 133 is different.
  • the voltage applied to the third sub-pixel electrode 134 in the sixth region 132 is smaller than the voltage applied to the third main sub-pixel electrode 133 in the fifth region 131.
  • the voltage difference between the sub-pixel electrode and the common electrode of the sixth region 132 is different from the voltage difference between the sub-pixel electrode and the common electrode in the third region 131, and therefore, is loaded in the sixth region.
  • the voltage of the sub-pixel electrode of 132 is different from the voltage of the sub-pixel loaded in the fifth region 131.
  • the voltage applied to the third main sub-pixel electrode 133 is different from the voltage applied to the third sub-pixel electrode 134, so that the color shift when the thin film transistor array substrate 10 drives the liquid crystal layer can be improved.
  • the voltage applied to the third sub-pixel electrode 134 corresponding to the sixth region 132 in only one of the three sub-pixels of one pixel 100 is different from that described above.
  • the voltage applied to the third main sub-pixel electrode 133 corresponding to the fifth region 131 can reduce the defect that the liquid crystal molecules in the liquid crystal layer cannot be completely rotated compared with the prior art, thereby reducing the loss when the light passes through the liquid crystal layer. Therefore, compared with the prior art, the thin film transistor array substrate 10 of the present embodiment can improve the large-view character bias when driving the liquid crystal layer and can increase the light transmittance when light passes through the liquid crystal layer.
  • the first sub-pixel 110 is a red sub-pixel
  • the second sub-pixel 120 is a green sub-pixel
  • the third sub-pixel 130 is a blue sub-pixel. Since the human eye is most sensitive to changes in blue sub-pixels, the change to the green sub-pixels is second, and the change to the red sub-pixels is second. Therefore, the voltage difference between the sub-pixel electrode and the common electrode in the sixth region 132 corresponding to the third sub-pixel 130 is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 131, thereby being able to perform well. Improve the role of the big vision and minimize the loss of penetration.
  • FIG. 3 is a schematic diagram of a thin film transistor array substrate according to a second preferred embodiment of the present invention
  • FIG. 4 is a schematic structural view of a pixel in a thin film transistor array substrate according to a second preferred embodiment of the present invention.
  • the thin film transistor array substrate 20 is provided with a plurality of pixels 200 distributed in an array, and each of the pixels 200 includes a first sub-pixel 210, a second sub-pixel 220, and a third array arranged in a first direction.
  • the sub-pixel 230, the first sub-pixel 210, the second sub-pixel 220, and the third sub-pixel 230 are connected to the same scan line GL.
  • the thin film transistor array substrate 20 is further provided with a first data line D1, a second data line D2, and a third data line D3 which are sequentially arranged in the first direction.
  • the first data line D1 is used to drive the first sub-pixel 210
  • the second data line D2 is used to drive the second sub-pixel 220
  • the third data line D3 is used to drive the third sub-pixel 230.
  • the first sub-pixel 210 includes a first region 211 and a second region 212 arranged in a second direction
  • the second sub-pixel 220 includes a third region 221 and a fourth region 222 arranged in a second direction
  • the fourth sub-pixel 230 includes a fifth region 231 and a sixth region 232 arranged in the second direction.
  • the voltage difference between the sub-pixel electrode and the common electrode in the sixth region 232 is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 231.
  • the first direction is a horizontal direction
  • the second direction is a vertical direction.
  • a first thin film transistor Q1 is disposed in the first region 211
  • a second thin film transistor Q2 is disposed in the second region 212
  • a third thin film transistor Q3 is disposed in the third region 221
  • the fourth region 222 is disposed in the fourth region 222.
  • the fourth thin film transistor Q4 and the eighth thin film transistor Q8 are provided with a fifth thin film transistor Q5 in the fifth region 231, and a sixth thin film transistor Q6 and a seventh thin film transistor Q7 are disposed in the sixth region 232.
  • the seventh thin film transistor Q7 and the eighth thin film transistor Q8 each include a gate, a source, and a drain.
  • the first region 211, the second region 212, the third region 221, the fourth region 222, the fifth region 231, and the sixth region 232 respectively correspond to one sub-pixel electrode
  • the corresponding sub-pixel electrode in the first region 211 is named as the first main sub-pixel electrode 213, and the corresponding sub-pixel electrode in the second region 212 is named as the first sub-pixel electrode 214
  • the third The corresponding sub-pixel electrode in the area 221 is named as the second main sub-pixel electrode 223, and the corresponding sub-pixel electrode in the fourth area 222 is named as the second sub-pixel electrode 224, and the corresponding sub-pixel in the fifth area 231
  • the electrode is named as the third main sub-pixel electrode 233, and the corresponding sub-pixel electrode in the sixth region 232 is named as the third sub-pixel electrode 234. It should be understood by those skilled in the art that the corresponding sub-pixel electrodes in each of the above regions are named only for distinguishing sub-pixels in different regions for convenience of description, and there is actually no primary or
  • the gates of the seventh thin film transistor Q7 and the eighth thin film transistor Q8 are connected to the same scanning line GL.
  • the drains of the first thin film transistor Q1 and the second thin film transistor Q2 are connected to the first data line D1, and the source of the first thin film transistor Q1 is sequentially connected to the first main sub-pixel.
  • a source of the second thin film transistor Q2 sequentially connects the first sub-pixel electrode 224 and the second capacitor C2 to the common electrode Cm .
  • the drains of the third thin film transistor Q3 and the fourth thin film transistor Q4 are connected to the second data line D2, and the source of the third thin film transistor Q3 is sequentially connected to the second main sub-pixel electrode 223 and the third capacitor C3.
  • the source of the fourth thin film transistor Q4 sequentially connects the second sub-pixel electrode 224 and the fourth capacitor C4 to the common electrode Cm.
  • the drain of the eighth thin film transistor Q8 is connected to the second sub-pixel electrode 224, and the source of the eighth thin film transistor Q8 is connected to the common electrode Cm.
  • the drains of the fifth thin film transistor Q5 and the sixth thin film transistor Q6 are connected to the third data line D3, and the source of the fifth thin film transistor Q5 is sequentially connected to the third main sub-pixel electrode 233 and the fifth capacitor C5.
  • the source of the sixth thin film transistor Q6 sequentially connects the third sub-pixel electrode 234 and the sixth capacitor C6 to the common electrode Cm.
  • the drain of the seventh thin film transistor Q7 is connected to the third sub-pixel electrode 234, and the source of the seventh thin film transistor Q7 is connected to the common electrode Cm.
  • the fifth thin film transistor Q5 of the fifth region 231 and the drain of the sixth thin film transistor Q6 of the sixth region 232 are simultaneously connected to the third data line D3, the fifth film.
  • the source of the transistor Q5 is sequentially connected to the third main sub-pixel electrode 233 and the fifth capacitor C5 to the common electrode Cm
  • the source of the sixth thin film transistor Q6 is sequentially connected to the third sub-pixel electrode 234 and the sixth capacitor.
  • the drain of the seventh thin film transistor Q7 is connected to the third sub-pixel electrode 234, and the source of the seventh thin film transistor Q7 is connected to the common electrode Cm.
  • the voltage of the third sub-pixel electrode 234 and the fifth region 231 are loaded in the sixth region 232 through the voltage division of the seventh thin film transistor Q7.
  • the voltage applied to the third main sub-pixel electrode 233 is different.
  • the voltage applied to the third sub-pixel electrode 234 in the sixth region 232 is smaller than the voltage applied to the third main sub-pixel electrode 233 in the fifth region 231.
  • the voltage applied to the second sub-pixel electrode 224 in the fourth region 222 and the second region 221 are loaded in the second portion through the voltage division of the eighth thin film transistor Q8.
  • the voltage of the main sub-pixel electrode 223 is different.
  • the voltage applied to the second sub-pixel electrode 224 in the fourth region 222 is smaller than the voltage applied to the second main sub-pixel electrode 223 in the third region 221 .
  • the voltage difference between the sub-pixel electrode and the common electrode of the sixth region 232 is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 231, and therefore, is loaded in the sixth region.
  • the voltage of the sub-pixel electrode of 232 is different from the voltage of the sub-pixel loaded in the fifth region 231.
  • the voltage applied to the third main sub-pixel electrode 233 is different from the voltage applied to the third sub-pixel electrode 234, so that the color shift when the thin film transistor array substrate 20 drives the liquid crystal layer can be improved.
  • the voltage applied to the second main sub-pixel electrode 223 is different from the voltage applied to the second sub-pixel electrode 224, which further improves the driving of the liquid crystal layer by the thin film transistor array substrate 20. Color shift.
  • the voltage applied to the third sub-pixel electrode 234 corresponding to the sixth region 232 in the third sub-pixel 230 in one pixel 200 is different from the corresponding portion of the fifth region 231.
  • a voltage applied to the third main sub-pixel electrode 233, a voltage applied to the second sub-pixel electrode 224 corresponding to the fourth region 222 of the second sub-pixel 220 is different from a second main sub-pixel corresponding to the third region 221.
  • the voltage applied to the electrode 221 can reduce the defect that the liquid crystal molecules in the liquid crystal layer cannot be completely rotated as compared with the prior art, thereby reducing the loss when the light passes through the liquid crystal layer. Therefore, compared with the prior art, the thin film transistor array substrate 20 of the present embodiment can improve the large-view character bias when driving the liquid crystal layer and can increase the light transmittance when light passes through the liquid crystal layer.
  • the first sub-pixel 210 is a red sub-pixel
  • the second sub-pixel 220 is a green sub-pixel
  • the third sub-pixel 230 is a blue sub-pixel.
  • FIG. 5 is a schematic diagram of a thin film transistor array substrate according to a third preferred embodiment of the present invention
  • FIG. 6 is a schematic structural view of a pixel in a thin film transistor array substrate according to a third preferred embodiment of the present invention.
  • a plurality of pixels 300 arranged in an array are disposed on the thin film transistor array substrate 30, and each of the pixels 300 includes a first sub-pixel 310, a second sub-pixel 320, and a third sub-pixel 330 arranged in a first direction.
  • One sub-pixel 310, the second sub-pixel 320, and the third sub-pixel 330 are connected to the same scan line GL.
  • the thin film transistor array substrate 30 is further provided with a first data line D1, a second data line D2, a third data line D3, and a fourth data line D4 which are sequentially arranged in the first direction.
  • the first data line D1 is used to drive the first sub-pixel 310
  • the second data line D2 is used to drive the second sub-pixel 320
  • the third data line D3 is used to drive the third sub-pixel 330.
  • the fourth data line D4 is used to drive the third sub-pixel 330.
  • the first sub-pixel 310 includes a first region 311 and a second region 312 arranged in a second direction
  • the second sub-pixel 320 includes a second
  • the third region 321 and the fourth region 322 are arranged in the direction
  • the third sub-pixel 330 includes a fifth region 331 and a sixth region 332 arranged in the second direction.
  • the voltage difference between the sub-pixel electrode and the common electrode in the sixth region 332 is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 331.
  • the first direction is a horizontal direction
  • the second direction is a vertical direction.
  • the third data line D3 drives the fifth area 331 of the third sub-pixel 330
  • the fourth data line D4 is used to drive the sixth area 332 of the third sub-pixel 330
  • the driving voltage loaded on D3 is different from the driving voltage loaded on the fourth data line.
  • the fifth region 331 and the sixth region 332 of the third sub-pixel 330 are driven by the third data line D3 and the fourth data line D4, respectively, and the third data line D3 and the fourth data line D4 are used.
  • the applied voltages are different to achieve a voltage difference between the sub-pixel electrode and the common electrode in the sixth region 332 that is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 331.
  • a first thin film transistor Q1 is disposed in the first region 311, a second thin film transistor Q2 is disposed in the second region 312, and a third thin film transistor Q3 is disposed in the third region 321 and is disposed in the fourth region 322.
  • a fifth thin film transistor Q5 is disposed in the fifth region 331, and a sixth thin film transistor Q6 is disposed in the sixth region 332.
  • the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, and the sixth thin film transistor Q6 each include a gate. Pole, source and drain.
  • the first region 311, the second region 312, the third region 321, the fourth region 322, the fifth region 331, and the sixth region 332 respectively correspond to one sub-pixel electrode
  • the corresponding sub-pixel electrode in the first region 311 is named as the first main sub-pixel electrode 313, and the corresponding sub-pixel electrode in the second region 312 is named as the first sub-pixel electrode 314, and the third
  • the corresponding sub-pixel electrode in the area 321 is named as the second main sub-pixel electrode 323, and the corresponding sub-pixel electrode in the fourth area 322 is named as the second sub-pixel electrode 324, and the corresponding sub-pixel in the fifth area 331
  • the electrode is named as the third main sub-pixel electrode 333, and the corresponding sub-pixel electrode in the sixth region 332 is named as the third sub-pixel electrode 334.
  • the gate of the tube Q6 is connected to the same scanning line GL.
  • the drains of the first thin film transistor Q1 and the second thin film transistor Q2 are connected to the first data line D1, and the source of the first thin film transistor Q1 is sequentially connected to the first main sub-pixel electrode 313 and the first capacitor C1.
  • the source of the second thin film transistor Q2 sequentially connects the first sub-pixel electrode 314 and the second capacitor C2 to the common electrode Cm.
  • the drains of the third thin film transistor Q3 and the fourth thin film transistor Q4 are connected to the second data line D2, and the source of the third thin film transistor Q3 is sequentially connected to the second main sub-pixel electrode 323 and the third capacitor C3.
  • the source of the fourth thin film transistor Q4 sequentially connects the second sub-pixel electrode 324 and the fourth capacitor C4 to the common electrode Cm.
  • the drain of the fifth thin film transistor Q5 is connected to the third data line D3, and the source of the fifth thin film transistor Q5 is sequentially connected to the third main sub-pixel electrode 333 and the fifth capacitor C5 to the common electrode Cm.
  • the drain of the sixth thin film transistor Q6 is connected to the fourth data line D4, and the elements of the sixth thin film transistor Q6 are sequentially connected to the third sub-pixel electrode 334 and the sixth capacitor to the common electrode Cm.
  • the fifth region 331 and the sixth region 332 of the third sub-pixel 330 are driven by the third data line D3 and the fourth data line D4, respectively, and the third data line D3 and the fourth data line D4 are used.
  • the applied voltages are different to achieve a voltage difference between the sub-pixel electrode and the common electrode in the sixth region 332 that is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 331.
  • the voltage applied to the third main sub-pixel electrode 333 is different from the voltage applied to the third sub-pixel electrode 334, so that the color shift of the thin film transistor array substrate 30 when driving the liquid crystal layer can be improved.
  • the voltage applied to the third sub-pixel electrode 334 corresponding to the sixth region 332 of only one of the three sub-pixels of one pixel 300 is different from that described above.
  • the voltage applied to the third main sub-pixel electrode 333 corresponding to the fifth region 331 can reduce the defect that the liquid crystal molecules in the liquid crystal layer cannot be completely rotated compared with the prior art, thereby reducing the loss when the light passes through the liquid crystal layer. Therefore, compared with the prior art, the thin film transistor array substrate 30 of the present embodiment can improve the large-view character bias when driving the liquid crystal layer and can increase the light transmittance when light passes through the liquid crystal layer.
  • the first sub-pixel 310 is a red sub-pixel
  • the second sub-pixel 320 is a green sub-pixel
  • the third sub-pixel 330 is a blue sub-pixel.
  • FIG. 7 is a schematic diagram of a thin film transistor array substrate according to a fourth preferred embodiment of the present invention
  • FIG. 8 is a pixel in a thin film transistor array substrate according to a third preferred embodiment of the present invention.
  • Schematic diagram of the structure A plurality of pixels 400 arranged in an array are disposed on the thin film transistor array substrate 30, and each of the pixels 400 includes a first sub-pixel 410, a second sub-pixel 420, and a third sub-pixel 430 arranged in a first direction.
  • One sub-pixel 410, the second sub-pixel 420, and the third sub-pixel 430 are connected to the same scan line GL.
  • the thin film transistor array substrate 40 is further provided with a first data line D1, a second data line D2, a third data line D3, a fourth data line D4, and a fifth data line D5 which are sequentially arranged in the first direction.
  • the first data line D1 is used to drive the first sub-pixel 410
  • the second data line D2 is used to drive the second sub-pixel 420
  • the third data line D3 is used to drive the third sub-pixel 430.
  • the fourth data line D4 is used to drive the third sub-pixel 430
  • the fifth data line D5 is used to drive the second sub-pixel 420.
  • the first sub-pixel 410 includes a first region 411 and a second region 412 arranged in a second direction
  • the second sub-pixel 420 includes a third region 421 and a fourth region 422 arranged in a second direction
  • the third sub-pixel 430 includes a fifth area 431 and a sixth area 432 arranged in the second direction.
  • the voltage difference between the sub-pixel electrode and the common electrode in the sixth region 432 is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 431.
  • the first direction is a horizontal direction
  • the second direction is a vertical direction.
  • the third data line D3 drives the fifth area 431 of the third sub-pixel 430, and the fourth data line D4 is used to drive the sixth area 432 of the third sub-pixel 430, the third data line
  • the driving voltage applied to D3 is different from the driving voltage applied to the fourth data line D4.
  • the second data line D2 is used to drive the third area 421 of the second sub-pixel 420, and the fifth data line D5 is used to drive the fourth area 422 of the second sub-pixel 420, the second The driving voltage applied to the data line D2 is different from the driving voltage applied to the fifth data line D5.
  • the driving voltage applied on the third data line D3 is different from the driving voltage loaded on the fourth data line D4 to achieve a different voltage applied to the sub-pixel electrode in the fifth region 331.
  • the voltage applied to the sub-pixel electrode in the third region 321 is different from the fourth region by the driving voltage applied to the second data line D2 being different from the driving voltage applied to the fifth data line D5.
  • a first thin film transistor Q1 is disposed in the first region 411
  • a second thin film transistor Q2 is disposed in the second region 412
  • a third thin film transistor Q3 is disposed in the third region 421, and the fourth region 422 is disposed in the fourth region 422.
  • a fifth thin film transistor Q5 is disposed in the fifth region 431
  • a sixth thin film transistor Q6 is disposed in the sixth region 432.
  • the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, and the sixth thin film transistor Q6 each include a gate, a source, and a drain. pole.
  • the first region 411, the second region 412, the third region 421, the fourth region 422, the fifth region 431, and the sixth region 432 respectively correspond to one sub-pixel electrode
  • the corresponding sub-pixel electrode in the first region 411 is named as the first main sub-pixel electrode 413
  • the corresponding sub-pixel electrode in the second region 412 is named as the first sub-pixel electrode 414
  • the corresponding sub-pixel electrode in the area 421 is named as the second main sub-pixel electrode 423
  • the corresponding sub-pixel electrode in the fourth area 422 is named as the second sub-pixel electrode 424, and the corresponding sub-pixel in the fifth area 431.
  • the electrode is named as the third main sub-pixel electrode 433, and the corresponding sub-pixel electrode in the sixth area 432 is named as the third sub-pixel electrode 434. It should be understood by those skilled in the art that the corresponding sub-pixel electrodes in each of the above regions are named only for distinguishing sub-pixels in different regions for convenience of description, and there is actually no primary or secondary.
  • a gate of the first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, the fourth thin film transistor Q4, the fifth thin film transistor Q5, and the sixth thin film transistor Q6 Connect the same scan line GL.
  • the drains of the first thin film transistor Q1 and the second thin film transistor Q2 are connected to the first data line D1, and the source of the first thin film transistor Q1 is sequentially connected to the first main sub-pixel electrode 413 and the first capacitor C1.
  • the source of the second thin film transistor Q2 sequentially connects the first sub-pixel electrode 414 and the second capacitor C2 to the common electrode Cm.
  • the drain of the third thin film transistor Q3 is connected to the two data lines D2, and the source of the third thin film transistor Q3 is sequentially connected to the second main sub-pixel electrode 423 and the third capacitor C3 to the common electrode Cm
  • the fourth The drain of the thin film transistor Q4 is connected to the fifth data line D5, and the source of the fourth thin film transistor Q4 is sequentially connected to the second sub-pixel electrode 424 and the fourth capacitor C4 to the common electrode Cm.
  • the drain of the fifth thin film transistor Q5 is connected to the third data line D3, and the source of the fifth thin film transistor Q5 sequentially connects the third main sub-pixel electrode 433 and the fifth capacitor C5 to the common electrode Cm.
  • the drain of the sixth thin film transistor Q6 is connected to the fourth data line D4, and the elements of the sixth thin film transistor Q6 are sequentially connected to the third sub-pixel electrode 434 and the sixth capacitor to the common electrode Cm.
  • the fifth region 431 and the sixth region 432 of the third sub-pixel 430 are driven by the third data line D3 and the fourth data line D4, respectively, and the third data line D3 and the fourth data are used.
  • the voltage applied to the line D4 is different to achieve a voltage difference between the sub-pixel electrode and the common electrode in the sixth region 432 that is different from the voltage difference between the sub-pixel electrode and the common electrode in the fifth region 431.
  • the voltage applied to the third main sub-pixel electrode 433 is different from the voltage applied to the third sub-pixel electrode 434, so that the color shift when the thin film transistor array substrate 40 drives the liquid crystal layer can be improved.
  • the third region 421 and the fourth region 422 of the second pixel 420 are driven by the second data line D2 and the fifth data line D5, and the second data line D2 and the fifth data line D5 are loaded.
  • the voltages are different to realize that the voltage difference between the sub-pixel electrode and the common electrode in the third region 421 is different from the voltage difference between the sub-pixel electrode and the common electrode in the fourth region 422.
  • the thin film transistor array substrate 30 of the present embodiment can improve the large-view character bias when driving the liquid crystal layer and can increase the light transmittance when light passes through the liquid crystal layer.
  • the first sub-pixel 410 is a red sub-pixel
  • the second sub-pixel 420 is a green sub-pixel
  • the third sub-pixel 430 is a blue sub-pixel.
  • the present invention further provides a display panel.
  • the display panel includes any one of the foregoing thin film transistor array substrates of FIG. 1 to FIG. Narration.

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Abstract

一种薄膜晶体管阵列基板（10）及显示面板。薄膜晶体管阵列基板（10）上设置多个像素（100），每个像素（100）包括沿第一方向依次排列的第一子像素（110）、第二子像素（120）及第三子像素（130），第一至第三子像素（110，120，130）连接至同一条扫描线（GL），薄膜晶体管阵列基板（10）上还设置沿第一方向依次排列的第一数据线（D1）、第二数据线（D2）及第三数据线（D3），第一数据线（D1）用于驱动第一子像素（110），第二数据线（D2）用于驱动第二子像素（120），第三数据线（D3）用于驱动第三子像素（130），第一子像素（110）包括沿第二方向排列的第一区域（111）及第二区域（112），第二子像素（120）包括沿第二方向排列的第三区域（121）及第四区域（122），第三子像素（130）包括沿第二方向排列的第五区域（131）及第六区域（132），第六区域（132）内的子像素电极与公共电极的电压差不同于第五区域（131）内的子像素电极与公共电极的电压差。

Description

薄膜晶体管阵列基板及显示面板
本发明要求2014年12月31日递交的发明名称为“薄膜晶体管阵列基板及显示面板”的申请号201410854643.2的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管阵列基板及显示面板。
背景技术
液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。目前的液晶显示器主要是以薄膜晶体管(Thin Film Transistor,TFT)液晶显示器为主。随着平面显示技术的发展，具有广视角的液晶显示器的需求被提出。传统的广视角液晶显示面板在大视角观看的时候往往会出现色偏的问题。因此，现有技术中液晶显示面板在大视角观看的时候会出现色偏等技术问题。
发明内容
本发明提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板上设置呈阵列分布的多个像素，每个像素包括沿第一方向依次排列的第一子像素、第二子像素及第三子像素，所述第一子像素、所述第二子像素及所述第三子像素连接至同一条扫描线，所述薄膜晶体管阵列基板上还设置沿第一方向依次排列的第一数据线、第二数据线及第三数据线，所述第一数据线用于驱动所述第一子像素，所述第二数据线用于驱动所述第二子像素，所述第三数据线用于驱动所述第三子像素，所述第一子像素包括沿第二方向排列的第一区域及第二区域，所述第二子像素包括沿第二方向排列的第三区域及第四区域，所述第三子像素包括沿第二方向排列的第五区域及第六区域，所述第六区域内的子像素电极与公共电极的电压差不同于所述第五区域内的子像素电极与公共电极的电压差。
其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄 膜晶体管，所述第三区域内设置第三薄膜晶体管，所述第四区域内设置第四薄膜晶体管，所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管和第七薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管及所述第七薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接第一次子像素电极、第二电容至公共电极，所述第三薄膜晶体管及所述第四薄膜晶体管的漏极连接所述第二数据线，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第五薄膜晶体管及所述第六薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极，所述第七薄膜晶体管的漏极连接所述第三次子像素电极，所述第七薄膜晶体管的源极连接所述公共电极。
其中，所述第四区域内的子像素电极与公共电极的电压差不同于所述第三区域内的子像素电极与公共电极的电压差。
其中，所述第四区域内设置第八薄膜晶体管，所述第八薄膜晶体管的栅极连接所述扫描线，所述第八薄膜晶体管的漏极连接所述第二次子像素电极，所述第八薄膜晶体管的源极连接所述公共电极。
其中，所述薄膜晶体管阵列基板上还设置的第四数据线，所述第三数据线驱动所述第三子像素的第五区域，所述第四数据线驱动所述第三子像素的第六区域，所述第三数据线上加载的驱动电压与所述第四数据线上加载的驱动电压不同。
其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管、所述第三区域内设置第四薄膜晶体管、所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜 晶体管、所述第六薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接所述第一次像素电极、第二电容至公共电极，所述第三薄膜晶体管及所述第四薄膜晶体管的漏极连接所述第二数据线，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第五薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的漏极连接所述第四数据线，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极。
其中，所述薄膜晶体管阵列基板上还设置第五数据线，所述第二数据线驱动所述第二子像素的第三区域，所述第五数据线驱动所述第二子像素的第四区域，所述第二数据线上加载的驱动电压与所述第五数据线上加载的驱动电压不同。
其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管，所述第三区域内设置第三薄膜晶体管，所述第四区域内设置第四薄膜晶体管，所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接所述第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接所述第一次子像素电极、第二电容至公共电极，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第三薄膜晶体管的漏极连接所述第二数据线，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第四薄膜晶体管的漏极连接所述第五数据线，所述第五薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的漏极连接所述第四数据线， 所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极。
其中，所述第一子像素为红色子像素，第二子像素为绿色子像素，所述第三子像素为蓝色子像素。
本发明还提供一种显示面板，所述显示面板包括上述各实施方式中任意一种实施方式的薄膜晶体管阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一较佳实施方式的薄膜晶体管阵列基板的示意图。
图2是本发明第一较佳实施方式中的薄膜晶体管阵列基板中像素的结构示意图。
图3是本发明第二较佳实施方式的薄膜晶体管阵列基板的示意图。
图4是本发明第二较佳实施方式中的薄膜晶体管阵列基板中像素的结构示意图。
图5为本发明第三较佳实施方式的薄膜晶体管阵列基板的示意图。
图6是本发明第三较佳实施方式中的薄膜晶体管阵列基板中像素的结构示意图。
图7为本发明第四较佳实施方式的薄膜晶体管阵列基板的示意图。
图8是本发明第三较佳实施方式中的薄膜晶体管阵列基板中像素的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造 性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1和图2，图1是本发明第一较佳实施方式的薄膜晶体管阵列基板的示意图；图2是本发明第一较佳实施方式中的薄膜晶体管阵列基板中像素的结构示意图。。所述薄膜晶体管阵列基板10上设置呈阵列分布的多个像素100，每个像素100包括沿第一方向排列的第一子像素110、第二子像素120及第三子像素130，所述第一子像素110、所述第二子像素120及所述第三子像素130连接至同一条扫描线GL。所述薄膜晶体管阵列基板10上还设置沿第一方向依次排列的第一数据线D1、第二数据线D2及第三数据线D3。所述第一数据线D1用于驱动第一子像素110，所述第二数据线D2用于驱动第二子像素120，所述第三数据线D3用于驱动所述第三子像素130。所述第一子像素110包括沿第二方向排列的第一区域111及第二区域112，所述第二子像素120包括沿第二方向排列的第三区域121及第四区域122，所述第三子像素130包括沿第二方向排列的第五区域131及第六区域132。所述第六区域132内的子像素电极与公共电极的电压差不同于所述第五区域131内的子像素电极与公共电极的电压差。在本实施方式中，所述第一方向为水平方向，所述第二方向为竖直方向。
所述第一区域111内设置第一薄膜晶体管Q1、所述第二区域112内设置第二薄膜晶体管Q2，所述第三区域121内设置第三薄膜晶体管Q3，所述第四区域122内设置第四薄膜晶体管Q4，所述第五区域131内设置第五薄膜晶体管Q5，所述第六区域132内设置第六薄膜晶体管Q6和第七薄膜晶体管Q7。所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5、所述第六薄膜晶体管Q6及所述第七薄膜晶体管Q7均包括栅极、源极和漏极。所述第一区域111、所述第二区域112、所述第三区域121、所述第四区域122、所述第五区域131及所述第六区域132内分别对应一个子像素电极，为了方便描述，所述第一区域111内对应的子像素电极命名为第一主子像素电极113，所述第二区域112内对应的子像素电极命名为第一次子像素电极114，所述第三区域121内对应的子像素电极命名为第二主子像素电极123，所述第四区域122内对应的子像素电极命名为第二次子像素电极124，所述第五区域131内对应的子像素电极 命名为第三主子像素电极133，所述第六区域132内对应的子像素电极命名为第三次子像素电极134。所属领域的一般技术人员应当理解，上述各个区域内对应的子像素电极的命名只是为了区分不同区域内的子像素，以方便描述之用，实际上并不存在主次之分。
所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5、所述第六薄膜晶体管Q6及所述第七薄膜晶体管Q7的栅极连接同一条扫描线GL。所述第一薄膜晶体管Q1和所述第二薄膜晶体管Q2的漏极连接所述第一数据线D1，所述第一薄膜晶体管Q1的源极依次连接第一主子像素电极113、第一电容C1至公共电极Cm(在图2中用三角符号△表示)，所述第二薄膜晶体管Q2的源极依次连接第一次子像素电极114、第二电容C2至公共电极Cm。所述第三薄膜晶体管Q3及所述第四薄膜晶体管Q4的漏极连接所述第二数据线D2，所述第三薄膜晶体管Q3的源极依次连接第二主子像素电极123、第三电容C3至公共电极Cm，所述第四薄膜晶体管Q4的源极依次连接第二次子像素电极124、第四电容C4至公共电极Cm。所述第五薄膜晶体管Q5及所述第六薄膜晶体管Q6的漏极连接所述第三数据线D3，所述第五薄膜晶体管Q5的源极依次连接第三主子像素电极133、第五电容C5至公共电极Cm，所述第六薄膜晶体管Q6的源极依次连接第三次子像素电极134、第六电容C6至公共电极Cm。所述第七薄膜晶体管Q7的漏极连接所述第三次子像素电极134，所述第七薄膜晶体管Q7的源极连接所述公共电极Cm。
在本实施方式中，由于所述第五区域131的第五薄膜晶体管Q5及所述第六区域132的第六薄膜晶体管Q6的漏极同时连接所述第三数据线D3，所述第五薄膜晶体管Q5的源极依次连接所述第三主子像素电极133、所述第五电容C5至公共电极Cm，所述第六薄膜晶体管Q6的源极依次连接第三次子像素电极134、第六电容C6至公共电极Cm，所述第七薄膜晶体管Q7的漏极连接所述第三次子像素电极134，所述第七薄膜晶体管Q7的源极连接所述公共电极Cm。即，由于薄膜晶体管有一定的电阻，经过所述第七薄膜晶体管Q7的分压作用，所述第六区域132中加载在所述第三次子像素电极134的电压与所述第五区域131中加载在所述第三主子像素电极133的电压不同。在本实施方 式中，所述第六区域132中加载在所述第三次子像素电极134的电压小于所述第五区域131中加载在所述第三主子像素电极133的电压。
在本实施方式中，所述第六区域132的子像素电极与公共电极的电压差不同于第五区域内131内的子像素电极与公共电极的电压差，因此，加载在所述第六区域132的子像素电极的电压不同于加载在所述第五区域131内的子像素的电压。换句话说，加载在所述第三主子像素电极133上的电压不同于加载在所述第三次子像素电极134的电压，从而能够改善所述薄膜晶体管阵列基板10驱动液晶层时的色偏。另一方面，在本实施方式中，在一个像素100的三个子像素中仅仅有一个第三子像素130中的第六区域132对应的第三次子像素电极134上加载的电压不同于所述第五区域131对应的第三主子像素电极133上加载的电压，相较于现有技术能够减小液晶层中的液晶分子不能完全转动的缺陷，从而将光线穿过液晶层时的损失降低。因此，相较于现有技术，本实施方式中的薄膜晶体管阵列基板10在驱动液晶层时能够改善大视角色偏且能够增大光线穿过液晶层时的光线穿透率。
在本实施方式中，所述第一子像素110为红色子像素，第二子像素120为绿色子像素，所述第三子像素130为蓝色子像素。由于所述人眼对蓝色子像素的变化最敏感，对绿色子像素的变化次之，对红色子像素的变化更次之。因此，对所述第三子像素130对应的第六区域132内的子像素电极与公共电极的电压差不同于第五区域131内的子像素电极与公共电极的电压差，从而能够很好地改善大视角色偏，且将穿透率的损失降到最低。
请参阅图3和图4，图3是本发明第二较佳实施方式的薄膜晶体管阵列基板的示意图；图4是本发明第二较佳实施方式中的薄膜晶体管阵列基板中像素的结构示意图。在本实施方式中，所述薄膜晶体管阵列基板20上设置呈阵列状分布的多个像素200，每个像素200包括沿第一方向排列的第一子像素210、第二子像素220及第三子像素230，所述第一子像素210、所述第二子像素220及所述第三子像素230连接至同一条扫描线GL。所述薄膜晶体管阵列基板20上还设置沿第一方向依次排列的第一数据线D1、第二数据线D2及第三数据线D3。所述第一数据线D1用于驱动所述第一子像素210，所述第二数据线D2用于驱动第二子像素220，所述第三数据线D3用于驱动第三子像素230。 所述第一子像素210包括沿第二方向排列的第一区域211及第二区域212，所述第二子像素220包括沿第二方向排列的第三区域221及第四区域222，所述第四子像素230包括沿第二方向排列的第五区域231及第六区域232。所述第六区域232内的子像素电极与公共电极的电压差不同于所述第五区域231内的子像素电极与公共电极的电压差。在本实施方式中，所述第一方向为水平方向，所述第二方向为竖直方向。
所述第一区域211内设置第一薄膜晶体管Q1，所述第二区域212内设置第二薄膜晶体管Q2，所述第三区域221内设置第三薄膜晶体管Q3，所述第四区域222内设置第四薄膜晶体管Q4及第八薄膜晶体管Q8，所述第五区域231内设置第五薄膜晶体管Q5，所述第六区域232内设置第六薄膜晶体管Q6和第七薄膜晶体管Q7。所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5、所述第六薄膜晶体管Q6、所述第七薄膜晶体管Q7及所述第八薄膜晶体管Q8均包括栅极、源极和漏极。所述第一区域211、所述第二区域212、所述第三区域221、所述第四区域222、所述第五区域231及所述第六区域232内分别对应一个子像素电极，为了方便描述，所述第一区域211内对应的子像素电极命名为第一主子像素电极213，所述第二区域212内对应的子像素电极命名为第一次子像素电极214，所述第三区域221内对应的子像素电极命名为第二主子像素电极223，所述第四区域222内对应的子像素电极命名为第二次子像素电极224，所述第五区域231内对应的子像素电极命名为第三主子像素电极233，所述第六区域232内对应的子像素电极命名为第三次子像素电极234。所属领域的一般技术人员应当理解，上述各个区域内对应的子像素电极的命名只是为了区分不同区域内的子像素，以方便描述之用，实际上并不存在主次之分。
所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5、所述第六薄膜晶体管Q6、所述第七薄膜晶体管Q7及所述第八薄膜晶体管Q8的栅极连接同一条扫描线GL。所述第一薄膜晶体管Q1和所述第二薄膜晶体管Q2的漏极连接所述第一数据线D1，所述第一薄膜晶体管Q1的源极依次连接第一主子像素电 极213、第一电池C1至公共电极Cm(在图4中用三角符号△表示)，所述第二薄膜晶体管Q2的源极依次连接第一次像素电极224、第二电容C2至公共电极Cm。所述第三薄膜晶体管Q3及所述第四薄膜晶体管Q4的漏极连接所述第二数据线D2，所述第三薄膜晶体管Q3的源极依次连接第二主子像素电极223、第三电容C3至公共电极Cm，所述第四薄膜晶体管Q4的源极依次连接所述第二次子像素电极224、第四电容C4至公共电极Cm。所述第八薄膜晶体管Q8的漏极连所述第二次子像素电极224，所述第八薄膜晶体管Q8的源极连接所述公共电极Cm。所述第五薄膜晶体管Q5及所述第六薄膜晶体管Q6的漏极连接所述第三数据线D3，所述第五薄膜晶体管Q5的源极依次连接第三主子像素电极233、第五电容C5至公共电极Cm，所述第六薄膜晶体管Q6的源极依次连接第三次子像素电极234、第六电容C6至公共电极Cm。所述第七薄膜晶体管Q7的漏极连接所述第三次子像素电极234，所述第七薄膜晶体管Q7的源极连接所述公共电极Cm。
在本实施方式中，由于所述第五区域231的第五薄膜晶体管Q5及所述第六区域232的第六薄膜晶体管Q6的漏极同时连接所述第三数据线D3，所述第五薄膜晶体管Q5的源极依次连接所述第三主子像素电极233、所述第五电容C5至公共电极Cm，所述第六薄膜晶体管Q6的源极依次连接第三次子像素电极234、第六电容C6至公共电极Cm，所述第七薄膜晶体管Q7的漏极连接所述第三次子像素电极234，所述第七薄膜晶体管Q7的源极连接所述公共电极Cm。即，由于薄膜晶体管有一定的电阻，经过所述第七薄膜晶体管Q7的分压作用，所述第六区域232中加载在所述第三次子像素电极234的电压与所述第五区域231中加载在所述第三主子像素电极233的电压不同。在本实施方式中，所述第六区域232中加载在所述第三次子像素电极234的电压小于所述第五区域231中加载在所述第三主子像素电极233的电压。同样原理，经过所述第八薄膜晶体管Q8的分压作用，所述第四区域222中加载在所述第二次子像素电极224的电压与所述第三区域221中加载在所述第二主子像素电极223的电压不同。在本实施方式中，所述第四区域222中加载在所述第二次子像素电极224的电压小于所述第三区域221中加载在所述第二主子像素电极223的电压。
在本实施方式中，所述第六区域232的子像素电极与公共电极的电压差不同于第五区域内231内的子像素电极与公共电极的电压差，因此，加载在所述第六区域232的子像素电极的电压不同于加载在所述第五区域231内的子像素的电压。换句话说，加载在所述第三主子像素电极233上的电压不同于加载在所述第三次子像素电极234的电压，从而能够改善所述薄膜晶体管阵列基板20驱动液晶层时的色偏。同样道理，在本实施方式中，加载在所述第二主子像素电极223上的电压不同于加载在所述第二次子像素电极224的电压，进一步改善了薄膜晶体管阵列基板20驱动液晶层时的色偏。另一方面，在本实施方式中，在一个像素200中第三子像素230中的第六区域232对应的第三次子像素电极234上加载的电压不同于所述第五区域231对应的第三主子像素电极233上加载的电压，所述第二子像素220中的第四区域222对应的第二次子像素电极224上加载的电压不同于所述第三区域221对应的第二主子像素电极221上加载的电压，相较于现有技术能够减小液晶层中的液晶分子不能完全转动的缺陷，从而将光线穿过液晶层时的损失降低。因此，相较于现有技术，本实施方式中的薄膜晶体管阵列基板20在驱动液晶层时能够改善大视角色偏且能够增大光线穿过液晶层时的光线穿透率。
同样地，在本实施方式中，所述第一子像素210为红色子像素，第二子像素220为绿色子像素，所述第三子像素230为蓝色子像素。
请参阅图5和图6，图5为本发明第三较佳实施方式的薄膜晶体管阵列基板的示意图；图6是本发明第三较佳实施方式中的薄膜晶体管阵列基板中像素的结构示意图。所述薄膜晶体管阵列基板30上设置呈阵列分布的多个像素300，每个像素300包括沿第一方向排列的第一子像素310、第二子像素320及第三子像素330，所述第一子像素310、所述第二子像素320及所述第三子像素330连接至同一条扫描线GL。所述薄膜晶体管阵列基板30上还设置沿第一方向依次排列的第一数据线D1、第二数据线D2、第三数据线D3及第四数据线D4。所述第一数据线D1用于驱动第一子像素310，所述第二数据线D2用于驱动第二子像素320，所述第三数据线D3用于驱动所述第三子像素330，所述第四数据线D4用于驱动第三子像素330。所述第一子像素310包括沿第二方向排列的第一区域311及第二区域312，所述第二子像素320包括沿第二 方向排列的第三区域321及第四区域322，所述第三子像素330包括沿第二方向排列的第五区域331及第六区域332。所述第六区域332内的子像素电极与公共电极的电压差不同于所述第五区域331内的子像素电极与公共电极的电压差。在本实施方式中，所述第一方向为水平方向，所述第二方向为竖直方向。所述第三数据线D3驱动所述第三子像素330的第五区域331，所述第四数据线D4用于驱动所述第三子像素330的第六区域332，所述第三数据线D3上加载的驱动电压与所述第四数据线上加载的驱动电压不同。在本实施方式中，通过分别用第三数据线D3及第四数据线D4驱动第三子像素330的第五区域331及第六区域332，并且第三数据线D3及第四数据线D4上加载的电压不同，以实现所述第六区域332内的子像素电极与公共电极的电压差不同于所述第五区域331内的子像素电极与公共电极的电压差。
所述第一区域311内设置第一薄膜晶体管Q1、所述第二区域312内设置第二薄膜晶体管Q2，所述第三区域321内设置第三薄膜晶体管Q3，所述第四区域322内设置第四薄膜晶体管Q4，所述第五区域331内设置第五薄膜晶体管Q5，所述第六区域332内设置第六薄膜晶体管Q6。所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5及所述第六薄膜晶体管Q6均包括栅极、源极和漏极。所述第一区域311、所述第二区域312、所述第三区域321、所述第四区域322、所述第五区域331及所述第六区域332内分别对应一个子像素电极，为了方便描述，所述第一区域311内对应的子像素电极命名为第一主子像素电极313，所述第二区域312内对应的子像素电极命名为第一次子像素电极314，所述第三区域321内对应的子像素电极命名为第二主子像素电极323，所述第四区域322内对应的子像素电极命名为第二次子像素电极324，所述第五区域331内对应的子像素电极命名为第三主子像素电极333，所述第六区域332内对应的子像素电极命名为第三次子像素电极334。所属领域的一般技术人员应当理解，上述各个区域内对应的子像素电极的命名只是为了区分不同区域内的子像素，以方便描述之用，实际上并不存在主次之分。
所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5及所述第六薄膜晶体 管Q6的栅极连接同一条扫描线GL。所述第一薄膜晶体管Q1和所述第二薄膜晶体管Q2的漏极连接所述第一数据线D1，所述第一薄膜晶体管Q1的源极依次连接第一主子像素电极313、第一电容C1至公共电极Cm(在图6中用三角符号△表示)，所述第二薄膜晶体管Q2的源极依次连接第一次子像素电极314、第二电容C2至公共电极Cm。所述第三薄膜晶体管Q3及所述第四薄膜晶体管Q4的漏极连接所述第二数据线D2，所述第三薄膜晶体管Q3的源极依次连接第二主子像素电极323、第三电容C3至公共电极Cm，所述第四薄膜晶体管Q4的源极依次连接第二次子像素电极324、第四电容C4至公共电极Cm。所述第五薄膜晶体管Q5的漏极连接所述第三数据线D3，所述第五薄膜晶体管Q5的源极依次连接第三主子像素电极333、第五电容C5至公共电极Cm。所述第六薄膜晶体管Q6的漏极连接所述第四数据线D4，所述第六薄膜晶体管Q6的元件依次连接第三次子像素电极334、第六电容至公共电极Cm。
在本实施方式中，通过分别用第三数据线D3及第四数据线D4驱动第三子像素330的第五区域331及第六区域332，并且第三数据线D3及第四数据线D4上加载的电压不同，以实现所述第六区域332内的子像素电极与公共电极的电压差不同于所述第五区域331内的子像素电极与公共电极的电压差。换句话说，加载在所述第三主子像素电极333上的电压不同于加载在所述第三次子像素电极334的电压，从而能够改善所述薄膜晶体管阵列基板30驱动液晶层时的色偏。另一方面，在本实施方式中，在一个像素300的三个子像素中仅仅有一个第三子像素330中的第六区域332对应的第三次子像素电极334上加载的电压不同于所述第五区域331对应的第三主子像素电极333上加载的电压，相较于现有技术能够减小液晶层中的液晶分子不能完全转动的缺陷，从而将光线穿过液晶层时的损失降低。因此，相较于现有技术，本实施方式中的薄膜晶体管阵列基板30在驱动液晶层时能够改善大视角色偏且能够增大光线穿过液晶层时的光线穿透率。
在本实施方式中，所述第一子像素310为红色子像素，第二子像素320为绿色子像素，所述第三子像素330为蓝色子像素。
请参阅图7和图8，图7为本发明第四较佳实施方式的薄膜晶体管阵列基板的示意图；图8是本发明第三较佳实施方式中的薄膜晶体管阵列基板中像素 的结构示意图。所述薄膜晶体管阵列基板30上设置呈阵列分布的多个像素400，每个像素400包括沿第一方向排列的第一子像素410、第二子像素420及第三子像素430，所述第一子像素410、所述第二子像素420及所述第三子像素430连接至同一条扫描线GL。所述薄膜晶体管阵列基板40上还设置沿第一方向依次排列的第一数据线D1、第二数据线D2、第三数据线D3、第四数据线D4及第五数据线D5。所述第一数据线D1用于驱动第一子像素410，所述第二数据线D2用于驱动第二子像素420，所述第三数据线D3用于驱动所述第三子像素430，所述第四数据线D4用于驱动第三子像素430，所述第五数据线D5用于驱动第二子像素420。所述第一子像素410包括沿第二方向排列的第一区域411及第二区域412，所述第二子像素420包括沿第二方向排列的第三区域421及第四区域422，所述第三子像素430包括沿第二方向排列的第五区域431及第六区域432。所述第六区域432内的子像素电极与公共电极的电压差不同于所述第五区域431内的子像素电极与公共电极的电压差。在本实施方式中，所述第一方向为水平方向，所述第二方向为竖直方向。所述第三数据线D3驱动所述第三子像素430的第五区域431，所述第四数据线D4用于驱动所述第三子像素430的第六区域432，所述第三数据线D3上加载的驱动电压与所述第四数据线D4上加载的驱动电压不同。所述第二数据线D2用于驱动所述第二子像素420的第三区域421，所述第五数据线D5用于驱动所述第二子像素420的第四区域422，所述第二数据线D2上加载的驱动电压与所述第五数据线D5上加载的驱动电压不同。在本实施方式中，通过第三数据线D3上加载的驱动电压与所述第四数据线D4上加载的驱动电压不同以实现所述第五区域331中的子像素电极上加载的电压不同于所述第六区域332中的子像素电极上加载的电压。通过所属第二数据线D2上加载的驱动电压与所述第五数据线D5上加载的驱动电压不同以实现所述第三区域321中的子像素电极上加载的电压不同于所述第四区域322中的子像素电极上加载的电压。
所述第一区域411内设置第一薄膜晶体管Q1、所述第二区域412内设置第二薄膜晶体管Q2，所述第三区域421内设置第三薄膜晶体管Q3，所述第四区域422内设置第四薄膜晶体管Q4，所述第五区域431内设置第五薄膜晶体管Q5，所述第六区域432内设置第六薄膜晶体管Q6。所述第一薄膜晶体管 Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5及所述第六薄膜晶体管Q6均包括栅极、源极和漏极。所述第一区域411、所述第二区域412、所述第三区域421、所述第四区域422、所述第五区域431及所述第六区域432内分别对应一个子像素电极，为了方便描述，所述第一区域411内对应的子像素电极命名为第一主子像素电极413，所述第二区域412内对应的子像素电极命名为第一次子像素电极414，所述第三区域421内对应的子像素电极命名为第二主子像素电极423，所述第四区域422内对应的子像素电极命名为第二次子像素电极424，所述第五区域431内对应的子像素电极命名为第三主子像素电极433，所述第六区域432内对应的子像素电极命名为第三次子像素电极434。所属领域的一般技术人员应当理解，上述各个区域内对应的子像素电极的命名只是为了区分不同区域内的子像素，以方便描述之用，实际上并不存在主次之分。
所述第一薄膜晶体管Q1、所述第二薄膜晶体管Q2、所述第三薄膜晶体管Q3、所述第四薄膜晶体管Q4、所述第五薄膜晶体管Q5及所述第六薄膜晶体管Q6的栅极连接同一条扫描线GL。所述第一薄膜晶体管Q1和所述第二薄膜晶体管Q2的漏极连接所述第一数据线D1，所述第一薄膜晶体管Q1的源极依次连接第一主子像素电极413、第一电容C1至公共电极Cm(在图8中用三角符号△表示)，所述第二薄膜晶体管Q2的源极依次连接第一次子像素电极414、第二电容C2至公共电极Cm。所述第三薄膜晶体管Q3的漏极连接所述二数据线D2，所述第三薄膜晶体管Q3的源极依次连接第二主子像素电极423、第三电容C3至公共电极Cm，所述第四薄膜晶体管Q4的漏极连接所述第五数据线D5，所述第四薄膜晶体管Q4的源极依次连接第二次子像素电极424、第四电容C4至公共电极Cm。所述第五薄膜晶体管Q5的漏极连接所述第三数据线D3，所述第五薄膜晶体管Q5的源极依次连接第三主子像素电极433、第五电容C5至公共电极Cm。所述第六薄膜晶体管Q6的漏极连接所述第四数据线D4，所述第六薄膜晶体管Q6的元件依次连接第三次子像素电极434、第六电容至公共电极Cm。
在本实施方式中，通过分别用第三数据线D3及第四数据线D4驱动第三子像素430的第五区域431及第六区域432，并且第三数据线D3及第四数据 线D4上加载的电压不同，以实现所述第六区域432内的子像素电极与公共电极的电压差不同于所述第五区域431内的子像素电极与公共电极的电压差。换句话说，加载在所述第三主子像素电极433上的电压不同于加载在所述第三次子像素电极434的电压，从而能够改善所述薄膜晶体管阵列基板40驱动液晶层时的色偏。同样地，通过用第二数据线D2及第五数据线D5驱动第二像素420的第三区域421和第四区域422，并且所述第二数据线D2与所述第五数据线D5上加载的电压不同，以实现第三区域421内的子像素电极与公共电极的电压差不同于第四区域422内的子像素电极与公共电极的电压差。相较于现有技术能够减小液晶层中的液晶分子不能完全转动的缺陷，从而将光线穿过液晶层时的损失降低。因此，相较于现有技术，本实施方式中的薄膜晶体管阵列基板30在驱动液晶层时能够改善大视角色偏且能够增大光线穿过液晶层时的光线穿透率。
在本实施方式中，所述第一子像素410为红色子像素，第二子像素420为绿色子像素，所述第三子像素430为蓝色子像素。
本发明还提供了一种显示面板，在所述显示面板的各个较佳的实施方式中，所述显示面板分别包括前述图1至图8中的任意一种薄膜晶体管阵列基板，在此不再赘述。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板上设置呈阵列分布的多个像素，每个像素包括沿第一方向依次排列的第一子像素、第二子像素及第三子像素，所述第一子像素、所述第二子像素及所述第三子像素连接至同一条扫描线，所述薄膜晶体管阵列基板上还设置沿第一方向依次排列的第一数据线、第二数据线及第三数据线，所述第一数据线用于驱动所述第一子像素，所述第二数据线用于驱动所述第二子像素，所述第三数据线用于驱动所述第三子像素，所述第一子像素包括沿第二方向排列的第一区域及第二区域，所述第二子像素包括沿第二方向排列的第三区域及第四区域，所述第三子像素包括沿第二方向排列的第五区域及第六区域，所述第六区域内的子像素电极与公共电极的电压差不同于所述第五区域内的子像素电极与公共电极的电压差。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管，所述第三区域内设置第三薄膜晶体管，所述第四区域内设置第四薄膜晶体管，所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管和第七薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管及所述第七薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接第一次子像素电极、第二电容至公共电极，所述第三薄膜晶体管及所述第四薄膜晶体管的漏极连接所述第二数据线，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第五薄膜晶体管及所述第六薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极，所述第七薄膜晶体管的漏极连接所述第三次子像 素电极，所述第七薄膜晶体管的源极连接所述公共电极。
  3. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述第四区域内的子像素电极与公共电极的电压差不同于所述第三区域内的子像素电极与公共电极的电压差。
  4. 如权利要求3所述的薄膜晶体管阵列基板，其中，所述第四区域内设置第八薄膜晶体管，所述第八薄膜晶体管的栅极连接所述扫描线，所述第八薄膜晶体管的漏极连接所述第二次子像素电极，所述第八薄膜晶体管的源极连接所述公共电极。
  5. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板上还设置的第四数据线，所述第三数据线驱动所述第三子像素的第五区域，所述第四数据线驱动所述第三子像素的第六区域，所述第三数据线上加载的驱动电压与所述第四数据线上加载的驱动电压不同。
  6. 如权利要求5所述的薄膜晶体管阵列基板，其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管、所述第三区域内设置第四薄膜晶体管、所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接所述第一次像素电极、第二电容至公共电极，所述第三薄膜晶体管及所述第四薄膜晶体管的漏极连接所述第二数据线，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第五薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电 极，所述第六薄膜晶体管的漏极连接所述第四数据线，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极。
  7. 如权利要求5所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板上还设置第五数据线，所述第二数据线驱动所述第二子像素的第三区域，所述第五数据线驱动所述第二子像素的第四区域，所述第二数据线上加载的驱动电压与所述第五数据线上加载的驱动电压不同。
  8. 如权利要求7所述的薄膜晶体管阵列基板，其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管，所述第三区域内设置第三薄膜晶体管，所述第四区域内设置第四薄膜晶体管，所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接所述第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接所述第一次子像素电极、第二电容至公共电极，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第三薄膜晶体管的漏极连接所述第二数据线，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第四薄膜晶体管的漏极连接所述第五数据线，所述第五薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的漏极连接所述第四数据线，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极。
  9. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述第一子像素为红色子像素，第二子像素为绿色子像素，所述第三子像素为蓝色子像素。
  10. 一种显示面板，其中，所述显示面板包括薄膜晶体管阵列基板，所述 薄膜晶体管阵列基板上设置呈阵列分布的多个像素，每个像素包括沿第一方向依次排列的第一子像素、第二子像素及第三子像素，所述第一子像素、所述第二子像素及所述第三子像素连接至同一条扫描线，所述薄膜晶体管阵列基板上还设置沿第一方向依次排列的第一数据线、第二数据线及第三数据线，所述第一数据线用于驱动所述第一子像素，所述第二数据线用于驱动所述第二子像素，所述第三数据线用于驱动所述第三子像素，所述第一子像素包括沿第二方向排列的第一区域及第二区域，所述第二子像素包括沿第二方向排列的第三区域及第四区域，所述第三子像素包括沿第二方向排列的第五区域及第六区域，所述第六区域内的子像素电极与公共电极的电压差不同于所述第五区域内的子像素电极与公共电极的电压差。
  11. 如权利要求10所述的显示面板，其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管，所述第三区域内设置第三薄膜晶体管，所述第四区域内设置第四薄膜晶体管，所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管和第七薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管及所述第七薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接第一次子像素电极、第二电容至公共电极，所述第三薄膜晶体管及所述第四薄膜晶体管的漏极连接所述第二数据线，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第五薄膜晶体管及所述第六薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极，所述第七薄膜晶体管的漏极连接所述第三次子像素电极，所述第七薄膜晶体管的源极连接所述公共电极。
  12. 如权利要求10所述的显示面板，其中，所述第四区域内的子像素电极与公共电极的电压差不同于所述第三区域内的子像素电极与公共电极的电压差。
  13. 如权利要求12所述的显示面板，其中，所述第四区域内设置第八薄膜晶体管，所述第八薄膜晶体管的栅极连接所述扫描线，所述第八薄膜晶体管的漏极连接所述第二次子像素电极，所述第八薄膜晶体管的源极连接所述公共电极。
  14. 如权利要求10所述的显示面板，其中，所述薄膜晶体管阵列基板上还设置的第四数据线，所述第三数据线驱动所述第三子像素的第五区域，所述第四数据线驱动所述第三子像素的第六区域，所述第三数据线上加载的驱动电压与所述第四数据线上加载的驱动电压不同。
  15. 如权利要求14所述的显示面板，其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管、所述第三区域内设置第四薄膜晶体管、所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接所述第一次像素电极、第二电容至公共电极，所述第三薄膜晶体管及所述第四薄膜晶体管的漏极连接所述第二数据线，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第五薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的漏极连接所述第四数据线，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极。
  16. 如权利要求14所述的显示面板，其中，所述薄膜晶体管阵列基板上还设置第五数据线，所述第二数据线驱动所述第二子像素的第三区域，所述第五数据线驱动所述第二子像素的第四区域，所述第二数据线上加载的驱动电压与所述第五数据线上加载的驱动电压不同。
  17. 如权利要求16所述的显示面板，其中，所述第一区域内设置第一薄膜晶体管，所述第二区域内设置第二薄膜晶体管，所述第三区域内设置第三薄膜晶体管，所述第四区域内设置第四薄膜晶体管，所述第五区域内设置第五薄膜晶体管，所述第六区域内设置第六薄膜晶体管，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管及所述第二薄膜晶体管的漏极连接所述第一数据线，所述第一薄膜晶体管的源极依次连接所述第一主子像素电极、第一电容至公共电极，所述第二薄膜晶体管的源极依次连接所述第一次子像素电极、第二电容至公共电极，所述第三薄膜晶体管的源极依次连接第二主子像素电极、第三电容至公共电极，所述第三薄膜晶体管的漏极连接所述第二数据线，所述第四薄膜晶体管的源极依次连接第二次子像素电极、第四电容至公共电极，所述第四薄膜晶体管的漏极连接所述第五数据线，所述第五薄膜晶体管的漏极连接所述第三数据线，所述第五薄膜晶体管的源极依次连接第三主子像素电极、第五电容至公共电极，所述第六薄膜晶体管的漏极连接所述第四数据线，所述第六薄膜晶体管的源极依次连接第三次子像素电极、第六电容至公共电极。
  18. 如权利要求10所述的显示面板，其中，所述第一子像素为红色子像素，第二子像素为绿色子像素，所述第三子像素为蓝色子像素。
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