WO2016090657A1 - 液晶显示器及其阵列基板 - Google Patents

液晶显示器及其阵列基板 Download PDF

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Publication number
WO2016090657A1
WO2016090657A1 PCT/CN2014/094063 CN2014094063W WO2016090657A1 WO 2016090657 A1 WO2016090657 A1 WO 2016090657A1 CN 2014094063 W CN2014094063 W CN 2014094063W WO 2016090657 A1 WO2016090657 A1 WO 2016090657A1
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Prior art keywords
pixel electrode
thin film
film transistor
data line
electrically connected
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PCT/CN2014/094063
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English (en)
French (fr)
Inventor
王勐
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深圳市华星光电技术有限公司
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Priority to DE112014007149.8T priority Critical patent/DE112014007149T5/de
Priority to US14/426,108 priority patent/US9563084B2/en
Priority to RU2017124184A priority patent/RU2656280C1/ru
Priority to KR1020177013745A priority patent/KR20170072303A/ko
Priority to JP2017530163A priority patent/JP6518327B2/ja
Priority to GB1705886.8A priority patent/GB2545851B/en
Publication of WO2016090657A1 publication Critical patent/WO2016090657A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a liquid crystal display and an array substrate thereof.
  • a data line is electrically connected to its adjacent pixel electrode through a thin film transistor, and a gray scale voltage is supplied thereto. Since the thin film transistor occupies a large space in the extending direction of the data line, in order to ensure the pixel aperture ratio, the two pixel open areas between the adjacent two data lines cannot be arranged in parallel along the extending direction of the scan line. .
  • this arrangement reduces the commonality of the RGB mask, increases the manufacturing cost of the pixel electrode, and the pixel opening area easily interferes optically with the optical film of the liquid crystal display, thereby reducing the display quality of the liquid crystal display. If the two pixel open areas are kept in parallel along the extending direction of the scanning line, the area of the opening area must be reduced, which lowers the pixel aperture ratio.
  • Embodiments of the present invention provide a liquid crystal display and an array substrate thereof, which can ensure display quality of a liquid crystal display and improve pixel aperture ratio.
  • a technical solution adopted by the present invention is to provide an array substrate, including: a first data line and a second data line, wherein the first data line and the second data line extend in a first direction and are perpendicular to the first direction
  • the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line, and are spaced apart along the second direction, the first pixel electrode Adjacent to the first data line, the second pixel electrode is disposed adjacent to the second data line, the first data line provides a gray scale voltage for the second pixel electrode, and the second data line provides a gray scale voltage for the first pixel electrode; a first thin film transistor and a second thin film transistor disposed between the first data line and the second data line, wherein the first data line is electrically connected to the source of the first thin film transistor, and the second pixel electrode and the drain of the first thin film transistor a first electrical connection is electrically connected to a source of the second thin film transistor, the first pixel electrode is electrically connected to a drain of the second
  • the first opening area and the second opening area are respectively disposed on the first pixel electrode and the second pixel electrode, and the first opening area and the second opening area are arranged flush in the second direction.
  • Another technical solution adopted by the present invention is to provide an array substrate, including: a first data line and a second data line, the first data line and the second data line extending in a first direction and perpendicular to the first direction
  • the second pixel is disposed at intervals; the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line, and are spaced apart along the second direction, the first pixel
  • the electrode is disposed adjacent to the first data line, the second pixel electrode is disposed adjacent to the second data line, the first data line provides a gray scale voltage for the second pixel electrode, and the second data line provides a gray scale voltage for the first pixel electrode .
  • the array substrate includes a first thin film transistor and a second thin film transistor disposed between the first data line and the second data line, and the first data line is electrically connected to one of a source and a drain of the first thin film transistor.
  • the second pixel electrode is electrically connected to the other of the source and the drain of the first thin film transistor, and the second data line is electrically connected to one of the source and the drain of the second thin film transistor, the first pixel electrode The other of the source and the drain of the second thin film transistor is electrically connected.
  • the first thin film transistor and the second thin film transistor are disposed on opposite sides of the first pixel electrode and the second pixel electrode at intervals in the first direction.
  • the first pixel electrode and the second pixel electrode are arranged flush in the second direction.
  • the first opening area and the second opening area are respectively disposed on the first pixel electrode and the second pixel electrode, and the first opening area and the second opening area are arranged flush in the second direction.
  • the array substrate further includes a first scan line and a second scan line.
  • the first scan line and the second scan line extend along the second direction and are disposed at intervals in the first direction.
  • the first pixel electrode, the second pixel electrode, and the first film The transistor and the second thin film transistor are further located between the first scan line and the second scan line, the first scan line is disposed adjacent to the first thin film transistor, and is electrically connected to the gate of the first thin film transistor, and the second scan line is The second thin film transistor is disposed adjacent to each other and is electrically connected to a gate of the second thin film transistor.
  • first via hole and the second via hole are further disposed on the array substrate, and the second pixel electrode is electrically connected to the other of the source and the drain of the first thin film transistor via the first via hole, and the first pixel is electrically connected
  • the pole is electrically connected to the other of the source and the drain of the second thin film transistor via the second via.
  • the first via and the first thin film transistor are spaced apart in the second direction, and the second via and the second thin film transistor are spaced apart in the second direction.
  • the first via and the first thin film transistor are disposed on the same straight line in the second direction, and the second via and the second thin film transistor are disposed on the same straight line in the second direction.
  • a technical solution adopted by the present invention is to provide a liquid crystal display including an array panel, the array substrate comprising: a first data line and a second data line, the first data line and the second data line edge a first direction extending and spaced apart along a second direction perpendicular to the first direction; a first pixel electrode and a second pixel electrode, the first pixel electrode and the second pixel electrode being disposed between the first data line and the second data line And spaced apart along the second direction, the first pixel electrode is disposed adjacent to the first data line, the second pixel electrode is disposed adjacent to the second data line, and the first data line provides a grayscale voltage for the second pixel electrode, The two data lines provide a gray scale voltage to the first pixel electrode.
  • the array substrate includes a first thin film transistor and a second thin film transistor disposed between the first data line and the second data line, and the first data line is electrically connected to one of a source and a drain of the first thin film transistor.
  • the second pixel electrode is electrically connected to the other of the source and the drain of the first thin film transistor, and the second data line is electrically connected to one of the source and the drain of the second thin film transistor, the first pixel electrode The other of the source and the drain of the second thin film transistor is electrically connected.
  • the first thin film transistor and the second thin film transistor are disposed on opposite sides of the first pixel electrode and the second pixel electrode at intervals in the first direction.
  • the first pixel electrode and the second pixel electrode are arranged flush in the second direction.
  • the first opening area and the second opening area are respectively disposed on the first pixel electrode and the second pixel electrode, and the first opening area and the second opening area are arranged flush in the second direction.
  • the array substrate further includes a first scan line and a second scan line.
  • the first scan line and the second scan line extend along the second direction and are disposed at intervals in the first direction.
  • the first pixel electrode, the second pixel electrode, and the first film The transistor and the second thin film transistor are further located between the first scan line and the second scan line, the first scan line is disposed adjacent to the first thin film transistor, and is electrically connected to the gate of the first thin film transistor, and the second scan line is The second thin film transistor is disposed adjacent to each other and is electrically connected to a gate of the second thin film transistor.
  • first via hole and the second via hole are further disposed on the array substrate, and the second pixel electrode is configured
  • the first via is electrically connected to the other of the source and the drain of the first thin film transistor
  • the first pixel is electrically connected to the other of the source and the drain of the second thin film transistor via the second via .
  • the first via and the first thin film transistor are spaced apart in the second direction, and the second via and the second thin film transistor are spaced apart in the second direction.
  • the first via and the first thin film transistor are disposed on the same straight line in the second direction, and the second via and the second thin film transistor are disposed on the same straight line in the second direction.
  • the embodiment of the present invention has the beneficial effects that the array substrate of the embodiment of the present invention is designed to extend the first data line and the second data line in the first direction and in the second direction perpendicular to the first direction.
  • the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line and are spaced apart along the second direction, the first pixel electrode is disposed adjacent to the first data line, and the second pixel electrode is disposed
  • the second data lines are disposed adjacent to each other, and the second pixel electrode is provided with a gray scale voltage by the first data line, and the second data line provides a gray scale voltage for the first pixel electrode, and increases the component arrangement space along the extending direction of the data line.
  • the elements connected to the pixel electrodes can be horizontally disposed along the extending direction of the scanning lines, and the two pixel opening areas located between the adjacent two data lines can be disposed in parallel along the extending direction of the scanning lines, thereby ensuring the liquid crystal display The display quality and increase the pixel aperture ratio.
  • FIG. 1 is a schematic structural view of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 2 is a partial schematic view showing a pixel structure of the liquid crystal display panel shown in FIG. 1;
  • FIG. 3 is a partial schematic view of an array substrate having the pixel structure of FIG. 2 of the present invention.
  • FIG. 1 is a schematic structural view of a liquid crystal display panel according to a preferred embodiment of the present invention
  • FIG. 2 is a schematic diagram of a pixel structure of the liquid crystal display panel shown in FIG. 1.
  • liquid crystal display The panel 10 includes a first substrate 11 , a second substrate 12 , and a liquid crystal layer 13 .
  • the first substrate 11 and the second substrate 12 are relatively spaced apart.
  • the second substrate 12 can be a CF (Color Filter) color filter substrate.
  • the first substrate 11 may be a TFT (Thin Film Transistor) array substrate.
  • TFT Thin Film Transistor
  • the first substrate 11 includes a transparent substrate, various wirings, pixel electrodes, and the like provided on the transparent substrate.
  • the first substrate 11 includes a plurality of data lines S n-1 , S n , S n+1 , S n+2 , and is perpendicular to the data lines S n-1 , S n , S n+1 , S n . +2 sets a plurality of scan lines G n-1 , G n , G n+1 , G n+2 and a plurality of pixel units P n-1 , P n ,... defined by scan lines and data lines, P x .
  • a plurality of scan lines G n-1 , G n , G n+1 , G n+2 are connected to the gate driver, and a plurality of data lines S n-1 , S n , S n+1 , S n+2 are connected to a source driver, the gate driver provides a scan voltage for the plurality of pixel units P n-1 , P n , . . . , P x through the corresponding connected scan lines, and the source driver is a plurality of pixel units through the corresponding connected data lines P n-1 , P n , ..., P x provide gray scale voltages.
  • any two adjacent data lines and corresponding two adjacent scan lines define two pixel open areas of the same structure, and each pixel open area includes one pixel electrode, which is the first embodiment of the present invention.
  • the two pixel open areas defined by the data line S n-1 , the second data line S n , the first scan line G n-1 , and the second scan line G n are described as an example.
  • a first data line S n-1 and the second data line S n extending along the first direction D 1 and D 2 in the second direction spaced from the first scan line G n-1 and the second along a second scan line G n
  • the direction D 2 extends and the first direction D 1 is spaced apart, and the first direction D 1 is perpendicular to the second direction D 2 .
  • a first thin film transistor T 1 and a second thin film transistor T 2 are further disposed between the first data line S n-1 and the second data line S n , and the first thin film transistor T 1 and the second thin film transistor T 2 are along the first The direction D 1 is spaced apart from the opposite sides of the first pixel electrode P n-1 and the second pixel electrode P n .
  • the first pixel electrode P n-1 and the second pixel electrode P n are flush with each other in the second direction D 2 .
  • the first pixel electrode P n-1 , the second pixel electrode P n , the first thin film transistor T 1 and the second thin film transistor T 2 are further located between the first scan line G n-1 and the second scan line G n the first scan line G n-1 is provided adjacent to the first thin film transistor T 1, and connected electrically to the gate of the first thin film transistor T 1, g 1, the second scanning line G n and the second thin film transistor T 2 with Adjacent to, and electrically connected to the gate g 2 of the second thin film transistor T 2 .
  • a first data line S n-1 and the source of the first transistor T 1 as the thin film electrode is electrically connected to s 1
  • a second pixel electrode connected to the drain of P n d 1 T 1 as a first thin film transistor
  • a second data line S n is electrically connected to the source s 2 of the second thin film transistor T 2
  • the first pixel electrode P n-1 is electrically connected to the drain d 2 of the second thin film transistor T 2 .
  • FIG. 3 is a partial schematic view of an array substrate having the pixel structure of FIG. 2 of the present invention.
  • the first pixel electrode P n-1 and the second pixel electrodes are disposed on the n-region of the first opening 31 and second opening P region 32, a first opening 32 in the second region 31 and the second opening region Direction D 2 is set flush.
  • a first via 33 and a second via 34 are further disposed on the array substrate 11.
  • the first via 33 and the first thin film transistor T 1 are spaced apart in the second direction D 2 , and the second via 34 and the second thin film transistor T 2 is disposed along the second direction D 2 , the second pixel electrode P n is electrically connected to the drain d 1 of the first thin film transistor T 1 via the first via 33, and the first pixel electrode P n-1 passes through the second via 34 is electrically connected to the drain d 2 of the second thin film transistor T 2 .
  • the first data line S n-1 can be electrically connected to the drain of the first thin film transistor T 1 D 1, P n second pixel electrode connected to the source of the first thin film transistor T 1 S 1 electrical second data line S n and the drain of the second thin film transistor T 2 D 2 is electrically connected to the first pixel electrode P n-1 and the second thin film transistor T 2, the source S 2 is electrically connected.
  • the second pixel electrode P n is electrically connected to the source s 1 of the first thin film transistor T 1 via the first via 33, and the first pixel electrode P n-1 passes through the second via 34 and the second thin film transistor T source 2 is electrically connected to electrode S 2.
  • Embodiments of the invention can increase the space elements arranged in the extending direction of the data line, for example, along the element 2 arranged in the second spatial direction D between the first data line S n-1 and the second pixel electrode P n,
  • the first via hole 33 and the first thin film transistor T 1 are disposed on the same straight line in the second direction D 2
  • the second via hole 34 and the second thin film transistor T 2 are disposed on the same straight line in the second direction D 2
  • the first opening area 31 and the second opening area 32 are located on the same straight line, and the pixel aperture ratio can be improved while ensuring the display quality of the liquid crystal display panel 10.
  • the embodiment of the invention further provides a liquid crystal display comprising the liquid crystal display panel 10 of the embodiment of the invention as claimed in FIG. 1 , and of course the array substrate 11 having the pixel structure of the embodiment described in FIG. 2 and FIG. 3 , thus having The same technical effect.

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Abstract

一种液晶显示器及其阵列基板（11）。阵列基板（11）包括：第一数据线（S n-1）和第二数据线（S n），沿第一方向（D 1）延伸且沿垂直于第一方向（D 1）的第二方向（D 2）间隔设置；第一像素电极（P n-1）和第二像素电极（P n），设置于第一数据线（S n-1）和第二数据线（S n）之间，且沿第二方向（D 2）间隔设置，第一像素电极（P n-1）与第一数据线（S n-1）相邻设置，第二像素电极（P n）与第二数据线（S n）相邻设置，第一数据线（S n-1）为第二像素电极（P n）提供灰阶电压，第二数据线（S n）为第一像素电极（P n-1）提供灰阶电压。通过这种方式，能够确保液晶显示器的显示品质，并提高像素开口率。

Description

液晶显示器及其阵列基板 【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及一种液晶显示器及其阵列基板。
【背景技术】
传统的像素结构设计中，数据线通过薄膜晶体管与其相邻的像素电极电连接，并为其提供灰阶电压。由于薄膜晶体管沿数据线的延伸方向上所占的元件排布空间较大，为保证像素开口率，位于相邻两条数据线之间的两个像素开口区无法沿扫描线的延伸方向平行设置。然而这种设置会降低RGB掩膜板的共用性，增加像素电极的制造成本，并且像素开口区容易与液晶显示器的光学膜片发生光学干涉，降低液晶显示器的显示品质。如果保持两个像素开口区沿扫描线的延伸方向平行设置，必须缩小开口区的面积，则会降低像素开口率。
【发明内容】
本发明实施例提供一种液晶显示器及其阵列基板，能够确保液晶显示器的显示品质，并提高像素开口率。
本发明采用的一个技术方案是：提供一种阵列基板，包括：第一数据线和第二数据线，第一数据线和第二数据线沿第一方向延伸且沿垂直于第一方向的第二方向间隔设置；第一像素电极和第二像素电极，第一像素电极和第二像素电极设置于第一数据线和第二数据线之间，且沿第二方向间隔设置，第一像素电极与第一数据线相邻设置，第二像素电极与第二数据线相邻设置，第一数据线为第二像素电极提供灰阶电压，第二数据线为第一像素电极提供灰阶电压；设置于第一数据线和第二数据线之间的第一薄膜晶体管和第二薄膜晶体管，第一数据线与第一薄膜晶体管的源极电连接，第二像素电极与第一薄膜晶体管的漏极电连接，第二数据线与第二薄膜晶体管的源极电连接，第一像素电极与第二薄膜晶体管的漏极电连接；第一过孔和第二过孔，第一过孔和第二过孔与第一薄膜晶体管和第二薄膜晶体 管沿垂直于第一数据线和第二数据线的方向设置于同一直线上，第二像素电极经第一过孔与第一薄膜晶体管的漏极电连接，第一像素电极经第二过孔与第二薄膜晶体管的漏极电连接。
其中，第一像素电极和第二像素电极上分别设置第一开口区和第二开口区，第一开口区和第二开口区沿第二方向平齐设置。
本发明采用的另一个技术方案是：提供一种阵列基板，包括：第一数据线和第二数据线，第一数据线和第二数据线沿第一方向延伸且沿垂直于第一方向的第二方向间隔设置；第一像素电极和第二像素电极，第一像素电极和第二像素电极设置于第一数据线和第二数据线之间，且沿第二方向间隔设置，第一像素电极与第一数据线相邻设置，第二像素电极与第二数据线相邻设置，第一数据线为第二像素电极提供灰阶电压，第二数据线为第一像素电极提供灰阶电压。
其中，阵列基板包括设置于第一数据线和第二数据线之间的第一薄膜晶体管和第二薄膜晶体管，第一数据线与第一薄膜晶体管的源极和漏极中的一者电连接，第二像素电极与第一薄膜晶体管的源极和漏极中的另一者电连接，第二数据线与第二薄膜晶体管的源极和漏极中的一者电连接，第一像素电极与第二薄膜晶体管的源极和漏极中的另一者电连接。
其中，第一薄膜晶体管和第二薄膜晶体管沿第一方向间隔设置于第一像素电极和第二像素电极的相对两侧。
其中，第一像素电极和第二像素电极沿第二方向平齐设置。
其中，第一像素电极和第二像素电极上分别设置第一开口区和第二开口区，第一开口区和第二开口区沿第二方向平齐设置。
其中，阵列基板进一步包括第一扫描线和第二扫描线，第一扫描线和第二扫描线沿第二方向延伸且第一方向间隔设置，第一像素电极、第二像素电极、第一薄膜晶体管和第二薄膜晶体管进一步位于第一扫描线和第二扫描线之间，第一扫描线与第一薄膜晶体管相邻设置，且与第一薄膜晶体管的栅极电连接，第二扫描线与第二薄膜晶体管相邻设置，且与第二薄膜晶体管的栅极电连接。
其中，阵列基板上进一步设置第一过孔和第二过孔，第二像素电极经第一过孔与第一薄膜晶体管的源极和漏极中的另一者电连接，第一像素电 极经第二过孔与第二薄膜晶体管的源极和漏极中的另一者电连接。
其中，第一过孔和第一薄膜晶体管沿第二方向间隔设置，第二过孔和第二薄膜晶体管沿第二方向间隔设置。
其中，第一过孔和第一薄膜晶体管沿第二方向设置于同一直线上，第二过孔和第二薄膜晶体管沿第二方向设置于同一直线上。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示器，包括阵列面板，该阵列基板包括：第一数据线和第二数据线，第一数据线和第二数据线沿第一方向延伸且沿垂直于第一方向的第二方向间隔设置；第一像素电极和第二像素电极，第一像素电极和第二像素电极设置于第一数据线和第二数据线之间，且沿第二方向间隔设置，第一像素电极与第一数据线相邻设置，第二像素电极与第二数据线相邻设置，第一数据线为第二像素电极提供灰阶电压，第二数据线为第一像素电极提供灰阶电压。
其中，阵列基板包括设置于第一数据线和第二数据线之间的第一薄膜晶体管和第二薄膜晶体管，第一数据线与第一薄膜晶体管的源极和漏极中的一者电连接，第二像素电极与第一薄膜晶体管的源极和漏极中的另一者电连接，第二数据线与第二薄膜晶体管的源极和漏极中的一者电连接，第一像素电极与第二薄膜晶体管的源极和漏极中的另一者电连接。
其中，第一薄膜晶体管和第二薄膜晶体管沿第一方向间隔设置于第一像素电极和第二像素电极的相对两侧。
其中，第一像素电极和第二像素电极沿第二方向平齐设置。
其中，第一像素电极和第二像素电极上分别设置第一开口区和第二开口区，第一开口区和第二开口区沿第二方向平齐设置。
其中，阵列基板进一步包括第一扫描线和第二扫描线，第一扫描线和第二扫描线沿第二方向延伸且第一方向间隔设置，第一像素电极、第二像素电极、第一薄膜晶体管和第二薄膜晶体管进一步位于第一扫描线和第二扫描线之间，第一扫描线与第一薄膜晶体管相邻设置，且与第一薄膜晶体管的栅极电连接，第二扫描线与第二薄膜晶体管相邻设置，且与第二薄膜晶体管的栅极电连接。
其中，阵列基板上进一步设置第一过孔和第二过孔，第二像素电极经 第一过孔与第一薄膜晶体管的源极和漏极中的另一者电连接，第一像素电极经第二过孔与第二薄膜晶体管的源极和漏极中的另一者电连接。
其中，第一过孔和第一薄膜晶体管沿第二方向间隔设置，第二过孔和第二薄膜晶体管沿第二方向间隔设置。
其中，第一过孔和第一薄膜晶体管沿第二方向设置于同一直线上，第二过孔和第二薄膜晶体管沿第二方向设置于同一直线上。
通过上述技术方案，本发明实施例产生的有益效果是：本发明实施例的阵列基板，设计第一数据线和第二数据线沿第一方向延伸且沿垂直于第一方向的第二方向间隔设置，第一像素电极和第二像素电极设置于第一数据线和第二数据线之间且沿第二方向间隔设置，第一像素电极与第一数据线相邻设置，第二像素电极与第二数据线相邻设置，通过第一数据线为第二像素电极提供灰阶电压，第二数据线为第一像素电极提供灰阶电压，增加沿数据线的延伸方向上的元件排布空间，使得与像素电极连接的元件沿扫描线的延伸方向能够水平设置，并且使得位于相邻两条数据线之间的两个像素开口区可以沿扫描线的延伸方向平行设置，从而能够确保液晶显示器的显示品质，并提高像素开口率。
【附图说明】
图1是本发明优选实施例的液晶显示面板的结构示意图；
图2是图1所示液晶显示面板的像素结构的局部示意图；
图3是本发明具有图2所示像素结构的阵列基板的局部示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，本发明以下所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
图1是本发明优选实施例的液晶显示面板的结构示意图，图2是图1所示液晶显示面板的像素结构示意图。请结合图1和图2所示，液晶显示 面板10包括第一基板11、第二基板12和液晶层13，第一基板11和第二基板12相对间隔设置，其中第二基板12可以为CF(Color Filter，彩色滤光片)彩膜基板，对应地，第一基板11可以为TFT(Thin Film Transistor，薄膜晶体管)阵列基板。
其中，第一基板11包括透明基体以及设置于该透明基体上的各种配线和像素电极等。具体地，第一基板11包括多条数据线Sn-1，Sn，Sn+1，Sn+2、沿垂直于数据线Sn-1，Sn，Sn+1，Sn+2设置的多条扫描线Gn-1，Gn，Gn+1，Gn+2以及由扫描线和数据线定义的多个像素单元Pn-1，Pn，...，Px。多条扫描线Gn-1，Gn，Gn+1，Gn+2连接于栅极驱动器，多条数据线Sn-1，Sn，Sn+1，Sn+2连接于源极驱动器，栅极驱动器通过对应连接的扫描线为多个像素单元Pn-1，Pn，...，Px提供扫描电压，源极驱动器通过对应连接的数据线为多个像素单元Pn-1，Pn，...，Px提供灰阶电压。
参阅图2所示，任意相邻两条数据线和对应的相邻两条扫描线定义结构相同的两个像素开口区，每一像素开口区包括一个像素电极，本发明实施例下文以第一数据线Sn-1、第二数据线Sn、第一扫描线Gn-1和第二扫描线Gn定义的两个像素开口区为例进行描述。
第一数据线Sn-1和第二数据线Sn沿第一方向D1延伸且沿第二方向D2间隔设置，第一扫描线Gn-1和第二扫描线Gn沿第二方向D2延伸且第一方向D1间隔设置，第一方向D1与第二方向D2相垂直。
第一像素电极Pn-1和第二像素电极Pn设置于第一数据线Sn-1和第二数据线Sn之间，并且两者沿第二方向D2间隔设置，其中第一像素电极Pn-1与第一数据线Sn-1相邻设置，第二像素电极Pn与第二数据线Sn相邻设置，第一数据线Sn-1为第二像素电极Pn提供灰阶电压，第二数据线Sn为第一像素电极Pn-1提供灰阶电压。
第一数据线Sn-1和第二数据线Sn之间还设置有第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1和第二薄膜晶体管T2沿第一方向D1间隔设置于第一像素电极Pn-1和第二像素电极Pn的相对两侧。第一像素电极Pn-1和第二像素电极Pn沿第二方向D2平齐设置。
并且，第一像素电极Pn-1、第二像素电极Pn、第一薄膜晶体管T1和第二薄膜晶体管T2进一步位于第一扫描线Gn-1和第二扫描线Gn之间，第一扫 描线Gn-1与第一薄膜晶体管T1相邻设置，且与第一薄膜晶体管T1的栅极g1电连接，第二扫描线Gn与第二薄膜晶体管T2相邻设置，且与第二薄膜晶体管T2的栅极g2电连接。
另外，第一数据线Sn-1与第一薄膜晶体管T1的源极s1电连接，第二像素电极Pn与第一薄膜晶体管T1的漏极d1电连接，第二数据线Sn与第二薄膜晶体管T2的源极s2电连接，第一像素电极Pn-1与第二薄膜晶体管T2的漏极d2电连接。
图3是本发明具有图2所示像素结构的阵列基板的局部示意图。结合图3所示，第一像素电极Pn-1和第二像素电极Pn上分别设置第一开口区31和第二开口区32，第一开口区31和第二开口区32沿第二方向D2平齐设置。阵列基板11上进一步设置第一过孔33和第二过孔34，第一过孔33和第一薄膜晶体管T1沿第二方向D2间隔设置，第二过孔34和第二薄膜晶体管T2沿第二方向D2间隔设置，第二像素电极Pn经第一过孔33与第一薄膜晶体管T1的漏极d1电连接，第一像素电极Pn-1经第二过孔34与第二薄膜晶体管T2的漏极d2电连接。
在其它实施例中，第一数据线Sn-1可以与第一薄膜晶体管T1的漏极d1电连接，第二像素电极Pn与第一薄膜晶体管T1的源极s1电连接，第二数据线Sn与第二薄膜晶体管T2的漏极d2电连接，第一像素电极Pn-1与第二薄膜晶体管T2的源极s2电连接。此时，第二像素电极Pn经第一过孔33与第一薄膜晶体管T1的源极s1电连接，第一像素电极Pn-1经第二过孔34与第二薄膜晶体管T2的源极s2电连接。
本发明实施例能够增加沿数据线的延伸方向上的元件排布空间，例如第一数据线Sn-1与第二像素电极Pn之间沿第二方向D2上的元件排布空间，使得第一过孔33和第一薄膜晶体管T1沿第二方向D2设置于同一直线上，第二过孔34和第二薄膜晶体管T2沿第二方向D2设置于同一直线上，并且第一开口区31和第二开口区32位于同一直线上，在确保液晶显示面板10的显示品质的同时，可提高像素开口率。
本发明实施例还提供一种液晶显示器，包括权利要求图1所述实施例的液晶显示面板10，当然也包括具有图2和图3所述实施例的像素结构的阵列基板11，因此具有与其相同的技术效果。
再次说明，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    第一数据线和第二数据线，所述第一数据线和第二数据线沿第一方向延伸且沿垂直于所述第一方向的第二方向间隔设置；
    第一像素电极和第二像素电极，所述第一像素电极和所述第二像素电极设置于所述第一数据线和第二数据线之间，且沿所述第二方向间隔设置，其中所述第一像素电极与所述第一数据线相邻设置，所述第二像素电极与所述第二数据线相邻设置，所述第一数据线为所述第二像素电极提供灰阶电压，所述第二数据线为所述第一像素电极提供灰阶电压；
    设置于所述第一数据线和第二数据线之间的第一薄膜晶体管和第二薄膜晶体管，所述第一数据线与所述第一薄膜晶体管的源极电连接，所述第二像素电极与所述第一薄膜晶体管的漏极电连接，所述第二数据线与所述第二薄膜晶体管的源极电连接，所述第一像素电极与所述第二薄膜晶体管的漏极电连接；
    第一过孔和第二过孔，所述第一过孔和所述第二过孔与所述第一薄膜晶体管和所述第二薄膜晶体管沿垂直于所述第一数据线和所述第二数据线的方向设置于同一直线上，所述第二像素电极经所述第一过孔与所述第一薄膜晶体管的漏极电连接，所述第一像素电极经所述第二过孔与所述第二薄膜晶体管的漏极电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一像素电极和所述第二像素电极上分别设置第一开口区和第二开口区，所述第一开口区和所述第二开口区沿所述第二方向平齐设置。
  3. 一种阵列基板，其中，所述阵列基板包括：
    第一数据线和第二数据线，所述第一数据线和第二数据线沿第一方向延伸且沿垂直于所述第一方向的第二方向间隔设置；
    第一像素电极和第二像素电极，所述第一像素电极和第二像素电极设置于所述第一数据线和第二数据线之间，且沿所述第二方向间隔设置，其中所述第一像素电极与所述第一数据线相邻设置，所述第二像素电极与所述第二数据线相邻设置，所述第一数据线为所述第二像素电极提供灰阶电 压，所述第二数据线为所述第一像素电极提供灰阶电压。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板包括设置于所述第一数据线和第二数据线之间的第一薄膜晶体管和第二薄膜晶体管，其中所述第一数据线与所述第一薄膜晶体管的源极和漏极中的一者电连接，所述第二像素电极与所述第一薄膜晶体管的源极和漏极中的另一者电连接，所述第二数据线与所述第二薄膜晶体管的源极和漏极中的一者电连接，所述第一像素电极与所述第二薄膜晶体管的源极和漏极中的另一者电连接。
  5. 根据权利要求4所述的阵列基板，其中，所述第一薄膜晶体管和第二薄膜晶体管沿所述第一方向间隔设置于所述第一像素电极和所述第二像素电极的相对两侧。
  6. 根据权利要求5所述的阵列基板，其中，所述第一像素电极和所述第二像素电极沿所述第二方向平齐设置。
  7. 根据权利要求6所述的阵列基板，其中，所述第一像素电极和所述第二像素电极上分别设置第一开口区和第二开口区，所述第一开口区和所述第二开口区沿所述第二方向平齐设置。
  8. 根据权利要求5所述的阵列基板，其中，所述阵列基板进一步包括第一扫描线和第二扫描线，所述第一扫描线和所述第二扫描线沿所述第二方向延伸且所述第一方向间隔设置，其中所述第一像素电极、所述第二像素电极、所述第一薄膜晶体管和所述第二薄膜晶体管进一步位于所述第一扫描线和所述第二扫描线之间，其中所述第一扫描线与所述第一薄膜晶体管相邻设置，且与所述第一薄膜晶体管的栅极电连接，其中所述第二扫描线与所述第二薄膜晶体管相邻设置，且与所述第二薄膜晶体管的栅极电连接。
  9. 根据权利要求4-8任意一项所述的阵列基板，其中，所述阵列基板上进一步设置第一过孔和第二过孔，所述第二像素电极经所述第一过孔与所述第一薄膜晶体管的源极和漏极中的另一者电连接，所述第一像素电极经所述第二过孔与所述第二薄膜晶体管的源极和漏极中的另一者电连接。
  10. 根据权利要求9所述的阵列基板，其中，所述第一过孔和所述第一薄膜晶体管沿所述第二方向间隔设置，所述第二过孔和所述第二薄膜晶体管沿所述第二方向间隔设置。
  11. 根据权利要求10所述的阵列基板，其中，所述第一过孔和所述第一薄膜晶体管沿所述第二方向设置于同一直线上，所述第二过孔和所述第二薄膜晶体管沿所述第二方向设置于同一直线上。
  12. 一种液晶显示器，其中，所述液晶显示器包括阵列基板，所述阵列基板包括：
    第一数据线和第二数据线，所述第一数据线和第二数据线沿第一方向延伸且沿垂直于所述第一方向的第二方向间隔设置；
    第一像素电极和第二像素电极，所述第一像素电极和第二像素电极设置于所述第一数据线和第二数据线之间，且沿所述第二方向间隔设置，其中所述第一像素电极与所述第一数据线相邻设置，所述第二像素电极与所述第二数据线相邻设置，所述第一数据线为所述第二像素电极提供灰阶电压，所述第二数据线为所述第一像素电极提供灰阶电压。
  13. 根据权利要求12所述的液晶显示器，其中，所述阵列基板包括设置于所述第一数据线和第二数据线之间的第一薄膜晶体管和第二薄膜晶体管，其中所述第一数据线与所述第一薄膜晶体管的源极和漏极中的一者电连接，所述第二像素电极与所述第一薄膜晶体管的源极和漏极中的另一者电连接，所述第二数据线与所述第二薄膜晶体管的源极和漏极中的一者电连接，所述第一像素电极与所述第二薄膜晶体管的源极和漏极中的另一者电连接。
  14. 根据权利要求13所述的液晶显示器，其中，所述第一薄膜晶体管和第二薄膜晶体管沿所述第一方向间隔设置于所述第一像素电极和所述第二像素电极的相对两侧。
  15. 根据权利要求14所述的液晶显示器，其中，所述第一像素电极和所述第二像素电极沿所述第二方向平齐设置。
  16. 根据权利要求15所述的液晶显示器，其中，所述第一像素电极和所述第二像素电极上分别设置第一开口区和第二开口区，所述第一开口区和所述第二开口区沿所述第二方向平齐设置。
  17. 根据权利要求16所述的液晶显示器，其中，所述阵列基板进一步包括第一扫描线和第二扫描线，所述第一扫描线和所述第二扫描线沿所述第二方向延伸且所述第一方向间隔设置，其中所述第一像素电极、所述第 二像素电极、所述第一薄膜晶体管和所述第二薄膜晶体管进一步位于所述第一扫描线和所述第二扫描线之间，其中所述第一扫描线与所述第一薄膜晶体管相邻设置，且与所述第一薄膜晶体管的栅极电连接，其中所述第二扫描线与所述第二薄膜晶体管相邻设置，且与所述第二薄膜晶体管的栅极电连接。
  18. 根据权利要求13-17任意一项所述的液晶显示器，其中，所述阵列基板上进一步设置第一过孔和第二过孔，所述第二像素电极经所述第一过孔与所述第一薄膜晶体管的源极和漏极中的另一者电连接，所述第一像素电极经所述第二过孔与所述第二薄膜晶体管的源极和漏极中的另一者电连接。
  19. 根据权利要求18所述的液晶显示器，其中，所述第一过孔和所述第一薄膜晶体管沿所述第二方向间隔设置，所述第二过孔和所述第二薄膜晶体管沿所述第二方向间隔设置。
  20. 根据权利要求19所述的液晶显示器，其中，所述第一过孔和所述第一薄膜晶体管沿所述第二方向设置于同一直线上，所述第二过孔和所述第二薄膜晶体管沿所述第二方向设置于同一直线上。
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