WO2020015175A1 - 像素驱动电路及液晶显示装置 - Google Patents

像素驱动电路及液晶显示装置 Download PDF

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Publication number
WO2020015175A1
WO2020015175A1 PCT/CN2018/107774 CN2018107774W WO2020015175A1 WO 2020015175 A1 WO2020015175 A1 WO 2020015175A1 CN 2018107774 W CN2018107774 W CN 2018107774W WO 2020015175 A1 WO2020015175 A1 WO 2020015175A1
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Prior art keywords
liquid crystal
thin film
film transistor
terminal
electrically connected
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PCT/CN2018/107774
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English (en)
French (fr)
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刘司洋
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深圳市华星光电技术有限公司
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Priority to US16/319,311 priority Critical patent/US10971094B1/en
Publication of WO2020015175A1 publication Critical patent/WO2020015175A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present invention relates to the field of display technology, and in particular, to a pixel driving circuit and a liquid crystal display device.
  • Liquid crystal display (Liquid Crystal Display, LCD) has many advantages such as thin body, power saving, no radiation, etc., and has been widely used, such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or Laptop screens, etc., dominate the field of flat panel displays.
  • LCD Liquid Crystal Display
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of a liquid crystal display panel is to fill liquid crystal molecules between a thin film transistor substrate (TFT, Array, Substrate, TFT, Array, Substrate) and a color filter substrate (Color Filter, CF), and apply a driving voltage to the two substrates.
  • TFT, Array, Substrate, TFT, Array, Substrate a color filter substrate
  • the rotation direction of the liquid crystal molecules is controlled to refract the light of the backlight module to generate a picture.
  • FIG. 1 is a schematic structural diagram of a conventional pixel driving circuit.
  • the pixel driving circuit includes a plurality of sub-pixels 100 arranged in an array, and a plurality of data lines 200 (d (1 ), D (2) ... d (m) ...), multi-line scan lines 300 (g (1), g (2) ...
  • Each sub-pixel 100 includes a first thin film transistor T10, a first liquid crystal capacitor C11, a first storage capacitor C21, a second thin film transistor T20, a third thin film transistor T30, a second liquid crystal capacitor C12, and a second storage capacitor C22.
  • a thin film transistor T10, a first liquid crystal capacitor C11, and a first storage capacitor C21 constitute a main region 110
  • a second thin film transistor T20, a third thin film transistor T30, a second liquid crystal capacitor C12, and a second storage capacitor C22 constitute a sub region 120
  • the gate of the first thin film transistor T10 is electrically connected to the corresponding scan line 300
  • the source is electrically connected to the corresponding data line 200
  • the drain is electrically connected to the first end of the first liquid crystal capacitor C11
  • the second terminal of the capacitor C11 is grounded
  • the first terminal of the first storage capacitor C21 is electrically connected to the first terminal of the first liquid crystal capacitor C10
  • the other terminal is electrically connected to the common voltage line 400 of the array substrate.
  • the gate of the second thin film transistor T20 is electrically connected to the corresponding scan line 300, the source is electrically connected to the corresponding data line 200, the drain is electrically connected to the first end of the second liquid crystal capacitor C12, and the second liquid crystal
  • the second end of the capacitor C12 is grounded, the first end of the second storage capacitor C22 is electrically connected to the first end of the second liquid crystal capacitor C12, and the other end is electrically connected to the array substrate common voltage line 400, and the third thin film transistor
  • the gate of T30 is electrically connected to the corresponding scan line 300, the source is electrically connected to the first end of the second liquid crystal capacitor C12, and the drain is electrically connected to the array substrate common voltage line 400.
  • the nth scan line g (n) controls the first thin film transistor T10, the second thin film transistor T20, and the third thin film transistor T30 in the nth row of the sub-pixels 100 to turn on
  • the data The data signal on line 200 is written into the first terminal of the first liquid crystal capacitor C11 through the corresponding first thin film transistor T10, and written into the first terminal of the second liquid crystal capacitor C12 through the corresponding second thin film transistor T20.
  • the thin film transistor T30 is released to the common voltage line 400 of the array substrate, so that the voltage difference across the first liquid crystal capacitor C11 and the voltage difference across the second liquid crystal capacitor C12 in a sub-pixel 100 are different, so as to improve the large viewing angle deviation.
  • the array substrate common voltage Acom on the array substrate common voltage line 400 will change and deviate.
  • the initially set voltage value causes different voltage values in different areas on the common voltage line 400 of the array substrate, resulting in abnormal screen display.
  • An object of the present invention is to provide a pixel driving circuit, which can ensure that the voltage values of the regions on the common voltage line of the array substrate are consistent, and can improve the display quality of the liquid crystal display device when applied to the liquid crystal display device.
  • Another object of the present invention is to provide a liquid crystal display device, in which the voltage values of the respective regions on the common voltage line of the array substrate are consistent, and the display quality is good.
  • the present invention first provides a pixel driving circuit including a plurality of sub-pixels arranged in an array, a plurality of scanning lines corresponding to a plurality of rows of sub-pixels, a plurality of data lines corresponding to a plurality of columns of sub-pixels, and an array Substrate common voltage line
  • the sub-pixel includes a first thin film transistor, a first liquid crystal capacitor, a first storage capacitor, a second thin film transistor, a third thin film transistor, a second liquid crystal capacitor, and a second storage capacitor;
  • the gate of the first thin film transistor is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the first end of the first liquid crystal capacitor;
  • the second terminal of a liquid crystal capacitor is connected to the common voltage of the color filter substrate;
  • the first terminal of the first storage capacitor is electrically connected to the first terminal of the first liquid crystal capacitor, and the second terminal is electrically connected to the common voltage line of the array substrate;
  • the gate of the second thin film transistor is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the first terminal of the second liquid crystal capacitor;
  • the second terminal of the second liquid crystal capacitor Connected to the common voltage of the color filter substrate;
  • the first terminal of the second storage capacitor is electrically connected to the first terminal of the second liquid crystal capacitor, and the second terminal is electrically connected to the common voltage line of the array substrate;
  • the gate of the third thin film transistor The electrode is electrically connected to the
  • N be a positive integer. Except for the last row of subpixels, in the Nth row of subpixels, the drain of the third thin film transistor of each subpixel corresponds to the second liquid crystal of a subpixel in the N + 1th row of subpixels. The first terminal of the capacitor is electrically connected.
  • M be a positive integer. Except for the last row of subpixels, the drain of the third thin film transistor of the Nth row and Mth column of the subpixel is electrically connected to the first terminal of the second liquid crystal capacitor of the N + 1th row and Mth column of the subpixel. .
  • the common voltage line of the array substrate is connected to the common voltage of the array substrate.
  • a second terminal of the first liquid crystal capacitor is grounded, a second terminal of the second liquid crystal capacitor is grounded, and a common voltage of the color filter substrate is a ground terminal voltage.
  • the drains of the third thin film transistors in the last row of sub-pixels are all electrically connected to the common voltage line of the array substrate.
  • the drain of the third thin film transistor of each sub-pixel is correspondingly electrically connected to the first terminal of the second liquid crystal capacitor of a sub-pixel in the first row of sub-pixels.
  • the drain of the third thin film transistor of the M pixel in the last row and the first terminal of the second liquid crystal capacitor in the M pixel of the first row are electrically connected.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are all N-type thin film transistors.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are all amorphous silicon thin film transistors, low temperature polysilicon thin film transistors, or oxide semiconductor thin film transistors.
  • the present invention also provides a liquid crystal display device including the above pixel driving circuit.
  • a pixel driving circuit provided by the present invention corresponds to the drain of the third thin film transistor of each sub-pixel in the N-th row of sub-pixels with that of a sub-pixel in the N + 1-th row of sub-pixels.
  • the first terminals of the two liquid crystal capacitors are electrically connected.
  • the voltage at one end is released to the first end of the second liquid crystal capacitor in the N + 1th row of sub-pixels, which will not affect the voltage on the common voltage line of the array substrate, effectively ensuring the The voltage values are consistent, and the display quality of the liquid crystal display device can be improved when applied to the liquid crystal display device.
  • the liquid crystal display device provided by the present invention has the same voltage value in each area of the common voltage line of the array substrate, and has good display quality.
  • FIG. 1 is a circuit diagram of a conventional pixel driving circuit
  • FIG. 2 is a circuit diagram of a pixel driving circuit of the present invention
  • FIG. 3 is a circuit diagram of the last row of sub-pixels in a preferred embodiment of a pixel driving circuit of the present invention.
  • FIG. 4 is a circuit diagram of a pixel driving circuit according to another preferred embodiment of the present invention in which the M-th sub-pixel in the last row and the M-th sub-pixel in the first row are connected.
  • the present invention provides a pixel driving circuit including a plurality of sub-pixels 10 arranged in an array, and a plurality of scanning lines 20 (G (1 ), G (2) ... G (N), G (N + 1) ...), multiple data lines 30 (D (1), D (2) ... D (1), D (2) ... D (1), D (1), D (2) ... M) Certainly and the array substrate common voltage line 40.
  • the sub-pixel 10 includes a first thin film transistor T1, a first liquid crystal capacitor C1, a first storage capacitor C2, a second thin film transistor T2, a third thin film transistor T3, a second liquid crystal capacitor C3, and a second storage capacitor C4.
  • the area where the first thin film transistor T1, the first liquid crystal capacitor C1, and the first storage capacitor C2 are located is the main area 11 of the sub-pixel 10.
  • the area where the second storage capacitor C4 is located is the sub-region 12 of the sub-pixel 10.
  • the gate of the first thin film transistor T1 is electrically connected to the corresponding scan line 20, the source is electrically connected to the corresponding data line 30, and the drain is electrically connected to the first of the first liquid crystal capacitor C1. end.
  • the second terminal of the first liquid crystal capacitor C1 is connected to the common voltage of the color filter substrate.
  • the first terminal of the first storage capacitor C1 is electrically connected to the first terminal of the first liquid crystal capacitor C1, and the second terminal of the first storage capacitor C1 is electrically connected to the common voltage line 40 of the array substrate.
  • the gate of the second thin film transistor T2 is electrically connected to the corresponding scan line 20, the source is electrically connected to the corresponding data line 30, and the drain is electrically connected to the first terminal of the second liquid crystal capacitor C3.
  • the second terminal of the second liquid crystal capacitor C3 is connected to the common voltage of the color filter substrate.
  • the first terminal of the second storage capacitor C4 is electrically connected to the first terminal of the second liquid crystal capacitor C3, and the second terminal is electrically connected to the common voltage line 40 of the array substrate.
  • the gate of the third thin film transistor T3 is electrically connected to the corresponding scan line 20, and the source is electrically connected to the first terminal of the second liquid crystal capacitor C3.
  • N be a positive integer. Except for the last row of sub-pixels 10, in the N-th row of sub-pixels 10, the drain of the third thin film transistor T3 of each sub-pixel 10 corresponds to one of the sub-pixels in the N + 1-th row of sub-pixels 10. The first terminal of the second liquid crystal capacitor C3 of the pixel 10 is electrically connected.
  • M be a positive integer, except for the last row of subpixels 10, the drain of the third thin film transistor T3 of the Nth row and the Mth column of the subpixel 10 and the N + 1th row and the Mth column of the subpixel 10
  • the first terminal of the second liquid crystal capacitor C3 is electrically connected.
  • the array substrate common voltage line 40 is connected to the array substrate common voltage Acom.
  • the common voltage of the color filter substrate is the ground terminal voltage.
  • the common voltage of the color filter substrate may also be set to other voltage values, and is not limited to the ground terminal voltage.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are all N-type thin film transistors.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 may all be P-type thin film transistors.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are all amorphous silicon thin film transistors, low temperature polysilicon thin film transistors, or oxide semiconductor thin film transistors.
  • the drains of the third thin film transistors T3 of the sub-pixels 10 in the last row may be electrically connected to the common voltage line 40 of the array substrate, that is, when the last row When the third thin film transistor T3 of the sub-pixel 10 is turned on, the voltage at the first end of the second liquid crystal capacitor C3 of the sub-pixel 10 in the last row is released to the array substrate common voltage trace 40.
  • the drain of the third thin film transistor T3 of the last row of sub-pixels 10 since the drain of the third thin film transistor T3 of the last row of sub-pixels 10 is electrically connected to the array substrate common voltage trace 40, the voltage on the array substrate common voltage trace 40 has a small influence.
  • the drain of the third thin film transistor T3 of each sub-pixel 10 corresponds to the first row of sub-pixels 10.
  • the first terminal of the second liquid crystal capacitor C3 of one of the sub-pixels 10 is electrically connected.
  • the drain of the third thin film transistor T3 of the M pixel sub-pixel 10 in the last row is electrically connected to the first terminal of the second liquid crystal capacitor C3 of the M pixel sub pixel 10 in the first row, that is, when the last pixel of the sub pixel 10
  • the third thin film transistor T3 is turned on, the voltage of the first terminal of the second liquid crystal capacitor C3 of the sub-pixel 10 in the last row is released to the first terminal of the second liquid crystal capacitor C3 of the sub-pixel 10 in the first row.
  • the pixel driving circuit of the present invention when it is driving, it sequentially supplies scanning signals to a plurality of scanning lines 20 to sequentially drive a plurality of rows of sub-pixels 10.
  • the scanning signal on the Nth scanning line G (N) controls the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 of the Nth row of the sub-pixels 10 to be turned on, the data signal voltage passes through multiple The data line 30 is written into the N-th row of the sub-pixels 10.
  • the data signal voltage is written into the N-th row through the M-th data line D (M) and the turned-on first thin film transistor T1.
  • the first terminal of a liquid crystal capacitor C1 at the same time, the data signal voltage is written into the first terminal of the second liquid crystal capacitor C3 via the Mth data line D (M) and the turned-on second thin film transistor T2.
  • the voltage of the first terminal of the two liquid crystal capacitors C3 will be released to the first terminal of the second liquid crystal capacitor C3 of the N + 1th row and the Mth column of the sub-pixel 10 via the turned-on third thin film transistor T3, so that the Nth and Mth columns will be
  • the voltage difference across the first liquid crystal capacitor C1 of the pixel 10 is different from the voltage difference across the second liquid crystal capacitor C3, thereby achieving the effect of eliminating large viewing role deviation, and comparing the voltage of the first terminal of the second liquid crystal capacitor with respect to the prior art.
  • the voltage value of the common voltage affecting Acom array substrate effectively ensure the voltage value of each region of the array substrate 40 on the same common voltage line, to ensure the quality of the display.
  • the voltage of the first terminal of the second liquid crystal capacitor C3 of the subpixel 10 in the Nth row is released to the first terminal of the second liquid crystal capacitor C3 of the subpixel 10 in the N + 1th row, and it does not affect the N + 1th
  • the voltage difference across the second liquid crystal capacitor C3 of the row of sub-pixels 10 affects, that is, does not affect normal display.
  • the present invention also provides a liquid crystal display device including the pixel driving circuit described above, and the structure of the pixel driving circuit is not described repeatedly here.
  • the data signal For the N-th row and the M-th column of the sub-pixels 10, the data signal The voltage is written into the first terminal of the first liquid crystal capacitor C1 via the M-th data line D (M) and the turned-on first thin film transistor T1, and at the same time, the data signal voltage is turned on through the M-th data line D (M) and turned on.
  • the second thin film transistor T2 is written into the first terminal of the second liquid crystal capacitor C3, and at this time, the voltage of the first terminal of the second liquid crystal capacitor C3 will go to the N + 1th row through the third thin film transistor T3 that is turned on.
  • the first end of the second liquid crystal capacitor C3 of the M pixel sub-pixel 10 is released, so that the voltage difference between the first liquid crystal capacitor C1 of the Nth row and the M pixel subpixel 10 is different from the voltage difference between the second liquid crystal capacitor C3, thereby achieving elimination.
  • the effect of large viewing role bias, and compared with the prior art, the The pressure is released to the common voltage line of the array substrate.
  • the present invention will not affect the voltage value of the common voltage Acom of the array substrate on the common voltage line 40 of the array substrate, which effectively ensures that the voltage values of the regions on the common voltage line 40 of the array substrate are consistent. To ensure the quality of the display.
  • the voltage of the first terminal of the second liquid crystal capacitor C3 of the subpixel 10 in the Nth row is released to the first terminal of the second liquid crystal capacitor C3 of the subpixel 10 in the N + 1th row, and it does not affect the N + 1th
  • the voltage difference across the second liquid crystal capacitor C3 of the row of sub-pixels 10 affects, that is, does not affect normal display.
  • the pixel driving circuit of the present invention corresponds to the drain of the third thin film transistor of each sub-pixel in the N-th row of sub-pixels with the second liquid crystal capacitor of a sub-pixel in the N + 1-th row of sub-pixels.
  • the first terminal is electrically connected.
  • the release to the first end of the second liquid crystal capacitor of the N + 1th row of sub-pixels will not affect the voltage on the common voltage line of the array substrate, which effectively ensures that the voltage values in all areas of the common voltage line of the array substrate are consistent.
  • Application in a liquid crystal display device can improve the display quality of the liquid crystal display device.
  • the voltage value of each area of the common voltage line of the array substrate of the liquid crystal display device of the present invention is consistent, and the display quality is good.

Abstract

一种像素驱动电路及液晶显示装置，其中，像素驱动电路将第N行子像素（10）中每一子像素（10）的第三薄膜晶体管（T3）的漏极对应与第N+1行子像素（10）中的一子像素（10）的第二液晶电容（C3）的第一端电性连接，驱动时，当对第N行子像素（10）进行扫描时，第N行子像素（10）的第三薄膜晶体管（T3）导通将第N行子像素（10）的第二液晶电容（C3）的第一端的电压向第N+1行子像素（10）的第二液晶电容（C3）的第一端释放，不会对阵列基板公共电压线（40）上的电压产生影响，有效地保证了阵列基板公共电压线（40）上各个区域的电压值一致，可提升液晶显示装置的显示品质。

Description

像素驱动电路及液晶显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种像素驱动电路及液晶显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
随着显示技术的不断发展，消费者对于TFT-LCD的画质要求越来越高。目前在设计TFT-LCD的像素驱动电路时，会将一个子像素分隔为主区(Main)及次区(Sub)，通过使主区与次区的液晶电容两端的电压差不同，达到改善TFT-LCD大视角色偏的效果。请参阅图1，为现有的一种像素驱动电路的结构示意图，该像素驱动电路包括阵列排布的多个子像素100、分别与多列子像素100对应连接的多条数据线200(d(1)、d(2)……d(m)……)、分别与多行子像素100对应连接的多行扫描线300(g(1)、g(2)……g(n)……)以及阵列基板公共电压线400。所述阵列基板公共电压线400用于接入阵列基板公共电压Acom。每个子像素100均包括第一薄膜晶体管T10、第一液晶电容C11、第一存储电容C21、第二薄膜晶体管T20、第三薄膜晶体管T30、第二液晶电容C12及第二存储电容C22，由第一薄膜晶体管T10、第一液晶电容C11、第一存储电容C21构成主区110，由第二薄膜晶体管T20、第三薄膜晶体管T30、第二液晶电容C12、第二存储电容C22构成次区120，所述第一薄膜晶体管T10的栅极电性连接对应的扫描线300，源极电性连接对应的数据线200，漏极电性连接第一液晶电容C11的第一端，所述第一液晶电容C11的第二端接地，所述第一存储电容C21的第一端电性连接第一 液晶电容C10的第一端，另一端电性连接阵列基板公共电压线400。所述第二薄膜晶体管T20的栅极电性连接对应的扫描线300，源极电性连接对应的数据线200，漏极电性连接第二液晶电容C12的第一端，所述第二液晶电容C12的第二端接地，所述第二存储电容C22的第一端电性连接第二液晶电容C12的第一端，另一端电性连接阵列基板公共电压线400，所述第三薄膜晶体管T30的栅极电性连接对应的扫描线300，源极电性连接第二液晶电容C12的第一端，漏极电性连接阵列基板公共电压线400。该像素驱动电路在工作时，当第n条扫描线g(n)控制第n行子像素100中的第一薄膜晶体管T10、第二薄膜晶体管T20、第三薄膜晶体管T30均导通时，数据线200上的数据信号经对应的第一薄膜晶体管T10写入第一液晶电容C11的第一端，并经对应的第二薄膜晶体管T20写入第二液晶电容C12的第一端后经第三薄膜晶体管T30向阵列基板公共电压线400释放，使得一个子像素100中第一液晶电容C11两端的电压差与第二液晶电容C12两端的电压差不同，以改善大视角色偏。然而，图1所示的像素驱动电路中，由于第二液晶电容C12一端的电压是向阵列基板公共电压线400释放，会导致阵列基板公共电压线400上的阵列基板公共电压Acom发生变化，偏离初始设置的电压值，从而造成阵列基板公共电压线400上不同区域的电压值不同，导致画面显示异常。
发明内容
本发明的目的在于提供一种像素驱动电路，能够保证阵列基板公共电压线上各个区域的电压值一致，应用于液晶显示装置中可提升液晶显示装置的显示品质。
本发明的另一目的在于提供一种液晶显示装置，其阵列基板公共电压线上各个区域的电压值一致，显示品质好。
为实现上述目的，本发明首先提供一种像素驱动电路，包括阵列排布的多个子像素、分别与多行子像素对应的多条扫描线、分别与多列子像素对应的多条数据线以及阵列基板公共电压线；
所述子像素包括第一薄膜晶体管、第一液晶电容、第一存储电容、第二薄膜晶体管、第三薄膜晶体管、第二液晶电容及第二存储电容；
每一子像素中，所述第一薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接对应的数据线，漏极电性连接第一液晶电容的第一端；所述第一液晶电容的第二端接入彩膜基板公共电压；所述第一存储电容的第一端电性连接第一液晶电容的第一端，第二端电性连接阵列基板公共电压线； 所述第二薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接对应的数据线，漏极电性连接第二液晶电容的第一端；所述第二液晶电容的第二端接入彩膜基板公共电压；所述第二存储电容的第一端电性连接第二液晶电容的第一端，第二端电性连接阵列基板公共电压线；所述第三薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接第二液晶电容的第一端；
设N正整数，除最后一行子像素以外，在第N行子像素中，每一子像素的第三薄膜晶体管的漏极对应与第N+1行子像素中的一子像素的第二液晶电容的第一端电性连接。
设M为正整数，除最后一行子像素以外，第N行第M列子像素的第三薄膜晶体管的漏极与第N+1行第M列子像素的第二液晶电容的第一端电性连接。
所述阵列基板公共电压线接入阵列基板公共电压。
所述第一液晶电容的第二端接地，所述第二液晶电容的第二端接地，所述彩膜基板公共电压为接地端电压。
最后一行子像素的第三薄膜晶体管的漏极均电性连接阵列基板公共电压线。
在最后一行子像素中，每一子像素的第三薄膜晶体管的漏极对应与第一行子像素中的一子像素的第二液晶电容的第一端电性连接。
最后一行第M列子像素的第三薄膜晶体管的漏极与第一行第M列子像素的第二液晶电容的第一端电性连接。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管均为N型薄膜晶体管。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管或氧化物半导体薄膜晶体管。
本发明还提供一种液晶显示装置，包括上述的像素驱动电路。
本发明的有益效果：本发明提供的一种像素驱动电路将第N行子像素中每一子像素的第三薄膜晶体管的漏极对应与第N+1行子像素中的一子像素的第二液晶电容的第一端电性连接，驱动时，当对第N行子像素进行扫描时，第N行子像素的第三薄膜晶体管导通将第N行子像素的第二液晶电容的第一端的电压向第N+1行子像素的第二液晶电容的第一端释放，不会对阵列基板公共电压线上的电压产生影响，有效地保证了阵列基板公共电压线上各个区域的电压值一致，应用于液晶显示装置中可提升液晶显示装置的显示品质。本发明提供的一种液晶显示装置的阵列基板公共电压线上各个区域的电压值一致，显示品质好。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种像素驱动电路的电路图；
图2为本发明的像素驱动电路的电路图；
图3为本发明的像素驱动电路的一优选实施例中最后一行子像素的电路图；
图4为本发明的像素驱动电路的另一优选实施例中最后一行第M列子像素与第一行第M列子像素连接的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，并结合图3或图4，本发明提供一种像素驱动电路，包括阵列排布的多个子像素10、分别与多行子像素10对应的多条扫描线20(G(1)、G(2)……G(N)、G(N+1)……)、分别与多列子像素10对应的多条数据线30(D(1)、D(2)……D(M)……)以及阵列基板公共电压线40。
所述子像素10包括第一薄膜晶体管T1、第一液晶电容C1、第一存储电容C2、第二薄膜晶体管T2、第三薄膜晶体管T3、第二液晶电容C3及第二存储电容C4。所述第一薄膜晶体管T1、第一液晶电容C1、第一存储电容C2所在区域为该子像素10的主区11，所述第二薄膜晶体管T2、第三薄膜晶体管T3、第二液晶电容C3、第二存储电容C4所在区域为该子像素10的次区12。
每一子像素10中，所述第一薄膜晶体管T1的栅极电性连接对应的扫描线20，源极电性连接对应的数据线30，漏极电性连接第一液晶电容C1的第一端。所述第一液晶电容C1的第二端接入彩膜基板公共电压。所述第一存储电容C1的第一端电性连接第一液晶电容C1的第一端，第二端电性连接阵列基板公共电压线40。所述第二薄膜晶体管T2的栅极电性连接对应的扫描线20，源极电性连接对应的数据线30，漏极电性连接第二液晶电容 C3的第一端。所述第二液晶电容C3的第二端接入彩膜基板公共电压。所述第二存储电容C4的第一端电性连接第二液晶电容C3的第一端，第二端电性连接阵列基板公共电压线40。所述第三薄膜晶体管T3的栅极电性连接对应的扫描线20，源极电性连接第二液晶电容C3的第一端。
设N正整数，除最后一行子像素10以外，在第N行子像素10中，每一子像素10的第三薄膜晶体管T3的漏极对应与第N+1行子像素10中的一子像素10的第二液晶电容C3的第一端电性连接。
具体地，请参阅图2，设M为正整数，除最后一行子像素10以外，第N行第M列子像素10的第三薄膜晶体管T3的漏极与第N+1行第M列子像素10的第二液晶电容C3的第一端电性连接。
具体地，所述阵列基板公共电压线40接入阵列基板公共电压Acom。
具体地，在图2所示的实施例中，所述第一液晶电容C1的第二端接地，所述第二液晶电容C2的第二端接地，所述彩膜基板公共电压为接地端电压。当然，在本发明的其他实施例中，所述彩膜基板公共电压也可设置为其他电压值，并不限于接地端电压。
具体地，在图2所示的实施例中，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3均为N型薄膜晶体管。当然，在本发明的其他实施例中，所述第一薄膜晶体管T1、第二薄膜晶体管T2及第三薄膜晶体管T3也可均为P型薄膜晶体管。
具体地，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管或氧化物半导体薄膜晶体管。
可选地，请参阅图3，在本发明的一优选实施例中，最后一行子像素10的第三薄膜晶体管T3的漏极可均电性连接阵列基板公共电压线40，也即当最后一行子像素10的第三薄膜晶体管T3导通时，最后一行子像素10的第二液晶电容C3的第一端的电压向阵列基板公共电压走线40释放。在该实施例中，由于仅有最后一行子像素10的第三薄膜晶体管T3的漏极电性连接阵列基板公共电压走线40，对阵列基板公共电压走线40的电压影响较小。
可选地，请参阅图4，在本发明的另一优选实施例中，在最后一行子像素10中，每一子像素10的第三薄膜晶体管T3的漏极对应与第一行子像素10中的一子像素10的第二液晶电容C3的第一端电性连接。进一步地，最后一行第M列子像素10的第三薄膜晶体管T3的漏极与第一行第M列子像素10的第二液晶电容C3的第一端电性连接，也即当最后一行子像素10的 第三薄膜晶体管T3导通时，最后一行子像素10的第二液晶电容C3的第一端的电压对应向第一行子像素10的第二液晶电容C3的第一端释放。
需要说明的是，以图2所示的实施例为例，本发明的像素驱动电路在进行驱动时，依次向多条扫描线20提供扫描信号，以对多行子像素10进行逐行驱动。当第N条扫描线G(N)上的扫描信号控制第N行子像素10的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3均导通时，数据信号电压经多条数据线30写入第N行子像素10中，对于第N行第M列子像素10来说，数据信号电压经第M条数据线D(M)及导通的第一薄膜晶体管T1写入第一液晶电容C1的第一端，同时，数据信号电压经第M条数据线D(M)及导通的第二薄膜晶体管T2写入第二液晶电容C3的第一端，并且此时，第二液晶电容C3的第一端的电压会经导通的第三薄膜晶体管T3向第N+1行第M列子像素10的第二液晶电容C3的第一端释放，使得第N行第M列子像素10的第一液晶电容C1两端的电压差与第二液晶电容C3两端的电压差不同，从而实现消除大视角色偏的效果，并且相对于现有技术将第二液晶电容第一端的电压向阵列基板公共电压线释放，本发明不会对阵列基板公共电压线40上的阵列基板公共电压Acom的电压值造成影响，有效地保证了阵列基板公共电压线40上各个区域的电压值一致，保证了显示的品质。随后，当第N+1条扫描线G(N+1)上的扫描信号控制第N+1行子像素10的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3均导通时，数据信号电压经多条数据线30写入第N+1行子像素10中，使得第N+1行子像素10的第二液晶电容C3的第一端的电压重新回到正确的电压值，因此将第N行子像素10的第二液晶电容C3的第一端的电压向第N+1行子像素10的第二液晶电容C3的第一端释放，不会对第N+1行子像素10的第二液晶电容C3两端的电压差产生影响，也即不会影响正常的显示。
基于同一发明构思，本发明还提供一种液晶显示装置，包括上述的像素驱动电路，在此不再对像素驱动电路的结构做重复性描述。
需要说明的是，以包括了图2所示的像素驱动电路的液晶显示装置为例，当第N条扫描线G(N)上的扫描信号控制第N行子像素10的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3均导通时，数据信号电压经多条数据线30写入第N行子像素10中，对于第N行第M列子像素10来说，数据信号电压经第M条数据线D(M)及导通的第一薄膜晶体管T1写入第一液晶电容C1的第一端，同时，数据信号电压经第M条数据线D(M)及导通的第二薄膜晶体管T2写入第二液晶电容C3的第一端，并且此时， 第二液晶电容C3的第一端的电压会经导通的第三薄膜晶体管T3向第N+1行第M列子像素10的第二液晶电容C3的第一端释放，使得第N行第M列子像素10的第一液晶电容C1两端的电压差与第二液晶电容C3两端的电压差不同，从而实现消除大视角色偏的效果，并且相对于现有技术将第二液晶电容第一端的电压向阵列基板公共电压线释放，本发明不会对阵列基板公共电压线40上的阵列基板公共电压Acom的电压值造成影响，有效地保证了阵列基板公共电压线40上各个区域的电压值一致，保证了显示的品质。随后，当第N+1条扫描线G(N+1)上的扫描信号控制第N+1行子像素10的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3均导通时，数据信号电压经多条数据线30写入第N+1行子像素10中，使得第N+1行子像素10的第二液晶电容C3的第一端的电压重新回到正确的电压值，因此将第N行子像素10的第二液晶电容C3的第一端的电压向第N+1行子像素10的第二液晶电容C3的第一端释放，不会对第N+1行子像素10的第二液晶电容C3两端的电压差产生影响，也即不会影响正常的显示。
综上所述，本发明的像素驱动电路将第N行子像素中每一子像素的第三薄膜晶体管的漏极对应与第N+1行子像素中的一子像素的第二液晶电容的第一端电性连接，驱动时，当对第N行子像素进行扫描时，第N行子像素的第三薄膜晶体管导通将第N行子像素的第二液晶电容的第一端的电压向第N+1行子像素的第二液晶电容的第一端释放，不会对阵列基板公共电压线上的电压产生影响，有效地保证了阵列基板公共电压线上各个区域的电压值一致，应用于液晶显示装置中可提升液晶显示装置的显示品质。本发明的液晶显示装置的阵列基板公共电压线上各个区域的电压值一致，显示品质好。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种像素驱动电路，包括阵列排布的多个子像素、分别与多行子像素对应的多条扫描线、分别与多列子像素对应的多条数据线以及阵列基板公共电压线；
    所述子像素包括第一薄膜晶体管、第一液晶电容、第一存储电容、第二薄膜晶体管、第三薄膜晶体管、第二液晶电容及第二存储电容；
    每一子像素中，所述第一薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接对应的数据线，漏极电性连接第一液晶电容的第一端；所述第一液晶电容的第二端接入彩膜基板公共电压；所述第一存储电容的第一端电性连接第一液晶电容的第一端，第二端电性连接阵列基板公共电压线；所述第二薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接对应的数据线，漏极电性连接第二液晶电容的第一端；所述第二液晶电容的第二端接入彩膜基板公共电压；所述第二存储电容的第一端电性连接第二液晶电容的第一端，第二端电性连接阵列基板公共电压线；所述第三薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接第二液晶电容的第一端；
    设N正整数，除最后一行子像素以外，在第N行子像素中，每一子像素的第三薄膜晶体管的漏极对应与第N+1行子像素中的一子像素的第二液晶电容的第一端电性连接。
  2. 如权利要求1所述的像素驱动电路，其中，设M为正整数，除最后一行子像素以外，第N行第M列子像素的第三薄膜晶体管的漏极与第N+1行第M列子像素的第二液晶电容的第一端电性连接。
  3. 如权利要求1所述的像素驱动电路，其中，所述阵列基板公共电压线接入阵列基板公共电压。
  4. 如权利要求1所述的像素驱动电路，其中，所述第一液晶电容的第二端接地，所述第二液晶电容的第二端接地，所述彩膜基板公共电压为接地端电压。
  5. 如权利要求1所述的像素驱动电路，其中，最后一行子像素的第三薄膜晶体管的漏极均电性连接阵列基板公共电压线。
  6. 如权利要求1所述的像素驱动电路，其中，在最后一行子像素中，每一子像素的第三薄膜晶体管的漏极对应与第一行子像素中的一子像素的第二液晶电容的第一端电性连接。
  7. 如权利要求6所述的像素驱动电路，其中，设M为正整数，最后一 行第M列子像素的第三薄膜晶体管的漏极与第一行第M列子像素的第二液晶电容的第一端电性连接。
  8. 如权利要求1所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管均为N型薄膜晶体管。
  9. 如权利要求1所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管或氧化物半导体薄膜晶体管。
  10. 一种液晶显示装置，包括一像素驱动电路；
    所述像素驱动电路包括阵列排布的多个子像素、分别与多行子像素对应的多条扫描线、分别与多列子像素对应的多条数据线以及阵列基板公共电压线；
    所述子像素包括第一薄膜晶体管、第一液晶电容、第一存储电容、第二薄膜晶体管、第三薄膜晶体管、第二液晶电容及第二存储电容；
    每一子像素中，所述第一薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接对应的数据线，漏极电性连接第一液晶电容的第一端；所述第一液晶电容的第二端接入彩膜基板公共电压；所述第一存储电容的第一端电性连接第一液晶电容的第一端，第二端电性连接阵列基板公共电压线；所述第二薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接对应的数据线，漏极电性连接第二液晶电容的第一端；所述第二液晶电容的第二端接入彩膜基板公共电压；所述第二存储电容的第一端电性连接第二液晶电容的第一端，第二端电性连接阵列基板公共电压线；所述第三薄膜晶体管的栅极电性连接对应的扫描线，源极电性连接第二液晶电容的第一端；
    设N正整数，除最后一行子像素以外，在第N行子像素中，每一子像素的第三薄膜晶体管的漏极对应与第N+1行子像素中的一子像素的第二液晶电容的第一端电性连接。
  11. 如权利要求10所述的液晶显示装置，其中，设M为正整数，除最后一行子像素以外，第N行第M列子像素的第三薄膜晶体管的漏极与第N+1行第M列子像素的第二液晶电容的第一端电性连接。
  12. 如权利要求10所述的液晶显示装置，其中，所述阵列基板公共电压线接入阵列基板公共电压。
  13. 如权利要求10所述的液晶显示装置，其中，所述第一液晶电容的第二端接地，所述第二液晶电容的第二端接地，所述彩膜基板公共电压为接地端电压。
  14. 如权利要求10所述的液晶显示装置，其中，最后一行子像素的第 三薄膜晶体管的漏极均电性连接阵列基板公共电压线。
  15. 如权利要求10所述的液晶显示装置，其中，在最后一行子像素中，每一子像素的第三薄膜晶体管的漏极对应与第一行子像素中的一子像素的第二液晶电容的第一端电性连接。
  16. 如权利要求15所述的液晶显示装置，其中，设M为正整数，最后一行第M列子像素的第三薄膜晶体管的漏极与第一行第M列子像素的第二液晶电容的第一端电性连接。
  17. 如权利要求10所述的液晶显示装置，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管均为N型薄膜晶体管。
  18. 如权利要求10所述的液晶显示装置，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管或氧化物半导体薄膜晶体管。
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