WO2016188036A1 - 一种阵列基板及显示装置 - Google Patents

一种阵列基板及显示装置 Download PDF

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Publication number
WO2016188036A1
WO2016188036A1 PCT/CN2015/093562 CN2015093562W WO2016188036A1 WO 2016188036 A1 WO2016188036 A1 WO 2016188036A1 CN 2015093562 W CN2015093562 W CN 2015093562W WO 2016188036 A1 WO2016188036 A1 WO 2016188036A1
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Prior art keywords
source
tft
drain
sub
pixel electrode
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PCT/CN2015/093562
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English (en)
French (fr)
Inventor
李文波
李盼
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to BR112017000086-5A priority Critical patent/BR112017000086B1/pt
Priority to EP15890157.9A priority patent/EP3306384B1/en
Priority to RU2017100017A priority patent/RU2710381C2/ru
Priority to MX2017000373A priority patent/MX360796B/es
Priority to US15/308,400 priority patent/US10078251B2/en
Publication of WO2016188036A1 publication Critical patent/WO2016188036A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction

Definitions

  • the present disclosure relates to the field of electronic technologies, and in particular, to an array substrate and a display device.
  • the present disclosure provides an array substrate and a display device, which can improve the viewing angle of the liquid crystal display and reduce the structural complexity of the TFT in the array substrate.
  • the present disclosure provides an array substrate including a plurality of pixel units defined by intersecting gate lines and data lines.
  • the pixel unit includes a first sub-pixel electrode, a second sub-pixel electrode, a first TFT, and a second TFT; the first sub-pixel electrode is connected to a drain of the first TFT, and the second sub-pixel electrode Connected to the drain of the second TFT;
  • the resistance between the source of the first TFT and the data line connected to the first TFT is greater than the resistance between the source of the second TFT and the data line connected to the second TFT; And/or, a resistance between a drain of the first TFT and the first sub-pixel electrode is greater than a resistance between a drain of the second TFT and the second sub-pixel electrode.
  • a source of the first TFT and a data line connected to the first TFT are connected by a line-shaped source line, and a source of the second TFT and a second TFT are connected Data lines are connected by linear source lines; and/or,
  • a first voltage dividing resistor is disposed on the source line connected to the source of the first TFT, and/or
  • the source line connected to a source of the first TFT includes a first interval a source segment
  • the first voltage dividing resistor includes a second source segment disposed in a different layer from the first source segment
  • the second source segment is connected to the spaced-apart first source segment through a via; the source of the second TFT is disposed in the same layer as the first source segment, or is coupled to the second source
  • the pole segment is set in the same layer.
  • the source line connected to a source of the first TFT includes a first source segment And a second source segment
  • the first voltage dividing resistor includes a diode pair
  • the forward diode and the reverse diode are respectively formed by shorting two thin film transistors, wherein
  • the forward diode includes: a first shorted source, a first shorted drain, and a first gate region,
  • the first shorting source is connected to the first source segment, the first shorting drain is connected to the second source segment, and the first gate region passes through a via The first shorting source is shorted;
  • first gate region and the second gate region are both disposed in the same layer as the gate of the first TFT and the gate of the second TFT.
  • a via hole is formed on the first gate region and the first short-circuit source, and a transparent conductive layer is connected on the two via holes;
  • a via hole is formed on the second gate region and the second short drain, and a transparent conductive layer is overlaid on the two via holes.
  • the drain line connected to the drain of the first TFT includes a first drain disposed at intervals a second voltage dividing resistor includes a second drain segment disposed in a different layer from the first drain segment; the second drain segment is connected to the spaced first drain segment through a via .
  • the gate line is provided with a non-penetrating groove, the opening of the groove faces the first sub-pixel electrode or the second sub-pixel electrode, and the source line of the first TFT passes The bottom of the recess overlaps the gate of the first TFT.
  • a source of the first TFT and a source of the second TFT are connected to a same data line; a gate of the first TFT and a gate of the second TFT The poles are connected to the same grid line.
  • the present disclosure also provides a display device including any of the above array substrates.
  • the present disclosure is directed to an array substrate and a display device, the array substrate including a plurality of pixel units defined by intersecting gate lines and data lines, each of the pixel units including a first sub-pixel electrode and a second sub-pixel electrode, respectively Driven by the first TFT and the second TFT, specifically, the first sub-pixel electrode is connected to the drain of the first TFT, and the second sub-pixel electrode is connected to the drain of the second TFT, wherein the source of the first TFT is The resistance between the connected data lines is greater than the source of the second TFT The resistance between the data lines; and/or the resistance between the drain of the first TFT and the first sub-pixel electrode is greater than the resistance between the drain of the second TFT and the second sub-pixel electrode.
  • the output voltage at the drain of the first TFT is smaller than the same driving voltage.
  • the deflection angle is such that when the incident light passes through the liquid crystal region corresponding to the same pixel unit, the emitted light is substantially uniform in different directions, thereby improving the viewing angle of the liquid crystal display and reducing the array while introducing no additional TFT. Structural complexity within the substrate.
  • FIG. 1 is a schematic plan view of a pixel unit structure on an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view 2 of a pixel unit structure on an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic plan view 3 of a pixel unit structure on an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a plan view 4 of a pixel unit structure on an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic plan view 5 of a pixel unit structure on an array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a plan view 6 of a pixel unit structure on an array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic plan view of a pixel unit structure on an array substrate according to an embodiment of the present disclosure.
  • first and second are used for descriptive purposes only, and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality of means two or more unless otherwise stated.
  • Embodiments of the present disclosure provide an array substrate including a plurality of pixel units divided by intersecting gate lines and data lines. Specifically, embodiments of the present disclosure are illustrated by one pixel unit.
  • the pixel unit 01 includes a first sub-pixel electrode 11 and a second sub-pixel electrode 21, and the first sub-pixel electrode 11 and the second sub-pixel electrode 21 are respectively composed of a first TFT 12 and a second TFT.
  • the gate of the first TFT 12 and the gate of the second TFT 22 may be respectively connected to different gate lines; the source of the first TFT 12 and the source of the second TFT 22 may also have different data respectively.
  • the lines are connected, and the disclosure does not limit this.
  • the resistance between the source of the first TFT 12 and the data line 03 connected thereto is greater than the resistance between the source of the second TFT 22 and the data line 03 connected thereto; and/or the first TFT 12
  • the resistance between the drain and the first sub-pixel electrode 11 is greater than the resistance between the drain of the second TFT 22 and the second sub-pixel electrode 21.
  • the second sub-pixel electrode 21 is charged.
  • the charging voltage is the same as or close to the voltage at B2, and UB2>UB1, therefore, the first sub-pixel
  • the charging voltage of the electrode 11 is smaller than the charging voltage of the second sub-pixel electrode 21, so that the electric field intensity of the liquid crystal domain corresponding to the two sub-pixel electrodes 11 and 21 is different, and finally the deflection angle of the liquid crystal molecules in the two domain regions is obtained. Different.
  • the liquid crystal still has optical anisotropy, the light transmission directions of the two domain regions are not the same, and the light rays emitted from the two domain regions complement each other, so that the emitted light can be made substantially uniform in all directions. Since the picture presented by the liquid crystal display device in a macroscopic view is a spatial integration effect of the light emitted from each pixel unit, in the embodiment of the present disclosure, substantially the same picture can be obtained from a wide range of viewing angles. The effect, that is, the viewing angle of the liquid crystal display device is improved, and the charge and discharge control of the sub-pixel electrode is not additionally increased by the TFT.
  • a second voltage dividing resistor R2 is added between the drain of the first TFT 12 and the first sub-pixel electrode 11 with respect to the drain of the second TFT 22, similar to the above analysis.
  • the second voltage dividing resistor R2 since the second voltage dividing resistor R2 also has a voltage dividing effect, the charging voltage at the drain of the first TFT 12 is smaller than the charging voltage at the drain of the second TFT 22, thereby making The liquid crystal domain regions corresponding to the two sub-pixel electrodes 11 and 12 are subjected to different electric field strengths, and finally the deflection angles of the liquid crystal molecules in the two domain regions are different.
  • a first voltage dividing resistor R1 may be added between the source of the first TFT 12 and the data line 03, and the drain of the first TFT 12 and the first
  • a second voltage dividing resistor R2 is added between the sub-pixel electrodes 11 so that the electric field strengths of the liquid crystal domains corresponding to the two sub-pixel electrodes 11 and 21 are different, and finally the deflection angles of the liquid crystal molecules in the two domain regions are different. the same.
  • the source of the first TFT 12 may be connected to the data line 03 through a line-shaped source line.
  • the source of the second TFT 22 is connected to the data line 03 through a linear source line, thereby increasing the number
  • the resistance between the source of the TFT 12 and the data line 03 forms a first voltage dividing resistor R1.
  • the drain of the first TFT 12 may also be connected to the first sub-pixel electrode 11 through a line-shaped drain line.
  • the drain of the second TFT 22 passes through the linear drain line and the second sub-pixel electrode. 21 is connected to increase the resistance between the drain of the first TFT 12 and the first sub-pixel electrode 11, thereby forming a second voltage dividing resistor R2.
  • the source of the first TFT 12 is connected to the data line 03 through a line-shaped source line.
  • the pixel unit 01 specifically includes a first sub-pixel electrode 11 and a second sub-pixel.
  • the first electrode 11 and the second sub-pixel electrode 21 are respectively located on two sides of one gate line 02 and one side of the data line 03; the gate line 02 is directly used as the gate of the two TFTs.
  • the first TFT and the data line 03 are connected by the source line 13, and the source line 13 is designed in a fold line shape, extending from the data line 03 to the first sub-pixel electrode 11 to form a first line on the gate line 02.
  • the source electrode 14 is connected to the data line 03 through a linear source line, extends from the data line 03 to the second sub-pixel electrode 21, and forms a second source 23 on the gate line 02 corresponding to the first source. 14 and the second source 23 respectively form a first drain 15 and a second drain 24, the first drain 15 is electrically connected to the first sub-pixel 11 through the via, and the second drain 24 passes through the via and the second The two sub-pixel electrodes 21 are electrically connected.
  • the first TFT source line 13 of the fold line forms the first voltage dividing resistor R1
  • it has a voltage dividing effect, so that the output voltage at the first drain 15 of the first TFT is smaller than the second.
  • the output voltage at the second drain 24 of the TFT causes a voltage difference to be formed between the sub-pixel electrodes respectively connected to the drain of the first TFT and the drain of the second TFT.
  • the drain of the first TFT 12 can also be connected to the first sub-pixel electrode 11 through a line-shaped drain line.
  • the source line 13 connected to the first TFT 12 is similar, and the drain line connected to the drain 15 in the first TFT 12 can also be designed as a fold line to form a second voltage dividing resistor R2.
  • the resistor R2 also has a voltage dividing action to form a voltage difference between the sub-pixel electrodes respectively connected to the drain of the first TFT and the drain of the second TFT.
  • connection relationship between the two TFTs may be a back-to-back connection of two source levels, and the corresponding drains are located at two source levels of the back-to-back connection.
  • the two sides or the two source stages are arranged side by side, and the corresponding two drains are disposed on the same side of the two source stages;
  • the TFT may be a long-shaped I-type TFT at the source level, or a U-shaped source-shaped U-shaped source
  • the TFT the person skilled in the art can adopt the most suitable connection relationship and shape type of the TFT according to the actual situation.
  • a non-penetrating groove 41 may be provided on the gate line 02.
  • the groove 41 extends in a direction from the second sub-pixel electrode 21 to the first sub-pixel electrode 11 and does not penetrate the gate line 02.
  • the opening of the groove 41 faces the first sub-pixel electrode 11 or the second sub-pixel electrode 21.
  • the overlap with the gate of the first TFT is such that the overlap area of the gate line 02 and the source line 13 of the first TFT is reduced, so that the interference of the coupling capacitance between the gate line 02 and the source line 13 can be reduced.
  • the source of the first TFT and the data line connected thereto may specifically include: a first source segment disposed at intervals, and a second source segment of a source segment disposed in a different layer, wherein the second source segment is connected to the spaced first source segment through a via; a source of the second TFT and the The first source segment is disposed in the same layer or in the same layer as the second source segment.
  • the source of the first TFT is Specifically, the method includes: a first source segment 131 disposed at intervals, and a second source segment 132 disposed in a different layer from the first source segment, and the second source segment 132 is supplemented by a via hole Connected to the first source segment 131 disposed at intervals, in this embodiment, the pixel unit 01 is disposed with the gate line 02 as the center line, and the two sub-pixel electrodes 11 and 21 are adjacent to the gate line 02 and the data line 03, directly With the gate line 02 as the gate of both TFTs, these settings can minimize the connection lines (such as the line between the gate and the gate line, the line between the data line and the source, the sub-pixel electrode and the drain). The line between the lines) simplifies the patterning process of each functional layer.
  • the second source segment 132 may be specifically an ITO resistor made of an ITO material, such that the second source segment 132 and the first sub-pixel electrode 11 and/or the second sub-pixel electrode 21 may be disposed in the same layer.
  • the number of patterning processes used to fabricate the array substrate is not increased.
  • the second source segment 132 can also be made of other materials having a large resistance value.
  • the second source segment 132 and the first sub-pixel electrode 11 and/or the second sub-pixel electrode 21 are different layers. Accordingly, after forming the source and drain electrodes of the first TFT and the second TFT, the second source region 132 is separately applied to the spaced-apart first source segment 131 using a patterning process alone.
  • a spaced first drain segment and a first drain may be disposed between the drain of the first TFT and the first sub-pixel electrode.
  • a second drain segment disposed in a different layer of the segment, thereby forming a second voltage dividing resistor R2.
  • the drain of the first TFT and the second TFT can be respectively A voltage difference is formed between the sub-pixel electrodes connected to the drain.
  • the source of the first TFT And the data line connected thereto may specifically include: a diode pair, a first source segment and a second source segment, one end of the diode pair being connected to the first source segment, the diode pair The other end is connected to the second source segment; wherein, since the diode has unidirectional conductivity, the diode pair can be turned on to ensure that the data line is turned on when a high voltage or a low voltage is supplied. Includes parallel diodes and reverse diodes in parallel.
  • the diode pair is formed by shorting two TFTs.
  • the forward diode and the reverse diode constitute the diode pair, one end of the diode pair is connected to the first source segment 53, and one end of the diode pair is connected to the second source segment 54.
  • the forward diode includes: a first shorted source 61, a first shorted drain 62, and a first gate region 63 (the first gate region 63 is disposed in the same layer as the gate of the first TFT)
  • the first shorting source 61 is connected to the first source segment 53
  • the first shorting drain 62 is connected to the second source segment 54
  • the first gate region 63 is shorted to the first through the via.
  • the source 61 is short-circuited; the reverse diode includes: a second shorted source 71, a second shorted drain 72, and a second gate region 73 (the second gate region 73 and the gate of the first TFT) The same layer is disposed), wherein the second shorted source 71 is connected to the first source segment 53, the second shorted drain 72 is connected to the second source segment 54, and the second gate region 73 is passed through the via The two shorted drains 72 are shorted.
  • FIG. 6 there are various methods for forming a forward diode and a reverse diode by short-circuiting TFTs, and those skilled in the art can adopt the most reasonable setting manner according to actual conditions, for example, as shown in FIG.
  • An ITO layer is disposed on the diode and the reverse diode, and the ITO layer is electrically connected to the first short source 61 through the via 81, and the ITO layer is electrically connected to the first gate region 63 through the via 82.
  • the first gate region 63 is shorted to the first shorting source 61 to form a forward diode; accordingly, the reverse diode can be formed by using the above method, so that there is no need to additionally increase the patterning process used to fabricate the array substrate.
  • the number of times can form a first voltage dividing resistor R1 at the source of the first TFT.
  • the same method as described above can be used to form a forward diode and a reverse diode at the drain 15 of the first TFT, thereby forming a second voltage dividing resistor R2, thus The second voltage dividing resistor R2 also has a voltage dividing action, thereby ensuring a voltage difference between the drain of the first TFT and the sub-pixel electrode connected to the drain of the second TFT.
  • the TFT since the TFT is in an on state (when a voltage is applied to the gate to turn on the active layer), it can be equivalent to a resistor, and the resistance of the TFT is determined by the width to length ratio of the TFT, wherein the aspect ratio is An intrinsic property of TFT, generally written as W/L, W and L represent the width and length of the channel, respectively. As shown in equation (1), the width to length ratio of W1/L1 of TFT is related to its resistance, namely:
  • the forward diode and // can be controlled by adjusting the aspect ratio W 1 /L 1 of the forward diode and/or the reverse diode. Or the resistance of the reverse diode, and thus the resistance of the voltage dividing resistor, so that the electric field strengths of the liquid crystal domains corresponding to the two sub-pixel electrodes are different, and finally the deflection angles of the liquid crystal molecules in the two domain regions are different. In the same manner, the outgoing light is kept uniform in all directions, and the viewing angle characteristics of the liquid crystal display device are improved.
  • the first voltage dividing resistor is added between the source of the first TFT and the source of the second TFT, and the first voltage dividing resistor is added between the data lines. It should be understood that The design of the second voltage-dividing resistor between the drain of the first TFT and the drain of the second TFT is similar to that of the first embodiment, and therefore the description is omitted here. .
  • the difference between the charging voltage of the first sub-pixel electrode in the same pixel unit and the charging voltage of the second sub-pixel electrode may be 0-0.5V.
  • the voltage difference causes the corresponding two liquid crystal domain regions to have an optimized deflection angle difference, thereby enabling the emitted light to be more uniform in all directions, thereby obtaining a more uniform picture effect in various directions in the macroscopic direction and improving the liquid crystal display.
  • the viewing angle characteristics of the device are examples of the device.
  • the present disclosure does not specifically limit the charging voltage difference between the two sub-pixel electrodes in the same pixel electrode, and even if the two differences are set in other ranges, as long as the emitted light can be kept uniform in all directions, It still falls within the scope of protection of the present disclosure.
  • the purpose of the above embodiments is to provide a more optimized substrate component.
  • the arrangement of the sub-pixel electrode, the position of the TFT, and the connection manner are not specifically limited. Those skilled in the art can adopt the most reasonable setting manner according to actual conditions.
  • Embodiments of the present disclosure also provide a display device including any one of the above array substrates.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • Embodiments of the present disclosure provide an array substrate and a display device including a plurality of pixel units divided by intersecting gate lines and data lines, each of the pixel units including a first sub-pixel electrode and a second sub-pixel The electrodes are respectively driven by the first TFT and the second TFT.
  • the first sub-pixel electrode is connected to the drain of the first TFT
  • the second sub-pixel electrode is connected to the drain of the second TFT; wherein, the first TFT
  • the resistance between the source and the data line connected thereto is greater than the resistance between the source of the second TFT and the data line connected thereto; and/or the resistance between the drain of the first TFT and the first sub-pixel electrode It is larger than the resistance between the drain of the second TFT and the second sub-pixel electrode.

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Abstract

一种阵列基板及显示装置。其中，像素单元（01）包括第一子像素电极（11）和第二子像素电极（21），第一子像素电极（11）与第一TFT（12）的漏极相连，第二子像素电极（21）与第二TFT（22）的漏极相连；其中，第一TFT（12）的源极与其相连的数据线（03）之间的电阻大于第二TFT（22）的源极与其相连的数据线（03）之间的电阻；和/或，第一TFT（12）的漏极与第一子像素电极（11）之间的电阻大于第二TFT（22）的漏极与第二子像素电极（21）之间的电阻。

Description

一种阵列基板及显示装置
相关申请的交叉引用
本申请主张在2015年5月26日在中国提交的中国专利申请号No.201520349040.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及电子技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
在液晶显示装置中，电场作用下的液晶分子呈规则排列，使液晶表现出晶体属性，在光学上具有各向异性。具体的，若液晶分子均沿同一方向整齐地排列，则通过液晶向各个方向出射的光线是不同的，因此，由出射的光线构成的宏观画面在各个观察视角上也并不相同。随视角变化而画面保持不变的能力称为液晶显示装置的视角特性，对于视角特性较差(即可视角度较小)的液晶显示装置而言，在从较大的视角上观看时，可能产生对比度下降、黑白反转、色差等问题。
然而，观察者经常需要从较大的角度观看液晶显示装置，因此，需要提高液晶显示装置的视角特性。
发明内容
本公开提供一种阵列基板及显示装置，可提高液晶显示器的可视角度，同时降低阵列基板内TFT的结构复杂度。
为达到上述目的，本公开采用如下技术方案：
本公开提供一种阵列基板，所述阵列基板包括由交叉设置的栅线和数据线划分出的多个像素单元，
所述像素单元包括第一子像素电极、第二子像素电极、第一TFT和第二TFT；所述第一子像素电极与所述第一TFT的漏极相连，所述第二子像素电极与所述第二TFT的漏极相连；
其中，所述第一TFT的源极和与所述第一TFT相连的数据线之间的电阻大于所述第二TFT的源极和与所述第二TFT相连的数据线之间的电阻；和/或，所述第一TFT的漏极与所述第一子像素电极之间的电阻大于所述第二TFT的漏极与所述第二子像素电极之间的电阻。
进一步地，所述第一TFT的源极和与所述第一TFT相连的数据线之间通过折线状的源极线相连，所述第二TFT的源极和与所述第二TFT相连的数据线之间通过直线状的源极线相连；和/或，
所述第一TFT的漏极与所述第一子像素电极之间通过折线状的漏极线相连，所述第二TFT的漏极与所述第二子像素电极之间通过直线状的漏极线相连。
进一步地，与所述第一TFT的源极相连的源极线上设有第一分压电阻，和/或，
与所述第一TFT的漏极相连的漏极线上设有第二分压电阻。
进一步地，当与所述第一TFT的源极相连的源极线上设有第一分压电阻时，与所述第一TFT的源极相连的所述源极线包括间隔设置的第一源极段，所述第一分压电阻包括与所述第一源极段异层设置的第二源极段；其中，
所述第二源极段通过过孔与所述间隔设置的第一源极段连接；所述第二TFT的源极与所述第一源极段同层设置，或与所述第二源极段同层设置。
进一步地，所述第二源极段与所述第一子像素电极和/或所述第二子像素电极同层设置。
又或者，当与所述第一TFT的源极相连的源极线上设有第一分压电阻时，与所述第一TFT的源极相连的所述源极线包括第一源极段和第二源极段，所述第一分压电阻包括二极管组对，其中，
所述二极管组对的一端与所述第一源极段连接，所述二极管组对的另一端与所述第二源极段连接；所述二极管组对包括并联的正向二极管和反向二极管。
进一步地，所述正向二极管和所述反向二极管，是由两个薄膜晶体管分别短接形成的，其中，
所述正向二极管包括：第一短接源极、第一短接漏极和第一栅极区，其 中，所述第一短接源极与所述第一源极段相连，所述第一短接漏极与所述第二源极段相连，所述第一栅极区通过过孔与所述第一短接源极短接；
所述反向二极管包括：第二短接源极、第二短接漏极和第二栅极区，其中，所述第二短接源极与所述第一源极段相连，所述第二短接漏极与所述第二源极段相连，所述第二栅极区通过过孔与所述第二短接漏极短接。
进一步地，所述第一栅极区、所述第二栅极区均与所述第一TFT的栅极、所述第二TFT的栅极同层设置。
进一步地，在所述第一栅极区和所述第一短接源极之上分别形成过孔，且两过孔之上覆盖透明导电层连接；
在所述第二栅极区和所述第二短接漏极之上分别形成过孔，且两过孔之上覆盖透明导电层连接。
进一步地，当与所述第一TFT的漏极相连的漏极线上设有第二分压电阻时，与所述第一TFT的漏极相连的漏极线包括间隔设置的第一漏极段；所述第二分压电阻包括与所述第一漏极段异层设置的第二漏极段；所述第二漏极段通过过孔与所述间隔设置的第一漏极段连接。
进一步地，所述栅线上设置有不穿透的凹槽，所述凹槽的开口朝向所述第一子像素电极或所述第二子像素电极，所述第一TFT的源极线经过所述凹槽的底部与所述第一TFT的栅极交叠。
进一步地，所述凹槽在从所述第二子像素电极到所述第一子像素电极的方向上延伸且未穿透所述栅线。
进一步地，在同一所述像素单元中，所述第一TFT的源极与所述第二TFT的源极连接同一条数据线；所述第一TFT的栅极与所述第二TFT的栅极连接同一条栅线。
本公开还提供一种显示装置，包括上述任一种阵列基板。
本公开供一种阵列基板及显示装置，该阵列基板包括由交叉设置的栅线和数据线划分出的多个像素单元，每一个像素单元包括第一子像素电极和第二子像素电极，分别由第一TFT和第二TFT驱动，具体的，第一子像素电极与第一TFT的漏极相连，第二子像素电极与第二TFT的漏极相连，其中，第一TFT的源极与其相连的数据线之间的电阻大于第二TFT的源极与其相连的 数据线之间的电阻；和/或，第一TFT的漏极与第一子像素电极之间的电阻大于第二TFT的漏极与第二子像素电极之间的电阻。可以看出，对于每个像素单元而言，由于在第一TFT的源极或漏极串联有电阻进行分压，那么，在相同的驱动电压下，第一TFT的漏极处的输出电压小于第二TFT的漏极处的输出电压，进而，使得分别与第一TFT的漏极和第二TFT的漏极相连的子像素电极之间形成电压差，改变各对应液晶区域内的液晶分子的偏转角度，这样，在入射光透过同一像素单元对应的液晶区域时，出射光在不同方向上大致保持均匀，从而在不引入额外TFT的同时，提高了液晶显示器的可视角度，同时降低阵列基板内的结构复杂度。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的阵列基板上的像素单元结构的平面示意图一；
图2为本公开实施例提供的阵列基板上的像素单元结构的平面示意图二；
图3为本公开实施例提供的阵列基板上的像素单元结构的平面示意图三；
图4为本公开实施例提供的阵列基板上的像素单元结构的平面示意图四；
图5为本公开实施例提供的阵列基板上的像素单元结构的平面示意图五；
图6为本公开实施例提供的阵列基板上的像素单元结构的平面示意图六；
图7为本公开实施例提供的阵列基板上的像素单元结构的平面示意图七。
具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本公开。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本公开。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本公开的描述。
另外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本公开的实施例提供一种阵列基板，包括由交叉设置的栅线和数据线划分出的多个像素单元，具体的，本公开的实施例以一个像素单元进行举例说明。
如图1或图2所示，像素单元01包括第一子像素电极11和第二子像素电极21，第一子像素电极11和第二子像素电极21分别由第一TFT 12和第二TFT 22驱动，具体的，第一子像素电极11与第一TFT 12的漏极相连，第二子像素电极21与第二TFT 22的漏极相连，并且，第一TFT 12的栅极与第二TFT 22的栅极均与同一条栅线02相连，第一TFT 12的源极与第二TFT 22的源极均与同一条数据线03相连。
当然，第一TFT 12的栅极与所述第二TFT 22的栅极可以分别与不同栅线相连；第一TFT 12的源极与所述第二TFT 22的源极也可以分别与不同数据线相连，本公开对此不作任何限定。
其中，第一TFT 12的源极和与其相连的数据线03之间的电阻，大于第二TFT 22的源极和与其相连的数据线03之间的电阻；和/或，第一TFT 12的漏极与第一子像素电极11之间的电阻，大于第二TFT 22的漏极与第二子像素电极21之间的电阻。
具体的，如图1所示，相对于第二TFT 22的源极而言，第一TFT 12的源极与数据线03之间增设有第一分压电阻R1，由于数据线03施加的驱动电压相同，第一TFT 12的源极与数据线03的连接点A1处的电压等于第二TFT 22的源极与数据线03的连接点A2处的电压(UA1＝UA2)，那么，第一TFT 12的源极上B1处经过第一分压电阻R1的分压作用后，B1处的电压UB1＝UA1-IR(I为经过第一分压电阻R1的电流值)，而第二TFT 22的源极上B2处的电压UB2＝UA1，因此，UB2大于UB1，进一步地，由于第一子像素电极11充电后的充电电压与B1处的电压相同或接近，第二子像素电极21充电后的充电电压与B2处的电压相同或接近，而UB2＞UB1，因此，第一子像素 电极11的充电电压小于第二子像素电极21的充电电压，使得两子像素电极11、21对应的液晶畴区所受到的电场强度各不相同，最终使得两畴区内的液晶分子的偏转角度各不相同。
此时，虽然液晶仍具有光学上的各向异性，但两畴区的透光方向并不相同，两畴区出射的光线互相补充，就能够使出射光在各个方向上大致均匀。由于液晶显示装置在宏观上呈现的画面是从每个像素单元出射的光线在空间上的积分效果，因此，在本公开实施例中，从范围较广的任意视角观察均能够得到大致相同的画面效果，即液晶显示装置的可视角度得到提高，同时不额外增加TFT对子像素电极进行充放电控制。
又或者，如图2所示，相对于第二TFT 22的漏极而言，第一TFT 12的漏极与第一子像素电极11之间增设有第二分压电阻R2，与上述分析类似的，在相同的驱动电压下，由于第二分压电阻R2同样具有分压作用，因此，第一TFT 12的漏极处的充电电压小于第二TFT 22的漏极处的充电电压，进而使得两子像素电极11、12对应的液晶畴区所受到的电场强度各不相同，最终使得两畴区内的液晶分子的偏转角度各不相同。
需要说明的是，与上述分压原理类似的，也可以同时在第一TFT 12的源极与数据线03之间增设第一分压电阻R1，并在第一TFT 12的漏极与第一子像素电极11之间增设第二分压电阻R2，使得两子像素电极11、21对应的液晶畴区所受到的电场强度各不相同，最终使得两畴区内的液晶分子的偏转角度各不相同。
进一步地，第一TFT 12的源极可以通过折线状的源极线与数据线03相连，此时，第二TFT 22的源极通过直线状的源极线与数据线03相连，从而增加第一TFT 12的源极与数据线03之间的电阻，进而形成第一分压电阻R1。
类似的，第一TFT12的漏极也可以通过折线状的漏极线与第一子像素电极11相连，此时，第二TFT 22的漏极通过直线状的漏极线与第二子像素电极21相连，从而增加第一TFT 12的漏极与第一子像素电极11之间的电阻，进而形成第二分压电阻R2。
示例性的，如图3所示，以第一TFT 12的源极通过折线状的源极线与数据线03相连为例，所述像素单元01具体包括第一子像素电极11和第二子像 素电极21，第一子像素电极11和第二子像素电极21分别位于一条栅线02的两侧，以及一条所述数据线03的同侧；直接以栅线02作为两TFT的栅极，并且，第一TFT与数据线03之间通过源极线13相连，源极线13采用折线状设计，从数据线03向所述第一子像素电极11延伸，在栅线02上形成第一源极14；第二TFT通过直线状的源极线与数据线03相连，从数据线03向第二子像素电极21延伸，在栅线02上形成第二源极23，对应第一源极14和第二源极23分别形成第一漏极15和第二漏极24，第一漏极15通过过孔与第一子像素11电极电性连接，第二漏极24通过过孔与第二子像素电极21电性连接。
这样，在相同的驱动电压下，由于折线状的第一TFT源极线13形成第一分压电阻R1，具有分压作用，使得第一TFT的第一漏极15处的输出电压小于第二TFT的第二漏极24处的输出电压，进而，使得分别与第一TFT的漏极和第二TFT的漏极相连的子像素电极之间形成电压差。
当然，与图3中所示的像素单元01类似的，该第一TFT 12的漏极也可以通过折线状的漏极线与第一子像素电极11相连，具体的，可以参照图3，与第一TFT 12相连的源极线13类似的，可以将第一TFT 12中与漏极15连接的漏极线也设计为折线状，形成第二分压电阻R2，这样，由于第二分压电阻R2同样具有分压作用，可以使分别与第一TFT的漏极和第二TFT的漏极相连的子像素电极之间形成电压差。
需要说明的是，本公开并未对TFT的连接关系以及形状类型进行特别限定，例如：两TFT的连接关系可为两源级背对连接，对应的漏极位于背对连接的两源级的两侧，或两源级并列排列，在两源级的同侧设置对应的两漏极；TFT可为源级呈长条状的I型TFT，也可为源级呈U字状的U型TFT，本领域技术人员可以根据实际情况采用最合适的TFT的连接关系和形状类型。
作为对上述实施例的一种改进，如图4所示，还可以在栅线02上设置不穿透的凹槽41。在一实施例中，凹槽41在从第二子像素电极21到第一子像素电极11的方向上延伸且未穿透栅线02。凹槽41的开口朝向第一子像素电极11或第二子像素电极21。第一TFT的源极线13上经过所述凹槽41的底部的部分与第一TFT的栅极交叠，而第一TFT的源极线13的其他部分均不 与第一TFT的栅极交叠，以使得栅线02与第一TFT的源极线13的交叠面积减小，这样，可以减小栅线02与源极线13之间耦合电容的干扰。
进一步地，在本公开实施例的另一种可能的实现方式中，第一TFT的源极和与其相连的数据线之间可以具体包括：间隔设置的第一源极段，以及与所述第一源极段异层设置的第二源极段，其中，所述第二源极段通过过孔与所述间隔设置的第一源极段连接；所述第二TFT的源极与所述第一源极段同层设置，或与所述第二源极段同层设置。
示例性的，如图5所示，在图4所示的像素单元结构的基础上，第一TFT的源极线13上设置一处或多处断开，此时，第一TFT的源极14与数据线03之间具体包括：间隔设置的第一源极段131，以及与所述第一源极段异层设置的第二源极段132，第二源极段132通过过孔补接在间隔设置的第一源极段131上，在该实施方式中，以栅线02为中线设置像素单元01，两子像素电极11、21均和栅线02和数据线03相邻，直接以栅线02作为两TFT的栅极，这些设置均能够最大程度地减短连接线路(如栅极和栅线之间的线路，数据线和源极之间的线路，子像素电极和漏极之间的线路)，简化各功能层的构图工艺。
其中，该第二源极段132可以具体为ITO材料制成的ITO电阻，这样，该第二源极段132与第一子像素电极11和/或第二子像素电极21可以同层设置，不增加制作阵列基板所使用的构图工艺的次数。
当然，第二源极段132还可以由电阻阻值较大的其他材料制成，此时，第二源极段132与第一子像素电极11和/或第二子像素电极21为异层设置，因此，在形成第一TFT和第二TFT的源漏极之后，单独使用一次构图工艺的将第二源极段132补接在间隔设置的第一源极段131上。
需要说明的是，与图4中所示的像素单元01类似的，还可以在第一TFT的漏极与第一子像素电极之间设置间隔的第一漏极段，以及与第一漏极段异层设置的第二漏极段，进而形成第二分压电阻R2，这样，由于第二分压电阻R2同样具有分压作用，可以使分别与第一TFT的漏极和第二TFT的漏极相连的子像素电极之间形成电压差。
又或者，在本公开实施例的另一种可能的实现方式中，第一TFT的源极 和与其相连的数据线之间可以具体包括：二极管组对、第一源极段和第二源极段，所述二极管组对的一端与所述第一源极段连接，所述二极管组对的另一端与所述第二源极段连接；其中，由于二极管具有单方向导电性，因此，为保证数据线在提供高电压或低电压时第一TFT均能导通，所述二极管组对包括并联的正向二极管和反向二极管。
进一步地，上述二极管组对的形成方法有多种，示例性的，本实施例以两个TFT短接的方式形成该二极管组对进行说明。
此时，如图6所示，正向二极管与反向二极管组成所述二极管组对，二极管组对的一端与第一源极段53连接，二极管组对的一端与第二源极段54连接，其中，该正向二极管包括：第一短接源极61、第一短接漏极62和第一栅极区63(所述第一栅极区63与第一TFT的栅极同层设置)，其中，第一短接源极61与第一源极段53相连，第一短接漏极62与第二源极段54相连，第一栅极区63通过过孔与第一短接源极61短接；该反向二极管包括：第二短接源极71、第二短接漏极72和第二栅极区73(所述第二栅极区73与第一TFT的栅极同层设置)，其中，第二短接源极71与第一源极段53相连，第二短接漏极72与第二源极段54相连，第二栅极区73通过过孔与第二短接漏极72短接。
与图6对应的，通过TFT短接形成正向二极管和反向二极管的方法可以有多种，本领域技术人员可根据实际情况采用最合理的设置方式，例如，如图7所示，在正向二极管和反向二极管上设置有ITO层，通过过孔81使ITO层与第一短接源极61电连接，并通过过孔82使ITO层与第一栅极区63电连接，以实现第一栅极区63与第一短接源极61的短接，进而形成正向二极管；相应的，可同样使用上述方法形成反向二极管，这样，无需额外增加制作阵列基板所使用的构图工艺的次数，便可在第一TFT的源极处形成第一分压电阻R1。
需要说明的是，对于第一TFT的漏极也可以使用上述相同的方法，在第一TFT的漏极15处形成正向二极管和反向二极管，进而形成第二分压电阻R2，这样，由于第二分压电阻R2同样具有分压作用，进而保证与第一TFT的漏极和第二TFT的漏极相连的子像素电极之间形成电压差。
进一步地，由于TFT处于开态时(向栅极施加电压使有源层导通时)可等效为一个电阻，此时TFT的阻值由TFT的宽长比决定，其中，宽长比是TFT的一个固有属性，一般写作W/L，W和L分别代表沟道的宽和长，如公式(1)所示，TFT的宽长比W1/L1与其阻值具有相关性，即：
Figure PCTCN2015093562-appb-000001
其中，Ron为TFT导通时的阻值，VGs1为栅极和源极间的电位差，Vth1为电荷对半导体层导带的起始受激电压，即阈值电压。Cox＝ε0εox/dox，式中Cox是栅绝缘层单位面积的电容，ε0是真空介电常数、εox为栅绝缘层介电常数、dox为栅绝缘层的厚度。μn代表半导体的电子迁移率。由该关系式可知，TFT导通时的阻值与宽长比W1/L1成反比。
由于TFT进行短接后形成的正向二极管或反向二极管仍具有上述特性，因此，可以通过调整正向二极管和/或反向二极管的宽长比W1/L1，控制正向二极管和/或反向二极管的阻值，进而控制分压电阻的阻值，使得两子像素电极对应的液晶畴区所受到的电场强度各不相同，最终使得两畴区内的液晶分子的偏转角度各不相同，使出射光在各个方向上保持均匀，提高液晶显示装置的视角特性。
需要说明的是，上述实施例中均以第一TFT的源极相对于第二TFT的源极而言，与数据线之间增设有第一分压电阻为例进行说明，应当理解的是，第一TFT的漏极相对于第二TFT的漏极而言，与第一子像素电极之间增设有第二分压电阻的设计方案与上述实施例中的涉及方案类似，故此处不再赘述。
进一步地，为了尽可能使出射光在所有方向上保持均匀，可选同一像素单元中的第一子像素电极的充电电压与所述第二子像素电极的充电电压的差值在0-0.5V范围内。该电压差值使对应的两液晶畴区具有最优化的偏转角度差值，进而能够使出射光在各个方向上更为均匀，从而在宏观的各个方向上获得更一致的画面效果，提高液晶显示装置的视角特性。
可以理解的是，本公开并未特殊限定同一像素电极中两子像素电极的充电电压差值，即使将上述两差值设定在其他范围内，只要能够使出射光在各个方向上保持均匀，则仍属于本公开的保护范围。
还需要说明的是，上述实施方式的目的在于提供较为优化的基板元器件 的设置思路，本公开并未对子像素电极、TFT的位置以及连接方式进行特殊限定，本领域技术人员可根据实际情况采用最合理的设置方式。
本公开的实施例还提供了一种显示装置，其包括上述任意一种阵列基板。其中，所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，本公开提供的显示装置所包括的阵列基板并不限于上述任一实施例，本领域技术人员可根据实际情况将上述任意实施例组合或变化，以制造具有良好的视角特性、且适于生产和使用的液晶显示装置。
本公开的实施例提供一种阵列基板及显示装置，该阵列基板包括由交叉设置的栅线和数据线划分出的多个像素单元，每一个像素单元包括第一子像素电极和第二子像素电极，分别由第一TFT和第二TFT驱动，具体的，第一子像素电极与第一TFT的漏极相连，第二子像素电极与第二TFT的漏极相连；其中，第一TFT的源极和与其相连的数据线之间的电阻大于第二TFT的源极和与其相连的数据线之间的电阻；和/或，第一TFT的漏极与第一子像素电极之间的电阻大于第二TFT的漏极与第二子像素电极之间的电阻。可以看出，对于每个像素单元而言，由于在第一TFT的源极或漏极设有分压电阻进行分压，那么，在相同的驱动电压下，第一TFT的漏极处的输出电压小于第二TFT的漏极处的输出电压，进而，使得分别与第一TFT的漏极和第二TFT的漏极相连的子像素电极之间形成电压差，改变各对应液晶区域内的液晶分子的偏转角度，这样，在入射光透过同一像素单元对应的液晶区域时，出射光在不同方向上大致保持均匀，从而在不引入额外TFT的同时，提高了液晶显示器的可视角度，同时降低阵列基板内的结构复杂度。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种阵列基板，包括由交叉设置的栅线和数据线划分出的多个像素单元，
    所述像素单元包括第一子像素电极、第二子像素电极、第一TFT和第二TFT；所述第一子像素电极与所述第一TFT的漏极相连，所述第二子像素电极与所述第二TFT的漏极相连；
    其中，所述第一TFT的源极和与所述第一TFT相连的数据线之间的电阻，大于所述第二TFT的源极和与所述第二TFT相连的数据线之间的电阻；和/或，所述第一TFT的漏极与所述第一子像素电极之间的电阻，大于所述第二TFT的漏极与所述第二子像素电极之间的电阻。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一TFT的源极和与所述第一TFT相连的数据线之间通过折线状的源极线相连，所述第二TFT的源极和与所述第二TFT相连的数据线之间通过直线状的源极线相连；和/或，
    所述第一TFT的漏极与所述第一子像素电极之间通过折线状的漏极线相连，所述第二TFT的漏极与所述第二子像素电极之间通过直线状的漏极线相连。
  3. 根据权利要求1或2所述的阵列基板，其中，
    与所述第一TFT的源极相连的源极线上设有第一分压电阻，和/或，
    与所述第一TFT的漏极相连的漏极线上设有第二分压电阻。
  4. 根据权利要求3所述的阵列基板，其中，当与所述第一TFT的源极相连的源极线上设有第一分压电阻时，与所述第一TFT的源极相连的所述源极线包括间隔设置的第一源极段，所述第一分压电阻包括与所述第一源极段异层设置的第二源极段；其中，
    所述第二源极段通过过孔与所述间隔设置的第一源极段连接；所述第二TFT的源极与所述第一源极段同层设置或与所述第二源极段同层设置。
  5. 根据权利要求4所述的阵列基板，其中，所述第二源极段与所述第一子像素电极和/或所述第二子像素电极同层设置。
  6. 根据权利要求3所述的阵列基板，其中，当与所述第一TFT的源极相连的源极线上设有第一分压电阻时，与所述第一TFT的源极相连的所述源极线包括第一源极段和第二源极段，所述第一分压电阻包括二极管组对，其中，
    所述二极管组对的一端与所述第一源极段连接，所述二极管组对的另一端与所述第二源极段连接；所述二极管组对包括并联的正向二极管和反向二极管。
  7. 根据权利要求6所述的阵列基板，其中，所述正向二极管和所述反向二极管，是由两个薄膜晶体管分别短接形成的，其中，
    所述正向二极管包括：第一短接源极、第一短接漏极和第一栅极区，其中，所述第一短接源极与所述第一源极段相连，所述第一短接漏极与所述第二源极段相连，所述第一栅极区通过过孔与所述第一短接源极短接；
    所述反向二极管包括：第二短接源极、第二短接漏极和第二栅极区，其中，所述第二短接源极与所述第一源极段相连，所述第二短接漏极与所述第二源极段相连，所述第二栅极区通过过孔与所述第二短接漏极短接。
  8. 根据权利要求7所述的阵列基板，其中，所述第一栅极区、所述第二栅极区均与所述第一TFT的栅极、所述第二TFT的栅极同层设置。
  9. 根据权利要求7所述的阵列基板，其中，
    在所述第一栅极区和所述第一短接源极之上分别形成过孔，且两过孔之上覆盖透明导电层连接；
    在所述第二栅极区和所述第二短接漏极之上分别形成过孔，且两过孔之上覆盖透明导电层连接。
  10. 根据权利要求3所述的阵列基板，其中，当与所述第一TFT的漏极相连的漏极线上设有第二分压电阻时，与所述第一TFT的漏极相连的漏极线包括间隔设置的第一漏极段；所述第二分压电阻包括与所述第一漏极段异层设置的第二漏极段；所述第二漏极段通过过孔与所述间隔设置的第一漏极段连接。
  11. 根据权利要求2所述的阵列基板，其中，所述栅线上设置有不穿透的凹槽，所述凹槽的开口朝向所述第一子像素电极或所述第二子像素电极， 所述第一TFT的源极线经过所述凹槽的底部与所述第一TFT的栅极交叠。
  12. 根据权利要求11所述的阵列基板，其中，所述凹槽在从所述第二子像素电极到所述第一子像素电极的方向上延伸且未穿透所述栅线。
  13. 根据权利要求1至12中任一项所述的阵列基板，其中，在同一所述像素单元中，所述第一TFT的源极与所述第二TFT的源极连接同一条数据线；所述第一TFT的栅极与所述第二TFT的栅极连接同一条栅线。
  14. 一种显示装置，其中，包括如权利要求1-13中任一项所述的阵列基板。
PCT/CN2015/093562 2015-05-26 2015-11-02 一种阵列基板及显示装置 WO2016188036A1 (zh)

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RU2710381C2 (ru) 2019-12-26
BR112017000086B1 (pt) 2022-07-12
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