WO2017113958A1 - 阵列基板、显示装置及其驱动方法 - Google Patents

阵列基板、显示装置及其驱动方法 Download PDF

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Publication number
WO2017113958A1
WO2017113958A1 PCT/CN2016/103246 CN2016103246W WO2017113958A1 WO 2017113958 A1 WO2017113958 A1 WO 2017113958A1 CN 2016103246 W CN2016103246 W CN 2016103246W WO 2017113958 A1 WO2017113958 A1 WO 2017113958A1
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Prior art keywords
gate
line
thin film
film transistor
array substrate
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PCT/CN2016/103246
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English (en)
French (fr)
Inventor
赵剑
蒋学兵
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/521,052 priority Critical patent/US10089944B2/en
Publication of WO2017113958A1 publication Critical patent/WO2017113958A1/zh

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133397—Constructional arrangements; Manufacturing methods for suppressing after-image or image-sticking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0266—Reduction of sub-frame artefacts

Definitions

  • the present disclosure relates to an array substrate, a display device, and a method of driving the same.
  • afterimage has been widely concerned for a long time.
  • a display device such as a liquid crystal display (LCD) panel
  • LCD liquid crystal display
  • a residual image appears on the screen when switching to another screen due to the influence of a long electric field.
  • the main cause of the afterimage is that the display device introduces some charged ions into the display device during the manufacturing process and the manufacturing materials.
  • the charged ions are separated by the external electric field.
  • An internal electric field is formed.
  • the internal electric field generated by the charged particles causes the display device to remain on the previous screen, resulting in a residual image.
  • the peripheral afterimage is an afterimage that often occurs in display devices.
  • One of the main causes of the peripheral image is that the sealant in the peripheral area of the LCD panel causes contamination of the liquid crystal molecules inside the LCD panel.
  • the charged ions generated by the pollution are distributed in the peripheral area of the LCD panel.
  • Embodiments of the present disclosure provide an array substrate, a display device, and a driving method thereof, which can effectively solve the problem of peripheral afterimages and improve the display quality of the display device.
  • An embodiment of the present disclosure provides an array substrate, including: a substrate substrate; a plurality of gate lines and a plurality of data lines disposed laterally across the substrate substrate; a control circuit; and at least a portion of the gate lines a plurality of gate line extension lines connected by the control circuit; and a plurality of data line extension lines connected to the at least a portion of the data lines through the control circuit, wherein the control circuit is configured to display an image of one frame Controlling the gate line and the gate line extension line to conduct, controlling the data line and the data line extension line to be turned on; and controlling the gate line and the gate during a period of time between displaying adjacent two frames of images
  • the line extension line is disconnected, the data line and the data line extension line are controlled to be disconnected, at least a portion of the gate line extension line is controlled to have a potential difference, and at least a portion of the data line extension line is controlled to have a potential difference.
  • the gate line extension lines are respectively disposed at two ends of each of the gate lines and are in one-to-one correspondence with the gate lines
  • the data line extension lines are respectively disposed on Both ends of each of the data lines are in one-to-one correspondence with the data lines.
  • an array substrate provided by an embodiment of the present disclosure includes a display area and a peripheral area surrounding the display area, wherein the gate line and the data line are disposed in the display area, the gate line extension line, The data line extension line and the control circuit are both disposed in the peripheral area.
  • control circuit is configured to control disconnection of the gate line and the gate line extension line during a period of time between displaying adjacent two frames of images, and control the The data line and the data line extension line are disconnected, the adjacent two rows of the gate line extension lines are controlled to have a potential difference, and the adjacent two lines of the data line extension lines are controlled to have a potential difference.
  • the control circuit includes a first control circuit and a second control circuit; the first control circuit is configured to control the gate line and when displaying one frame of image Conducting between the extension lines of the gate lines, controlling conduction between the data lines and the extension lines of the data lines; controlling the discontinuity of the gate lines and the extension lines of the gate lines during a period between displaying images of two adjacent frames Opening and controlling disconnection between the data line and the data line extension line; the second control circuit is configured to control adjacent two rows of the gate line extension line during a period of time between displaying adjacent two frames of images There is a potential difference between them, and there is a potential difference between the adjacent two rows of the data line extension lines.
  • the first control circuit includes a first switching thin film transistor and a second switching thin film transistor; the first switching thin film transistor is configured to control when displaying one frame of image The gate line and the gate line extension line are turned on, and the gate line and the gate line extension line are controlled to be disconnected during a period between displaying adjacent two frames of images; the second switching transistor is Configuring to control the data line and the data line extension line to be turned on when displaying one frame of image, and controlling the data line and the data line extension line during a period of time between displaying adjacent two frames of images disconnect.
  • the source of the first switching thin film transistor is connected to the gate line extension line, the drain is connected to the gate line, and the gate is used to access the first voltage.
  • the source of the second switching thin film transistor is connected to the data line extension line, the drain is connected to the data line, and the gate is used to access the second voltage.
  • the second control circuit includes a third switching thin film transistor and a fourth switching thin film transistor; the third switching thin film transistor is configured to display adjacent two frames of images.
  • the gate line extension line located in the interval row is placed in a high voltage state during a period of time; the fourth switching thin film transistor is configured to control the interval at a time interval between displaying adjacent two frames of images
  • the data line extension of the row is placed in a high voltage state.
  • the drain of the third switching thin film transistor is connected to the gate line extension line located in the interval row, and the gate is used to access the third voltage, the source and the gate.
  • the drain of the fourth switching thin film transistor is connected to the data line extension line located in the spaced row, the gate is used to access the fourth voltage, and the source and the gate are connected.
  • the second control circuit further includes a fifth switching thin film transistor and a sixth switching thin film transistor;
  • the fifth switching thin film transistor is configured to display adjacent two frames of images Controlling, in a period of time, other gate line extension lines other than the connection of the third switching thin film transistor are placed in a low voltage state;
  • the sixth switching thin film transistor is configured to display between adjacent two frames of images During the period of time, the control data line extension other than the fourth switching thin film transistor is placed in a low voltage state.
  • the drain of the fifth switching thin film transistor is connected to other gate line extension lines other than the third switching thin film transistor, and the source is used for low access.
  • the gate is used to access the sixth voltage.
  • An embodiment of the present disclosure further provides a display device including an array substrate, a counter substrate, and a voltage control circuit, wherein the array substrate is the array substrate according to any one of the above; the voltage control circuit
  • the array substrate is the array substrate according to any one of the above; the voltage control circuit
  • the image of one frame is displayed, inputting a first control signal to the control circuit in the array substrate, causing the gate line and the gate line extension line in the array substrate to be turned on, and extending the data line and the data line extension line Transmitting a second control signal to the control circuit in the array substrate during a period between displaying adjacent two frames of images to cause the gate line in the array substrate and the Disconnecting the gate line extension line, disconnecting the data line and the data line extension line, and inputting a third control signal to the control circuit in the array substrate to extend the adjacent two rows of the gate lines There is a potential difference between the lines, so that there is a potential difference between the adjacent two rows of the data line extension lines.
  • the first voltage end of the voltage control circuit is connected to the gate of the first switching thin film transistor in the array substrate; the second voltage end of the voltage control circuit Connected to the gate of the second switching thin film transistor in the array substrate.
  • the first voltage terminal and the second voltage terminal are the same port, and the port is respectively connected to the gate of the first switching thin film transistor through the first control line. Connected to the gate of the second switching thin film transistor.
  • the third voltage terminal of the voltage control circuit is connected to the gate of the third switching thin film transistor in the array substrate; the fourth voltage terminal of the voltage control circuit Connected to a gate of a fourth switching thin film transistor in the array substrate.
  • the third voltage terminal and the fourth voltage terminal are the same port, and the port is respectively connected to the gate and the third of the third switching thin film transistor through the second control line.
  • the gate of the four-switch thin film transistor is connected.
  • the fifth voltage terminal of the voltage control circuit is connected to the gate of the fifth switching thin film transistor in the array substrate; the sixth voltage terminal of the voltage control circuit Connected to a gate of a sixth switching thin film transistor in the array substrate.
  • the fifth voltage terminal and the sixth voltage terminal are the same port, and the port is respectively connected to the gate and the fifth of the fifth switching thin film transistor through the third control line.
  • the gate of the six-switch thin film transistor is connected.
  • a black matrix is disposed on the array substrate or the opposite substrate, and at least a portion of the orthographic projection of the black matrix on the substrate substrate covers the periphery of the array substrate. region.
  • the embodiment of the present disclosure further provides a driving method of any one of the above display devices, comprising: turning on a gate line, a gate line extension line, and a conduction data line in response to a first control signal when displaying one frame of image And a data extension line; disconnecting the gate line and the gate line extension line, disconnecting the data line, and the data in response to a second control signal during a period between displaying adjacent two frames of images An extension line; in response to the third control signal, controlling a potential difference between the adjacent two rows of the gate line extension lines and controlling a potential difference between the adjacent two rows of the data line extension lines.
  • adjacent two rows of gate line extension lines and adjacent two rows of data line extension lines are respectively introduced into, for example, a pole by control of the control circuit.
  • the opposite voltage causes a voltage potential to adsorb positive and negative charged ions in the peripheral region of the array substrate, thereby effectively solving the problem of residual images around the display device and improving the display quality of the display device.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a third schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • Figure 5 is a timing chart showing the operation of the display device of Figure 4.
  • 6a is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure, after adsorbing ions along the line A-A' in FIG. 4;
  • FIG. 6b is a cross-sectional structural view of the display device according to the embodiment of the present disclosure after adsorbing ions along the line B-B' in FIG. 4;
  • FIG. 7 is a second schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • Figure 8 is a timing chart showing the operation of the display device of Figure 7;
  • FIG. 9 is a flowchart of a driving method of a display device according to an embodiment of the present disclosure.
  • the source and drain of the switching thin film transistor used in all embodiments of the present disclosure are symmetrical, so that the source and the drain are interchangeable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain.
  • the array substrate includes: a substrate substrate; a plurality of gate lines 1 and a plurality of data lines 2 disposed on the substrate substrate; a plurality of gate line extension lines 3 connected to at least a portion of the gate lines 1 through the control circuit; and a plurality of data line extension lines 4 connected to the at least part of the data lines 2 through the control circuit, the control circuit being configured to display a frame In the image, the control gate line 1 and the gate line extension line 3 are turned on, the control data line 2 and the data line extension line 4 are turned on (electrical connection); and in a period of time between displaying adjacent two frames of images (ie, After the current frame image is displayed, the non-display period before the next frame image is displayed), the control gate line 1 and the gate line extension line 3 are disconnected (no longer electrically connected), the control data line 2 and the data line extension line 4 are disconnected. And controlling at least a portion of the gate line extension lines 3 to have a potential difference
  • the gate line extension lines 3 are respectively disposed at two ends of each of the gate lines 1 and are in one-to-one correspondence with the gate lines 1.
  • the data line extension lines 4 are respectively disposed at both ends of each of the data lines 2 and are connected to the data lines 2, respectively. correspond.
  • the array substrate includes a display area and a peripheral area surrounding the display area, the gate line 1 and the data line 2 are disposed in the display area, and the gate line extension line 3, the data line extension line 4, and the control circuit are disposed in the peripheral area.
  • control circuit is configured to control the gate during a time period between displaying two adjacent frames of images
  • the line 1 and the gate line extension line 3 are disconnected, the control data line 2 and the data line extension line 4 are disconnected, the potential difference between the adjacent two rows of gate line extension lines 3 is controlled, and the adjacent two rows of data line extension lines are controlled. There is a potential difference between them.
  • the array substrate provided by the embodiment of the present disclosure includes but is not limited to the case illustrated in FIG. 1 .
  • the gate line extension line may be disposed only at one end or both ends of the partial gate line, and the data line extension line may also be disposed only at one or both ends of the partial data line.
  • the control circuit may be configured to have a potential difference between the control portion of the gate line extension lines and a potential difference between the control portion data line extension lines during a period of time between displaying adjacent two frames of images. That is to say, there is necessarily a potential difference between the extension lines of the gate lines of each adjacent two rows, and there is necessarily a potential difference between the extension lines of the data lines of each adjacent two rows.
  • the peripheral region of the array substrate is provided with a gate line extension line, a data line extension line, and a control circuit, and then a display device is formed, when displaying one frame of image, control is performed.
  • Conducting between the circuit control gate line and the gate line extension line, and controlling conduction between the data line and the data line extension line, and the gate driver transmits the gate scan signal to the gate line through the gate line extension line, and is passed by the data driver
  • the data line extension line transmits the data signal to the data line, thereby displaying the picture normally; after the normal display is completed, the control circuit controls the disconnection between the gate line and the gate line extension line during the period between displaying the adjacent two frames of images.
  • the control circuit controls the adjacent two rows of gate line extension lines to have a potential difference, and controlling the adjacent two rows of data line extension lines to have a potential difference, such that the control circuit is Control, the adjacent two rows of gate line extension lines and the adjacent two rows of data line extension lines are respectively introduced into different voltages (for example, high voltage and low).
  • the voltage or the opposite polarity voltage causes a voltage potential to adsorb positive and negative charged ions in the peripheral region of the display device, thereby effectively solving the problem of residual images around the display device and improving the display quality of the display device.
  • the control circuit includes a first control circuit (the dotted line frame mark 100 is a part of the first control circuit) and a second control circuit (marked by a broken line frame).
  • the portion 200 is a part of the second control circuit;
  • the first control circuit is configured to control the conduction between the gate line and the gate line extension line when displaying one frame of image, and control the conduction between the data line and the data line extension line
  • the control gate line and the gate line extension line are disconnected, and the control data line and the data line extension line are disconnected during the period between displaying the adjacent two frames of images;
  • the second control circuit is used; Controlling adjacent two in a period of time between displaying adjacent two frames of images
  • the gate line extension line of the row has a potential difference
  • the data line extension line controlling the adjacent two rows has a potential difference.
  • the first control circuit includes a first switching thin film transistor 101 and a second switching thin film transistor 102; the first switching thin film transistor 101 is used to display one In the frame image, the control gate line and the gate line extension line are turned on, and after the normal display is completed, the control gate line and the gate line extension line are disconnected during the period between displaying the adjacent two frames of images;
  • the switching transistor 102 is configured to control conduction between the data line and the data line extension line when displaying one frame of image, and control the extension of the data line and the data line during a period of time between displaying adjacent two frames of images The line is disconnected.
  • the source of the first switching thin film transistor 101 is connected to the gate line extension 3, the drain is connected to the gate line 1, and the gate is used for connection.
  • the first voltage is applied;
  • the source of the second switching thin film transistor 102 is connected to the data line extension line 4, the drain is connected to the data line 2, and the gate is used to access the second voltage. Therefore, the first switching thin film transistor 101 can control the gate line 1 to be connected or disconnected from the gate line extension line 3, and the second switching thin film transistor 102 can control the data line 2 to be connected or disconnected from the data line extension line 4.
  • the first switching thin film transistor and the second switching thin film transistor can be kept in an open state, that is, the gate line extension line is kept in communication with the gate line, and the data line extension line is connected to the data line to complete normal display of the frame image.
  • the first switching thin film transistor and the second switching thin film transistor are turned off, that is, the gate line extension line is disconnected from the gate line, and the data line extension line is disconnected from the data line.
  • the gate line extension line and the data line extension line not connected to the second control circuit can be left floating, which is equivalent to being in a low voltage state.
  • the second control circuit includes a third switching thin film transistor 201 and a fourth switching thin film transistor 202; and the third switching thin film transistor 201 is used for displaying phase During a period between two adjacent frames of images, the gate line extension line that controls the interval line is placed in a high voltage state; and the fourth switching thin film transistor 202 is configured to control the time period between displaying two adjacent frames of images.
  • the data line extension of the spaced row is placed in a high voltage state.
  • the low voltage in the embodiment of the present disclosure is, for example, 0 V
  • the high voltage is, for example, 5 V.
  • the drain of the third switching thin film transistor 201 is connected to the gate line extension line 3 located in the spaced row, and the gate is used to access the third voltage.
  • the source and the gate are connected;
  • the drain of the fourth switching thin film transistor 202 is connected to the data line extension line 4 located in the spaced row, the gate is used to access the fourth voltage, and the source and the gate are connected.
  • the gate line extension line of the interval line may be a gate line extension line located in an odd row or a gate line extension line of an even row, and the data line extension line of the same interval row may be extended for the data line located in an odd row. Lines can also be data line extensions for even rows.
  • the voltage state of the gate line extension line and the data line extension line output in the odd/even line can be controlled by the third switching thin film transistor and the fourth switching thin film transistor, and during the period between displaying the adjacent two frames of images,
  • the gate line extension line and the data line extension line that respectively connect the third switching thin film transistor and the fourth switching thin film transistor are respectively placed in a high voltage state.
  • the second control circuit may further include a fifth switching thin film transistor 203 and a sixth switching thin film transistor 204; and the fifth switching thin film transistor 203 is used in During the period between displaying adjacent two frames of images, the control gate extension lines other than the third switching thin film transistor 201 are controlled to be placed in a low voltage state; the sixth switching thin film transistor 204 is for displaying adjacent two frames During the period between images, the control data extension lines other than the fourth switching thin film transistor 202 are controlled to be placed in a low voltage state.
  • the drain of the fifth switching thin film transistor 203 is connected to other gate line extension lines 3 other than the third switching thin film transistor 201.
  • the pole is used to connect to the low voltage, the gate is used to access the fifth voltage;
  • the drain of the sixth switching thin film transistor 204 is connected to the other data line extension line 4 except the fourth switching thin film transistor 202, and the source is used.
  • the gate is used to access the sixth voltage.
  • the drain of the third switching thin film transistor is connected to the gate line extension line located in the odd row, the other gate line extension lines other than the third switching thin film transistor are the gate line extension lines located in the even rows.
  • the other gate line extension lines other than the third switching thin film transistor are the gate line extension lines located in the odd rows, for the same reason.
  • the data line extension line other than the fourth switching thin film transistor is the data line extension line located in the even row, when the fourth switch When the drain of the thin film transistor is connected to the data line extension line located in the even rows, the data line extension lines other than the fourth switching thin film transistor are the data line extension lines located in the odd rows.
  • the first switching thin film transistor and the second switching thin film transistor are turned off during the period between displaying the adjacent two frames of images, and the third switching thin film transistor, the fourth thin film transistor thin film transistor, the fifth switching thin film transistor and the third switching thin film transistor are turned on.
  • a sixth switching thin film transistor capable of placing a gate line extension line and a data line extension line connecting the fifth switching thin film transistor and the sixth switching thin film transistor at a low level In the pressed state, the ability of the formed electric field to adsorb ions can be improved, and the ability to improve the peripheral afterimage is further improved.
  • the first switching thin film transistor, the second switching thin film transistor, the third switching thin film transistor, the fourth switching thin film transistor, the fifth switching thin film transistor, and the sixth switching thin film transistor can be combined with the switching film of the display region.
  • the transistors are prepared by the same process, that is, they can be formed simultaneously, which simplifies the manufacturing process and saves costs.
  • the array substrate provided by the embodiment of the present disclosure further includes an insulating layer, a passivation layer, an alignment film, and the like, and a structure such as a common electrode line is formed on the substrate, and the specific structures may be various.
  • the implementation method is not limited here.
  • an embodiment of the present disclosure further provides a display device, as shown in FIG. 4, including an array substrate of any of the above modes, an opposite substrate disposed opposite the array substrate, and a voltage control circuit 300.
  • a display device as shown in FIG. 4, including an array substrate of any of the above modes, an opposite substrate disposed opposite the array substrate, and a voltage control circuit 300.
  • the display device can be a display panel.
  • the voltage control circuit 300 is configured to input a first control signal to the control circuit in the array substrate when the image of one frame is displayed, to turn on between the gate line 1 and the gate line extension 3 in the array substrate, and the data line 2 And the data line extension line 4 is turned on, and the display device can display the picture normally; after completing the display of the frame image, inputting to the control circuit in the array substrate during the time period between displaying the adjacent two frames of images a second control signal for disconnecting between the gate line 1 and the gate line extension 3 in the array substrate, and disconnecting between the data line 2 and the data line extension line 4, and inputting a third control signal to the control circuit in the array substrate,
  • the adjacent two rows of gate line extension lines 3 have a potential difference
  • the adjacent two rows of data line extension lines 4 are controlled to have a potential difference.
  • the first voltage terminal 5 of the voltage control circuit 300 is connected to the gate of the first switching thin film transistor 101 in the array substrate, the first voltage.
  • the terminal outputs a first voltage for controlling the first switching thin film transistor 101 to be turned on when displaying one frame of image, and the gate line and the gate line extension line are turned on at the same time, and after displaying the normal display, displaying the adjacent two frames of images
  • the first switching thin film transistor 101 is controlled to be turned off, and the gate line and the gate line extension line are disconnected at this time;
  • the second voltage terminal 6 of the voltage control circuit 300 and the second switching thin film transistor 102 in the array substrate The second voltage terminal 6 outputs a second voltage for controlling the second switching thin film transistor 102 to be turned on when displaying one frame of image, and the data line and the data line extension line are turned on, and the normal operation is completed.
  • the first voltage terminal 5 and the second voltage terminal 6 may be set to the same port, and the port may be The gate of the first switching thin film transistor 101 and the gate of the second switching thin film transistor 102 are respectively connected through the first control line 7.
  • the first control line 7 can transmit a first control signal when displaying one frame of image, and can transmit a second control signal during a period of time between displaying adjacent two frames of images.
  • the first control line 7 and the gate line 1 may be of the same material in the same layer, that is, the pattern of the first control line and the gate line may be formed by the same patterning process, or the first control line 7 and the data line 2 can be the same material in the same layer, that is, the pattern of the first control line and the data line can be formed by the same patterning process, which can reduce the manufacturing process and save costs.
  • the third voltage terminal 8 of the voltage control circuit 300 is connected to the gate of the third switching thin film transistor 201 in the array substrate, the third voltage.
  • the terminal 8 outputs a third voltage for controlling the third switching thin film transistor 201 to be turned on during a period between displaying adjacent two frames of images, and the gate line extension line located at the interval line is placed in a high voltage state; voltage control
  • the fourth voltage terminal 9 of the circuit 300 is connected to the gate of the fourth switching thin film transistor 202 in the array substrate, and the fourth voltage terminal 9 outputs a fourth voltage for displaying a period of time between adjacent two frames of images.
  • the fourth switching thin film transistor 202 is controlled to be turned on, and the data line extension line located at the interval line is placed in a high voltage state.
  • the third voltage terminal 8 and the fourth voltage terminal 9 may be disposed as the same port, and the port may be The gate of the third switching thin film transistor 201 and the gate of the fourth switching thin film transistor 202 are respectively connected through the second control line 10.
  • the second control line 10 can transmit a third control signal during a period of time between displaying adjacent two frames of images.
  • the second control line 10 and the gate line 1 may be of the same material in the same layer, that is, the pattern of the second control line and the gate line may be formed by the same patterning process, or the second control line 10 and the data line 2 can be the same material in the same layer, that is, the second control line and the data line can be formed by the same patterning process, which can reduce the manufacturing process and save costs.
  • the first control line when displaying one frame of image, transmits a high voltage signal, and the first switching thin film transistor and the second switching thin film transistor remain in an open state, that is, the gate line is extended.
  • the line and the gate line are turned on, and the data line extension line and the data line are turned on, so that the display device can complete the display of the normal picture under the action of the gate driver and the data driver.
  • the first control line transmits a low voltage signal, and the first switching thin film transistor and the second switching thin film transistor are turned off, and the gate line extension line and the data line extension line are controlled at this time.
  • the gate line and the data line of the display area are not affected.
  • the second control line After the first control line transmits the low voltage signal, the second control line transmits the high voltage signal, and the third switching thin film transistor and the fourth switching thin film transistor are turned on.
  • the gate line extension line of the odd line and the data line extension line of the odd line are placed in a high voltage state, and the gate line extension line of the even line and the data line extension line of the odd line are suspended, and the gate line extension line of the adjacent line is An electric field is formed between the data line extension lines of the adjacent and adjacent rows.
  • the positive and negative charged ions inside the display device are adsorbed into the peripheral region, which can significantly improve the residual image around the display device.
  • the fifth voltage terminal 12 of the voltage control circuit 300 is connected to the gate of the fifth switching thin film transistor 203 in the array substrate, and the fifth voltage is The terminal 12 outputs a fifth voltage for controlling the fifth switching thin film transistor 203 to be turned on during a period between displaying adjacent two frames of images; the sixth voltage terminal 13 of the voltage control circuit 300 and the sixth switch in the array substrate The gate of the thin film transistor 204 is connected, and the sixth voltage terminal 13 outputs a sixth voltage for controlling the sixth switching thin film transistor 204 to be turned on during a period of time between displaying adjacent two frames of images.
  • the source of the fifth switching thin film transistor 203 is used to connect to a low voltage
  • the source of the sixth switching thin film transistor 204 is used to access a low voltage. Therefore, the low voltage terminal 11 of the voltage control circuit can be The source of the fifth switching thin film transistor 203 and the source of the sixth switching thin film transistor 204 are connected, and the low voltage terminal outputs a low voltage. At this time, other gate line extension lines other than the third switching thin film transistor 201 are placed at a low voltage. The state, except for the connection of the fourth switching thin film transistor 202, the data line extension line is placed in a low voltage state.
  • the fifth voltage terminal 12 and the sixth voltage terminal 13 may be disposed as the same port.
  • the port is connected to the gate of the fifth switching thin film transistor 203 and the gate of the sixth switching thin film transistor 204 through the third control line 14, respectively.
  • the third control line can transmit a third control signal during a time period between displaying adjacent two frames of images.
  • the third control line 14 and the gate line 1 may be of the same material in the same layer, that is, a pattern of the third control line and the gate line may be formed by the same patterning process, or the third control line 14 and the data line may be formed.
  • 2 can be the same material in the same layer, that is, pass
  • the patterning process of the third control line and the data line can be formed through the same patterning process, which can reduce the manufacturing process and save costs.
  • the first control line transmits a low voltage signal
  • the second control line and The third control line transmits a high voltage signal.
  • the gate line extension line and the data line extension line of the odd rows are both introduced with high voltage, because the third switching thin film transistor, the fourth switching thin film transistor, and the fifth The switching thin film transistor and the sixth switching thin film transistor are simultaneously turned on, and the low voltage in the low voltage control line connected to the low voltage end is applied to the gate line extension line and the data line extension line of the even line to make the gate line extension line of the adjacent line
  • An electric field is formed between the extension lines of the data lines and the adjacent lines, and the positive and negative charged ions inside the display device can be adsorbed into the peripheral region, which significantly improves the problem of residual images around the display device.
  • a black matrix is disposed on the array substrate or the opposite substrate for shielding, and an orthographic projection of the black matrix on the substrate substrate at least partially covers the peripheral region of the array substrate. In this way, the peripheral area of the array substrate can be blocked, so that the peripheral area is not used for displaying a picture.
  • an embodiment of the present disclosure further provides a driving method of the above display device provided by an embodiment of the present disclosure. Since the principle of solving the problem is similar to the foregoing display device, the implementation of the method can be referred to the array. The implementation of the substrate and the display device will not be repeated here.
  • the driving method of the display device provided by the embodiment of the present disclosure specifically includes the following steps:
  • S902 in a time period between displaying adjacent two frames of images, disconnecting the gate line and the gate line extension line, disconnecting the data line and the data extension line in response to the second control signal; controlling in response to the third control signal There is a potential difference between the adjacent two rows of gate line extension lines, and there is a potential difference between the adjacent two rows of data line extension lines.
  • the array base includes: a base substrate; a plurality of gate lines and a plurality of data lines disposed transversely across the base substrate; a control circuit; and a gate line extension line connected to the control circuit by at least a portion of the gate lines And a data line extension line connected to the control circuit by at least a portion of the data lines, wherein the control circuit is configured to control the gate line and the gate line extension line to be turned on when displaying one frame of image, Controlling the data line and the data line extension line to be turned on; and controlling the gate line and the gate line extension line to be disconnected, controlling the data line and the data line extension during a period of time between displaying adjacent two frames of images
  • the line is disconnected, at least a portion of the gate line extension lines are controlled to have a potential difference, and at least a portion of the data line extension lines are controlled to have a potential difference.
  • two adjacent rows of gate line extension lines and two adjacent rows of data line extension lines are respectively introduced into different voltages (for example, voltages having opposite polarities), thereby causing a voltage potential to adsorb the array substrate.
  • Positive and negative charged ions in the surrounding area effectively solve the problem of residual images around the display device and improve the display quality of the display device.

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Abstract

一种阵列基板、显示装置及其驱动方法，阵列基板的周边区域设置了栅线延长线(3)、数据线延长线(4)和控制电路；控制电路用于在显示一帧图像时，控制栅线(1)和栅线延长线(3)导通、控制数据线(2)和数据线延长线(4)导通；以及在显示相邻两帧图像之间的时间段内，控制栅线(1)和栅线延长线(3)断开、控制数据线(2)和数据线延长线(4)断开、控制至少部分栅线延长线(3)之间具有电位差、控制至少部分数据线延长线(4)之间具有电位差。这样通过控制电路的控制，将至少部分栅线延长线(3)之间和至少部分数据线延长线(4)之间均造成电压势，可以吸附阵列基板周边区域的正负带电离子，从而有效解决显示装置周边残像的问题，提高显示装置的显示品质。

Description

阵列基板、显示装置及其驱动方法 技术领域
本公开涉及一种阵列基板、显示装置及其驱动方法。
背景技术
目前，显示技术被广泛应用，用于显示画面的显示装置也多种多样，而且可以显示丰富多彩的画面。随着平板显示技术的快速发展，对显示装置画面品质的需求越来越高。
残像作为画面品质评价的重要内容，长期以来得到广泛关注。在显示装置，例如液晶显示(Liquid Crystal Display，简称LCD)面板，长期保持一个画面显示的情况下，因为长时间电场的影响，切换到其他画面时，画面就会出现残留影像。造成残像的主要原因是：显示装置在制造过程中及制造材料中，会引入一些带电离子进入显示装置中，在长期保持一个画面显示的情况下，这些带电离子会在外部电场的作用下分离，形成内部电场。当切换画面时，由带电粒子产生的内部电场使显示装置仍然保持上一个画面，造成残留影像。
周边残像是在显示装置中经常出现的一种残像。产生周边残像的一个主要原因是位于LCD面板的周边区域的封框胶对LCD面板内部的液晶分子造成污染，污染产生的带电离子分布在LCD面板的周边区域，在显示装置显示一帧图像时，带电离子产生内部电场，当切换图像时，由带电离子产生的内部电场使显示装置仍然保持上一个图像，从而形成周边残像。
因此，需要解决显示装置周边残像的问题。
发明内容
本公开实施例提供一种阵列基板、显示装置及其驱动方法，可以有效解决周边残像的问题，提高显示装置的显示品质。
本公开的实施例提供一种阵列基板，包括：衬底基板；设置在所述衬底基板上横纵交叉的多条栅线和多条数据线；控制电路；与至少部分所述栅线 通过所述控制电路连接的多条栅线延长线；以及与至少部分所述数据线通过所述控制电路连接的多条数据线延长线，其中，所述控制电路被配置为在显示一帧图像时，控制所述栅线和栅线延长线导通、控制所述数据线和数据线延长线导通；以及在显示相邻两帧图像之间的时间段内，控制所述栅线和栅线延长线断开、控制所述数据线和数据线延长线断开、控制至少部分所述栅线延长线之间具有电位差、控制至少部分所述数据线延长线之间具有电位差。
例如，在本公开实施例提供的阵列基板中，所述栅线延长线分别设置于每条所述栅线的两端并与所述栅线一一对应，所述数据线延长线分别设置于每条所述数据线的两端并与所述数据线一一对应。
例如，本公开实施例提供的阵列基板，包括显示区域和围绕所述显示区域的周边区域，其中，所述栅线和所述数据线设置于所述显示区域中，所述栅线延长线、所述数据线延长线和所述控制电路均设置于所述周边区域。
例如，在本公开实施例提供的阵列基板中，所述控制电路被配置为在显示相邻两帧图像之间的时间段内，控制所述栅线和栅线延长线断开、控制所述数据线和数据线延长线断开、控制相邻两行所述栅线延长线之间具有电位差、控制相邻两行所述数据线延长线之间具有电位差。
例如，在本公开实施例提供的阵列基板中，所述控制电路包括第一控制电路和第二控制电路；所述第一控制电路被配置为在显示一帧图像时，控制所述栅线和栅线延长线之间导通、控制所述数据线和数据线延长线之间导通；在显示相邻两帧图像之间的时间段内，控制所述栅线和栅线延长线之间断开、控制所述数据线和数据线延长线之间断开；所述第二控制电路被配置为在显示相邻两帧图像之间的时间段内，控制相邻两行所述栅线延长线之间具有电位差，以及控制相邻两行所述数据线延长线之间具有电位差。
例如，在本公开实施例提供的阵列基板中，所述第一控制电路包括第一开关薄膜晶体管和第二开关薄膜晶体管；所述第一开关薄膜晶体管被配置为在显示一帧图像时，控制所述栅线和所述栅线延长线导通，在显示相邻两帧图像之间的时间段内，控制所述栅线和所述栅线延长线断开；所述第二开关晶体管被配置为在显示一帧图像时，控制所述数据线和所述数据线延长线导通，在显示相邻两帧图像之间的时间段内，控制所述数据线和所述数据线延长线断开。
例如，在本公开实施例提供的阵列基板中，所述第一开关薄膜晶体管的源极与所述栅线延长线连接，漏极与所述栅线连接，栅极用于接入第一电压；所述第二开关薄膜晶体管的源极与所述数据线延长线连接，漏极与所述数据线连接，栅极用于接入第二电压。
例如，在本公开实施例提供的阵列基板中，所述第二控制电路包括第三开关薄膜晶体管和第四开关薄膜晶体管；所述第三开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制位于间隔行的所述栅线延长线置于高电压状态；所述第四开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制位于间隔行的所述数据线延长线置于高电压状态。
例如，在本公开实施例提供的阵列基板中，所述第三开关薄膜晶体管的漏极与位于间隔行的所述栅线延长线连接，栅极用于接入第三电压，源极和栅极连接；所述第四开关薄膜晶体管的漏极与位于间隔行的所述数据线延长线连接，栅极用于接入第四电压，源极和栅极连接。
例如，在本公开实施例提供的阵列基板中，所述第二控制电路还包括第五开关薄膜晶体管和第六开关薄膜晶体管；所述第五开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制除连接所述第三开关薄膜晶体管之外的其它栅线延长线置于低电压状态；所述第六开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制除连接所述第四开关薄膜晶体管之外的其它数据线延长线置于低电压状态。
例如，在本公开实施例提供的阵列基板中，所述第五开关薄膜晶体管的漏极与除连接所述第三开关薄膜晶体管之外的其他栅线延长线连接，源极用于接入低电压，栅极用于接入第五电压；所述第六开关薄膜晶体管的漏极与除连接所述第四开关薄膜晶体管之外的其他数据线延长线连接，源极用于接入低电压，栅极用于接入第六电压。
本公开的实施例还提供一种显示装置，包括相对而置的阵列基板、对置基板以及电压控制电路，其中，所述阵列基板为上述任一项所述的阵列基板；所述电压控制电路用于在显示一帧图像时，向所述阵列基板中的控制电路输入第一控制信号，使所述阵列基板中的栅线和栅线延长线导通、使数据线和数据线延长线导通；在显示相邻两帧图像之间的时间段内，向所述阵列基板中的所述控制电路输入第二控制信号，使所述阵列基板中的所述栅线和所述 栅线延长线断开、使所述数据线和所述数据线延长线断开，以及向所述阵列基板中的所述控制电路输入第三控制信号，使相邻两行所述栅线延长线之间具有电位差、使相邻两行所述数据线延长线之间具有电位差。
例如，在本公开实施例提供的显示装置中，所述电压控制电路的第一电压端与所述阵列基板中的第一开关薄膜晶体管的栅极连接；所述电压控制电路的第二电压端与所述阵列基板中的第二开关薄膜晶体管的栅极连接。
例如，在本公开实施例提供的显示装置中，所述第一电压端和所述第二电压端为同一端口，所述端口通过第一控制线分别与所述第一开关薄膜晶体管的栅极和第二开关薄膜晶体管的栅极连接。
例如，在本公开实施例提供的显示装置中，所述电压控制电路的第三电压端与所述阵列基板中的第三开关薄膜晶体管的栅极连接；所述电压控制电路的第四电压端与所述阵列基板中的第四开关薄膜晶体管的栅极连接。
例如，在本公开实施例提供的显示装置中，所述第三电压端和第四电压端为同一端口，所述端口通过第二控制线分别与所述第三开关薄膜晶体管的栅极和第四开关薄膜晶体管的栅极连接。
例如，在本公开实施例提供的显示装置中，所述电压控制电路的第五电压端与所述阵列基板中的第五开关薄膜晶体管的栅极连接；所述电压控制电路的第六电压端与所述阵列基板中的第六开关薄膜晶体管的栅极连接。
例如，在本公开实施例提供的显示装置中，所述第五电压端和第六电压端为同一端口，所述端口通过第三控制线分别与所述第五开关薄膜晶体管的栅极和第六开关薄膜晶体管的栅极连接。
例如，在本公开实施例提供的显示装置中，所述阵列基板或所述对置基板上设置有黑矩阵，所述黑矩阵在衬底基板上的正投影至少一部分覆盖所述阵列基板的周边区域。
例如，本公开实施例还提供一种上述任一项显示装置的驱动方法，包括：在显示一帧图像时，响应于第一控制信号，导通栅线和栅线延长线、导通数据线和数据延长线；在显示相邻两帧图像之间的时间段内，响应于第二控制信号，断开所述栅线和所述栅线延长线、断开所述数据线和所述数据延长线；响应于第三控制信号，控制相邻两行所述栅线延长线之间具有电位差、控制相邻两行所述数据线延长线之间具有电位差。
在本公开实施例提供的阵列基板、显示装置及其驱动方法中，通过控制电路的控制，将例如相邻两行的栅线延长线和相邻两行的数据线延长线均分别导入例如极性相反的电压，造成电压势，可以吸附阵列基板周边区域的正负带电离子，从而有效解决显示装置周边残像的问题，提高显示装置的显示品质。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本公开实施例提供的阵列基板的结构示意图之一；
图2为本公开实施例提供的阵列基板的结构示意图之二；
图3为本公开实施例提供的阵列基板的结构示意图之三；
图4为本公开实施例提供的显示装置的结构示意图之一；
图5为图4中显示装置的工作时序图；
图6a为本公开实施例提供的显示装置沿图4中的A-A’线吸附离子后的剖面结构示意图；
图6b为本公开实施例提供的显示装置沿图4中的B-B’线吸附离子后的剖面结构示意图；
图7为本公开实施例提供的显示装置的结构示意图之二；
图8为图7中显示装置的工作时序图；以及
图9是本公开实施例提供的一种显示装置的驱动方法的流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
附图中各结构的大小和形状不反映阵列基板的真实比例，目的只是示意说明本公开的内容。
本公开所有实施例中采用的开关薄膜晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。
本公开的实施例提供了一种阵列基板，如图1所示，该阵列基板包括：衬底基板；设置在衬底基板上横纵交叉的多条栅线1和多条数据线2；控制电路；与至少部分栅线1通过控制电路连接的多条栅线延长线3；以及与至少部分数据线2通过控制电路连接的多条数据线延长线4，控制电路被配置为在显示一帧图像时，控制栅线1和栅线延长线3导通、控制数据线2和数据线延长线4导通(电连接)；以及在显示相邻两帧图像之间的时间段内(即在显示当前帧图像之后，显示下一帧图像之前的非显示时间段)，控制栅线1和栅线延长线3断开(不再电连接)、控制数据线2和数据线延长线4断开、控制至少部分栅线延长线3之间具有电位差、控制至少部分数据线延长线4之间具有电位差。
例如，栅线延长线3分别设置于每条栅线1的两端并与栅线1一一对应，数据线延长线4分别设置于每条数据线2的两端并与数据线2一一对应。
例如，阵列基板包括显示区域和围绕显示区域的周边区域，栅线1和数据线2设置于显示区域中，栅线延长线3、数据线延长线4和控制电路均设置于周边区域。
例如，控制电路被配置为在显示相邻两帧图像之间的时间段内，控制栅 线1和栅线延长线3断开、控制数据线2和数据线延长线4断开、控制相邻两行栅线延长线3之间具有电位差、控制相邻两行数据线延长线4之间具有电位差。
需要说明的是，本公开实施例提供的阵列基板包括但不局限于图1所示的情形。例如，栅线延长线可以仅设置于部分栅线的一端或两端，数据线延长线也可以仅设置于部分数据线的一端或两端。例如，控制电路也可以被配置为在显示相邻两帧图像之间的时间段内，控制部分栅线延长线之间具有电位差、控制部分数据线延长线之间具有电位差。也就是说，不是每相邻两行的栅线延长线之间一定具有电位差，不是每相邻两行的数据线延长线之间一定具有电位差。
例如，在本公开实施例提供的上述阵列基板中，由于该阵列基板的周边区域设置了栅线延长线、数据线延长线和控制电路，进而形成显示装置后，在显示一帧图像时，控制电路控制栅线和栅线延长线之间导通，以及控制数据线和数据线延长线之间导通，由栅极驱动器通过栅线延长线向栅线传递栅极扫描信号，由数据驱动器通过数据线延长线向数据线传递数据信号，进而可以正常显示画面；在完成正常显示后，在显示相邻两帧图像之间的时间段内，控制电路控制栅线和栅线延长线之间断开，以及控制数据线和数据线延长线之间断开，同时控制电路控制相邻两行栅线延长线具有电位差，以及控制相邻两行数据线延长线具有电位差，这样，通过控制电路的控制，将相邻两行的栅线延长线和相邻两行的数据线延长线均分别导入不同的电压(例如，高电压和低电压或极性相反的电压)，造成电压势，可以吸附显示装置周边区域的正负带电离子，从而有效解决显示装置周边残像的问题，提高显示装置的显示品质。
例如，在本公开实施例提供的上述阵列基板中，如图2所示，控制电路包括第一控制电路(虚线框标注处100为第一控制电路的一部分)和第二控制电路(虚线框标注处200为第二控制电路的一部分)；第一控制电路用于在显示一帧图像时，控制栅线和栅线延长线之间导通，以及控制数据线和数据线延长线之间导通；完成正常显示后，在显示相邻两帧图像之间的时间段内，控制栅线和栅线延长线之间断开，以及控制数据线和数据线延长线之间断开；第二控制电路用于在显示相邻两帧图像之间的时间段内，控制相邻两 行的栅线延长线具有电位差，以及控制相邻两行的数据线延长线具有电位差。
例如，在本公开实施例提供的上述阵列基板中，如图2所示，第一控制电路包括第一开关薄膜晶体管101和第二开关薄膜晶体管102；第一开关薄膜晶体管101用于在显示一帧图像时，控制栅线和栅线延长线之间导通，完成正常显示后，在显示相邻两帧图像之间的时间段内，控制栅线和栅线延长线之间断开；第二开关晶体管102用于在显示一帧图像时，控制所述数据线和数据线延长线之间导通，在显示相邻两帧图像之间的时间段内，控制所述数据线和数据线延长线之间断开。
例如，在本公开实施例提供的上述阵列基板中，如图2所示，第一开关薄膜晶体管101的源极与栅线延长线3连接，漏极与栅线1连接，栅极用于接入第一电压；第二开关薄膜晶体管102的源极与数据线延长线4连接，漏极与数据线2连接，栅极用于接入第二电压。因此，第一开关薄膜晶体管101可以控制栅线1与栅线延长线3连接或断开，第二开关薄膜晶体管102可以控制数据线2与数据线延长线4连接或断开。在显示一帧图像时，第一开关薄膜晶体管和第二开关薄膜晶体管可以保持打开状态，即保持栅线延长线与栅线连通，数据线延长线与数据线连通，完成该帧图像的正常显示后，在显示相邻两帧图像之间的时间段内，关闭第一开关薄膜晶体管和第二开关薄膜晶体管，即栅线延长线与栅线断开，数据线延长线与数据线断开，可以保持没有与第二控制电路连接的栅线延长线和数据线延长线悬空，相当于处于低电压状态。
例如，在本公开实施例提供的上述阵列基板中，如图2所示，第二控制电路包括第三开关薄膜晶体管201和第四开关薄膜晶体管202；第三开关薄膜晶体管201用于在显示相邻两帧图像之间的时间段内，控制位于间隔行的栅线延长线置于高电压状态；第四开关薄膜晶体管202用于在显示相邻两帧图像之间的时间段内，控制位于间隔行的数据线延长线置于高电压状态。
例如，本公开实施例中的低电压例如为0V，高电压例如为5V。
例如，在本公开实施例提供的上述阵列基板中，如图2所示，第三开关薄膜晶体管201的漏极与位于间隔行的栅线延长线3连接，栅极用于接入第三电压，源极和栅极连接；第四开关薄膜晶体管202的漏极与位于间隔行的数据线延长线4连接，栅极用于接入第四电压，源极和栅极连接。需要说明 的是，间隔行的栅线延长线可以为位于奇数行的栅线延长线，也可以为偶数行的栅线延长线，同理间隔行的数据线延长线可以为位于奇数行的数据线延长线，也可以为偶数行的数据线延长线。这样，通过第三开关薄膜晶体管和第四开关薄膜晶体管可以控制位于奇/偶数行的栅线延长线和数据线延长线输出的电压状态，在显示相邻两帧图像之间的时间段内，可以保持分别连接第三开关薄膜晶体管和第四开关薄膜晶体管的栅线延长线和数据线延长线均置于高电压状态。
例如，在本公开实施例提供的上述阵列基板中，如图3所示，第二控制电路还可以包括第五开关薄膜晶体管203和第六开关薄膜晶体管204；第五开关薄膜晶体管203用于在显示相邻两帧图像之间的时间段内，控制除连接第三开关薄膜晶体管201之外的其它栅线延长线置于低电压状态；第六开关薄膜晶体管204用于在显示相邻两帧图像之间的时间段内，控制除连接第四开关薄膜晶体管202之外的其它数据线延长线置于低电压状态。
例如，在本公开实施例提供的上述阵列基板中，如图3所示，第五开关薄膜晶体管203的漏极与除连接第三开关薄膜晶体管201之外的其他栅线延长线3连接，源极用于接入低电压，栅极用于接入第五电压；第六开关薄膜晶体管204的漏极与除连接第四开关薄膜晶体管202之外的其他数据线延长线4连接，源极用于接入低电压，栅极用于接入第六电压。需要说明的是，当第三开关薄膜晶体管的漏极与位于奇数行的栅线延长线连接时，除连接第三开关薄膜晶体管之外的其他栅线延长线为位于偶数行的栅线延长线，当第三开关薄膜晶体管的漏极与位于偶数行的栅线延长线连接时，除连接第三开关薄膜晶体管之外的其他栅线延长线为位于奇数行的栅线延长线，同理，当第四开关薄膜晶体管的漏极与位于奇数行的数据线延长线连接时，除连接第四开关薄膜晶体管之外的其他数据线延长线为位于偶数行的数据线延长线，当第四开关薄膜晶体管的漏极与位于偶数行的数据线延长线连接时，除连接第四开关薄膜晶体管之外的其他数据线延长线为位于奇数行的数据线延长线。这样，在显示相邻两帧图像之间的时间段内，关闭第一开关薄膜晶体管和第二开关薄膜晶体管，同时打开第三开关薄膜晶体管、第四薄膜晶体管薄膜晶体管、第五开关薄膜晶体管和第六开关薄膜晶体管，可以将连接第五开关薄膜晶体管和第六开关薄膜晶体管的栅线延长线和数据线延长线置于低电 压状态，可以使形成的电场吸附离子能力得到提高，周边残像的改善能力得到进一步提高。
需要说明的是，例如，第一开关薄膜晶体管、第二开关薄膜晶体管、第三开关薄膜管、第四开关薄膜晶体管、第五开关薄膜晶体管和第六开关薄膜晶体管均可以与显示区域的开关薄膜晶体管通过同一过程制备而成，即可以同步形成，这样可以简化制作工艺，节省成本。
例如，本公开实施例提供的阵列基板中还包括绝缘层、钝化层、取向膜等其他膜层结构，以及在衬底基板上还形成有公共电极线等结构，这些具体结构可以有多种实现方式，在此不做限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，如图4所示，包括上述任一种方式的阵列基板和与该阵列基板相对设置的对置基板，以及电压控制电路300。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。该显示装置可以为显示面板。上述电压控制电路300用于在显示一帧图像时，向阵列基板中的控制电路输入第一控制信号，使阵列基板中的栅线1和栅线延长线3之间导通，以及数据线2和数据线延长线4之间导通，进而显示装置可以正常显示画面；在完成该帧图像显示后，在显示相邻两帧图像之间的时间段内，向阵列基板中的控制电路输入第二控制信号，使阵列基板中的栅线1和栅线延长线3之间断开，以及数据线2和数据线延长线4之间断开，以及向阵列基板中的控制电路输入第三控制信号，使相邻两行栅线延长线3具有电位差，以及控制相邻两行数据线延长线4具有电位差。
例如，在本公开实施例提供的上述显示装置中，如图4所示，电压控制电路300的第一电压端5与阵列基板中的第一开关薄膜晶体管101的栅极连接，该第一电压端输出第一电压，用于在显示一帧图像时，控制第一开关薄膜晶体管101开启，此时栅线和栅线延长线之间导通，完成正常显示后，在显示相邻两帧图像之间的时间段内，控制第一开关薄膜晶体管101关闭，此时栅线和栅线延长线之间断开；电压控制电路300的第二电压端6与阵列基板中的第二开关薄膜晶体管102的栅极连接，该第二电压端6输出第二电压，用于在显示一帧图像时，控制第二开关薄膜晶体管102开启，此时数据线和数据线延长线之间导通，完成正常显示后，在显示相邻两帧图像之间的时间 段内，控制第二开关薄膜晶体管102关闭，此时数据线和数据线延长线之间断开。
例如，在本公开实施例提供的上述阵列基板中，为了使周边区域的布线设计简单化，如图4所示，第一电压端5和第二电压端6可以设置为同一端口，该端口可以通过第一控制线7分别与第一开关薄膜晶体管101的栅极和第二开关薄膜晶体管102的栅极连接。该第一控制线7在显示一帧图像时可以传输第一控制信号，在显示相邻两帧图像之间的时间段可以传输第二控制信号。需要说明的是，例如，第一控制线7和栅线1可以同层同材质，即通过同一次构图工艺可以形成第一控制线和栅线的图形，或者，第一控制线7和数据线2可以同层同材质，即通过同一次构图工艺可以形成第一控制线和数据线的图形，这样可以减少制作工艺，节省成本。
例如，在本公开实施例提供的上述显示装置中，如图4所示，电压控制电路300的第三电压端8与阵列基板中的第三开关薄膜晶体管201的栅极连接，该第三电压端8输出第三电压，用于在显示相邻两帧图像之间的时间段内，控制第三开关薄膜晶体管201开启，此时位于间隔行的栅线延长线置于高电压状态；电压控制电路300的第四电压端9与阵列基板中的第四开关薄膜晶体管202的栅极连接，该第四电压端9输出第四电压，用于在显示相邻两帧图像之间的时间段内，控制第四开关薄膜晶体管202开启，此时位于间隔行的数据线延长线置于高电压状态。
例如，在本公开实施例提供的上述阵列基板中，为了使周边区域的布线设计简单化，如图4所示，第三电压端8和第四电压端9可以设置为同一端口，该端口可以通过第二控制线10分别与第三开关薄膜晶体管201的栅极和第四开关薄膜晶体管202的栅极连接。该第二控制线10在显示相邻两帧图像之间的时间段内可以传输第三控制信号。需要说明的是，例如，第二控制线10和栅线1可以同层同材质，即通过同一次构图工艺可以形成第二控制线和栅线的图形，或者，第二控制线10和数据线2可以同层同材质，即通过同一次构图工艺可以形成第二控制线和数据线的图形，这样可以减少制作工艺，节省成本。
例如，如图5所示，在显示一帧图像时，第一控制线传输高电压信号，第一开关薄膜晶体管和第二开关薄膜晶体管保持打开状态，即保持栅线延长 线和栅线导通，数据线延长线和数据线导通，这样在栅极驱动器和数据驱动器的作用下，显示装置可以完成正常画面的显示。在显示相邻两帧图像之间的时间段内，第一控制线传输低电压信号，关闭第一开关薄膜晶体管和第二开关薄膜晶体管，此时对栅线延长线和数据线延长线的控制不会影响显示区域的栅线和数据线，在第一控制线传输低电压信号后，第二控制线传输高电压信号，打开第三开关薄膜晶体管和第四开关薄膜晶体管，此时以图4为例，奇数行的栅线延长线和奇数行的数据线延长线置于高电压状态，偶数行的栅线延长线和奇数行的数据线延长线悬空，相邻行的栅线延长线之间和相邻行的数据线延长线之间均形成电场，如图6a和6b所示，将显示装置内部的正负带电离子吸附到周边区域内，可以明显改善显示装置周边残像的问题。
例如，在本公开实施例提供的上述显示装置中，如图7所示，电压控制电路300的第五电压端12与阵列基板中的第五开关薄膜晶体管203的栅极连接，该第五电压端12输出第五电压，用于在显示相邻两帧图像之间的时间段内，控制第五开关薄膜晶体管203开启；电压控制电路300的第六电压端13与阵列基板中的第六开关薄膜晶体管204的栅极连接，该第六电压端13输出第六电压，用于在显示相邻两帧图像之间的时间段内，控制第六开关薄膜晶体管204开启。
需要说明的是，第五开关薄膜晶体管203的源极用于接入低电压，且第六开关薄膜晶体管204的源极用于接入低电压，因此，电压控制电路的低电压端11可以与第五开关薄膜晶体管203的源极以及第六开关薄膜晶体管204的源极连接，低电压端输出低电压，此时除连接第三开关薄膜晶体管201之外的其它栅线延长线置于低电压状态，除连接第四开关薄膜晶体管202之外的其它数据线延长线置于低电压状态。
例如，在本公开实施例提供的上述阵列基板中，为了使布线设计简单化，简化显示装置的结构，如图7所示，第五电压端12和第六电压端13可以设置为同一端口，该端口通过第三控制线14分别与第五开关薄膜晶体管203的栅极和第六开关薄膜晶体管204的栅极连接。该第三控制线在显示相邻两帧图像之间的时间段内可以传输第三控制信号。需要说明的是，例如，第三控制线14和栅线1可以同层同材质，即通过同一次构图工艺可以形成第三控制线和栅线的图形，或者，第三控制线14和数据线2可以同层同材质，即通 过同一次构图工艺可以形成第三控制线和数据线的图形，这样可以减少制作工艺，节省成本。
例如，如图8所示，在显示相邻两帧图像之间的时间段内，第一控制线传输低电压信号，关闭第一开关薄膜晶体管和第二开关薄膜晶体管之后，第二控制线和第三控制线均传输高电压信号，此时以图7为例，奇数行的栅线延长线和数据线延长线均导入高电压，由于第三开关薄膜晶体管、第四开关薄膜晶体管、第五开关薄膜晶体管和第六开关薄膜晶体管同时打开，将低电压端连接的低电压控制线中的低电压加载到偶数行的栅线延长线和数据线延长线，使相邻行的栅线延长线之间和相邻行的数据线延长线之间均形成电场，可以将显示装置内部的正负带电离子吸附到周边区域内，明显进一步改善显示装置周边残像的问题。
例如，在本公开实施例提供的上述显示装置中，为了进行遮光，阵列基板或对置基板上设置有黑矩阵，且黑矩阵在衬底基板上的正投影应至少一部分覆盖阵列基板的周边区域，这样可以遮挡阵列基板的周边区域，使周边区域不用来显示画面。
对于该显示装置的其它必不可少的组成部分均为本领域技术人员应该理解的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例还提供了一种本公开实施例提供的上述显示装置的驱动方法，由于该方法解决问题的原理与前述一种显示装置相似，因此该方法的实施可以参见阵列基板和显示装置的实施，重复之处不再赘述。
例如，本公开实施例提供的显示装置的驱动方法，如图9所示，具体包括以下步骤：
S901：在显示一帧图像时，响应于第一控制信号，导通栅线和栅线延长线、导通数据线和数据延长线；
S902：在显示相邻两帧图像之间的时间段内，响应于第二控制信号，断开栅线和栅线延长线、断开数据线和数据延长线；响应于第三控制信号，控制相邻两行栅线延长线之间具有电位差、控制相邻两行数据线延长线之间具有电位差。
本公开实施例提供的一种阵列基板、显示装置及其驱动方法，该阵列基 板包括：衬底基板；设置在所述衬底基板上横纵交叉的多条栅线和多条数据线；控制电路；与至少部分所述栅线通过所述控制电路连接的栅线延长线；以及与至少部分所述数据线通过所述控制电路连接的数据线延长线，其中，所述控制电路被配置为在显示一帧图像时，控制所述栅线和栅线延长线导通、控制所述数据线和数据线延长线导通；以及在显示相邻两帧图像之间的时间段内，控制所述栅线和栅线延长线断开、控制所述数据线和数据线延长线断开、控制至少部分所述栅线延长线之间具有电位差、控制至少部分所述数据线延长线之间具有电位差。通过控制电路的控制，将例如相邻两行的栅线延长线和相邻两行的数据线延长线均分别导入不同的电压(例如极性相反的电压)，造成电压势，可以吸附阵列基板周边区域的正负带电离子，从而有效解决显示装置周边残像的问题，提高显示装置的显示品质。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本专利申请要求于2015年12月31日递交的中国专利申请第201511031927.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    设置在所述衬底基板上横纵交叉的多条栅线和多条数据线；
    控制电路；
    与至少部分所述栅线通过所述控制电路连接的多条栅线延长线；以及
    与至少部分所述数据线通过所述控制电路连接的多条数据线延长线，
    其中，所述控制电路被配置为在显示一帧图像时，控制所述栅线和栅线延长线导通、控制所述数据线和数据线延长线导通，以及在显示相邻两帧图像之间的时间段内，控制所述栅线和栅线延长线断开、控制所述数据线和数据线延长线断开、控制至少部分所述栅线延长线之间具有电位差、控制至少部分所述数据线延长线之间具有电位差。
  2. 根据权利要求1所述的阵列基板，其中，所述栅线延长线分别设置于每条所述栅线的两端并与所述栅线一一对应，所述数据线延长线分别设置于每条所述数据线的两端并与所述数据线一一对应。
  3. 根据权利要求1或2所述的阵列基板，包括显示区域和围绕所述显示区域的周边区域，其中，所述栅线和所述数据线设置于所述显示区域中，所述栅线延长线、所述数据线延长线和所述控制电路均设置于所述周边区域。
  4. 根据权利要求1-3任一项所述的阵列基板，其中，所述控制电路被配置为在显示相邻两帧图像之间的时间段内，控制所述栅线和栅线延长线断开、控制所述数据线和数据线延长线断开、控制相邻两行所述栅线延长线之间具有电位差、控制相邻两行所述数据线延长线之间具有电位差。
  5. 如权利要求4所述的阵列基板，其中，所述控制电路包括第一控制电路和第二控制电路；
    所述第一控制电路被配置为在显示一帧图像时，控制所述栅线和栅线延长线之间导通、控制所述数据线和数据线延长线之间导通；在显示相邻两帧图像之间的时间段内，控制所述栅线和栅线延长线之间断开、控制所述数据线和数据线延长线之间断开；
    所述第二控制电路被配置为在显示相邻两帧图像之间的时间段内，控制 相邻两行所述栅线延长线之间具有电位差，以及控制相邻两行所述数据线延长线之间具有电位差。
  6. 如权利要求5所述的阵列基板，其中，所述第一控制电路包括第一开关薄膜晶体管和第二开关薄膜晶体管；
    所述第一开关薄膜晶体管被配置为在显示一帧图像时，控制所述栅线和所述栅线延长线导通，在显示相邻两帧图像之间的时间段内，控制所述栅线和所述栅线延长线断开；
    所述第二开关晶体管被配置为在显示一帧图像时，控制所述数据线和所述数据线延长线导通，在显示相邻两帧图像之间的时间段内，控制所述数据线和所述数据线延长线断开。
  7. 如权利要求6所述的阵列基板，其中，所述第一开关薄膜晶体管的源极与所述栅线延长线连接，漏极与所述栅线连接，栅极用于接入第一电压；
    所述第二开关薄膜晶体管的源极与所述数据线延长线连接，漏极与所述数据线连接，栅极用于接入第二电压。
  8. 如权利要求5-7任一项所述的阵列基板，其中，所述第二控制电路包括第三开关薄膜晶体管和第四开关薄膜晶体管；
    所述第三开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制位于间隔行的所述栅线延长线置于高电压状态；
    所述第四开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制位于间隔行的所述数据线延长线置于高电压状态。
  9. 如权利要求8所述的阵列基板，其中，所述第三开关薄膜晶体管的漏极与位于间隔行的所述栅线延长线连接，栅极用于接入第三电压，源极和栅极连接；
    所述第四开关薄膜晶体管的漏极与位于间隔行的所述数据线延长线连接，栅极用于接入第四电压，源极和栅极连接。
  10. 如权利要求8所述的阵列基板，其中，所述第二控制电路还包括第五开关薄膜晶体管和第六开关薄膜晶体管；
    所述第五开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制除连接所述第三开关薄膜晶体管之外的其它栅线延长线置于低电压状态；
    所述第六开关薄膜晶体管被配置为在显示相邻两帧图像之间的时间段内，控制除连接所述第四开关薄膜晶体管之外的其它数据线延长线置于低电压状态。
  11. 如权利要求10所述的阵列基板，其中，所述第五开关薄膜晶体管的漏极与除连接所述第三开关薄膜晶体管之外的其他栅线延长线连接，源极用于接入低电压，栅极用于接入第五电压；
    所述第六开关薄膜晶体管的漏极与除连接所述第四开关薄膜晶体管之外的其他数据线延长线连接，源极用于接入低电压，栅极用于接入第六电压。
  12. 一种显示装置，包括相对而置的阵列基板、对置基板以及电压控制电路，其中，
    所述阵列基板为如权利要求1-11任一项所述的阵列基板；
    所述电压控制电路用于在显示一帧图像时，向所述阵列基板中的控制电路输入第一控制信号，使所述阵列基板中的栅线和栅线延长线导通、使数据线和数据线延长线导通；在显示相邻两帧图像之间的时间段内，向所述阵列基板中的所述控制电路输入第二控制信号，使所述阵列基板中的所述栅线和所述栅线延长线断开、使所述数据线和所述数据线延长线断开，以及向所述阵列基板中的所述控制电路输入第三控制信号，使相邻两行所述栅线延长线之间具有电位差、使相邻两行所述数据线延长线之间具有电位差。
  13. 如权利要求12所述的显示装置，其中，所述阵列基板为如权利要求6-11任一项所述的阵列基板，所述电压控制电路的第一电压端与所述阵列基板中的第一开关薄膜晶体管的栅极连接；
    所述电压控制电路的第二电压端与所述阵列基板中的第二开关薄膜晶体管的栅极连接。
  14. 如权利要求13所述的显示装置，其中，所述第一电压端和所述第二电压端为同一端口，所述端口通过第一控制线分别与所述第一开关薄膜晶体管的栅极和第二开关薄膜晶体管的栅极连接。
  15. 如权利要求12-14任一项所述的显示装置，其中，所述阵列基板为如权利要求6-11任一项所述的阵列基板，所述电压控制电路的第三电压端与所述阵列基板中的第三开关薄膜晶体管的栅极连接；
    所述电压控制电路的第四电压端与所述阵列基板中的第四开关薄膜晶体 管的栅极连接。
  16. 如权利要求15所述的显示装置，其中，所述第三电压端和第四电压端为同一端口，所述端口通过第二控制线分别与所述第三开关薄膜晶体管的栅极和第四开关薄膜晶体管的栅极连接。
  17. 如权利要求12-16任一项所述的显示装置，其中，所述阵列基板为如权利要求10或11所述的阵列基板，所述电压控制电路的第五电压端与所述阵列基板中的第五开关薄膜晶体管的栅极连接；
    所述电压控制电路的第六电压端与所述阵列基板中的第六开关薄膜晶体管的栅极连接。
  18. 如权利要求17所述的显示装置，其中，所述第五电压端和第六电压端为同一端口，所述端口通过第三控制线分别与所述第五开关薄膜晶体管的栅极和第六开关薄膜晶体管的栅极连接。
  19. 如权利要求12所述的显示装置，其中，所述阵列基板为如权利要求3-11任一项所述的阵列基板，所述阵列基板或所述对置基板上设置有黑矩阵，所述黑矩阵在衬底基板上的正投影至少一部分覆盖所述阵列基板的周边区域。
  20. 一种如权利要求12-19任一项所述显示装置的驱动方法，包括：
    在显示一帧图像时，响应于第一控制信号，导通栅线和栅线延长线、导通数据线和数据延长线；
    在显示相邻两帧图像之间的时间段内，响应于第二控制信号，断开所述栅线和所述栅线延长线、断开所述数据线和所述数据延长线；响应于第三控制信号，控制相邻两行所述栅线延长线之间具有电位差、控制相邻两行所述数据线延长线之间具有电位差。
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