WO2019223623A1 - 显示基板、显示面板和显示装置 - Google Patents

显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2019223623A1
WO2019223623A1 PCT/CN2019/087449 CN2019087449W WO2019223623A1 WO 2019223623 A1 WO2019223623 A1 WO 2019223623A1 CN 2019087449 W CN2019087449 W CN 2019087449W WO 2019223623 A1 WO2019223623 A1 WO 2019223623A1
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WIPO (PCT)
Prior art keywords
signal line
signal
display
display substrate
switch
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PCT/CN2019/087449
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English (en)
French (fr)
Inventor
邱亚栋
霍培荣
王志强
罗鹏
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/640,866 priority Critical patent/US20200225516A1/en
Publication of WO2019223623A1 publication Critical patent/WO2019223623A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel, and a display device.
  • CT_SWITCH adopts a design of a common MUX unit.
  • VCOM common electrode signal line
  • VCOM_SWITCH common electrode switch control line
  • An embodiment of the present disclosure provides a display substrate including a display area on a base substrate and a peripheral area around the display area.
  • the peripheral area includes a first peripheral area on a side of the display substrate.
  • the display substrate includes a test circuit, and the test circuit is located in the first peripheral region and includes a signal output terminal.
  • the test circuit further includes a first signal line, a second signal line, and a switch structure.
  • the first signal line, the second signal line, and the switch structure are located in the first peripheral region.
  • the switch structure And connected to the first signal line, the second signal line, and the signal output terminal.
  • the switch structure is turned on under the control of a conductive signal output from the second signal line, so that the first signal line is electrically connected to the signal output terminal.
  • the test circuit further includes a signal input terminal configured to input a driving signal of the test circuit, wherein the first signal line, the second signal line, and the switch structure are located at Between the signal input terminal and the signal output terminal.
  • the switch structure is further configured to be disconnected under the control of a shutdown signal output by the second signal line to disconnect the first signal line from the signal output terminal.
  • the signal output terminal includes a plurality of output pins
  • the switch structure includes a switch tube corresponding to each of the output pins; a control electrode of the switch tube is connected to the second signal A first pole of the switch tube is connected to the first signal line; a second pole of the switch tube is connected to a corresponding output pin.
  • the switch includes a thin film transistor.
  • the first pole of the switch tube is the source of the thin film transistor
  • the second pole of the switch tube is the drain of the thin film transistor
  • the control of the switch tube is the The gate of a thin film transistor.
  • the first signal line is a common electrode signal line
  • the second signal line is a common electrode switch control line
  • the display substrate is an array substrate.
  • Another embodiment of the present disclosure provides a display panel including an opposite substrate and the above-mentioned display substrate.
  • Another embodiment of the present disclosure provides a display device including the above display panel.
  • the display panel is a liquid crystal display panel.
  • FIG. 1 is a schematic structural diagram of a display substrate in the related art
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a partial schematic diagram of the first peripheral region in FIG. 2.
  • FIG. 1 is a schematic structural diagram of a display substrate in the related art.
  • the display substrate is provided with a display area (a dotted frame area) and a peripheral area located around the display area.
  • the peripheral area includes a first peripheral area (that is, a region where a test circuit is located) opposite to the first peripheral area
  • the second peripheral area and the GOA (Gate On Array) side area the display substrate includes a substrate substrate 1, and the test circuit includes a signal input terminal 2 and a signal output terminal 3, a signal input terminal 2 and a signal located on the substrate substrate 1.
  • the output terminal 3 is located in the first peripheral region.
  • the display substrate further includes a test circuit including a first signal line (ie, a common electrode signal line) 4, a second signal line (ie, a common electrode switch control line) 5, and a switch structure 6 located on the base substrate 1.
  • the first signal line 4 and the second signal line 5 surround the screen of the display panel.
  • the wiring method of the first signal line and the second signal line in the related art occupies a large space; and it will have a certain impact on the peripheral capacitance value, causing the capacitance value of the GOA side area and the second peripheral area to be high, and the capacitance value
  • the capacitance value of the touch control circuit reduces the uniformity of the capacitance of the display panel.
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a partial schematic view of a first peripheral area in FIG. 2.
  • a display area is provided on the display substrate ( Dotted frame area) and a peripheral area around the display area.
  • the peripheral area includes a first peripheral area, a second peripheral area, and a GOA side area on one side of the display substrate.
  • the display substrate includes a base substrate 1 and The signal input terminal 2 and the signal output terminal 3, the signal input terminal 2 and the signal output terminal 3 are located in the first peripheral area.
  • the display substrate further includes a test circuit.
  • the test circuit includes a first signal line 4, a second signal line 5, and a switch structure 6 located on the substrate 1.
  • the first signal line 4, the second signal line 5, and the switch structure 6 are located on the substrate substrate 1. In the first peripheral region, the switch structure 6 is connected to the first signal line 4, the second signal line 5 and the signal output terminal 3. The switch structure 6 is used for conducting under the control of the ON signal output from the second signal line 5, so that the first signal line 4 and the signal output terminal 3 are electrically connected.
  • the first signal line 4, the second signal line 5 and the switch structure 6 are located between the signal input terminal 2 and the signal output terminal 3.
  • switch structure 6 is further configured to be disconnected under the control of a shutdown signal output by the second signal line 5 so as to disconnect the first signal line 4 from the signal output terminal 3.
  • the peripheral region includes four side regions.
  • the four side regions are a first peripheral region, a second peripheral region, and two GOA side regions.
  • the two peripheral areas are oppositely disposed, and the two GOA side areas are oppositely disposed.
  • the signal input terminal 2 includes a plurality of input pins 21.
  • the number of input pins 21 can be set according to product design requirements, and only three are used as an example for description in FIG. 3.
  • the signal output terminal 3 includes a plurality of output pins 31.
  • the number of output pins 31 can be set according to product design requirements, and only three are described as examples in FIG. 3.
  • the switch structure 6 includes a switch T corresponding to each output pin 31.
  • the switch structure 6 includes a plurality of switch tubes T, and the switch tubes T and the output pins 31 are arranged one-to-one correspondingly.
  • the control pole of the switch T is connected to the second signal line 5, the first pole of the switch T is connected to the first signal line 4, and the second pole of the switch T is connected to the corresponding output pin 31.
  • Each switch tube T is turned on under the control of a turn-on signal output from the second signal line 5, so that the first signal line 4 is electrically connected to the corresponding signal output terminal 3 through the turned-on switch tube T, for example, the second The signal line 5 outputs a conduction signal.
  • the switch T When the conduction signal is a high-level signal, the switch T is turned on under the control of the high-level signal. At this time, the first signal line 4 is electrically connected to the corresponding signal output terminal 3. Each switching tube T is disconnected under the control of the shutdown signal output from the second signal line 5 to disconnect the switching tube T from the first signal line 4 and the corresponding signal output terminal 3, for example, the second signal line 5 When a shutdown signal is output, and the shutdown signal is a low-level signal, the switch T is disconnected under the control of the low-level signal. At this time, the first signal line 4 and the corresponding signal output terminal 3 are disconnected.
  • the switching tube T includes a thin film transistor (TFT).
  • TFT thin film transistor
  • the signal output terminal is connected to the display area through a screen touch signal (Touch panel metal (TPM) line). As shown in FIG. 3, the output pin 31 is connected to the display area through a TPM line 7.
  • TPM screen touch signal
  • the display substrate further includes a ground line (GND line) 8 on the base substrate 1.
  • the ground line 8 may be located in the second peripheral area and the GOA side area.
  • a lighting test is performed on the display panel.
  • the second signal line 5 outputs a conduction signal, and the switch T is turned on under the control of the conduction signal.
  • the first signal line 4 is electrically connected to the corresponding signal output terminal 3.
  • the common electrode signal output by the first signal line 4 is sequentially output to the display area through the corresponding output pin 31 and the TPM line.
  • the second signal line 5 outputs a shutdown signal, and the switch T is disconnected under the control of the shutdown signal.
  • the switch T is equivalent to being suspended, and the first signal line 4 and the corresponding signal output terminal 3 are disconnected. Open connection. At this time, the signal can normally output the display signal to the display area through the signal input terminal and the signal output terminal.
  • the switch T in the off state will not affect the normal output of the signal.
  • the display substrate may be an array substrate
  • the opposite substrate may be a color filter substrate
  • the display panel may be a liquid crystal display panel.
  • the first signal line, the second signal line, and the switch structure are all located in the first peripheral area, and the space between the signal input terminal and the signal output terminal is fully utilized, so that the second periphery The edge space of the area and the GOA side area is released to further realize the narrow border display; the first signal line, the second signal line and the switch structure no longer occupy the edge space of the second peripheral area and the GOA side area, thereby reducing The capacitance values of the second peripheral region and the GOA side region improve the uniformity of the capacitance values of the display panel.
  • Another embodiment of the present disclosure provides a display panel including a counter substrate and a display substrate which are oppositely disposed.
  • the display substrate may be the display substrate provided in the foregoing embodiment, and details are not described herein again.
  • the display substrate may be an array substrate
  • the opposite substrate may be a color filter substrate
  • the display panel may be a liquid crystal display panel.
  • the first signal line, the second signal line, and the switch structure are all located in the first peripheral area, and the space between the signal input terminal and the signal output terminal is fully utilized, so that the second periphery The edge space of the area and the GOA side area is released to further realize the narrow border display; the first signal line, the second signal line and the switch structure no longer occupy the edge space of the second peripheral area and the GOA side area, thereby reducing The capacitance values of the second peripheral region and the GOA side region improve the uniformity of the capacitance values of the display panel.
  • Another embodiment of the present disclosure provides a display device including the display panel provided by the foregoing embodiment.
  • the first signal line, the second signal line, and the switch structure are all located in the first peripheral area, and the space between the signal input terminal and the signal output terminal is fully utilized, so that the second periphery The edge space of the area and the GOA side area is released to further realize the narrow border display; the first signal line, the second signal line and the switch structure no longer occupy the area of the edge area of the second peripheral area and the GOA side, thereby reducing The capacitance values of the second peripheral region and the GOA side region improve the uniformity of the capacitance values of the display panel.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

显示基板、显示面板和显示装置。显示基板包括位于衬底基板（1）上的显示区和位于显示区四周的周边区，周边区包括显示基板一侧的第一周边区，显示基板包括测试电路（2），测试电路（2）位于第一周边区中并且包括信号输出端（3）；测试电路（2）还包括第一信号线（4）、第二信号线（5）和开关结构（6），第一信号线（4）、第二信号线（5）和开关结构（6）位于第一周边区中，开关结构（6）与第一信号线（4）、第二信号线（5）和信号输出端（3）连接；开关结构（6）在第二信号线（5）输出的导通信号的控制下导通，以使第一信号线（4）与信号输出端（3）电连接。

Description

显示基板、显示面板和显示装置
相关申请的交叉引用
本公开要求于2018年5月24日提交的中国专利申请No.201810508751.2的优先权，所公开的全部内容通过引用合并在此。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板、显示面板和显示装置。
背景技术
随着高屏占比手机屏逐渐成为市场主流，缩小边框距离，释放边缘空间成为目前面板(panel)设计的主要努力方向之一。
相关技术的显示面板中将测试数据信号(Cell Test Data，简称CTD)单元设置于位于同侧的MUX(数据选择器)单元上方，同时CT_SWITCH采用共用MUX单元的设计。这种设计方式下，公共电极信号线(VCOM)和公共电极开关控制线(VCOM_SWITCH)环绕显示面板的屏幕一周。
发明内容
本公开的一个实施例提供了一种显示基板，包括位于衬底基板上的显示区和位于所述显示区四周的周边区，所述周边区包括位于所述显示基板一侧的第一周边区，所述显示基板包括测试电路，所述测试电路位于所述第一周边区中并且包括信号输出端。
所述测试电路还包括第一信号线、第二信号线和开关结构，所述第一信号线、所述第二信号线和所述开关结构位于所述第一周边区中，所述开关结构与所述第一信号线、所述第二信号线和所述信号输出端连接。所述开关结构在所述第二信号线输出的导 通信号的控制下导通，以使所述第一信号线与所述信号输出端电连接。
在一些实施方式中，所述测试电路还包括信号输入端，配置用于输入所述测试电路的驱动信号，其中，所述第一信号线、所述第二信号线和所述开关结构位于所述信号输入端和所述信号输出端之间。
在一些实施方式中，所述开关结构还配置为在所述第二信号线输出的关闭信号的控制下断开，以使所述第一信号线与所述信号输出端之间断开连接。
在一些实施方式中，所述信号输出端包括多个输出管脚，所述开关结构包括与每个所述输出管脚对应的开关管；所述开关管的控制极连接至所述第二信号线；所述开关管的第一极连接至所述第一信号线；所述开关管的第二极连接至对应的输出管脚。
在一些实施方式中，所述开关管包括薄膜晶体管。
在一些实施方式中，所述，所述开关管的第一极为所述薄膜晶体管的源极，所述开关管的第二极为所述薄膜晶体管的漏极，所述开关管的控制极为所述薄膜晶体管的栅极。
在一些实施方式中，所述第一信号线为公共电极信号线，所述第二信号线为公共电极开关控制线。
在一些实施方式中，所述显示基板为阵列基板。
本公开的另一个实施例提供了一种显示面板，包括相对设置的对置基板和上述显示基板。
本公开的又一个实施例提供了一种显示装置，包括上述显示面板。
在一些实施方式中，所述显示面板为液晶显示面板。
附图说明
图1为相关技术中的显示基板的结构示意图；
图2为本公开的一个实施例提供的一种显示基板的结构示意图；
图3为图2中第一周边区的局部示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的显示基板、显示面板和显示装置进行详细描述。
图1为相关技术中的显示基板的结构示意图。如图1所示，显示基板上设置有显示区(虚线框区域)和位于显示区四周的周边区，周边区包括第一周边区(即，测试电路所在的区域)、与第一周边区相对的第二周边区和GOA(Gate On Array)侧区域，显示基板包括衬底基板1，测试电路包括位于衬底基板1之上的信号输入端2和信号输出端3，信号输入端2和信号输出端3位于第一周边区。显示基板还包括测试电路，测试电路包括位于衬底基板1之上的第一信号线(即，公共电极信号线)4、第二信号线(即，公共电极开关控制线)5和开关结构6，第一信号线4和第二信号线5环绕显示面板的屏幕一周。相关技术中的第一信号线和第二信号线的布线方式占用较大空间；且会对周边容值产生一定影响，造成GOA侧区域及第二周边区容值偏高，所述容值为触控控制电路的电容值，从而降低了显示面板的容值均一性。
图2为本公开的一个实施例提供的一种显示基板的结构示意图，图3为图2中第一周边区的局部示意图，如图2和图3所示，显示基板上设置有显示区(虚线框区域)和位于显示区四周的周边区，周边区包括位于显示基板一侧的第一周边区、第二周边区和GOA侧区域，显示基板包括衬底基板1和位于衬底基板1之上的信号输入端2和信号输出端3，信号输入端2和信号输出端3位于第一周边区。显示基板还包括测试电路，测试电路包括位于衬底基板1之上的第一信号线4、第二信号线5和开关结构6，第一信号线4、第二信号线5和开关结构6位于第一周边区，开关结构6与第一信号线4、第二信号线5和信号输出端3连接。开关结构6用于在第二信号线5输出的导通信号的控制下导通，以使第 一信号线4与信号输出端3电连接。
本实施例中，优选地，第一信号线4、第二信号线5和开关结构6位于信号输入端2和信号输出端3之间。
进一步地，开关结构6还用于在第二信号线5输出的关闭信号的控制下断开，以使所述第一信号线4与信号输出端3之间断开连接。
由于显示基板包括四个侧边区域，因此周边区包括四个侧边区域，该四个侧边区域分别为第一周边区、第二周边区和两个GOA侧区域，第一周边区与第二周边区相对设置，两个GOA侧区域相对设置。信号输入端2和信号输出端3之间存在较大的空闲空间，因此可将第一信号线4、第二信号线5和开关结构6设置于该空闲空间内。
如图3所示，信号输入端2包括多个输入管脚21。输入管脚21的数量可根据产品设计需要进行设置，图3中仅以三个为例进行描述。
如图3所示，信号输出端3包括多个输出管脚31。输出管脚31的数量可根据产品设计需要进行设置，图3中仅以三个为例进行描述。
如图3所示，开关结构6包括与每个输出管脚31对应的开关管T。换言之，开关结构6包括多个开关管T，开关管T与输出管脚31一一对应设置。开关管T的控制极连接至第二信号线5，开关管T的第一极连接至第一信号线4，开关管T的第二极连接至对应的输出管脚31。每个开关管T在第二信号线5输出的导通信号的控制下导通，以使第一信号线4通过导通的开关管T与对应的信号输出端3电连接，例如，第二信号线5输出导通信号，该导通信号为高电平信号，则开关管T在高电平信号的控制下导通，此时第一信号线4与对应的信号输出端3电连接。每个开关管T在第二信号线5输出的关闭信号的控制下断开，以使第一信号线4开关管T与对应的信号输出端3之间断开连接，例如，第二信号线5输出关闭信号，该关闭信号为低电平信号，则开关管T在低 电平信号的控制下断开，此时第一信号线4与对应的信号输出端3之间断开连接。
本实施例中，优选地，开关管T包括薄膜晶体管TFT(Thin Film Transistor)。
进一步地，信号输出端通过屏幕触摸信号(Touch panel metal，简称TPM)线连接至显示区。如图3所示，输出管脚31通过TPM线7连接至显示区。
进一步地，如图2所示，该显示基板还包括：位于衬底基板1上的接地线(GND线)8。接地线8可位于第二周边区和GOA侧区域。
当本实施例中的显示基板与对置基板对盒后形成显示面板之后，需要对显示面板进行点灯测试。在点灯状态下，第二信号线5输出导通信号，开关管T在导通信号的控制下导通，此时第一信号线4与对应的信号输出端3电连接。第一信号线4输出的公共电极信号依次通过对应的输出管脚31和TPM线输出至显示区。在显示面板完成点灯测试之后，第二信号线5输出关闭信号，开关管T在关闭信号的控制下断开，开关管T相当于悬空，第一信号线4与对应的信号输出端3之间断开连接，此时信号可通过信号输入端和信号输出端向显示区正常输出显示信号，处于关闭状态的开关管T不会影响信号的正常输出。
本实施例中，显示基板可以为阵列基板，则对置基板可以为彩膜基板，显示面板可以为液晶显示面板。
本实施例提供的显示基板的技术方案中，第一信号线、第二信号线和开关结构均位于第一周边区，充分利用了信号输入端和信号输出端之间的空间，使得第二周边区和GOA侧区域的边缘空间得到了释放，从而进一步实现窄边框显示；由于第一信号线、第二信号线和开关结构不再占用第二周边区和GOA侧区域的边缘空间，从而降低了第二周边区和GOA侧区域的容值，从而提高了显示面板的容值均一性。
本公开的另一个实施例提供了一种显示面板，该显示面板包 括相对设置的对置基板和显示基板。
其中，显示基板可采用上述实施例提供的显示基板，此处不再赘述。
本实施例中，显示基板可以为阵列基板，对置基板可以为彩膜基板，则显示面板可以为液晶显示面板。
本实施例提供的显示面板的技术方案中，第一信号线、第二信号线和开关结构均位于第一周边区，充分利用了信号输入端和信号输出端之间的空间，使得第二周边区和GOA侧区域的边缘空间得到了释放，从而进一步实现窄边框显示；由于第一信号线、第二信号线和开关结构不再占用第二周边区和GOA侧区域的边缘空间，从而降低了第二周边区和GOA侧区域的容值，从而提高了显示面板的容值均一性。
本公开又一个实施例提供了一种显示装置，该显示装置包括上述实施例提供的显示面板。
本实施例提供的显示装置的技术方案中，第一信号线、第二信号线和开关结构均位于第一周边区，充分利用了信号输入端和信号输出端之间的空间，使得第二周边区和GOA侧区域的边缘空间得到了释放，从而进一步实现窄边框显示；由于第一信号线、第二信号线和开关结构不再占用第二周边区和GOA侧的区域边缘空间，从而降低了第二周边区和GOA侧区域的容值，从而提高了显示面板的容值均一性。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (11)

  1. 一种显示基板，包括位于衬底基板上的显示区和位于所述显示区四周的周边区，所述周边区包括位于所述显示基板一侧的第一周边区，所述显示基板包括测试电路，所述测试电路位于所述第一周边区中并且包括信号输出端，其中，
    所述测试电路还包括第一信号线、第二信号线和开关结构，所述第一信号线、所述第二信号线和所述开关结构位于所述第一周边区中，
    所述开关结构与所述第一信号线、所述第二信号线和所述信号输出端连接，并且所述开关结构在所述第二信号线输出的导通信号的控制下导通，以使所述第一信号线与所述信号输出端电连接。
  2. 根据权利要求1所述的显示基板，所述测试电路还包括信号输入端，配置用于输入所述测试电路的驱动信号，其中，所述第一信号线、所述第二信号线和所述开关结构位于所述信号输入端和所述信号输出端之间。
  3. 根据权利要求1或2所述的显示基板，所述开关结构还配置为在所述第二信号线输出的关闭信号的控制下断开，以使所述第一信号线与所述信号输出端之间断开连接。
  4. 根据权利要求1至3中任一项所述的显示基板，所述信号输出端包括多个输出管脚，所述开关结构包括与每个所述输出管脚对应的开关管；
    所述开关管的控制极连接至所述第二信号线；
    所述开关管的第一极连接至所述第一信号线；并且
    所述开关管的第二极连接至对应的输出管脚。
  5. 根据权利要求4所述的显示基板，所述开关管包括薄膜晶体管。
  6. 根据权利要求5所述的显示基板，所述开关管的第一极为所述薄膜晶体管的源极，所述开关管的第二极为所述薄膜晶体管的漏极，所述开关管的控制极为所述薄膜晶体管的栅极。
  7. 根据权利要求6所述的显示基板，所述第一信号线为公共电极信号线，所述第二信号线为公共电极开关控制线。
  8. 根据权利要求1所述的显示基板，所述显示基板为阵列基板。
  9. 一种显示面板，包括相对设置的对置基板和显示基板，所述显示基板包括权利要求1至8任一项所述的显示基板。
  10. 一种显示装置，包括权利要求9所述的显示面板。
  11. 根据权利要求10所述的显示装置，所述显示面板为液晶显示面板。
PCT/CN2019/087449 2018-05-24 2019-05-17 显示基板、显示面板和显示装置 WO2019223623A1 (zh)

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