WO2020155408A1 - 下窄边框显示面板 - Google Patents

下窄边框显示面板 Download PDF

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Publication number
WO2020155408A1
WO2020155408A1 PCT/CN2019/082970 CN2019082970W WO2020155408A1 WO 2020155408 A1 WO2020155408 A1 WO 2020155408A1 CN 2019082970 W CN2019082970 W CN 2019082970W WO 2020155408 A1 WO2020155408 A1 WO 2020155408A1
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WIPO (PCT)
Prior art keywords
unit
test
array
switches
signal line
Prior art date
Application number
PCT/CN2019/082970
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English (en)
French (fr)
Inventor
余文静
严志成
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/488,590 priority Critical patent/US11373564B2/en
Publication of WO2020155408A1 publication Critical patent/WO2020155408A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present disclosure relates to the field of liquid crystal display, in particular to a display panel with a lower narrow frame.
  • liquid crystal display devices Liquid Crystal Display, LCD
  • Plasma Display Panel PDP
  • Electro Luminescences Display ELD
  • Vacuum Fluorescence Display Vacuum Fluorescence Display
  • the driver integrated circuit plays an important role.
  • the commonly used structure of the driver integrated circuit is to set the driver integrated circuit on the polyimide substrate, and the array test (array test) which detects the electrical properties of the entire display panel
  • the test circuit and the celltest circuit are directly placed between the input and output circuits of the driver integrated circuit.
  • the size of the driver integrated circuit will gradually shrink, and the remaining space is not enough to place the array test circuit and the unit test circuit.
  • the existing display panel has the problem that there is no room for the array test circuit and the unit test circuit. Therefore, it is necessary to provide a low-bezel display panel to improve this defect.
  • the commonly used structure of the driver integrated circuit is to set the driver integrated circuit on the polyimide substrate, and the array test (array test) which detects the electrical properties of the entire display panel
  • the test circuit and the celltest circuit are directly placed between the input and output circuits of the driver integrated circuit.
  • the size of the driver integrated circuit will gradually shrink, and the remaining space is not enough to place the array test circuit and the unit test circuit.
  • the present disclosure provides a narrow-frame display panel, which is used to solve the problem that the existing display panel does not have enough space for array test circuits and unit test circuits.
  • the present disclosure provides a lower narrow frame display panel, including:
  • An array test unit including a plurality of array test switches and a plurality of array test pads;
  • a unit test unit including a plurality of unit test switches
  • the array test unit is arranged between the pixel unit and the unit test unit, one end of the plurality of array test switches is connected to a plurality of data lines of the pixel unit, and the plurality of unit test switches Connected to the other end of the plurality of array test switches.
  • the plurality of array test switches are arranged between the pixel unit and the plurality of array test pads.
  • the plurality of array test switches includes a plurality of first array test switches, a plurality of second array test switches, a plurality of third array test switches, and a plurality of fourth array test switches.
  • the test unit includes a first array test control signal line, a second array test control signal line, a third array test control signal line, and a fourth array test control signal line.
  • the gates of the plurality of first array test switches and the The first array test control signal line is connected, the gates of the second array test switches are connected to the second array test control signal line, and the gates of the third array test switches are connected to the The third array test control signal line is connected, and the gates of the plurality of fourth array test switches are connected to the fourth array test control signal line.
  • the multiple unit test switches include multiple first unit test switches, multiple second unit test switches, multiple third unit test switches, and multiple fourth unit test switches.
  • the test unit includes a first unit test signal line, a second unit test signal line, and a third unit test signal line.
  • the drains of the plurality of first unit test switches are connected to the first unit test signal line.
  • the drains of the plurality of second unit test switches are connected to the second unit test signal line, the drains of the plurality of third unit test switches are connected to the third unit test signal line, and the plurality of The drain of the fourth unit test switch is connected to the second unit test signal line.
  • the unit test unit includes a unit test control signal line for providing signals for opening and closing the plurality of unit test switches.
  • the gates of the plurality of unit test switches are all connected to the unit test control signal line.
  • the unit test unit remains in an off state when the array test is executed.
  • the array test unit maintains a conductive state when performing a unit test.
  • the pixel unit includes a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels.
  • the first pixel and the second pixel are alternately arranged in the same column, and the third pixel is arranged at the phase of the column having the first pixel and the second pixel. In the neighborhood.
  • the present disclosure also provides a lower narrow bezel display panel, including:
  • An array test unit including a plurality of array test switches and a plurality of array test pads;
  • a unit test unit the unit test unit includes a plurality of unit test switches and a unit test control signal line, the unit test control signal line is connected with the unit test switch;
  • the array test unit is arranged between the pixel unit and the unit test unit, one end of the plurality of array test switches is connected to a plurality of data lines of the pixel unit, and the plurality of unit test switches Connected to the other end of the plurality of array test switches.
  • the plurality of array test switches are arranged between the pixel unit and the plurality of array test pads.
  • the plurality of array test switches includes a plurality of first array test switches, a plurality of second array test switches, a plurality of third array test switches, and a plurality of fourth array test switches.
  • the test unit includes a first array test control signal line, a second array test control signal line, a third array test control signal line, and a fourth array test control signal line.
  • the gates of the plurality of first array test switches and the The first array test control signal line is connected, the gates of the second array test switches are connected to the second array test control signal line, and the gates of the third array test switches are connected to the The third array test control signal line is connected, and the gates of the plurality of fourth array test switches are connected to the fourth array test control signal line.
  • the multiple unit test switches include multiple first unit test switches, multiple second unit test switches, multiple third unit test switches, and multiple fourth unit test switches.
  • the test unit includes a first unit test signal line, a second unit test signal line, and a third unit test signal line.
  • the drains of the plurality of first unit test switches are connected to the first unit test signal line.
  • the drains of the plurality of second unit test switches are connected to the second unit test signal line, the drains of the plurality of third unit test switches are connected to the third unit test signal line, and the plurality of The drain of the fourth unit test switch is connected to the second unit test signal line.
  • the unit test unit remains in an off state when the array test is executed.
  • the array test unit maintains a conductive state when performing a unit test.
  • the pixel unit includes a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels.
  • the first pixel and the second pixel are alternately arranged in the same column, and the third pixel is arranged at the phase of the column having the first pixel and the second pixel. In the neighborhood.
  • the present disclosure also provides a lower narrow bezel display panel, including:
  • a pixel unit includes a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels, the first pixels and the second pixels are alternately arranged in the same column, and the third pixels are arranged In an adjacent column of the column having the first pixel and the second pixel;
  • An array test unit including a plurality of array test switches and a plurality of array test pads;
  • a unit test unit the unit test unit includes a plurality of unit test switches and a unit test control signal line, the unit test control signal line is connected with the unit test switch;
  • the array test unit is arranged between the pixel unit and the unit test unit, the plurality of array test switches are arranged between the pixel unit and the plurality of array test pads, and the One end of the plurality of array test switches is connected to the plurality of data lines of the pixel unit, and the plurality of unit test switches are connected to the other end of the plurality of array test switches.
  • the plurality of array test switches are arranged between the pixel unit and the plurality of array test pads.
  • one end of the multiple array test switches of the array test unit is connected to the multiple data lines of the pixel unit, and the multiple unit test switches of the unit test unit are connected to the other ends of the multiple array test switches.
  • the array test circuit and the unit test circuit are combined, while ensuring the measurement effect, the space originally occupied by the array test circuit and the unit test circuit is reduced, thereby narrowing the width of the lower frame of the display panel.
  • FIG. 1 is a schematic diagram of a circuit structure provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the AC signal of the GOA provided by the embodiment of the disclosure.
  • the embodiments of the present disclosure provide a display panel with a lower narrow frame, which will be described in detail below with reference to FIGS. 1 to 2.
  • the embodiment of the present disclosure provides a lower narrow bezel display panel.
  • the lower narrow bezel display panel includes, as shown in FIG. 1, a pixel unit 101, an array test unit 102, and a cell test unit. test) unit 103, the array test unit is arranged between the pixel unit 101 and the unit test unit 103.
  • the array test unit 102 is used to detect whether the thin film transistors (Thin Film Transistor, TFT) and capacitors formed in each pixel in the pixel unit 101 are defective.
  • TFT Thin Film Transistor
  • the array test unit 102 receives the array test signal and the array test control signal, and corresponding to the array test control signal, selectively supplies the array test signal to the pixel unit 101.
  • the unit test unit 103 is used to detect the light-emitting characteristics of the display panel. When performing a unit test, the unit test unit 103 receives a unit test signal and a unit test control signal, and corresponds to the unit test control signal to selectively supply the pixel unit 101 Unit test signal.
  • the array test unit 102 includes a plurality of array test switches 104 and a plurality of array test pads 106 (array test pads) and a plurality of array test control signal lines 107, and the unit test unit includes a plurality of unit test switches 105, A unit test signal line 108 and a unit test control signal line 109.
  • One end of the multiple array test switches 104 is connected to the multiple data lines of the pixel unit 101, the other end of the multiple array test switches 104 is connected to the multiple array test pads 106, and the multiple The unit test switch 105 is connected to the other end of the plurality of array test switches 104.
  • the plurality of array test switches 104 are arranged between the pixel unit 101 and the array test pad 106.
  • the plurality of array test switches 104 includes: a plurality of first array test switches AT_SW1, a plurality of second array test switches AT_SW2, a plurality of third array test switches AT_SW3, and a plurality of fourth array test switches AT_SW4, the array test unit further includes a first array test control signal line 107a, a second array test control signal line 107b, a third array test control signal line 107c, and a fourth array test control signal line 107d.
  • the gate of an array test switch AT_SW1 is connected to the first array test control signal line 107a, the first array test control signal line 107a provides the control signal EN_R/B, and the gates of the plurality of second array test switches AT_SW2 Connected to the second array test control signal line 107b, the second array test control signal line 107b provides the control signal EN_G, and the gates of the plurality of third array test switches AT_SW3 are connected to the third array test control signal line 107c,
  • the third array test control signal line 107c provides control signals EN_B/R, the gates of the plurality of fourth array test switches AT_SW4 are connected to the fourth array test control signal line 107d, and the fourth array test control signal
  • the line 107d provides the control signal EN_G.
  • the plurality of unit test switches 105 includes: a plurality of first unit test switches CT_SW1, a plurality of second unit test switches CT_SW2, a plurality of third unit test switches CT_SW3, and a plurality of fourth unit test switches CT_SW4, the unit test unit further includes a first unit test signal line 108a, a second unit test signal line 108b, and a third unit test signal line 108c.
  • the drains of the plurality of first unit test switches CT_SW1 and the first unit The test signal line 108a is connected, the first unit test signal line 108a provides the unit test signal CT_Data_R/B, the drains of the plurality of second unit test switches CT_SW2 are connected to the second unit test signal line 108b, The second unit test signal line 108b provides the unit test signal CT_Data_G, the drains of the plurality of third unit test switches CT_SW3 are connected to the third unit test signal line 108c, and the third unit test signal line 108c provides the unit test signal CT_Data_B/R, the drains of the plurality of fourth unit test switches CT_SW4 are connected to the second unit test signal line 108b.
  • the unit test unit 103 includes a unit test control signal line 109, and the unit test control signal line 109 is used to provide the unit test control signal EN_CT for turning on or off the plurality of unit test switches 105, so The gates of the plurality of unit test switches 105 are all connected to the unit test control signal line 109.
  • the unit test unit 103 is kept in an off state when the array test is executed.
  • the multiple unit test signal lines 108 that provide unit test signals are turned off when performing array testing.
  • the multiple first unit test switches CT_SW1, multiple second unit test switches CT_SW2, multiple third unit test switches CT_SW3, and multiple fourth unit test switches CT_SW4 connected to the control signal line 109 are also closed. At this time, the array test unit 102 The circuit keeps working normally.
  • the array test unit 102 maintains a conducting state when performing a unit test.
  • a conducting state As shown in Figure 1, in order to make the unit test signal pass through the array test unit when performing the unit test, multiple first array test switches AT_SW1, multiple second array test switches AT_SW2, multiple third array test switches AT_SW3, and The multiple fourth array test switches AT_SW4 are all clocked in, the array test pad 106 does not provide a signal, and the circuit of the unit test unit 103 keeps working normally.
  • the pixel unit 101 includes a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels emitting different colors, the first pixels and the second pixels are alternately arranged In the same column, the third pixel is arranged in alignment with the adjacent column in which the first pixel and the second pixel are arranged.
  • the first pixel is a red pixel R emitting red light
  • the second pixel is a blue pixel B emitting blue light
  • the third pixel is a green pixel G emitting green light.
  • the red pixels R and the blue pixels B are alternately arranged in the same column, and the green pixels G are arranged in alignment with the adjacent columns D2 and D4 in which the red pixels R and the blue pixels B are arranged.
  • the smallest pixel repeat unit is two rows of pixels in the horizontal direction and four columns of pixels perpendicular to the horizontal direction.
  • the light-emitting pixel unit in the first row is RGBG
  • the light-emitting unit in the second row is BGRG.
  • the AC signal shown in FIG. 2 needs to be supplied.
  • the R pixel in the first row lights up, and the array substrate row drive (Gate Driver On Array (GOA) circuit signal is low level; B pixel located in the second row is lit, at this time GOA circuit signal is also low level signal.
  • GOA Gate Driver On Array
  • one end of the multiple array test switches of the array test unit is connected to the multiple data lines of the pixel unit, and the multiple unit test switches of the unit test unit are connected to the other ends of the multiple array test switches, so that the array test circuit and The unit test circuit is combined to reduce the space originally occupied by the array test circuit and the unit test circuit while ensuring the measurement effect, thereby narrowing the width of the lower frame of the display panel.
  • the embodiments of the present disclosure provide a display panel with a lower narrow frame, which will be described in detail below with reference to FIGS. 1 to 2.
  • the embodiment of the present disclosure provides a lower narrow bezel display panel.
  • the lower narrow bezel display panel includes, as shown in FIG. 1, a pixel unit 101, an array test unit 102, and a cell test unit. test) unit 103, the array test unit is arranged between the pixel unit 101 and the unit test unit 103.
  • the array test unit 102 is used to detect whether the thin film transistors (Thin Film Transistor, TFT) and capacitors formed in each pixel in the pixel unit 101 are defective.
  • TFT Thin Film Transistor
  • the array test unit 102 receives the array test signal and the array test control signal, and corresponding to the array test control signal, selectively supplies the array test signal to the pixel unit 101.
  • the unit test unit 103 is used to detect the light-emitting characteristics of the display panel. When performing a unit test, the unit test unit 103 receives a unit test signal and a unit test control signal, and corresponds to the unit test control signal to selectively supply the pixel unit 101 Unit test signal.
  • the array test unit 102 includes a plurality of array test switches 104 and a plurality of array test pads 106 (array test pads) and a plurality of array test control signal lines 107, and the unit test unit includes a plurality of unit test switches 105, A unit test signal line 108 and a unit test control signal line 109.
  • the unit test control signal line 109 is used to provide the unit test control signal EN_CT for turning on or off the plurality of unit test switches 105.
  • the gates of 105 are all connected to the unit test control signal line 109.
  • One end of the multiple array test switches 104 is connected to the multiple data lines of the pixel unit 101, the other end of the multiple array test switches 104 is connected to the multiple array test pads 106, and the multiple The unit test switch 105 is connected to the other end of the plurality of array test switches 104.
  • the plurality of array test switches 104 are arranged between the pixel unit 101 and the array test pad 106.
  • the plurality of array test switches 104 includes: a plurality of first array test switches AT_SW1, a plurality of second array test switches AT_SW2, a plurality of third array test switches AT_SW3, and a plurality of fourth array test switches AT_SW4, the array test unit further includes a first array test control signal line 107a, a second array test control signal line 107b, a third array test control signal line 107c, and a fourth array test control signal line 107d.
  • the gate of an array test switch AT_SW1 is connected to the first array test control signal line 107a, the first array test control signal line 107a provides the control signal EN_R/B, and the gates of the plurality of second array test switches AT_SW2 Connected to the second array test control signal line 107b, the second array test control signal line 107b provides the control signal EN_G, and the gates of the plurality of third array test switches AT_SW3 are connected to the third array test control signal line 107c,
  • the third array test control signal line 107c provides control signals EN_B/R, the gates of the plurality of fourth array test switches AT_SW4 are connected to the fourth array test control signal line 107d, and the fourth array test control signal
  • the line 107d provides the control signal EN_G.
  • the plurality of unit test switches 105 includes: a plurality of first unit test switches CT_SW1, a plurality of second unit test switches CT_SW2, a plurality of third unit test switches CT_SW3, and a plurality of fourth unit test switches CT_SW4, the unit test unit further includes a first unit test signal line 108a, a second unit test signal line 108b, and a third unit test signal line 108c.
  • the drains of the plurality of first unit test switches CT_SW1 and the first unit The test signal line 108a is connected, the first unit test signal line 108a provides the unit test signal CT_Data_R/B, the drains of the plurality of second unit test switches CT_SW2 are connected to the second unit test signal line 108b, The second unit test signal line 108b provides the unit test signal CT_Data_G, the drains of the plurality of third unit test switches CT_SW3 are connected to the third unit test signal line 108c, and the third unit test signal line 108c provides the unit test signal CT_Data_B/R, the drains of the plurality of fourth unit test switches CT_SW4 are connected to the second unit test signal line 108b.
  • the unit test unit 103 is kept in an off state when the array test is executed.
  • the multiple unit test signal lines 108 that provide unit test signals are turned off when performing array testing.
  • the multiple first unit test switches CT_SW1, multiple second unit test switches CT_SW2, multiple third unit test switches CT_SW3, and multiple fourth unit test switches CT_SW4 connected to the control signal line 109 are also closed. At this time, the array test unit 102 The circuit keeps working normally.
  • the array test unit 102 maintains a conducting state when performing a unit test.
  • a conducting state As shown in Figure 1, in order to make the unit test signal pass through the array test unit when performing the unit test, multiple first array test switches AT_SW1, multiple second array test switches AT_SW2, multiple third array test switches AT_SW3, and The multiple fourth array test switches AT_SW4 are all clocked in, the array test pad 106 does not provide a signal, and the circuit of the unit test unit 103 keeps working normally.
  • the pixel unit 101 includes a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels emitting different colors, the first pixels and the second pixels are alternately arranged In the same column, the third pixel is arranged in alignment with the adjacent column in which the first pixel and the second pixel are arranged.
  • the first pixel is a red pixel R emitting red light
  • the second pixel is a blue pixel B emitting blue light
  • the third pixel is a green pixel G emitting green light.
  • the red pixels R and the blue pixels B are alternately arranged in the same column, and the green pixels G are arranged in alignment with the adjacent columns D2 and D4 in which the red pixels R and the blue pixels B are arranged.
  • the smallest pixel repeat unit is two rows of pixels in the horizontal direction and four columns of pixels perpendicular to the horizontal direction.
  • the light-emitting pixel unit in the first row is RGBG
  • the light-emitting unit in the second row is BGRG.
  • the AC signal shown in FIG. 2 needs to be supplied.
  • the R pixel in the first row lights up, and the array substrate row drive (Gate Driver On Array (GOA) circuit signal is low level; B pixel located in the second row is lit, at this time GOA circuit signal is also low level signal.
  • GOA Gate Driver On Array
  • the embodiments of the present disclosure provide a display panel with a lower narrow frame, which will be described in detail below with reference to FIGS. 1 to 2.
  • the embodiment of the present disclosure provides a lower narrow bezel display panel.
  • the lower narrow bezel display panel includes, as shown in FIG. 1, a pixel unit 101, an array test unit 102, and a cell test unit. test) unit 103, the array test unit is arranged between the pixel unit 101 and the unit test unit 103.
  • the array test unit 102 is used to detect whether the thin film transistors (Thin Film Transistor, TFT) and capacitors formed in each pixel in the pixel unit 101 are defective.
  • TFT Thin Film Transistor
  • the array test unit 102 receives the array test signal and the array test control signal, and corresponding to the array test control signal, selectively supplies the array test signal to the pixel unit 101.
  • the unit test unit 103 is used to detect the light-emitting characteristics of the display panel. When performing a unit test, the unit test unit 103 receives a unit test signal and a unit test control signal, and corresponds to the unit test control signal to selectively supply the pixel unit 101 Unit test signal.
  • the array test unit 102 includes a plurality of array test switches 104 and a plurality of array test pads 106 (array test pads) and a plurality of array test control signal lines 107, and the unit test unit includes a plurality of unit test switches 105, A unit test signal line 108 and a unit test control signal line 109.
  • the unit test control signal line 109 is used to provide the unit test control signal EN_CT for turning on or off the plurality of unit test switches 105.
  • the gates of 105 are all connected to the unit test control signal line 109.
  • One end of the multiple array test switches 104 is connected to the multiple data lines of the pixel unit 101, the other end of the multiple array test switches 104 is connected to the multiple array test pads 106, and the multiple The unit test switch 105 is connected to the other end of the plurality of array test switches 104.
  • the pixel unit 101 includes a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels emitting different colors, the first pixels and the second pixels are alternately arranged in the same column, The three pixels are arranged in alignment with the adjacent column in which the first pixel and the second pixel are arranged.
  • the plurality of array test switches 104 are arranged between the pixel unit 101 and the array test pad 106.
  • one end of the multiple array test switches 104 of the array test unit 102 is connected to multiple data lines of the pixel unit 101, and the multiple unit test switches 105 of the unit test unit 103 are connected to the other end of the multiple array test switches 104.
  • the array test circuit and the unit test circuit are combined, while ensuring the measurement effect, the space originally occupied by the array test circuit and the unit test circuit is reduced, thereby narrowing the width of the lower frame of the display panel.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种下窄边框显示面板，包括像素单元（101）、阵列测试单元（102）以及单元测试单元（103），通过将阵列测试电路与单元测试电路合并，在保证测量效果的同时，减小了阵列测试电路和单元测试电路原本所占据的空间，从而缩窄显示面板的下边框宽度。

Description

下窄边框显示面板 技术领域
本揭示涉及液晶显示领域，尤其涉及一种下窄边框显示面板。
 背景技术
随着全球信息社会的兴起增加了对各种显示装置的需求。因此，对各种平面显示装置的研究和开发投入了很大的努力，如液晶显示装置(Liquid Crystal Display, LCD)、等离子显示装置(Plasma Display Panel, PDP)、场致发光显示装置(Electro Luminescences Display,ELD)以及真空荧光显示装置(Vacuum Fluorescent Display, VFD)等。
在显示装置普及的同时，用户不仅对显示装置所具备的功能种类和性能要求越来越高，而且用户对显示装置的外观上的要求也越来越高，显示装置的轻薄化以及窄边框等条件也越来越多成为用于选择的显示装置的因素。
在影响手机边框众多的因素中，驱动集成电路占据着重要的作用。目前驱动集成电路常用的结构是将驱动集成电路设置在聚酰亚胺基板上，而检测整个显示面板电性的阵列测试 (array test)电路和单元测试（celltest）电路则直接放在驱动集成电路的输入和输出电路中间。随着手机边框逐渐缩窄，驱动集成电路的大小也会逐渐缩减，剩余的空间不足以放置阵列测试电路和单元测试电路。
综上所述，现有显示面板存在没有富余空间放置阵列测试电路和单元测试电路的问题。故，有必要提供一种下窄边框显示面板来改善这一缺陷。
 技术问题
目前驱动集成电路常用的结构是将驱动集成电路设置在聚酰亚胺基板上，而检测整个显示面板电性的阵列测试 (array test)电路和单元测试（celltest）电路则直接放在驱动集成电路的输入和输出电路中间。随着手机边框逐渐缩窄，驱动集成电路的大小也会逐渐缩减，剩余的空间不足以放置阵列测试电路和单元测试电路。
 技术解决方案
本揭示提供一种窄边框显示面板，用于解决现有显示面板没有富余空间放置阵列测试电路和单元测试电路的问题。
本揭示提供一种下窄边框显示面板，包括:
像素单元；
阵列测试单元，所述阵列测试单元包括多个阵列测试开关和多个阵列测试焊盘；以及
单元测试单元，所述单元测试单元包括多个单元测试开关；
其中，所述阵列测试单元设置于所述像素单元与所述单元测试单元之间，所述多个阵列测试开关的一端连接至所述像素单元的多条数据线，所述多个单元测试开关连接至所述多个阵列测试开关的另一端。
根据本揭示一实施例，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间。
根据本揭示一实施例，所述多个阵列测试开关包括多个第一阵列测试开关、多个第二阵列测试开关、多个第三阵列测试开关以及多个第四阵列测试开关，所述阵列测试单元包括第一阵列测试控制信号线、第二阵列测试控制信号线、第三阵列测试控制信号线以及第四阵列测试控制信号线，所述多个第一阵列测试开关的栅极与所述第一阵列测试控制信号线相连接，所述多个第二阵列测试开关的栅极与所述第二阵列测试控制信号线相连接，所述多个第三阵列测试开关的栅极与所述第三阵列测试控制信号线相连接，所述多个第四阵列测试开关的栅极与所述第四阵列测试控制信号线相连接。
根据本揭示一实施例，所述多个单元测试开关包括多个第一单元测试开关、多个第二单元测试开关、多个第三单元测试开关以及多个第四单元测试开关，所述单元测试单元包括第一单元测试信号线、第二单元测试信号线以及第三单元测试信号线，所述多个第一单元测试开关的漏极与所述第一单元测试信号线相连接，所述多个第二单元测试开关的漏极与所述第二单元测试信号线相连接，所述多个第三单元测试开关的漏极与所述第三单元测试信号线相连接，所述多个第四单元测试开关的漏极与所述第二单元测试信号线相连接。
根据本揭示一实施例，所述单元测试单元包括单元测试控制信号线，用于提供所述多个单元测试开关打开和关闭的信号。
根据本揭示一实施例，所述多个单元测试开关的栅极均连接至所述单元测试控制信号线。
根据本揭示一实施例，所述单元测试单元在执行阵列测试时保持截止状态。
根据本揭示一实施例，所述阵列测试单元在执行单元测试时保持导通状态。
根据本揭示一实施例，所述像素单元包括多个第一像素、多个第二像素和多个第三像素。
根据本揭示一实施例，所述第一像素和所述第二像素交替设置在同一列中，所述第三像素设置在具有所述第一像素和所述第二像素的所述列的相邻列中。
本揭示还提供一种下窄边框显示面板，包括:
像素单元；
阵列测试单元，所述阵列测试单元包括多个阵列测试开关和多个阵列测试焊盘；以及
单元测试单元，所述单元测试单元包括多个单元测试开关以及单元测试控制信号线，所述单元测试控制信号线与所述单元测试开关相连接；
其中，所述阵列测试单元设置于所述像素单元与所述单元测试单元之间，所述多个阵列测试开关的一端连接至所述像素单元的多条数据线，所述多个单元测试开关连接至所述多个阵列测试开关的另一端。
根据本揭示一实施例，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间。
根据本揭示一实施例，所述多个阵列测试开关包括多个第一阵列测试开关、多个第二阵列测试开关、多个第三阵列测试开关以及多个第四阵列测试开关，所述阵列测试单元包括第一阵列测试控制信号线、第二阵列测试控制信号线、第三阵列测试控制信号线以及第四阵列测试控制信号线，所述多个第一阵列测试开关的栅极与所述第一阵列测试控制信号线相连接，所述多个第二阵列测试开关的栅极与所述第二阵列测试控制信号线相连接，所述多个第三阵列测试开关的栅极与所述第三阵列测试控制信号线相连接，所述多个第四阵列测试开关的栅极与所述第四阵列测试控制信号线相连接。
根据本揭示一实施例，所述多个单元测试开关包括多个第一单元测试开关、多个第二单元测试开关、多个第三单元测试开关以及多个第四单元测试开关，所述单元测试单元包括第一单元测试信号线、第二单元测试信号线以及第三单元测试信号线，所述多个第一单元测试开关的漏极与所述第一单元测试信号线相连接，所述多个第二单元测试开关的漏极与所述第二单元测试信号线相连接，所述多个第三单元测试开关的漏极与所述第三单元测试信号线相连接，所述多个第四单元测试开关的漏极与所述第二单元测试信号线相连接。
根据本揭示一实施例，所述单元测试单元在执行阵列测试时保持截止状态。
根据本揭示一实施例，所述阵列测试单元在执行单元测试时保持导通状态。
根据本揭示一实施例，所述像素单元包括多个第一像素、多个第二像素和多个第三像素。
根据本揭示一实施例，所述第一像素和所述第二像素交替设置在同一列中，所述第三像素设置在具有所述第一像素和所述第二像素的所述列的相邻列中。
本揭示还提供一种下窄边框显示面板，包括:
像素单元，所述像素单元包括多个第一像素、多个第二像素以及多个第三像素，所述第一像素和所述第二像素交替设置在同一列中，所述第三像素设置在具有所述第一像素和所述第二像素的所述列的相邻列中；
阵列测试单元，所述阵列测试单元包括多个阵列测试开关和多个阵列测试焊盘；以及
单元测试单元，所述单元测试单元包括多个单元测试开关以及单元测试控制信号线，所述单元测试控制信号线与所述单元测试开关相连接；
其中，所述阵列测试单元设置于所述像素单元与所述单元测试单元之间，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间，并且所述多个阵列测试开关的一端连接至所述像素单元的多条数据线，所述多个单元测试开关连接至所述多个阵列测试开关的另一端。
根据本揭示一实施例，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间。
 有益效果
本揭示的有益效果：本揭示实施例将阵列测试单元的多个阵列测试开关的一端连接至像素单元的多条数据线，单元测试单元的多个单元测试开关连接至多个阵列测试开关的另一端，使得阵列测试电路与单元测试电路合并，在保证测量效果的同时，减小了阵列测试电路和单元测试电路原本所占据的空间，从而缩窄显示面板的下边框宽度。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示实施例提供的电路结构示意图；
图2为本揭示实施例提供的GOA的交流信号示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
实施例一：
本揭示实施例提供了一种下窄边框显示面板，下面结合图1至图2进行详细说明。
本揭示实施例提供一种下窄边框显示面板，所述下窄边框显示面板包括，如图1所示，像素单元101，阵列测试(array test)单元102以及单元测试(cell test)单元103，所述阵列测试单元设置于所述像素单元101和所述单元测试单元103之间。
所述阵列测试单元102用于检测像素单元101中的各像素中形成的薄膜晶体管（Thin Film Transistor，TFT）和电容器是否有缺陷。在执行阵列测试时，阵列测试单元102接收阵列测试信号和阵列测试控制信号，并且对应于阵列测试控制信号，向像素单元101选择性供应阵列测试信号。所述单元测试单元103用于检测显示面板的发光特性，在执行单元测试时，单元测试单元103接受单元测试信号和单元测试控制信号，并且对应于单元测试控制信号，向像素单元101选择性供应单元测试信号。
所述阵列测试单元102包括多个阵列测试开关104和多个阵列测试焊盘106（array test pad）以及多条阵列测试控制信号线107，所述单元测试单元包括多个单元测试开关105、多条单元测试信号线108以及单元测试控制信号线109。所述多个阵列测试开关104的一端连接至所述像素单元101的多条数据线，所述多个阵列测试开关104的另一端连接至所述多个阵列测试焊盘106，所述多个单元测试开关105连接至所述多个阵列测试开关104的另一端。
优选的，所述多个阵列测试开关104设置于所述像素单元101和所述阵列测试焊盘106之间。
在本实施例中，所述多个阵列测试开关104包括：多个第一阵列测试开关AT_SW1、多个第二阵列测试开关AT_SW2、多个第三阵列测试开关AT_SW3以及多个第四阵列测试开关AT_SW4，所述阵列测试单元还包括第一阵列测试控制信号线107a、第二阵列测试控制信号线107b、第三阵列测试控制信号线107c以及第四阵列测试控制信号线107d，所述多个第一阵列测试开关AT_SW1的栅极与第一阵列测试控制信号线107a相连接,所述第一阵列测试控制信号线107a提供控制信号EN_R/B，所述多个第二阵列测试开关AT_SW2的栅极与第二阵列测试控制信号线107b相连接，第二阵列测试控制信号线107b提供控制信号EN_G，所述多个第三阵列测试开关AT_SW3的栅极与第三阵列测试控制信号线107c相连接,所述第三阵列测试控制信号线107c提供控制信号EN_B/R，所述多个第四阵列测试开关AT_SW4的栅极与第四阵列测试控制信号线107d相连接, 所述第四阵列测试控制信号线107d提供控制信号EN_G。
如图1所示，所述多个单元测试开关105包括：多个第一单元测试开关CT_SW1、多个第二单元测试开关CT_SW2、多个第三单元测试开关CT_SW3、多个第四单元测试开关CT_SW4，所述单元测试单元还包括第一单元测试信号线108a以及第二单元测试信号线108b、第三单元测试信号线108c，所述多个第一单元测试开关CT_SW1的漏极与第一单元测试信号线108a相连接，所述第一单元测试信号线108a提供单元测试信号CT_Data_R/B，所述多个第二单元测试开关CT_SW2的漏极与第二单元测试信号线108b相连接,所述第二单元测试信号线108b提供单元测试信号CT_Data_G，所述多个第三单元测试开关CT_SW3的漏极与第三单元测试信号线108c相连接，所述第三单元测试信号线108c提供单元测试信号CT_Data_B/R，所述多个第四单元测试开关CT_SW4的漏极与所述第二单元测试信号线108b相连接。
如图1所示，所述单元测试单元103包括单元测试控制信号线109，所述单元测试控制信号线109用于提供所述多个单元测试开关105打开或关闭的单元测试控制信号EN_CT,所述多个单元测试开关105的栅极均连接至所述单元测试控制信号线109。
优选的，所述单元测试单元103在执行阵列测试时保持截止状态。如图1所示，在执行阵列测试时，为了避免阵列测试焊盘106与多条数据线相互连接出现短路的情况，提供单元测试信号的多条单元测试信号线108关闭，与所述单元测试控制信号线109相连的多个第一单元测试开关CT_SW1、多个第二单元测试开关CT_SW2、多个第三单元测试开关CT_SW3以及多个第四单元测试开关CT_SW4同样关闭，此时阵列测试单元102的电路保持正常工作。
优选的，所述阵列测试单元102在执行单元测试时保持导通状态。如图1所示，在执行单元测试时，为了使单元测试信号从阵列测试单元通过，多个第一阵列测试开关AT_SW1、多个第二阵列测试开关AT_SW2、多个第三阵列测试开关AT_SW3以及多个第四阵列测试开关AT_SW4均打卡，阵列测试焊盘106不提供信号，单元测试单元103的电路保持正常工作。
在本实施例中，如图1所示，所述像素单元101包括发射各自不同颜色的多个第一像素、多个第二像素以及多个第三像素，第一像素和第二像素交替布置在同一列中，第三像素对齐地设置在与其中布置有第一像素和第二像素的相邻列中。
优选的，如图1所示，第一像素是发射红光的红色像素R，第二像素是发射蓝光的蓝色像素B，第三像素是发射绿光的绿色像素G。红色像素R和蓝色像素B交替布置在同一列中，绿色像素G对齐设置在与其中布置有红色像素R和蓝色像素B的相邻列D2列和D4列中。
若像素排列顺序为优选实施例中的排列顺序，最小像素重复单元为横向两行、垂直于横向方向的四列像素。其中，第一行的发光像素单元为RGBG,第二行发光单元为BGRG。如图2所示，若需要保证第一行的R像素和第二行的B像素均能点亮，需要供给如图2所示的交流信号。位于第一行的R像素点亮，此时阵列基板行驱动（Gate Driver On Array,GOA）电路信号为低电平；位于第二行的B像素点亮，此时GOA电路信号也为低电平信号。
本揭示实施例将阵列测试单元的多个阵列测试开关的一端连接至像素单元的多条数据线，单元测试单元的多个单元测试开关连接至多个阵列测试开关的另一端，使得阵列测试电路与单元测试电路合并，在保证测量效果的同时，减小了阵列测试电路和单元测试电路原本所占据的空间，从而缩窄显示面板的下边框宽度。
实施例二：
本揭示实施例提供了一种下窄边框显示面板，下面结合图1至图2进行详细说明。
本揭示实施例提供一种下窄边框显示面板，所述下窄边框显示面板包括，如图1所示，像素单元101，阵列测试(array test)单元102以及单元测试(cell test)单元103，所述阵列测试单元设置于所述像素单元101和所述单元测试单元103之间。
所述阵列测试单元102用于检测像素单元101中的各像素中形成的薄膜晶体管（Thin Film Transistor，TFT）和电容器是否有缺陷。在执行阵列测试时，阵列测试单元102接收阵列测试信号和阵列测试控制信号，并且对应于阵列测试控制信号，向像素单元101选择性供应阵列测试信号。所述单元测试单元103用于检测显示面板的发光特性，在执行单元测试时，单元测试单元103接受单元测试信号和单元测试控制信号，并且对应于单元测试控制信号，向像素单元101选择性供应单元测试信号。
所述阵列测试单元102包括多个阵列测试开关104和多个阵列测试焊盘106（array test pad）以及多条阵列测试控制信号线107，所述单元测试单元包括多个单元测试开关105、多条单元测试信号线108以及单元测试控制信号线109，所述单元测试控制信号线109用于提供所述多个单元测试开关105打开或关闭的单元测试控制信号EN_CT,所述多个单元测试开关105的栅极均连接至所述单元测试控制信号线109。所述多个阵列测试开关104的一端连接至所述像素单元101的多条数据线，所述多个阵列测试开关104的另一端连接至所述多个阵列测试焊盘106，所述多个单元测试开关105连接至所述多个阵列测试开关104的另一端。
优选的，所述多个阵列测试开关104设置于所述像素单元101和所述阵列测试焊盘106之间。
在本实施例中，所述多个阵列测试开关104包括：多个第一阵列测试开关AT_SW1、多个第二阵列测试开关AT_SW2、多个第三阵列测试开关AT_SW3以及多个第四阵列测试开关AT_SW4，所述阵列测试单元还包括第一阵列测试控制信号线107a、第二阵列测试控制信号线107b、第三阵列测试控制信号线107c以及第四阵列测试控制信号线107d，所述多个第一阵列测试开关AT_SW1的栅极与第一阵列测试控制信号线107a相连接,所述第一阵列测试控制信号线107a提供控制信号EN_R/B，所述多个第二阵列测试开关AT_SW2的栅极与第二阵列测试控制信号线107b相连接，第二阵列测试控制信号线107b提供控制信号EN_G，所述多个第三阵列测试开关AT_SW3的栅极与第三阵列测试控制信号线107c相连接,所述第三阵列测试控制信号线107c提供控制信号EN_B/R，所述多个第四阵列测试开关AT_SW4的栅极与第四阵列测试控制信号线107d相连接, 所述第四阵列测试控制信号线107d提供控制信号EN_G。
如图1所示，所述多个单元测试开关105包括：多个第一单元测试开关CT_SW1、多个第二单元测试开关CT_SW2、多个第三单元测试开关CT_SW3、多个第四单元测试开关CT_SW4，所述单元测试单元还包括第一单元测试信号线108a以及第二单元测试信号线108b、第三单元测试信号线108c，所述多个第一单元测试开关CT_SW1的漏极与第一单元测试信号线108a相连接，所述第一单元测试信号线108a提供单元测试信号CT_Data_R/B，所述多个第二单元测试开关CT_SW2的漏极与第二单元测试信号线108b相连接,所述第二单元测试信号线108b提供单元测试信号CT_Data_G，所述多个第三单元测试开关CT_SW3的漏极与第三单元测试信号线108c相连接，所述第三单元测试信号线108c提供单元测试信号CT_Data_B/R，所述多个第四单元测试开关CT_SW4的漏极与所述第二单元测试信号线108b相连接。
优选的，所述单元测试单元103在执行阵列测试时保持截止状态。如图1所示，在执行阵列测试时，为了避免阵列测试焊盘106与多条数据线相互连接出现短路的情况，提供单元测试信号的多条单元测试信号线108关闭，与所述单元测试控制信号线109相连的多个第一单元测试开关CT_SW1、多个第二单元测试开关CT_SW2、多个第三单元测试开关CT_SW3以及多个第四单元测试开关CT_SW4同样关闭，此时阵列测试单元102的电路保持正常工作。
优选的，所述阵列测试单元102在执行单元测试时保持导通状态。如图1所示，在执行单元测试时，为了使单元测试信号从阵列测试单元通过，多个第一阵列测试开关AT_SW1、多个第二阵列测试开关AT_SW2、多个第三阵列测试开关AT_SW3以及多个第四阵列测试开关AT_SW4均打卡，阵列测试焊盘106不提供信号，单元测试单元103的电路保持正常工作。
在本实施例中，如图1所示，所述像素单元101包括发射各自不同颜色的多个第一像素、多个第二像素以及多个第三像素，第一像素和第二像素交替布置在同一列中，第三像素对齐地设置在与其中布置有第一像素和第二像素的相邻列中。
优选的，如图1所示，第一像素是发射红光的红色像素R，第二像素是发射蓝光的蓝色像素B，第三像素是发射绿光的绿色像素G。红色像素R和蓝色像素B交替布置在同一列中，绿色像素G对齐设置在与其中布置有红色像素R和蓝色像素B的相邻列D2列和D4列中。
若像素排列顺序为优选实施例中的排列顺序，最小像素重复单元为横向两行、垂直于横向方向的四列像素。其中，第一行的发光像素单元为RGBG,第二行发光单元为BGRG。如图2所示，若需要保证第一行的R像素和第二行的B像素均能点亮，需要供给如图2所示的交流信号。位于第一行的R像素点亮，此时阵列基板行驱动（Gate Driver On Array,GOA）电路信号为低电平；位于第二行的B像素点亮，此时GOA电路信号也为低电平信号。
实施例三：
本揭示实施例提供了一种下窄边框显示面板，下面结合图1至图2进行详细说明。
本揭示实施例提供一种下窄边框显示面板，所述下窄边框显示面板包括，如图1所示，像素单元101，阵列测试(array test)单元102以及单元测试(cell test)单元103，所述阵列测试单元设置于所述像素单元101和所述单元测试单元103之间。
所述阵列测试单元102用于检测像素单元101中的各像素中形成的薄膜晶体管（Thin Film Transistor，TFT）和电容器是否有缺陷。在执行阵列测试时，阵列测试单元102接收阵列测试信号和阵列测试控制信号，并且对应于阵列测试控制信号，向像素单元101选择性供应阵列测试信号。所述单元测试单元103用于检测显示面板的发光特性，在执行单元测试时，单元测试单元103接受单元测试信号和单元测试控制信号，并且对应于单元测试控制信号，向像素单元101选择性供应单元测试信号。
所述阵列测试单元102包括多个阵列测试开关104和多个阵列测试焊盘106（array test pad）以及多条阵列测试控制信号线107，所述单元测试单元包括多个单元测试开关105、多条单元测试信号线108以及单元测试控制信号线109，所述单元测试控制信号线109用于提供所述多个单元测试开关105打开或关闭的单元测试控制信号EN_CT,所述多个单元测试开关105的栅极均连接至所述单元测试控制信号线109。所述多个阵列测试开关104的一端连接至所述像素单元101的多条数据线，所述多个阵列测试开关104的另一端连接至所述多个阵列测试焊盘106，所述多个单元测试开关105连接至所述多个阵列测试开关104的另一端。
在本实施例中，所述像素单元101包括发射各自不同颜色的多个第一像素、多个第二像素以及多个第三像素，第一像素和第二像素交替布置在同一列中，第三像素对齐地设置在与其中布置有第一像素和第二像素的相邻列中。
优选的，所述多个阵列测试开关104设置于所述像素单元101和所述阵列测试焊盘106之间。
本揭示实施例将阵列测试单元102的多个阵列测试开关104的一端连接至像素单元101的多条数据线，单元测试单元103的多个单元测试开关105连接至多个阵列测试开关104的另一端，使得阵列测试电路与单元测试电路合并，在保证测量效果的同时，减小了阵列测试电路和单元测试电路原本所占据的空间，从而缩窄显示面板的下边框宽度。
综上所述，虽然本揭示以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种下窄边框显示面板，包括:
    像素单元；
    阵列测试单元，所述阵列测试单元包括多个阵列测试开关和多个阵列测试焊盘；以及
    单元测试单元，所述单元测试单元包括多个单元测试开关；
    其中，所述阵列测试单元设置于所述像素单元与所述单元测试单元之间，所述多个阵列测试开关的一端连接至所述像素单元的多条数据线，所述多个单元测试开关连接至所述多个阵列测试开关的另一端。
  2. 如权利要求1所述的下窄边框显示面板，其中，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间。
  3. 如权利要求1所述的下窄边框显示面板，其中，所述多个阵列测试开关包括多个第一阵列测试开关、多个第二阵列测试开关、多个第三阵列测试开关以及多个第四阵列测试开关，所述阵列测试单元包括第一阵列测试控制信号线、第二阵列测试控制信号线、第三阵列测试控制信号线以及第四阵列测试控制信号线，所述多个第一阵列测试开关的栅极与所述第一阵列测试控制信号线相连接，所述多个第二阵列测试开关的栅极与所述第二阵列测试控制信号线相连接，所述多个第三阵列测试开关的栅极与所述第三阵列测试控制信号线相连接，所述多个第四阵列测试开关的栅极与所述第四阵列测试控制信号线相连接。
  4. 如权利要求3所述的下窄边框显示面板，其中，所述多个单元测试开关包括多个第一单元测试开关、多个第二单元测试开关、多个第三单元测试开关以及多个第四单元测试开关，所述单元测试单元包括第一单元测试信号线、第二单元测试信号线以及第三单元测试信号线，所述多个第一单元测试开关的漏极与所述第一单元测试信号线相连接，所述多个第二单元测试开关的漏极与所述第二单元测试信号线相连接，所述多个第三单元测试开关的漏极与所述第三单元测试信号线相连接，所述多个第四单元测试开关的漏极与所述第二单元测试信号线相连接。
  5. 如权利要求1所述的下窄边框显示面板，其中，所述单元测试单元包括单元测试控制信号线，用于提供所述多个单元测试开关打开和关闭的信号。
  6. 如权利要求5所述的下窄边框显示面板，其中，所述多个单元测试开关的栅极均连接至所述单元测试控制信号线。
  7. 如权利要求1所述的下窄边框显示面板，其中，所述单元测试单元在执行阵列测试时保持截止状态。
  8. 如权利要求7所述的下窄边框显示面板，其中，所述阵列测试单元在执行单元测试时保持导通状态。
  9. 如权利要求1所述的下窄边框显示面板，其中，所述像素单元包括多个第一像素、多个第二像素和多个第三像素。
  10. 如权利要求9所述的下窄边框显示面板，其中，所述第一像素和所述第二像素交替设置在同一列中，所述第三像素设置在具有所述第一像素和所述第二像素的所述列的相邻列中。
  11. 一种下窄边框显示面板，包括:
    像素单元；
    阵列测试单元，所述阵列测试单元包括多个阵列测试开关和多个阵列测试焊盘；以及
    单元测试单元，所述单元测试单元包括多个单元测试开关以及单元测试控制信号线，所述单元测试控制信号线与所述单元测试开关相连接；
    其中，所述阵列测试单元设置于所述像素单元与所述单元测试单元之间，所述多个阵列测试开关的一端连接至所述像素单元的多条数据线，所述多个单元测试开关连接至所述多个阵列测试开关的另一端。
  12. 如权利要求11所述的下窄边框显示面板，其中，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间。
  13. 如权利要求11所述的下窄边框显示面板，其中，所述多个阵列测试开关包括多个第一阵列测试开关、多个第二阵列测试开关、多个第三阵列测试开关以及多个第四阵列测试开关，所述阵列测试单元包括第一阵列测试控制信号线、第二阵列测试控制信号线、第三阵列测试控制信号线以及第四阵列测试控制信号线，所述多个第一阵列测试开关的栅极与所述第一阵列测试控制信号线相连接，所述多个第二阵列测试开关的栅极与所述第二阵列测试控制信号线相连接，所述多个第三阵列测试开关的栅极与所述第三阵列测试控制信号线相连接，所述多个第四阵列测试开关的栅极与所述第四阵列测试控制信号线相连接。
  14. 如权利要求13所述的下窄边框显示面板，其中，所述多个单元测试开关包括多个第一单元测试开关、多个第二单元测试开关、多个第三单元测试开关以及多个第四单元测试开关，所述单元测试单元包括第一单元测试信号线、第二单元测试信号线以及第三单元测试信号线，所述多个第一单元测试开关的漏极与所述第一单元测试信号线相连接，所述多个第二单元测试开关的漏极与所述第二单元测试信号线相连接，所述多个第三单元测试开关的漏极与所述第三单元测试信号线相连接，所述多个第四单元测试开关的漏极与所述第二单元测试信号线相连接。
  15. 如权利要求11所述的下窄边框显示面板，其中，所述单元测试单元在执行阵列测试时保持截止状态。
  16. 如权利要求15所述的下窄边框显示面板，其中，所述阵列测试单元在执行单元测试时保持导通状态。
  17. 如权利要求11所述的下窄边框显示面板，其中，所述像素单元包括多个第一像素、多个第二像素和多个第三像素。
  18. 如权利要求17所述的下窄边框显示面板，其中，所述第一像素和所述第二像素交替设置在同一列中，所述第三像素设置在具有所述第一像素和所述第二像素的所述列的相邻列中。
  19. 一种下窄边框显示面板，包括:
    像素单元，所述像素单元包括多个第一像素、多个第二像素以及多个第三像素，所述第一像素和所述第二像素交替设置在同一列中，所述第三像素设置在具有所述第一像素和所述第二像素的所述列的相邻列中；
    阵列测试单元，所述阵列测试单元包括多个阵列测试开关和多个阵列测试焊盘；以及
    单元测试单元，所述单元测试单元包括多个单元测试开关以及单元测试控制信号线，所述单元测试控制信号线与所述单元测试开关相连接；
    其中，所述阵列测试单元设置于所述像素单元与所述单元测试单元之间，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间，并且所述多个阵列测试开关的一端连接至所述像素单元的多条数据线，所述多个单元测试开关连接至所述多个阵列测试开关的另一端。
  20. 如权利要求19所述的下窄边框显示面板，其中，所述多个阵列测试开关设置于所述像素单元和所述多个阵列测试焊盘之间。
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