WO2021056771A1 - 一种阵列基板、显示面板 - Google Patents

一种阵列基板、显示面板 Download PDF

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Publication number
WO2021056771A1
WO2021056771A1 PCT/CN2019/119476 CN2019119476W WO2021056771A1 WO 2021056771 A1 WO2021056771 A1 WO 2021056771A1 CN 2019119476 W CN2019119476 W CN 2019119476W WO 2021056771 A1 WO2021056771 A1 WO 2021056771A1
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WIPO (PCT)
Prior art keywords
test
array
pads
pad
area
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PCT/CN2019/119476
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English (en)
French (fr)
Inventor
付宝琴
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/631,457 priority Critical patent/US11222828B1/en
Publication of WO2021056771A1 publication Critical patent/WO2021056771A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N2021/9513—Liquid crystal panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the control of the display pixels on the OLED panel needs to be completed by thin film transistors (TFT).
  • TFT thin film transistors
  • the electrical characteristics of the thin film transistors are easily changed due to the manufacturing process of the production line or environmental changes, which affects the display effect of the OLED panel.
  • Monitoring the actual electrical signal of the circuit on the OLED panel is of great significance for improving the display effect and yield of the OLED panel.
  • Box testing of existing OLED panels (cell test)
  • the electrical signals in the circuit area are vulnerable to array testing during production line testing. test)
  • the influence of the circuit the actual display effect of the OLED panel will change after the electrical signal changes.
  • the existing OLED panel is tested on a half-board lighting machine, it is necessary to make probe fixtures with different pitches to perform corresponding tests, and there is a risk that the test cannot be lit.
  • the present application provides an array substrate and a display panel, which can avoid being affected by the array test loop during the box-forming test, thereby improving the success rate of the box-forming (lighting) test.
  • the application provides an array substrate, including:
  • a base substrate includes a fan-out area corresponding to one side of the display area, and a first signal line extending from the display area is arranged in the fan-out area, and the first signal line extends To the array test area on one side of the fan-out area;
  • the array test area is arranged side by side with spaced array test pads, both sides of the array test area are respectively provided with boxed test areas, and the boxed test area is arranged side by side with boxed test pads and at least A dummy pad;
  • the array test area is further provided with test switches corresponding to the array test pads one-to-one, each of the test switches is connected in series with each other, and the control terminal of each of the test switches is connected to at least one of the dummy pads, The array test pad is connected to the first signal line through the test switch;
  • the dummy pad when the array test is performed, the dummy pad is connected to a high-level signal, and the test switch is turned on to conduct the array test pad and the first signal line.
  • the test switch is turned on. The dummy pad is connected to a low-level signal, and the test switch is closed to disconnect the array test pad and the first signal line.
  • GOA circuit areas are provided on both sides of the base substrate corresponding to the display area, and the second signal line in the GOA circuit area is connected to the boxed test pad.
  • the dummy pads and the boxed test pads are distributed at equal intervals, and the dummy pads are located between the boxed test pads and the array test pads.
  • the array test pads of the array test area and the boxed test pads and the dummy pads of the boxed test area are distributed at equal intervals.
  • the array test area further includes a first lead
  • the boxed test area further includes a second lead
  • one end of the first lead is connected to the array test pad, and the other end passes through
  • the test switch is connected to the first signal line
  • one end of part of the second lead is connected to the boxed test pad, and the other end is connected to the second signal line.
  • the test switch is a thin film transistor
  • the gate of the thin film transistor is connected to the dummy pad through the remaining second lead, and the source of the thin film transistor is connected through the first
  • the lead is connected to the array test pad, and the drain of the thin film transistor is connected to the first signal line.
  • test probes are set corresponding to the array test pad and the dummy pad, and the test probe corresponding to the dummy pad is the dummy pad input
  • the test switch is turned on, and the test probe corresponding to the array test pad is used to input the array test signal to the first signal line.
  • the test probes are set corresponding to the boxed test pads and the dummy pads, and the test probes corresponding to the dummy pads are the dummy pads.
  • the pad receives the low-level signal, the test switch is turned off, and the test probe corresponding to the boxed test pad is used to input the boxed test signal to the second signal line.
  • the present application also provides a display panel, including the above-mentioned array substrate.
  • an array substrate including:
  • a base substrate includes a fan-out area corresponding to one side of the display area, and a first signal line extending from the display area is arranged in the fan-out area, and the first signal line extends To the array test area on one side of the fan-out area;
  • the array test area is arranged side by side with spaced array test pads, both sides of the array test area are respectively provided with boxed test areas, and the boxed test area is arranged side by side with boxed test pads and at least A dummy pad;
  • the array test area is further provided with test switches corresponding to the array test pads one-to-one, each of the test switches is connected in series with each other, and the control terminal of each of the test switches is connected to at least one of the dummy pads, The array test pad is connected to the first signal line through the test switch;
  • the dummy pad when the array test is performed, the dummy pad is connected to a high-level signal, and the test switch is turned on to conduct the array test pad and the first signal line.
  • the test switch is turned on. The dummy pad is connected to a low-level signal, and the test switch is closed to disconnect the array test pad and the first signal line.
  • GOA circuit areas are provided on both sides of the base substrate corresponding to the display area, and the second signal line in the GOA circuit area is connected to the boxed test pad.
  • the dummy pads and the boxed test pads are distributed at equal intervals, and the dummy pads are located between the boxed test pads and the array test pads.
  • the array test pads of the array test area and the boxed test pads and the dummy pads of the boxed test area are distributed at equal intervals.
  • the array test area further includes a first lead
  • the boxed test area further includes a second lead
  • one end of the first lead is connected to the array test pad, and the other end passes through
  • the test switch is connected to the first signal line
  • one end of part of the second lead is connected to the boxed test pad, and the other end is connected to the second signal line.
  • the test switch is a thin film transistor
  • the gate of the thin film transistor is connected to the dummy pad through the remaining second lead, and the source of the thin film transistor is connected through the first
  • the lead is connected to the array test pad, and the drain of the thin film transistor is connected to the first signal line.
  • test probes are set corresponding to the array test pad and the dummy pad, and the test probe corresponding to the dummy pad is the dummy pad input
  • the test switch is turned on, and the test probe corresponding to the array test pad is used to input the array test signal to the first signal line.
  • the test probes are set corresponding to the boxed test pads and the dummy pads, and the test probes corresponding to the dummy pads are the dummy pads.
  • the pad receives the low-level signal, the test switch is turned off, and the test probe corresponding to the boxed test pad is used to input the boxed test signal to the second signal line.
  • the beneficial effect of the present application is that compared with the existing display panel, the array substrate and the display panel provided by the present application add dummy pads to the substrate, so that the control terminals of each test switch corresponding to the array test pads are connected to the dummy pads.
  • Pad connection the array test pad is connected to the first signal line of the fan-out area through the test switch, and the test switch is turned on or off by controlling the high/low level of the dummy pad to ensure that the box is completed The test is not affected by the array test loop, thereby increasing the success rate of the box test.
  • probe fixtures with the same pitch can be used in the array test and the box test, which reduces the cost of the test.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the application.
  • Fig. 2 is an enlarged schematic diagram of area A in Fig. 1.
  • the present application is directed to the existing display panel.
  • the electrical signals in the boxed test area are easily affected by the array test loop, which affects the actual display effect, as well as the technical problem that the test cannot be lit due to the use of probe fixtures with different pitches. This embodiment can solve this defect.
  • the array substrate includes a base substrate 1 which includes GOA circuit areas 2 corresponding to both sides of the display area 3 and a fan-out area 4 located on the other side of the display area 3.
  • a first signal line extending from the display area 3 is arranged in the fan-out area 4, and the first signal line extends to the array test area 5 on the side of the fan-out area 4;
  • a signal line is used to provide a driving signal in the vertical direction for the array substrate.
  • a plurality of second signal lines are provided in the GOA circuit area 2, and the second signal lines provide horizontal driving signals for the array substrate.
  • a boxed test area 6 is provided on both sides of the array test area 5, and boxed test pads and at least one dummy pad are arranged side by side in the boxed test area 6; the array test area 5 is arranged side by side There are spaced array test pads.
  • FIG. 2 is an enlarged schematic diagram of area A in FIG. 1.
  • the boxed test pads 60 and the dummy pads 61 are arranged side by side in the boxed test area 6, and the arrayed test pads 50 are arranged side by side in the array test area 5 at intervals.
  • the first signal line 40 is arranged in the fan-out area 4, wherein the first signal line 40 may be a data signal line.
  • the array test area 5 is also provided with a test switch 51 corresponding to the array test pad 50 one-to-one, and the test switch 51 is used to turn on or off the array test pad 50 and the first signal. Line 40.
  • each test switch 51 is connected to at least one dummy pad 61, and the array test pad 50 is connected to the first signal line 40 through the test switch 51.
  • the second signal line 20 in the GOA circuit area 2 is connected to the boxed test pad 60.
  • the array test pads 50 of the array test area 5 and the boxed test pads 60 and the dummy pads 61 of the boxed test area 6 are distributed at equal intervals.
  • the space between the boxed test pads 60 and the dummy pads 61 of the boxed test area 6 and the array test pads 50 of the array test area 5 is different. equal.
  • the dummy pad 61 is located between the boxed test pad 60 and the array test pad 50.
  • the specific number of the dummy pads 61 can be set according to the actual manufacturing process, and it can be one or multiple, which is not limited here.
  • the number of the dummy pads 61 in the boxed test area 6 on both sides of the array test area 5 may be equal or different.
  • the array test area 5 further includes a first lead 52
  • the boxed test area 6 further includes a second lead 62.
  • One end of the first lead 52 is connected to the array test pad 50, and the other end passes through
  • the test switch 51 is connected to the first signal line 40
  • one end of a part of the second lead 62 is connected to the boxed test pad 60
  • the other end is connected to the second signal line 20.
  • the test switch 51 is a thin film transistor
  • the gate of the thin film transistor is connected to the dummy pad 61 through the remaining second lead 62
  • the source of the thin film transistor is connected to the dummy pad 61 through the second lead 62.
  • a lead 52 is connected to the array test pad 50, and the drain of the thin film transistor is connected to the first signal line 40.
  • each of the test switches 51 is connected in series with each other through a wire 53 and is connected to the dummy pad 61.
  • each of the test switches 51 is connected to a dummy pad 61, but it is not limited to this, a part of the test switches 51 may be connected to a dummy pad 61, and the remaining part of the test switches 51 is connected to the other dummy pad 61.
  • each of the test switches 51 may also be respectively connected to the dummy pads 61 in the boxed test area 6 on both sides of the array test area 5.
  • the dummy pad 61 for connecting the test switch 51 is located on the side of the boxed test area 6 close to the array test area 5, but it is not limited to this.
  • the dummy pad 61 when the array test is performed, the dummy pad 61 is connected to a high-level signal, and the test switch 51 is turned on to conduct the array test pad 50 and the first signal line 40. During testing, the dummy pad 61 is connected to a low-level signal, and the test switch 51 is closed to disconnect the array test pad 50 and the first signal line 40.
  • test probes are set corresponding to the array test pad 50 and the dummy pad 61, and the test probe corresponding to the dummy pad 61 is input to the dummy pad 61.
  • the test switch 51 is turned on, and the test probe corresponding to the array test pad 50 is used to input an array test signal to the first signal line 40 to perform an array test.
  • test probes are set corresponding to the boxed test pad 60 and the dummy pad 61, and the test probe corresponding to the dummy pad 61 is input by the dummy pad 61
  • the test switch 51 is closed, and the test probe corresponding to the boxed test pad 60 is used to input a boxed test signal to the second signal line 20 to perform a boxed test.
  • the array test pads 50, the boxed test pads 60, and the dummy pads 61 may be arranged in multiple rows.
  • probe fixtures with the same spacing can be used in the array test and the boxed test. , Which reduces the cost of testing and avoids the risk of not being able to light up the test.
  • the present application also provides a display panel, including the above-mentioned array substrate, and the display panel is an OLED display panel or a liquid crystal display panel, which is not limited here.
  • the array substrate and display panel provided by the present application add dummy pads to the substrate, and connect the control terminals of each test switch corresponding to the array test pads to the dummy pads, so that the array test pads pass the test.
  • the switch is connected to the first signal line of the fan-out area, and the test switch is fully turned on or off by controlling the high/low level input to the dummy pad, so as to ensure that it is not affected by the array test loop during the box test, and then Improve the success rate of box testing.
  • probe fixtures with the same pitch can be used in the array test and the box test, which reduces the cost of the test.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种阵列基板、显示面板，阵列基板包括扇出区（4）、设有阵列测试焊盘（50）和测试开关（51）的阵列测试区（5）、设有成盒测试焊盘（60）和虚设焊盘（61）的成盒测试区（6），测试开关（51）的控制端连接至虚设焊盘（61），阵列测试焊盘（50）通过测试开关（51）与扇出区（4）的第一信号线（40）连接，根据虚设焊盘（61）接入信号的电平高低用以控制测试开关（51），实现阵列测试与成盒测试的切换。

Description

一种阵列基板、显示面板
本申请要求于2019年9月29日提交中国专利局、申请号为201910932611.2、发明名称为“一种阵列基板、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板。
 背景技术
OLED面板上显示像素的控制需要通过薄膜晶体管（Thin Film Transistor，即TFT）来完成，薄膜晶体管的电学特性容易因生产线的制程或环境变化而发生改变，从而影响OLED面板的显示效果。监控OLED面板上电路的实际电信号对于提升OLED面板的显示效果及良率具有重要意义。现有OLED面板的成盒测试（cell test）电路区的电信号在产线测试过程中，容易受到阵列测试(Array  test）回路的影响，电信号发生改变后OLED面板的实际显示效果会发生变化。另外，现有OLED面板在半板点灯机进行测试时，需要制作不同间距的探针治具，进行对应测试，存在无法点亮测试的风险。
因此，现有技术存在缺陷，急需改进。
 技术问题
本申请提供一种阵列基板、显示面板，能够避免在成盒测试时受到阵列测试回路的影响，从而提高成盒（点灯）测试的成功率。
 技术解决方案
为实现上述目的，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括：
衬底基板，所述衬底基板包括对应显示区一侧的扇出区，所述扇出区内排布有由所述显示区延伸出的第一信号线，且所述第一信号线延伸至所述扇出区一侧的阵列测试区；
所述阵列测试区内并排设置有间隔分布的阵列测试焊盘，所述阵列测试区的两侧分别设置有成盒测试区，所述成盒测试区内并排设置有成盒测试焊盘和至少一虚设焊盘；
所述阵列测试区还设有与所述阵列测试焊盘一一对应的测试开关，各所述测试开关相互串联连接，且各所述测试开关的控制端至少连接至一所述虚设焊盘，所述阵列测试焊盘通过所述测试开关与所述第一信号线连接；
其中，当进行阵列测试时，所述虚设焊盘接入高电平信号，所述测试开关开启以导通所述阵列测试焊盘与所述第一信号线，当进行成盒测试时，所述虚设焊盘接入低电平信号，所述测试开关关闭以断开所述阵列测试焊盘与所述第一信号线。
在本申请的阵列基板中，在所述衬底基板上对应所述显示区的两侧设置有GOA电路区，所述GOA电路区中的第二信号线与所述成盒测试焊盘连接。
在本申请的阵列基板中，所述虚设焊盘与所述成盒测试焊盘等间距分布，且所述虚设焊盘位于所述成盒测试焊盘与所述阵列测试焊盘之间。
在本申请的阵列基板中，所述阵列测试区的所述阵列测试焊盘与所述成盒测试区的所述成盒测试焊盘以及所述虚设焊盘均为等间距分布。
在本申请的阵列基板中，所述阵列测试区还包括第一引线，所述成盒测试区还包括第二引线，所述第一引线的一端与所述阵列测试焊盘连接，另一端通过所述测试开关与所述第一信号线连接，部分所述第二引线的一端与所述成盒测试焊盘连接，另一端与所述第二信号线连接。
在本申请的阵列基板中，所述测试开关为薄膜晶体管，所述薄膜晶体管的栅极通过剩余所述第二引线与所述虚设焊盘连接，所述薄膜晶体管的源极通过所述第一引线和所述阵列测试焊盘连接，所述薄膜晶体管的漏极与所述第一信号线连接。
在本申请的阵列基板中，当阵列测试时，测试探针对应所述阵列测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述高电平信号，所述测试开关开启，对应所述阵列测试焊盘的所述测试探针用于将阵列测试信号输入至所述第一信号线。
在本申请的阵列基板中，当成盒测试时，所述测试探针对应所述成盒测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述低电平信号，所述测试开关关闭，对应所述成盒测试焊盘的所述测试探针用于将成盒测试信号输入至所述第二信号线。
本申请还提供一种显示面板，包括如上所述的阵列基板。
为实现上述目的，本申请还提供一种阵列基板，包括：
衬底基板，所述衬底基板包括对应显示区一侧的扇出区，所述扇出区内排布有由所述显示区延伸出的第一信号线，且所述第一信号线延伸至所述扇出区一侧的阵列测试区；
所述阵列测试区内并排设置有间隔分布的阵列测试焊盘，所述阵列测试区的两侧分别设置有成盒测试区，所述成盒测试区内并排设置有成盒测试焊盘和至少一虚设焊盘；
所述阵列测试区还设有与所述阵列测试焊盘一一对应的测试开关，各所述测试开关相互串联连接，且各所述测试开关的控制端至少连接至一所述虚设焊盘，所述阵列测试焊盘通过所述测试开关与所述第一信号线连接；
其中，当进行阵列测试时，所述虚设焊盘接入高电平信号，所述测试开关开启以导通所述阵列测试焊盘与所述第一信号线，当进行成盒测试时，所述虚设焊盘接入低电平信号，所述测试开关关闭以断开所述阵列测试焊盘与所述第一信号线。
在本申请的阵列基板中，在所述衬底基板上对应所述显示区的两侧设置有GOA电路区，所述GOA电路区中的第二信号线与所述成盒测试焊盘连接。
在本申请的阵列基板中，所述虚设焊盘与所述成盒测试焊盘等间距分布，且所述虚设焊盘位于所述成盒测试焊盘与所述阵列测试焊盘之间。
在本申请的阵列基板中，所述阵列测试区的所述阵列测试焊盘与所述成盒测试区的所述成盒测试焊盘以及所述虚设焊盘均为等间距分布。
在本申请的阵列基板中，所述阵列测试区还包括第一引线，所述成盒测试区还包括第二引线，所述第一引线的一端与所述阵列测试焊盘连接，另一端通过所述测试开关与所述第一信号线连接，部分所述第二引线的一端与所述成盒测试焊盘连接，另一端与所述第二信号线连接。
在本申请的阵列基板中，所述测试开关为薄膜晶体管，所述薄膜晶体管的栅极通过剩余所述第二引线与所述虚设焊盘连接，所述薄膜晶体管的源极通过所述第一引线和所述阵列测试焊盘连接，所述薄膜晶体管的漏极与所述第一信号线连接。
在本申请的阵列基板中，当阵列测试时，测试探针对应所述阵列测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述高电平信号，所述测试开关开启，对应所述阵列测试焊盘的所述测试探针用于将阵列测试信号输入至所述第一信号线。
在本申请的阵列基板中，当成盒测试时，所述测试探针对应所述成盒测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述低电平信号，所述测试开关关闭，对应所述成盒测试焊盘的所述测试探针用于将成盒测试信号输入至所述第二信号线。
 有益效果
本申请的有益效果为：相较于现有的显示面板，本申请提供的阵列基板、显示面板，通过对基板增设虚设焊盘，将对应阵列测试焊盘的各测试开关的控制端均与虚设焊盘连接，使阵列测试焊盘通过测试开关与扇出区的第一信号线连接，通过控制给入虚设焊盘的高/低电平以全部开启或关闭测试开关，从而能够保证在成盒测试时不受阵列测试回路的影响，进而提高成盒测试的成功率。另外，本申请在阵列测试和成盒测试中可以使用相同间距的探针治具，降低了测试的成本。
 附图说明
图1为本申请实施例提供的阵列基板的结构示意图；
图2为图1中A区域的放大示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有的显示面板，存在成盒测试区的电信号容易受到阵列测试回路的影响，从而影响实际显示效果，以及由于使用不同间距的探针治具导致无法点亮测试的技术问题，本实施例能够解决该缺陷。
如图1所示，为本申请实施例提供的阵列基板的结构示意图。所述阵列基板包括：衬底基板1，所述衬底基板1包括对应显示区3两侧的GOA电路区2，以及位于所述显示区3另外一侧的扇出区4。所述扇出区4内排布有由所述显示区3延伸出的第一信号线，且所述第一信号线延伸至所述扇出区4一侧的阵列测试区5；所述第一信号线用于为所述阵列基板提供竖直方向上的驱动信号。所述GOA电路区2内设置有多条第二信号线，所述第二信号线为所述阵列基板提供水平方向的驱动信号。所述阵列测试区5的两侧分别设置有成盒测试区6，所述成盒测试区6内并排设置有成盒测试焊盘和至少一虚设焊盘；所述阵列测试区5内并排设置有间隔分布的阵列测试焊盘。
具体请参照图2，图2为图1中A区域的放大示意图。所述成盒测试区6内并排设置有所述成盒测试焊盘60和所述虚设焊盘61，所述阵列测试区5内并排设置有间隔分布的所述阵列测试焊盘50。所述扇出区4内排布有所述第一信号线40，其中，所述第一信号线40可以为数据信号线。所述阵列测试区5还设有与所述阵列测试焊盘50一一对应的测试开关51，所述测试开关51用于导通或关断所述阵列测试焊盘50与所述第一信号线40。各所述测试开关51的控制端至少连接至一所述虚设焊盘61，所述阵列测试焊盘50通过所述测试开关51与所述第一信号线40连接。所述GOA电路区2中的第二信号线20与所述成盒测试焊盘60连接。
在本实施例中，所述阵列测试区5的所述阵列测试焊盘50与所述成盒测试区6的所述成盒测试焊盘60以及所述虚设焊盘61均为等间距分布。
在另一种实施例中，所述成盒测试区6的所述成盒测试焊盘60以及所述虚设焊盘61与所述阵列测试区5的所述阵列测试焊盘50分布的间距不相等。
其中，所述虚设焊盘61位于所述成盒测试焊盘60与所述阵列测试焊盘50之间。所述虚设焊盘61的具体数目可根据实际制程而设定，可以为一个，也可以为多个，此处不做限制。所述阵列测试区5两侧的所述成盒测试区6内的所述虚设焊盘61的数目可以相等，也可以不等。
所述阵列测试区5内还包括第一引线52，所述成盒测试区6内还包括第二引线62，所述第一引线52的一端与所述阵列测试焊盘50连接，另一端通过所述测试开关51与所述第一信号线40连接，部分所述第二引线62的一端与所述成盒测试焊盘60连接，另一端与所述第二信号线20连接。
在本实施例中，所述测试开关51为薄膜晶体管，所述薄膜晶体管的栅极通过剩余所述第二引线62与所述虚设焊盘61连接，所述薄膜晶体管的源极通过所述第一引线52和所述阵列测试焊盘50连接，所述薄膜晶体管的漏极与所述第一信号线40连接。
其中，各所述测试开关51通过走线53相互串联连接，且连接至所述虚设焊盘61。在图中，各所述测试开关51均连接至一所述虚设焊盘61，但并不限于此，可以一部分所述测试开关51连接至一所述虚设焊盘61，剩余部分所述测试开关51连接至另一所述虚设焊盘61上。另外，各所述测试开关51还可以分别连接至所述阵列测试区5两侧的所述成盒测试区6中的所述虚设焊盘61上。
在图中，用于连接所述测试开关51的所述虚设焊盘61位于所述成盒测试区6靠近所述阵列测试区5的一侧，但并不以此为限。
其中，当进行阵列测试时，所述虚设焊盘61接入高电平信号，所述测试开关51开启以导通所述阵列测试焊盘50与所述第一信号线40，当进行成盒测试时，所述虚设焊盘61接入低电平信号，所述测试开关51关闭以断开所述阵列测试焊盘50与所述第一信号线40。
具体地，当阵列测试时，测试探针对应所述阵列测试焊盘50与所述虚设焊盘61设置，对应所述虚设焊盘61的所述测试探针为所述虚设焊盘61输入所述高电平信号，所述测试开关51开启，对应所述阵列测试焊盘50的所述测试探针用于将阵列测试信号输入至所述第一信号线40，以进行阵列测试。
当成盒测试时，所述测试探针对应所述成盒测试焊盘60与所述虚设焊盘61设置，对应所述虚设焊盘61的所述测试探针为所述虚设焊盘61输入所述低电平信号，所述测试开关51关闭，对应所述成盒测试焊盘60的所述测试探针用于将成盒测试信号输入至所述第二信号线20，以进行成盒测试。
在其他实施例中，所述阵列测试焊盘50、所述成盒测试焊盘60以及所述虚设焊盘61可以呈多排排布。
其中，由于所述阵列测试焊盘50、所述成盒测试焊盘60以及所述虚设焊盘61均为等间距分布，因此在阵列测试和成盒测试中可以使用相同间距的探针治具，降低了测试的成本，避免了无法点亮测试的风险。
本申请还提供一种显示面板，包括如上所述的阵列基板，所述显示面板为OLED显示面板或液晶显示面板，此处不做限制。
综上所述，本申请提供的阵列基板、显示面板，通过对基板增设虚设焊盘，将对应阵列测试焊盘的各测试开关的控制端均与虚设焊盘连接，使阵列测试焊盘通过测试开关与扇出区的第一信号线连接，通过控制给入虚设焊盘的高/低电平以全部开启或关闭测试开关，从而能够保证在成盒测试时不受阵列测试回路的影响，进而提高成盒测试的成功率。另外，本申请在阵列测试和成盒测试中可以使用相同间距的探针治具，降低了测试的成本。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种阵列基板，其包括：
    衬底基板，所述衬底基板包括对应显示区一侧的扇出区，所述扇出区内排布有由所述显示区延伸出的第一信号线，且所述第一信号线延伸至所述扇出区一侧的阵列测试区；
    所述阵列测试区内并排设置有间隔分布的阵列测试焊盘，所述阵列测试区的两侧分别设置有成盒测试区，所述成盒测试区内并排设置有成盒测试焊盘和至少一虚设焊盘；
    所述阵列测试区还设有与所述阵列测试焊盘一一对应的测试开关，各所述测试开关的控制端至少连接至一所述虚设焊盘，所述阵列测试焊盘通过所述测试开关与所述第一信号线连接；
    其中，当进行阵列测试时，所述虚设焊盘接入高电平信号，所述测试开关开启以导通所述阵列测试焊盘与所述第一信号线，当进行成盒测试时，所述虚设焊盘接入低电平信号，所述测试开关关闭以断开所述阵列测试焊盘与所述第一信号线。
  2. 根据权利要求1所述的阵列基板，其中，在所述衬底基板上对应所述显示区的两侧设置有GOA电路区，所述GOA电路区中的第二信号线与所述成盒测试焊盘连接。
  3. 根据权利要求1所述的阵列基板，其中，所述虚设焊盘与所述成盒测试焊盘等间距分布，且所述虚设焊盘位于所述成盒测试焊盘与所述阵列测试焊盘之间。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列测试区的所述阵列测试焊盘与所述成盒测试区的所述成盒测试焊盘以及所述虚设焊盘均为等间距分布。
  5. 根据权利要求2所述的阵列基板，其中，所述阵列测试区还包括第一引线，所述成盒测试区还包括第二引线，所述第一引线的一端与所述阵列测试焊盘连接，另一端通过所述测试开关与所述第一信号线连接，部分所述第二引线的一端与所述成盒测试焊盘连接，另一端与所述第二信号线连接。
  6. 根据权利要求5所述的阵列基板，其中，所述测试开关为薄膜晶体管，所述薄膜晶体管的栅极通过剩余所述第二引线与所述虚设焊盘连接，所述薄膜晶体管的源极通过所述第一引线和所述阵列测试焊盘连接，所述薄膜晶体管的漏极与所述第一信号线连接。
  7. 根据权利要求2所述的阵列基板，其中，当阵列测试时，测试探针对应所述阵列测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述高电平信号，所述测试开关开启，对应所述阵列测试焊盘的所述测试探针用于将阵列测试信号输入至所述第一信号线。
  8. 根据权利要求7所述的阵列基板，其中，当成盒测试时，所述测试探针对应所述成盒测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述低电平信号，所述测试开关关闭，对应所述成盒测试焊盘的所述测试探针用于将成盒测试信号输入至所述第二信号线。
  9. 一种显示面板，其包括如权利要求1所述的阵列基板。
  10. 一种阵列基板，其包括：
    衬底基板，所述衬底基板包括对应显示区一侧的扇出区，所述扇出区内排布有由所述显示区延伸出的第一信号线，且所述第一信号线延伸至所述扇出区一侧的阵列测试区；
    所述阵列测试区内并排设置有间隔分布的阵列测试焊盘，所述阵列测试区的两侧分别设置有成盒测试区，所述成盒测试区内并排设置有成盒测试焊盘和至少一虚设焊盘；
    所述阵列测试区还设有与所述阵列测试焊盘一一对应的测试开关，各所述测试开关相互串联连接，且各所述测试开关的控制端至少连接至一所述虚设焊盘，所述阵列测试焊盘通过所述测试开关与所述第一信号线连接；
    其中，当进行阵列测试时，所述虚设焊盘接入高电平信号，所述测试开关开启以导通所述阵列测试焊盘与所述第一信号线，当进行成盒测试时，所述虚设焊盘接入低电平信号，所述测试开关关闭以断开所述阵列测试焊盘与所述第一信号线。
  11. 根据权利要求10所述的阵列基板，其中，在所述衬底基板上对应所述显示区的两侧设置有GOA电路区，所述GOA电路区中的第二信号线与所述成盒测试焊盘连接。
  12. 根据权利要求10所述的阵列基板，其中，所述虚设焊盘与所述成盒测试焊盘等间距分布，且所述虚设焊盘位于所述成盒测试焊盘与所述阵列测试焊盘之间。
  13. 根据权利要求10所述的阵列基板，其中，所述阵列测试区的所述阵列测试焊盘与所述成盒测试区的所述成盒测试焊盘以及所述虚设焊盘均为等间距分布。
  14. 根据权利要求11所述的阵列基板，其中，所述阵列测试区还包括第一引线，所述成盒测试区还包括第二引线，所述第一引线的一端与所述阵列测试焊盘连接，另一端通过所述测试开关与所述第一信号线连接，部分所述第二引线的一端与所述成盒测试焊盘连接，另一端与所述第二信号线连接。
  15. 根据权利要求14所述的阵列基板，其中，所述测试开关为薄膜晶体管，所述薄膜晶体管的栅极通过剩余所述第二引线与所述虚设焊盘连接，所述薄膜晶体管的源极通过所述第一引线和所述阵列测试焊盘连接，所述薄膜晶体管的漏极与所述第一信号线连接。
  16. 根据权利要求11所述的阵列基板，其中，当阵列测试时，测试探针对应所述阵列测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述高电平信号，所述测试开关开启，对应所述阵列测试焊盘的所述测试探针用于将阵列测试信号输入至所述第一信号线。
  17. 根据权利要求16所述的阵列基板，其中，当成盒测试时，所述测试探针对应所述成盒测试焊盘与所述虚设焊盘设置，对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述低电平信号，所述测试开关关闭，对应所述成盒测试焊盘的所述测试探针用于将成盒测试信号输入至所述第二信号线。
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