CN110676268A - 一种阵列基板、显示面板 - Google Patents
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Abstract
本申请提供一种阵列基板、显示面板,包括扇出区和位于扇出区一侧的阵列测试区和成盒测试区,阵列测试区内间隔的设有阵列测试焊盘和对应阵列测试焊盘设置的测试开关,成盒测试区内间隔的设有成盒测试焊盘和虚设焊盘,各测试开关的控制端均连接至虚设焊盘,阵列测试焊盘通过测试开关与扇出区的第一信号线连接,当进行阵列测试时,虚设焊盘接入高电平信号,测试开关开启以导通阵列测试焊盘与第一信号线,当进行成盒测试时,虚设焊盘接入低电平信号,测试开关关闭以断开阵列测试焊盘与第一信号线。
Description
技术领域
本申请涉及显示技术领域,尤其涉及一种阵列基板、显示面板。
背景技术
OLED面板上显示像素的控制需要通过薄膜晶体管(Thin Film Transistor,即TFT)来完成,薄膜晶体管的电学特性容易因生产线的制程或环境变化而发生改变,从而影响OLED面板的显示效果。监控OLED面板上电路的实际电信号对于提升OLED面板的显示效果及良率具有重要意义。现有OLED面板的成盒测试(cell test)电路区的电信号在产线测试过程中,容易受到阵列测试(Array test)回路的影响,电信号发生改变后OLED面板的实际显示效果会发生变化。另外,现有OLED面板在半板点灯机进行测试时,需要制作不同间距的探针治具,进行对应测试,存在无法点亮测试的风险。
因此,现有技术存在缺陷,急需改进。
发明内容
本申请提供一种阵列基板、显示面板,能够避免在成盒测试时受到阵列测试回路的影响,从而提高成盒(点灯)测试的成功率。
为实现上述目的,本申请提供的技术方案如下:
本申请提供一种阵列基板,包括:
衬底基板,所述衬底基板包括对应显示区一侧的扇出区,所述扇出区内排布有由所述显示区延伸出的第一信号线,且所述第一信号线延伸至所述扇出区一侧的阵列测试区;
所述阵列测试区内并排设置有间隔分布的阵列测试焊盘,所述阵列测试区的两侧分别设置有成盒测试区,所述成盒测试区内并排设置有成盒测试焊盘和至少一虚设焊盘;
所述阵列测试区还设有与所述阵列测试焊盘一一对应的测试开关,各所述测试开关的控制端至少连接至一所述虚设焊盘,所述阵列测试焊盘通过所述测试开关与所述第一信号线连接;
其中,当进行阵列测试时,所述虚设焊盘接入高电平信号,所述测试开关开启以导通所述阵列测试焊盘与所述第一信号线,当进行成盒测试时,所述虚设焊盘接入低电平信号,所述测试开关关闭以断开所述阵列测试焊盘与所述第一信号线。
在本申请的阵列基板中,在所述衬底基板上对应所述显示区的两侧设置有GOA电路区,所述GOA电路区中的第二信号线与所述成盒测试焊盘连接。
在本申请的阵列基板中,所述虚设焊盘与所述成盒测试焊盘等间距分布,且所述虚设焊盘位于所述成盒测试焊盘与所述阵列测试焊盘之间。
在本申请的阵列基板中,所述阵列测试区的所述阵列测试焊盘与所述成盒测试区的所述成盒测试焊盘以及所述虚设焊盘均为等间距分布。
在本申请的阵列基板中,所述阵列测试区还包括第一引线,所述成盒测试区还包括第二引线,所述第一引线的一端与所述阵列测试焊盘连接,另一端通过所述测试开关与所述第一信号线连接,部分所述第二引线的一端与所述成盒测试焊盘连接,另一端与所述第二信号线连接。
在本申请的阵列基板中,所述测试开关为薄膜晶体管,所述薄膜晶体管的栅极通过剩余所述第二引线与所述虚设焊盘连接,所述薄膜晶体管的源极通过所述第一引线和所述阵列测试焊盘连接,所述薄膜晶体管的漏极与所述第一信号线连接。
在本申请的阵列基板中,当阵列测试时,测试探针对应所述阵列测试焊盘与所述虚设焊盘设置,对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述高电平信号,所述测试开关开启,对应所述阵列测试焊盘的所述测试探针用于将阵列测试信号输入至所述第一信号线。
在本申请的阵列基板中,当成盒测试时,所述测试探针对应所述成盒测试焊盘与所述虚设焊盘设置,对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述低电平信号,所述测试开关关闭,对应所述成盒测试焊盘的所述测试探针用于将成盒测试信号输入至所述第二信号线。
在本申请的阵列基板中,各所述测试开关相互串联连接。
本申请还提供一种显示面板,包括如上所述的阵列基板。
本申请的有益效果为:相较于现有的显示面板,本申请提供的阵列基板、显示面板,通过对基板增设虚设焊盘,将对应阵列测试焊盘的各测试开关的控制端均与虚设焊盘连接,使阵列测试焊盘通过测试开关与扇出区的第一信号线连接,通过控制给入虚设焊盘的高/低电平以全部开启或关闭测试开关,从而能够保证在成盒测试时不受阵列测试回路的影响,进而提高成盒测试的成功率。另外,本申请在阵列测试和成盒测试中可以使用相同间距的探针治具,降低了测试的成本。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的结构示意图;
图2为图1中A区域的放大示意图。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本申请,而非用以限制本申请。在图中,结构相似的单元是用以相同标号表示。
本申请针对现有的显示面板,存在成盒测试区的电信号容易受到阵列测试回路的影响,从而影响实际显示效果,以及由于使用不同间距的探针治具导致无法点亮测试的技术问题,本实施例能够解决该缺陷。
如图1所示,为本申请实施例提供的阵列基板的结构示意图。所述阵列基板包括:衬底基板1,所述衬底基板1包括对应显示区3两侧的GOA电路区2,以及位于所述显示区3另外一侧的扇出区4。所述扇出区4内排布有由所述显示区3延伸出的第一信号线,且所述第一信号线延伸至所述扇出区4一侧的阵列测试区5;所述第一信号线用于为所述阵列基板提供竖直方向上的驱动信号。所述GOA电路区2内设置有多条第二信号线,所述第二信号线为所述阵列基板提供水平方向的驱动信号。所述阵列测试区5的两侧分别设置有成盒测试区6,所述成盒测试区6内并排设置有成盒测试焊盘和至少一虚设焊盘;所述阵列测试区5内并排设置有间隔分布的阵列测试焊盘。
具体请参照图2,图2为图1中A区域的放大示意图。所述成盒测试区6内并排设置有所述成盒测试焊盘60和所述虚设焊盘61,所述阵列测试区5内并排设置有间隔分布的所述阵列测试焊盘50。所述扇出区4内排布有所述第一信号线40,其中,所述第一信号线40可以为数据信号线。所述阵列测试区5还设有与所述阵列测试焊盘50一一对应的测试开关51,所述测试开关51用于导通或关断所述阵列测试焊盘50与所述第一信号线40。各所述测试开关51的控制端至少连接至一所述虚设焊盘61,所述阵列测试焊盘50通过所述测试开关51与所述第一信号线40连接。所述GOA电路区2中的第二信号线20与所述成盒测试焊盘60连接。
在本实施例中,所述阵列测试区5的所述阵列测试焊盘50与所述成盒测试区6的所述成盒测试焊盘60以及所述虚设焊盘61均为等间距分布。
在另一种实施例中,所述成盒测试区6的所述成盒测试焊盘60以及所述虚设焊盘61与所述阵列测试区5的所述阵列测试焊盘50分布的间距不相等。
其中,所述虚设焊盘61位于所述成盒测试焊盘60与所述阵列测试焊盘50之间。所述虚设焊盘61的具体数目可根据实际制程而设定,可以为一个,也可以为多个,此处不做限制。所述阵列测试区5两侧的所述成盒测试区6内的所述虚设焊盘61的数目可以相等,也可以不等。
所述阵列测试区5内还包括第一引线52,所述成盒测试区6内还包括第二引线62,所述第一引线52的一端与所述阵列测试焊盘50连接,另一端通过所述测试开关51与所述第一信号线40连接,部分所述第二引线62的一端与所述成盒测试焊盘60连接,另一端与所述第二信号线20连接。
在本实施例中,所述测试开关51为薄膜晶体管,所述薄膜晶体管的栅极通过剩余所述第二引线62与所述虚设焊盘61连接,所述薄膜晶体管的源极通过所述第一引线52和所述阵列测试焊盘50连接,所述薄膜晶体管的漏极与所述第一信号线40连接。
其中,各所述测试开关51通过走线53相互串联连接,且连接至所述虚设焊盘61。在图中,各所述测试开关51均连接至一所述虚设焊盘61,但并不限于此,可以一部分所述测试开关51连接至一所述虚设焊盘61,剩余部分所述测试开关51连接至另一所述虚设焊盘61上。另外,各所述测试开关51还可以分别连接至所述阵列测试区5两侧的所述成盒测试区6中的所述虚设焊盘61上。
在图中,用于连接所述测试开关51的所述虚设焊盘61位于所述成盒测试区6靠近所述阵列测试区5的一侧,但并不以此为限。
其中,当进行阵列测试时,所述虚设焊盘61接入高电平信号,所述测试开关51开启以导通所述阵列测试焊盘50与所述第一信号线40,当进行成盒测试时,所述虚设焊盘61接入低电平信号,所述测试开关51关闭以断开所述阵列测试焊盘50与所述第一信号线40。
具体地,当阵列测试时,测试探针对应所述阵列测试焊盘50与所述虚设焊盘61设置,对应所述虚设焊盘61的所述测试探针为所述虚设焊盘61输入所述高电平信号,所述测试开关51开启,对应所述阵列测试焊盘50的所述测试探针用于将阵列测试信号输入至所述第一信号线40,以进行阵列测试。
当成盒测试时,所述测试探针对应所述成盒测试焊盘60与所述虚设焊盘61设置,对应所述虚设焊盘61的所述测试探针为所述虚设焊盘61输入所述低电平信号,所述测试开关51关闭,对应所述成盒测试焊盘60的所述测试探针用于将成盒测试信号输入至所述第二信号线20,以进行成盒测试。
在其他实施例中,所述阵列测试焊盘50、所述成盒测试焊盘60以及所述虚设焊盘61可以呈多排排布。
其中,由于所述阵列测试焊盘50、所述成盒测试焊盘60以及所述虚设焊盘61均为等间距分布,因此在阵列测试和成盒测试中可以使用相同间距的探针治具,降低了测试的成本,避免了无法点亮测试的风险。
本申请还提供一种显示面板,包括如上所述的阵列基板,所述显示面板为OLED显示面板或液晶显示面板,此处不做限制。
综上所述,本申请提供的阵列基板、显示面板,通过对基板增设虚设焊盘,将对应阵列测试焊盘的各测试开关的控制端均与虚设焊盘连接,使阵列测试焊盘通过测试开关与扇出区的第一信号线连接,通过控制给入虚设焊盘的高/低电平以全部开启或关闭测试开关,从而能够保证在成盒测试时不受阵列测试回路的影响,进而提高成盒测试的成功率。另外,本申请在阵列测试和成盒测试中可以使用相同间距的探针治具,降低了测试的成本。
综上所述,虽然本申请已以优选实施例揭露如上,但上述优选实施例并非用以限制本申请,本领域的普通技术人员,在不脱离本申请的精神和范围内,均可作各种更动与润饰,因此本申请的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种阵列基板,其特征在于,包括:
衬底基板,所述衬底基板包括对应显示区一侧的扇出区,所述扇出区内排布有由所述显示区延伸出的第一信号线,且所述第一信号线延伸至所述扇出区一侧的阵列测试区;
所述阵列测试区内并排设置有间隔分布的阵列测试焊盘,所述阵列测试区的两侧分别设置有成盒测试区,所述成盒测试区内并排设置有成盒测试焊盘和至少一虚设焊盘;
所述阵列测试区还设有与所述阵列测试焊盘一一对应的测试开关,各所述测试开关的控制端至少连接至一所述虚设焊盘,所述阵列测试焊盘通过所述测试开关与所述第一信号线连接;
其中,当进行阵列测试时,所述虚设焊盘接入高电平信号,所述测试开关开启以导通所述阵列测试焊盘与所述第一信号线,当进行成盒测试时,所述虚设焊盘接入低电平信号,所述测试开关关闭以断开所述阵列测试焊盘与所述第一信号线。
2.根据权利要求1所述的阵列基板,其特征在于,在所述衬底基板上对应所述显示区的两侧设置有GOA电路区,所述GOA电路区中的第二信号线与所述成盒测试焊盘连接。
3.根据权利要求1所述的阵列基板,其特征在于,所述虚设焊盘与所述成盒测试焊盘等间距分布,且所述虚设焊盘位于所述成盒测试焊盘与所述阵列测试焊盘之间。
4.根据权利要求1所述的阵列基板,其特征在于,所述阵列测试区的所述阵列测试焊盘与所述成盒测试区的所述成盒测试焊盘以及所述虚设焊盘均为等间距分布。
5.根据权利要求2所述的阵列基板,其特征在于,所述阵列测试区还包括第一引线,所述成盒测试区还包括第二引线,所述第一引线的一端与所述阵列测试焊盘连接,另一端通过所述测试开关与所述第一信号线连接,部分所述第二引线的一端与所述成盒测试焊盘连接,另一端与所述第二信号线连接。
6.根据权利要求5所述的阵列基板,其特征在于,所述测试开关为薄膜晶体管,所述薄膜晶体管的栅极通过剩余所述第二引线与所述虚设焊盘连接,所述薄膜晶体管的源极通过所述第一引线和所述阵列测试焊盘连接,所述薄膜晶体管的漏极与所述第一信号线连接。
7.根据权利要求2所述的阵列基板,其特征在于,当阵列测试时,测试探针对应所述阵列测试焊盘与所述虚设焊盘设置,对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述高电平信号,所述测试开关开启,对应所述阵列测试焊盘的所述测试探针用于将阵列测试信号输入至所述第一信号线。
8.根据权利要求7所述的阵列基板,其特征在于,当成盒测试时,所述测试探针对应所述成盒测试焊盘与所述虚设焊盘设置,对应所述虚设焊盘的所述测试探针为所述虚设焊盘输入所述低电平信号,所述测试开关关闭,对应所述成盒测试焊盘的所述测试探针用于将成盒测试信号输入至所述第二信号线。
9.根据权利要求1所述的阵列基板,其特征在于,各所述测试开关相互串联连接。
10.一种显示面板,其特征在于,包括如权利要求1-9任一项所述的阵列基板。
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