WO2016019663A1 - 基板和显示装置 - Google Patents

基板和显示装置 Download PDF

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Publication number
WO2016019663A1
WO2016019663A1 PCT/CN2014/093011 CN2014093011W WO2016019663A1 WO 2016019663 A1 WO2016019663 A1 WO 2016019663A1 CN 2014093011 W CN2014093011 W CN 2014093011W WO 2016019663 A1 WO2016019663 A1 WO 2016019663A1
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WO
WIPO (PCT)
Prior art keywords
common electrode
line
substrate
common
lines
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PCT/CN2014/093011
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English (en)
French (fr)
Inventor
先建波
乔勇
程鸿飞
李文波
李盼
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/769,690 priority Critical patent/US10386682B2/en
Publication of WO2016019663A1 publication Critical patent/WO2016019663A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • Embodiments of the present invention relate to the field of display, and in particular, to a substrate and a display device.
  • LCD Liquid crystal display
  • the liquid crystal display includes a color filter substrate and an array substrate, and a liquid crystal layer sandwiched therebetween.
  • a common electrode and a pixel electrode are respectively disposed on the color filter substrate and the array substrate.
  • the pixel electrode and the common electrode are applied with a voltage, and a pressure difference between the two causes an electric field, and the electric field changes the orientation of the liquid crystal molecules in the liquid crystal layer, and further The transmittance of light passing through the liquid crystal layer is changed to achieve the purpose of displaying an image.
  • Embodiments of the present invention provide a substrate and a display device capable of reducing resistance on a common electrode line and improving display uniformity.
  • At least one embodiment of the present invention provides a substrate comprising: a plurality of spaced apart common electrode lines, the common electrode lines providing a common voltage to respective pixel units; at least two connecting lines, the connecting lines are located a display area for electrically connecting each other between at least two adjacent two or more common electrode lines.
  • each common electrode line is connected to a common electrode in at least one row/column of pixels.
  • the substrate is divided into a plurality of regions through which common electrode lines located in the same region are electrically connected.
  • the substrate further includes a common lead disposed at an edge of the substrate, and a common electrode line located in the same region is connected to the same common lead.
  • the voltages of the common leads connecting the common electrode lines in different regions are different.
  • connection line includes a first connection line and a second connection line; common electrodes of at least 4 pixel units located in different rows are electrically connected to each other through the first connection line and the second connection line, forming A closed annular common electrode unit.
  • the common electrode units located in the same row/column are electrically connected to each other.
  • the common lead when the common electrode line included in the common electrode unit is an odd number, the common lead is connected to the (N+1)/2th common electrode line; or the common electrode unit includes When the common electrode line is an even number, the common lead is connected to the N/2th and (N/2+1) common electrode lines.
  • the substrate is an array substrate or a counter substrate.
  • the substrate is an array substrate
  • the array substrate further includes: a data line and a gate line, the common electrode line is parallel to the gate line and disposed in the same layer, and the connection line is The data lines are arranged in parallel and in the same layer; or the common electrode lines are arranged in parallel with the data lines and in the same layer; the connection lines are parallel to the gate lines and are disposed in the same layer.
  • the common electrode line and the connection line are connected through a via.
  • At least one embodiment of the present invention provides a display device comprising the substrate of any of the above.
  • 1 is a schematic plan view showing a planar structure of an array substrate
  • FIG. 2 is a schematic plan view of a planar structure of an array substrate according to a first specific example of the present invention
  • FIG. 3 is a second schematic structural view of an array substrate according to a first specific example of the present invention.
  • FIG. 4 is a schematic plan view 3 of a planar structure of an array substrate according to a first specific example of the present invention.
  • FIG. 5 is a schematic plan view showing a planar structure of an array substrate according to a second specific example of the embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing the planar structure of an array substrate according to a third specific example of the embodiment of the present invention.
  • the common electrode in the liquid crystal display is generally an entire film layer (plate structure) covering the display area or has a divided design structure as shown, for example, in FIG.
  • a common electrode 10 is disposed in each pixel unit in FIG. 1, and a common electrode line 11 (for example, Com1 to Com 4) is disposed in each row of pixel units, and common electrodes required for liquid crystal driving are provided to the respective common electrodes 10 in the row of pixels.
  • Voltage With the extension of the length, there is a voltage drop on the common electrode line 11, so that the distribution of the voltage of the common electrode inside the entire panel is uneven, which reduces the uniformity of display.
  • At least one embodiment of the present invention provides an array substrate.
  • the array substrate includes a plurality of spaced-apart common electrode lines 11 that provide a common voltage to corresponding pixel units.
  • the method further includes: at least two connecting lines 12, each of which is located in the display area for mutually electrically connecting between at least two adjacent common electrode lines 11.
  • connection line 12 is generally electrically connected to two or more adjacent common electrode lines 11 in a direction perpendicular to the common electrode line 11.
  • rows in the field of liquid crystal displays generally refer to directions parallel to the gate lines, and columns generally refer to directions parallel to the data lines, and the description herein can be understood in this manner.
  • rows or columns in this embodiment are only describing relative concepts, and may not be distinguished.
  • two (or more) common electrode lines are electrically connected to each other through at least two connecting lines, and adjacent common electrode lines may be connected in parallel or partial line segments of adjacent common electrode lines may be connected in parallel.
  • the two resistors are connected in parallel, the total resistance will decrease, so setting the connection line can reduce the resistance on the common electrode line and improve display uniformity.
  • the connecting line since the connecting line is located in the display area, it can be completed synchronously in the array substrate process, and no additional process is required.
  • the array substrate shown in Fig. 2 is a first specific example consistent with the present embodiment.
  • the array substrate includes: laterally distributed gate lines 13 (for example, G1 to G4), longitudinally distributed data lines 14 (for example, D1 to D3), and gate lines 13 and data lines 14 are arranged in a crisscross region with pixel units, each of which A common electrode 10 and a pixel electrode (above or below the common electrode 10, not shown) are disposed in the pixel unit, and a thin film transistor as a switching element is further disposed at the intersection of the gate line 13 and the data line 14.
  • the source of the thin film transistor is connected to the data line 14
  • the drain is connected to the pixel electrode
  • the gate is connected to the gate line 13.
  • a common electrode line 11 (for example, Com1 to Com4) parallel to the gate line 13 is further disposed on the array substrate, and each of the common electrode lines 11 is connected to the row of common electrodes 10 for supplying a common voltage to the row of common electrodes 10, upper and lower phases.
  • the common electrode lines 11 of each of the two adjacent rows are connected by at least two connecting lines 11.
  • connection lines 11 of every three rows or every four rows or more rows adjacent to each other up and down by at least two connection lines 11.
  • the connecting line 12 may include: a first connecting line 121 and a second connecting line 122; the common electrode 10 of at least 4 pixel units located in different rows passes through the first connecting line 121 and the second connecting line 122 to each other Electrically connected to form a closed annular common electrode unit 20.
  • the common electrode 10 may be connected in a manner such that the common electrode of at least four pixel units of each of the two adjacent rows of pixel units is electrically connected to each other through the first connection line 121 and the second connection line 122. Forming a closed annular common electrode unit 20. Although only four rows and two columns of pixel cells are shown in FIG. 2, in practice, similarly, a common electrode unit 20 of the same structure may exist in a region not shown in the drawing.
  • the common electrode 10 of each of three or four rows of pixel units adjacent to each other may be connected to each other to form one common electrode unit 20.
  • the number of pixel units in the common electrode unit 20 is not limited to the above manner, and the arrangement of the embodiment of the present invention can reduce the resistance on the common electrode line, thereby reducing the voltage drop of the common electrode signal and improving the uniformity of display.
  • common electrode units 20 located in the same row or the same column are electrically connected to each other.
  • the common electrode units 20 of the same row or the same column are electrically connected to each other by at least one trace.
  • the same row of common electrode units 20 adjacent to each other may be connected by a single row, or the same column of common electrode units 20 may be used. Connected, or a combination of two connections.
  • the common electrode line 11 may be parallel to the gate line 13 and disposed in the same layer, and the connection line 12 Parallel to the data line 14 and disposed in the same layer, the common electrode line 11 and the connection line 12 are located in different layers, and are connected to each other by providing via holes.
  • the connection line 12 is disposed in the same layer as the gate line 13, the gate line 13 and the connection line 12 can be formed in synchronization in the array substrate process, and there is no need to additionally increase the process.
  • the second specific example provided in this embodiment is different from the above example in that the common electrode lines 11 (for example, Com1 to Com4) in this example are disposed in parallel with the data line 14, each A common electrode line 11 is connected to a column of common electrodes 10 for supplying a common voltage to the column of common electrodes 10.
  • the common electrodes 10 of each of the two columns adjacent to each other are connected by at least two connecting lines 12, the connecting lines 12 and the gate lines. 13 parallel settings.
  • the three or four or more columns of the common electrodes 10 adjacent to each other may be connected by at least two connecting lines 12.
  • the more detailed connection manner that can be employed in the present example is as follows: the common electrode 10 of the four pixel units of each of the two adjacent columns of pixel units is electrically connected to each other through the common electrode line 11 and the two connection lines 12 Connected to form a closed annular common electrode unit 20.
  • the common electrode of each of three or four or more columns of pixel units adjacent to each other is a common electrode unit 20.
  • the common electrode units 20 located in the same column are electrically connected to each other.
  • the common electrode lines arranged in parallel with the data lines are electrically connected to each other by the connecting wires, so that the resistance of the common electrode lines and the voltage drop of the common electrode signals can be reduced, thereby improving display uniformity.
  • the substrate is divided into a plurality of regions 15 and common electrode lines located in the same region 15 in the present example. 11 is connected by at least two connecting lines 12.
  • FIG. 6 omits a detailed illustration of the common electrode, showing only the common electrode lines 11 (Com1 to Com12) and the connection lines 12, the connection of the common electrode lines 11 to the common electrodes, and the connection lines 12 and the common electrode lines.
  • 11 refer to FIGS. 2 to 5 .
  • 12 common electrode lines 11 (Com1 to Com12) are shown, and each of the adjacent four common electrode lines 11 is divided into a region 15, that is, the common electrode lines Com1 to Com4 are divided into a first region 15, and the common electrode line Com4
  • the -Com8 is divided into the second region 15, and the common electrode lines Com8 to Com12 are divided into the third region 15. If there are more common electrode lines, the following analogy is performed.
  • the four common electrode lines Com1 to Com4 in the region 15 are connected to each other by at least two connecting lines 12, Each black dot in the figure represents a connection of a connecting line 12 and a common electrode line 11. Further, a plurality of connecting lines 12 are used to connect the common electrodes in each region into a mesh structure to reduce the resistance on the common electrode lines and improve display uniformity.
  • the substrate edge is further provided with a common lead, and the common electrode line 11 located in the same region 15 is connected to the same common lead.
  • the common electrode lines Com1 to Com4 in the first region 15 are connected to one common lead 16; similarly, the common electrode lines Com4 to Com8 in the second region 15 are combined with the second common lead. (not shown) connected; similarly, the common electrode lines Com8 to Com12 in the third region 15 are connected to a third common lead (not shown), and so on, and the rest of the regions will not be described again.
  • the voltages of the common leads connecting the common electrode lines in different regions are different.
  • different common voltages can be supplied to different regions through the common lead according to actual needs, thereby compensating for the voltage drop when the common electrode signals are transmitted.
  • This embodiment further provides a modification of the third specific example, which is different from the third specific example in that the common electrodes in the adjacent pixel units are electrically connected to each other through the first connection line and the second connection line, A plurality of closed annular common electrode units are formed.
  • the edge of the substrate is provided with a common lead, and if the common electrode line included in the common electrode unit is an odd number, the common lead is connected to the (N+1)/2th common electrode line; if the common electrode unit includes a common electrode line When the number is even, the common lead is connected to the N/2th and (N/2+1) common electrode lines.
  • This connection mode can be provided to the area where the common electrode unit is located through the common lead according to actual needs. Different common voltages are used to compensate for the voltage drop at the time of common electrode signal transmission, and the common voltage can be distributed more evenly over the common electrode line network of the region where the common electrode unit is located.
  • the resistance on the common electrode line can be reduced, and the voltage drop at the time of signal transmission of the common electrode can be compensated, thereby improving display uniformity.
  • the embodiment of the invention further provides a display device comprising any of the above array substrates.
  • the display device includes an array substrate and a counter substrate, which are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • the voltage drop at the time of the common electrode signal transmission is smaller, so that higher display quality can be obtained.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED Any product or component with display function such as panel, mobile phone, tablet, TV, monitor, laptop, digital photo frame, navigator, watch, etc.
  • Embodiments of the present invention provide a substrate and a display device.
  • the two (or more) common electrode lines are electrically connected to each other by providing at least two connecting lines, and the total resistance is reduced by using two resistors in parallel. Thereby, the electric resistance on the common electrode line is lowered, and display uniformity is improved.
  • the substrate may be an array substrate, and the connection line is located in the display area, and can be completed synchronously in the array substrate process without additional steps.
  • the substrate of the above embodiment is described by taking the substrate as an array substrate.
  • the substrate may also be an opposite substrate (for example, a color filter substrate).
  • the common electrode may not be formed on the array substrate.
  • the corresponding "pixel unit" at this time can be a pixel unit on the array substrate.

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Abstract

提供了一种基板和显示装置。基板包括：多条间隔排列的公共电极线（11），公共电极线（11）向相应的像素单元提供公共电压，至少两条连接线（12），连接线（12）均位于显示区域，用于在至少两条相邻的公共电极线（11）之间实现相互电连接。

Description

基板和显示装置 技术领域
本发明的实施例涉及显示领域，尤其涉及一种基板和显示装置。
背景技术
液晶显示器(LCD，Liquid Crystal Display)因其具有体积小、重量轻、功耗低、驱动电压低以及无辐射等优点，已广泛应用于电视、手机以及公共信息的显示，是目前使用最广泛的显示技术。
液晶显示器包括彩膜基板和阵列基板以及夹置在二者中间的液晶层。彩膜基板和阵列基板上分别设置有公共电极和像素电极，工作时像素电极和公共电极被施以电压，其二者间的压差造成电场，该电场改变液晶层中液晶分子的取向，进而改变光通过液晶层的透射率，从而达到显示图像的目的。
发明内容
本发明的实施例提供一种基板和显示装置，能够降低公共电极线上的电阻，提高显示均匀性。
本发明的至少一个实施例提供了一种基板，包括：多条间隔排列的公共电极线，所述公共电极线向相应的像素单元提供公共电压；至少两条连接线，所述连接线均位于显示区域，用于在至少两条相邻的两条或多条公共电极线之间实现相互电连接。
在一个示例中，例如，每一条公共电极线与至少一行/列像素中的公共电极相连。
在一个示例中，例如，所述基板划分为多个区域，位于同一所述区域内的公共电极线通过所述连接线实现电连接。
在一个示例中，例如，所述基板还包括设置在所述基板边缘的公共引线，位于同一所述区域内的公共电极线与同一所述公共引线相连。
在一个示例中，例如，连接不同所述区域内的公共电极线的所述公共引线的电压不同。
在一个示例中，例如，所述连接线包括第一连接线和第二连接线；位于不同行中的至少4个像素单元的公共电极通过第一连接线和第二连接线相互电连接，形成一个封闭环状的公共电极单元。
在一个示例中，例如，位于同一行/列的所述公共电极单元相互电连接。
在一个示例中，例如，所述公共电极单元包括的公共电极线为奇数时，所述公共引线与所述第(N+1)/2条公共电极线连接；或者所述公共电极单元包括的公共电极线为偶数时，所述公共引线与所述第N/2和(N/2+1)条公共电极线连接。
在一个示例中，例如，所述基板为阵列基板或对置基板。
在一个示例中，例如，所述基板为阵列基板，且所述阵列基板还包括：数据线和栅线，所述公共电极线与所述栅线平行且同层设置，所述连接线与所述数据线平行且同层设置；或者，所述公共电极线与所述数据线平行且同层设置；所述连接线与所述栅线平行且同层设置。
在一个示例中，例如，所述公共电极线与所述连接线通过过孔相连接。
本发明的至少一实施例还提供一种显示装置，包括上述任一项所述的基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种阵列基板的平面结构示意图；
图2为本发明实施例第一种具体示例中阵列基板的平面结构示意图一；
图3为本发明实施例第一种具体示例中阵列基板的平面结构示意图二；
图4为本发明实施例第一种具体示例中阵列基板的平面结构示意图三；
图5为本发明实施例第二种具体示例中阵列基板的平面结构示意图；
图6为本发明实施例第三种具体示例中阵列基板的平面结构示意图。
附图标记
10-公共电极，11-公共电极线，12-连接线，121-第一连接线，
122-第二连接线，13-栅线，14-数据线，15-区域，20-公共电极单元。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
液晶显示器中的公共电极一般为覆盖显示区域的整张的膜层(板式结构)或者具有例如如图1所示的分割设计结构。图1中每一像素单元中设置有一个公共电极10，每行像素单元设置一条公共电极线11(例如，Com1～Com 4)，向该行像素中的各个公共电极10提供液晶驱动需要的公共电压。随长度的延伸，公共电极线11上会存在压降，使得公共电极的电压在整个面板内部的分布是不均匀的，这会降低显示的均匀性。
本发明的至少一实施例提供一种阵列基板，参照图2所示，该阵列基板包括：多条间隔排列的公共电极线11，公共电极线11向相应的像素单元提供公共电压，该阵列基板还包括：至少两条连接线12，所述连接线12均位于显示区域，用于在至少两条相邻的公共电极线11之间实现相互电连接。
本实施例中通过连接线12将相邻的两条或者更多条公共电极线11相互电连接，该连接可以是直接相连，即连接线12的一端与一条公共电极线11相连，另一端与另一条公共电极线11相连，连接线12两端之间的中间点还可以与更多其他公共电极线11相连；该连接也可以是间接相连，即每一条公共电极线11与至少一行(或列)像素中的公共电极10相连，然后相邻行(或列)的公共电极10通过上述连接线12相连。连接线12一般在与公共电极线11垂直的方向，将相邻两条或者更多条公共电极线11相互电连接。
一般而言，在液晶显示器领域中的行一般指与栅线平行的方向，列一般指与数据线平行的方向，本文的叙述可以参照此方式理解。但本领域技术人员可以理解的是，本实施例中的行或列只是描述相对概念，可以不作区分。
本发明实施例中，通过至少两条连接线将相邻的两条(或多条)公共电极线相互电连接，可以将相邻公共电极线并联或者相邻公共电极线的部分线段并联，众所周知两个电阻并联后总阻值会降低，因而设置连接线可以降低公共电极线上的电阻，提高显示均匀性。另外，因所述连接线位于显示区域，可以在阵列基板制程中同步完成，不需要额外增加工序。
为了本领域技术人员更好的理解本发明实施例提供的技术方案，下面通 过具体的实施例对本发明提供的基板进行详细说明。
如图2所示阵列基板，为符合本实施例的第一种具体示例。该阵列基板包括：横向分布的栅线13(例如，G1～G4)，纵向分布的数据线14(例如，D1～D3)，栅线13和数据线14纵横交错区域设置有像素单元，每一像素单元内设置有一公共电极10和一像素电极(位于公共电极10的上方或下方，图中未示出)，栅线13与数据线14的交叉处还设置有作为开关元件的薄膜晶体管。每个像素单元中中，薄膜晶体管的源极与数据线14相连，漏极与像素电极相连，栅极与栅线13相连。阵列基板上还设置有与栅线13平行的公共电极线11(例如，Com1～Com4)，每一条公共电极线11与一行公共电极10相连，用于向一行公共电极10提供公共电压，上下相邻的每两行的公共电极线11通过至少两条连接线11相连。
可选地，还可以将上下相邻的每三行或者每四行，或者更多行的公共电极线11通过至少两条连接线11相连。
可选地，上述连接线12可包括：第一连接线121和第二连接线122；位于不同行中的至少4个像素单元的公共电极10通过第一连接线121和第二连接线122相互电连接，形成一个封闭环状的公共电极单元20。
例如，公共电极10的连接方式可以如图2所示，上下相邻的每两行像素单元的中的至少4个像素单元的公共电极通过第一连接线121和第二连接线122相互电连接，形成一个封闭环状的公共电极单元20。虽然图2中仅示出4行2列像素单元，实际上相类似地，图中未示出区域可以存在更多相同结构的公共电极单元20。
或者，还可以如图3和图4所示，上下相邻的每3行或每4行的像素单元的公共电极10相互连接形成一个公共电极单元20。当然，公共电极单元20中像素单元的数量不局限上述方式，本发明的实施例的设置都可以降低公共电极线上的电阻，从而降低公共电极信号的压降，提高显示的均匀性。
进一步地，上述位于同一行或同一列的公共电极单元20相互电连接。同一行或同一列的公共电极单元20之间至少通过一条走线相互电连接，例如可以单一采用将左右相邻的同一行公共电极单元20相连，也可以采用上下相邻同一列公共电极单元20相连，或者两种连接方式组合使用。
可选地，上述公共电极线11可以与栅线13平行且同层设置，连接线12 与数据线14平行且同层设置，公共电极线11与连接线12位于不同层，通过设置过孔相互连接。制备时因连接线12与栅线13同层设置，在阵列基板制程中可以同步形成栅线13和连接线12，不需要因此额外增加工序。
如图5所示，为本实施例提供的第二种具体示例，与上述示例的区别之处在于，该示例中的公共电极线11(例如，Com1～Com4)与数据线14平行设置，每一条公共电极线11与一列公共电极10相连，用于向该列公共电极10提供公共电压，左右相邻的每两列的公共电极10通过至少两条连接线12相连，连接线12与栅线13平行设置。同样可选地，本示例中也可以将左右相邻的每三列或者每四列，或者更多列的公共电极10通过至少两条连接线12相连。
具体而言，本示例可采用的更为详细的连接方式如下：左右相邻的每两列像素单元的中的4个像素单元的公共电极10通过公共电极线11和两条连接线12相互电连接，形成一个封闭环状的公共电极单元20。与图3和图4所示相类似地，还可以是左右相邻的每3列或每4列甚至更多列的像素单元的公共电极为一个公共电极单元20。进一步地，位于同一列的公共电极单元20相互电连接。
本示例中通过连接线将与数据线平行排列的公共电极线相互电连接，可以降低公共电极线上的电阻以及公共电极信号的压降，从而提高显示的均匀性。
如图6所示，为符合本实施例的第三种具体示例，与上述两种示例的区别之处在于，本示例中将基板划分为多个区域15，位于同一区域15内的公共电极线11通过至少两个连接线12相连。
为简略起见，图6省去公共电极的具体图示，只示出公共电极线11(Com1～Com12)和连接线12，公共电极线11与公共电极的连接，以及连接线12与公共电极线11的连接具体可参照图2～5。图中示出12条公共电极线11(Com1～Com12)，相邻的每四条公共电极线11划分为一个区域15，即公共电极线Com1～Com4划分为第一个区域15，公共电极线Com4～Com8划分为第二个区域15，公共电极线Com8～Com12划分为第三个区域15，如有更多公共电极线，则以下类推进行划分。以第一个区域15为例，该区域15中这4行公共电极线Com1～Com4中都通过至少两条连接线12相互连接， 图中的每一黑点即代表一个连接线12与公共电极线11的连接处。进一步地，采用多条连接线12将每一区域内的公共电极都连接成网状结构，以降低公共电极线上的电阻，提高显示的均匀性。
进一步地，所述基板边缘还设置有公共引线，位于同一区域15内的公共电极线11与同一公共引线相连。参照图6所示，第一个区域15中的公共电极线Com1～Com4中与一条公共引线16相连；类似地，第二个区域15中的公共电极线Com4～Com8中与第二条公共引线(未示出)相连；类似地，第三个区域15中的公共电极线Com8～Com12中与第三条公共引线(未示出)相连，与此类推，其余区域不再赘述。
可选地，连接不同区域内的公共电极线的公共引线的电压不同。为进一步提高显示均匀性，可以根据实际需要，通过公共引线向不同区域提供不同的公共电压，以补偿公共电极信号传递时的压降。
本实施例还提供第三种具体示例的一种变型，与第三种具体示例不同之处在于，先通过第一连接线和第二连接线将相邻像素单元中的公共电极相互电连接，形成多个封闭环状的公共电极单元。基板的边缘设置有公共引线，如果公共电极单元包括的公共电极线为奇数时，则公共引线与所述第(N+1)/2条公共电极线连接；如果公共电极单元包括的公共电极线为偶数时，则公共引线与所述第N/2和(N/2+1)条公共电极线连接，这种连接方式，可以根据实际需要，通过公共引线向各公共电极单元所在的区域提供不同的公共电压，以补偿公共电极信号传递时的压降，并且可以使公共电压在公共电极单元所在的区域的公共电极线网络上分布更均匀。
本示例通过划分不同区域，并分区域提供不同大小的公共电压的方式，可以降低公共电极线上的电阻，并补偿公共电极信号传递时的压降，从而提高显示的均匀性。
本发明实施例还提供一种显示装置，其包括上述任意一种阵列基板。该显示装置包括阵列基板与对置基板，二者彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
根据本发明实施例的显示装置，因公共电极信号传递时的压降更小，从而可获得更高的显示品质。所述显示装置可以为：液晶面板、电子纸、OLED 面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、手表等任何具有显示功能的产品或部件。
本发明实施例提供一种基板和显示装置，通过设置至少两条连接线将相邻的两条(或多条)公共电极线相互电连接，利用两个电阻并联后总阻值降低的原理，从而降低了公共电极线上的电阻，提高了显示均匀性。另外，所述基板可以为阵列基板，因所述连接线位于显示区域，可以在阵列基板制程中同步完成，不需要额外增加工序。
上述实施例的所述基板均以基板为阵列基板为例进行介绍，可选的，所述基板还可以为对置基板(例如彩膜基板)，此时公共电极可以并非形成在阵列基板之上。可以理解的，此时相应的“像素单元”可以为阵列基板上的像素单元。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于设备实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年8月5日递交的中国专利申请第201420438070.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种基板，包括：
    多条间隔排列的公共电极线，所述公共电极线向相应的像素单元提供公共电压；
    至少两条连接线，所述连接线均位于显示区域，用于在至少两条相邻的公共电极线之间实现相互电连接。
  2. 根据权利要求1所述的基板，其中，每一条公共电极线与至少一行/列像素单元中的公共电极相连。
  3. 根据权利要求1或2所述的基板，其中，所述基板划分为多个区域，位于同一所述区域内的公共电极线通过所述连接线实现电连接。
  4. 根据权利要求3所述的基板，还包括：设置在所述基板边缘的公共引线，位于同一所述区域内的公共电极线与同一所述公共引线相连。
  5. 根据权利要求4所述的基板，其中，连接不同所述区域内的公共电极线的所述公共引线的电压不同。
  6. 根据权利要求3或4所述的基板，其中，所述连接线包括第一连接线和第二连接线；
    位于不同行中的至少4个像素单元的公共电极通过第一连接线和第二连接线相互电连接，形成一个封闭环状的公共电极单元。
  7. 根据权利要求6所述的基板，其中，位于同一行/列的所述公共电极单元相互电连接。
  8. 根据权利要求7所述的基板，其中，所述公共电极单元包括的公共电极线为奇数时，所述公共引线与所述第(N+1)/2条公共电极线连接；或者所述公共电极单元包括的公共电极线为偶数时，所述公共引线与所述第N/2和(N/2+1)条公共电极线连接。
  9. 根据权利要求1-8任一项所述的基板，其中，所述基板为阵列基板或对置基板。
  10. 根据权利要求9所述的基板，其中，所述基板为阵列基板，所述基板还包括数据线和栅线，所述公共电极线与所述栅线平行且同层设置，所述连接线与所述数据线平行且同层设置；或者，
    所述公共电极线与所述数据线平行且同层设置；所述连接线与所述栅线平行且同层设置。
  11. 根据权利要求10所述的基板，其中，所述公共电极线与所述连接线通过过孔相连接。
  12. 一种显示装置，包括权利要求1-11任一项所述的基板。
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CN204028524U (zh) * 2014-06-23 2014-12-17 京东方科技集团股份有限公司 显示基板及显示装置

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