WO2019196840A1 - 阵列基板及其制作方法、显示面板和显示装置 - Google Patents

阵列基板及其制作方法、显示面板和显示装置 Download PDF

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Publication number
WO2019196840A1
WO2019196840A1 PCT/CN2019/081941 CN2019081941W WO2019196840A1 WO 2019196840 A1 WO2019196840 A1 WO 2019196840A1 CN 2019081941 W CN2019081941 W CN 2019081941W WO 2019196840 A1 WO2019196840 A1 WO 2019196840A1
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Prior art keywords
layer
electrode
forming
source
drain
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PCT/CN2019/081941
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English (en)
French (fr)
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刘威
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京东方科技集团股份有限公司
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Priority to US16/610,261 priority Critical patent/US11380720B2/en
Publication of WO2019196840A1 publication Critical patent/WO2019196840A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a method of fabricating the same, a display panel, and a display device.
  • Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, a display panel, and a display device to solve the problem that a process of forming a source/drain layer pattern is complicated in the fabrication of an array substrate.
  • At least one embodiment of the present disclosure provides an array substrate including: a photosensitive member on a substrate substrate, the photosensitive member including a photosensitive layer; and a thin film transistor located at the photosensitive member away from the substrate One side of the substrate.
  • the photosensitive member further includes a first electrode, the first electrode, the photosensitive layer, and the second electrode are stacked, and the first The electrode is closer to the base substrate than the second electrode;
  • the thin film transistor includes an active layer, a material of the active layer includes a semiconductor;
  • the first electrode is a light shielding layer, and the first electrode is at The orthographic projection on the substrate substrate completely covers the orthographic projection of the active layer on the substrate.
  • the second electrode is located between the base substrate and the active layer.
  • the thin film transistor further includes a source and drain layer, the source and drain layers include a source and a drain, and the source and the drain respectively and the active layer Electrically connecting; an orthographic projection of the source and the drain on the substrate substrate falls within an orthographic projection of the first electrode on the substrate.
  • the first electrode and the source and drain layers are respectively located in different layers, and one of the source and the drain is electrically connected to the first electrode.
  • one of the source and the drain is in contact with the first electrode.
  • the array substrate further includes a conductive layer electrically connected to the second electrode, the conductive layer being in the same layer as the source drain layer.
  • the array substrate further includes an interlayer insulating layer located on a side of the photosensitive member remote from the substrate, and located at the source and The conductive layer and the source/drain layer are in contact with a surface of the interlayer insulating layer remote from the substrate.
  • the array substrate further includes a gate insulating layer and a gate electrode disposed on a side of the active layer away from the substrate substrate, the gate insulating layer and the gate An orthographic projection of the gate on the substrate substrate falls within an orthographic projection of the active layer on the substrate.
  • the array substrate further includes a buffer layer between the photosensitive member and the thin film transistor, the source or the drain passing through the buffer layer and the The first vias of the interlayer insulating layer are electrically connected, and the conductive layer is electrically connected by a second via hole penetrating the buffer layer and the interlayer insulating layer.
  • the material of the photosensitive layer includes a PIN type semiconductor material.
  • At least one embodiment of the present disclosure also provides a display panel including any of the above array substrates.
  • At least one embodiment of the present disclosure also provides a display device including any of the above display panels.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, comprising: forming a photosensitive member on a substrate, forming the photosensitive member including forming a photosensitive layer; and forming a thin film transistor, wherein the thin film transistor is located The photosensitive member is away from one side of the substrate.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, comprising: forming a photosensitive member, the forming the photosensitive member comprising forming a photosensitive layer on a substrate; and forming a thin film transistor after forming the photosensitive member .
  • forming the photosensitive member further includes forming a first electrode before forming the photosensitive layer and forming a second electrode after forming the photosensitive layer; forming the thin film transistor further includes Forming an active layer and forming an interlayer insulating layer, an orthographic projection of the active layer on the substrate substrate falling within an orthographic projection of the first electrode on the substrate; the method further comprising Forming a buffer layer after forming the photosensitive member and before forming the active layer; forming first vias and second vias penetrating the interlayer insulating layer and the buffer layer; forming a conductive film; Forming the conductive film to form a conductive layer and a source and a drain of the thin film transistor, the source and the drain are respectively electrically connected to the active layer, and one of the source and the drain passes through The first via is electrically connected to the first electrode, and the conductive layer is electrically connected to the second electrode.
  • the first via and the second via are formed in the same patterning process, and the source, the drain, and the conductive layer are in the same patterning process. Formed in the middle.
  • 1 is a schematic structural view of an array substrate
  • FIG. 2A is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • 2B is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • 3A is a flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 3B is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • 3C is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • 4A-4K are schematic diagrams showing a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • compensation technology is mainly used to improve the display quality of the display panel, and the optical sensor is built in the display panel for compensation.
  • a photosensitive member for example, a PIN
  • TFT thin film transistor
  • FIG. 1 is a schematic structural view of an array substrate.
  • a light shielding layer 02 is provided on the substrate 01.
  • the light shielding layer 02 can be patterned by using any metal conductive film having a light blocking effect.
  • a light-shielding layer 02 is provided with a switching TFT 001, and a photosensitive member 09 is disposed on the TFT 001.
  • the TFT 001 includes a source/drain layer 08, a semiconductor active layer 012, and a gate electrode 06, and the source/drain layer 08 includes a source 081 and a drain 082.
  • the photosensitive member 09 includes a first electrode 091, a photosensitive layer 090, and a second electrode 092.
  • the photosensitive layer 090 is formed on the source/drain layer 08. Since a large amount of hydrogen is generated during the fabrication of the photosensitive member 09, the hydrogen element has a great influence on the electrical properties of the TFT, so that hydrogen deposition on the TFT 001 is avoided in the fabrication process. Therefore, it is necessary to perform the patterning process to form the pattern of the source/drain layer 08, that is, after the gate electrode 06 and the buffer layer 07 (ILD) pattern are formed, the source/drain layer 08 is formed, and the source/drain layer 08 needs to be first.
  • ILD buffer layer 07
  • the sub-patterning process preserves the metal of the source and drain layers over the gate 06 of the TFT, preventing the hydrogen element from affecting the TFT 001 during the subsequent formation of the photosensitive layer 090.
  • the source/drain layer 08 is subjected to a second patterning process to etch away the source/drain layer metal above the gate 06 of the TFT to form a complete source/drain layer pattern, and then passivation.
  • Layer 010 PVX
  • a via is formed on the passivation layer 010, and the photosensitive member 09 is connected to the external signal of the display panel through the metal layer 011 at the via.
  • the pattern of the source and drain layers is formed by a two-step patterning process, which has a complicated manufacturing process and affects the yield of the product.
  • FIG. 2A is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • an array substrate according to an embodiment of the present disclosure includes: a photosensitive member 3 on a substrate substrate 1 and a thin film transistor 5, the photosensitive member 3 includes a photosensitive layer 32; and the thin film transistor 5 is located away from the lining of the photosensitive member 3.
  • the thin film transistor 5 is located on a side of the photosensitive member 3 away from the substrate 1, and the photosensitive layer 32 is formed before the thin film transistor 5 is formed to avoid the hydrogen element-to-film generated during the process of forming the photosensitive layer 32.
  • the transistor 5 has an effect, and the layer in which the source and drain of the thin film transistor are located can be completed in a one-step patterning process, simplifying the process steps.
  • the array substrate further includes a source drain layer 55 and a conductive layer 6.
  • the conductive layer 6 is electrically connected to the second electrode 33, and the conductive layer 6 is located in the same layer as the source/drain layer 55.
  • the source and drain layer 55 includes a drain 501 and a source 502.
  • the source 502 and the drain 501 are electrically connected to the active layer 51, respectively.
  • the orthographic projection of the source 502 and the drain 501 on the substrate 1 falls into the first electrode. 31 is within the orthographic projection on the base substrate 1.
  • the first electrode 31 and the source/drain layer 55 are respectively located in different layers.
  • the first electrode 31 is electrically connected to one of the drain 501 and the source 502.
  • the drain 501 and the source 502 are interchangeable, and the embodiment of the present disclosure is described by taking the drain 501 electrically connected to the first electrode 31 as an example.
  • the photosensitive member 3 includes a first electrode 31, a photosensitive layer 32, and a second electrode 33 which are laminated, and the first electrode 31 is closer to the substrate 1 than the second electrode 33.
  • the first electrode 31 is electrically connected to the drain 501 of the thin film transistor 5, and the second electrode 33 is electrically connected to the conductive layer 6.
  • the thin film transistor 5 includes an active layer 51, and the material of the active layer 51 includes a semiconductor; the first electrode 31 is a light shielding layer, and the orthographic projection of the first electrode 31 on the substrate substrate 1 is completely covered with The orthographic projection of the source layer 51 on the base substrate 1.
  • the first electrode 31 simultaneously functions as a light blocking to prevent the light irradiated onto the active layer 51 from affecting the thin film transistor 5.
  • the second electrode 33 is located between the base substrate 1 and the active layer 51.
  • the first electrode 31 of the photosensitive member 3 is electrically connected to the source or the drain of the thin film transistor 5, the second electrode 33 is electrically connected to the conductive layer 6, and the conductive layer 6 can be electrically connected to the peripheral circuit of the array substrate.
  • the photosensitive member 3 having the photocurrent sensing function is combined with a thin film transistor 5 as a switch to form a detectable real-time optical change, and is connected to the peripheral circuit through the conductive layer 6, and the photosensitive member 3 is regulated, and the display is improved by the compensation technique. quality.
  • the photosensitive member 3 is provided on the base substrate 1, and the thin film transistor 5 and the conductive layer 6 are provided on the photosensitive member 3.
  • the photosensitive member 3 includes a first electrode 31, a photosensitive layer 32, and a second electrode 33 which are disposed in a stacked manner.
  • the first electrode 31 is disposed adjacent to the substrate 1, and the first electrode 31 of the photosensitive member 3 and the drain 501 of the thin film transistor 5 are One of the sources 502 is electrically connected, and the second electrode 33 of the photosensitive member 3 is electrically connected to the conductive layer 6.
  • the photosensitive member 3 is formed first, and then the thin film transistor 5 is formed on the photosensitive member 3.
  • the hydrogen element is prevented from affecting the thin film transistor 5 during the formation of the photosensitive member 5.
  • the pattern of the source/drain layer 55 of the thin film transistor 5 can be It is formed by a single patterning process, which simplifies the manufacturing process.
  • the thin film transistor 5 further includes a gate insulating layer 52 and a gate electrode 53 which are disposed on the side of the active layer 51 away from the substrate 1 and the gate insulating layer 52 and the gate 53 are on the substrate.
  • the orthographic projection on 1 falls within the orthographic projection of the active layer 51 on the base substrate 1.
  • the material of the gate electrode 53 includes a metal
  • the material of the gate insulating layer 52 includes an insulating material.
  • a thin film transistor having the above-described thin film transistor 5 as a top gate structure will be described as an example, but it is understood that the structure of the embodiment of the present disclosure is also applicable in the bottom gate structure. That is, in the array substrate provided by another embodiment of the present disclosure, the TFT of the top gate structure in FIG. 2A is replaced with the TFT of the bottom gate structure.
  • the first electrode 31 may extend below the active layer 51 as the light shielding layer 34, that is, the first electrode 31 of the light shielding layer 34 is integrally formed.
  • the orthographic projection of the first electrode 31 or the light shielding layer 34 on the base substrate 1 covers the orthographic projection of the active layer 51 of the thin film transistor 5 on the base substrate 1, and the channel of the thin film transistor 5 can be prevented.
  • the electrical characteristics of the thin film transistor are prevented from being deteriorated by the influence of the illumination under the base substrate 1.
  • the light shielding layer 34 is located directly under the active layer 51, and the first electrode 31 of the light shielding layer 34 is integrally formed.
  • the first electrode 31 simultaneously functions as a light-shielding and one electrode of the photosensor, that is, the light-shielding layer 34 can serve as an electrode of the photo-sensor 3.
  • the process steps are simplified, and a light-shielding electrode layer can be formed on the base substrate, and the integrated light-shielding layer 34 and the first electrode 31 are formed by one patterning process.
  • a photosensitive layer 32 is formed on the first electrode 31.
  • the photosensitive layer 32 may be made of a photosensitive material, and may be a PIN-type semiconductor material having a thickness of about 1 ⁇ m.
  • the photosensitive layer 32 can be produced by a usual method.
  • a second electrode 33 is formed on the photosensitive layer 32.
  • the material of the second electrode 33 may be a transparent conductive layer material such as indium tin oxide (ITO) or the like.
  • the forming process of the first electrode 31, the photosensitive layer 32, and the second electrode 33 of the photosensitive member 3 described above may include the following steps. Step 1), forming a first electrode layer having a light shielding effect on the base substrate; Step 2) forming a PIN film layer of about 1 ⁇ m by a chemical vapor deposition process on the first electrode layer, and step 3) in the PIN film layer A transparent conductive second electrode layer is formed by sputtering, and then a pattern of the photosensitive member 3 is formed by a wet etching process.
  • the thin film transistor 5 is formed thereon.
  • the fabrication process of the thin film transistor 5 can be referred to a general process, and details are not described herein.
  • the conductive layer 6 is disposed in the same layer as the drain 501 of the thin film transistor 5, that is, the conductive layer 6 is disposed in the same layer as the source/drain layer 55 of the thin film transistor 5.
  • the material of the conductive layer 6 may be the same as that of the source/drain layer 55.
  • the material of the conductive layer 6 and the source and drain layer 55 includes, for example, a metal or alloy material. This structure can simplify the fabrication process, and simultaneously forms a pattern of the source and drain layer 55 and a pattern of the conductive layer 6 in one step.
  • the conductive layer 6 is used to connect with peripheral circuits of the array substrate to regulate the photosensitive member 3.
  • the hydrogen element generated during the formation of the photosensitive layer of the photosensitive member may generate electrical characteristics of the thin film transistor.
  • the effect is that the source and drain layers are not completely patterned before the photosensitive member is formed, and the portion of the source/drain film layer above the active layer of the thin film transistor is retained, and after the photosensitive layer of the photosensitive member is formed, the source/drain film layer is further formed. A second patterning is performed to form a complete source/drain layer pattern.
  • the fabrication process of the present application is simpler and simplifies the formation steps of the thin film transistor.
  • a stacked buffer layer 4 and an interlayer insulating layer are formed between the first electrode 31 and the drain 501 of the thin film transistor 5, that is, between the first electrode 31 and the source/drain layer 55.
  • the buffer layer 4 is closer to the base substrate 1 than the interlayer insulating layer 54, and the buffer layer 4 and the interlayer insulating layer 54 completely cover the photosensitive member 3.
  • a via hole V1 is disposed in the buffer layer 4, and a via hole V2 is disposed in the interlayer insulating layer 54, the via hole V1 and the via hole V2 constitute a first via hole V01, and the drain electrode 501 of the thin film transistor 5 passes through the first via hole V01 is electrically connected to the first electrode 31.
  • the drain 501 of the thin film transistor 5 is electrically connected to the light shielding layer 34, and the electrical characteristics of the thin film transistor can be improved.
  • the via hole V1 and the via hole V2 can be formed by an exposure etching process before the source/drain layer 55 is formed, and the drain electrode 501 of the thin film transistor 5 is passed through the source/drain film layer while forming the source/drain film layer.
  • a portion of the metal material is electrically connected to the first electrode 31.
  • via V1 and via V2 can be formed in the same patterning process.
  • a via hole V3 is further disposed in the buffer layer 4, and a via hole V4 is further disposed in the interlayer insulating layer 54, the via hole V3 and the via hole V4 constitute a second via hole V02, and the conductive layer 6 passes through the second pass.
  • the hole V02 is electrically connected to the second electrode 33.
  • via V3 and via V4 can be formed in the same patterning process.
  • via V1, via V2, via V3, and via V4 can be formed in the same patterning process.
  • the first via hole V01 penetrates the buffer layer 4 and the interlayer insulating layer 54
  • the second via hole V02 penetrates through the buffer layer 4 and the interlayer insulating layer 54
  • the first via hole V01 and the second via hole V02 may be in the same patterning process. Formed in the middle.
  • the interlayer insulating layer 54 is located on the side of the photosensitive member 3 remote from the substrate 1 and is located between the source 502 and the drain 501; the conductive layer 6 and the source/drain layer 55 and the interlayer The surface of the insulating layer 54 that is away from the substrate 1 is in contact.
  • the source 502 or the drain 501 is electrically connected through the first via hole V01 penetrating the buffer layer 4 and the interlayer insulating layer 54, and the conductive layer 6 passes through the buffer layer 4 and the interlayer insulating layer 54.
  • the second via hole V02 is electrically connected.
  • the array substrate further includes a passivation layer 7 to protect the source 502, the drain 501, and the conductive layer 6.
  • the passivation layer 7 can be made of an insulating material.
  • the electrical connection between the thin film transistor 5 and the photosensitive member 3 and the electrical connection between the photosensitive member 3 and the peripheral circuit of the array substrate may pass through the via hole located in the buffer layer 4 and the interlayer insulating layer 54 and
  • the material of the portion of the power supply leakage film layer located in the via hole is realized by only one exposure etching, and the four via holes are formed and electrically connected.
  • the drain or source of the source/drain layer serves as one electrode of the photosensitive member at the same time, and the other electrode of the photosensitive member needs to pass through the via hole located thereon, and then through the conductive metal and the peripheral circuit.
  • the above description only uses the thin film transistor 5 as the top gate structure. It can be understood that, in the bottom gate structure, similarly, the above structure can be employed, and after the photosensitive member 3 is formed, the thin film transistor 5 and the conductive layer 6 are formed. Any one of the source and the drain of the thin film transistor 5 is electrically connected to the first electrode 31 of the photosensitive member 3, and the conductive layer 6 is electrically connected to the second electrode 33 of the photosensitive member 3.
  • the patterning process of the source/drain layer pattern of the thin film transistor of the array substrate can be simplified. The specific structure is similar to that of the above embodiment, and details are not described herein again.
  • FIG. 2B is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • the drain electrode 501 is connected to the first electrode 31 through the connection electrode 521 as compared with the structure shown in FIG. 2A.
  • FIG. 3A is a flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure. At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, comprising: forming a photosensitive member on a substrate, forming a photosensitive member including forming a photosensitive layer; and forming a thin film transistor located at a photosensitive member away from the substrate One side.
  • FIG. 3B is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure. At least one embodiment of the present disclosure also provides a method of fabricating an array substrate, comprising: forming a photosensitive member, forming the photosensitive member including forming a photosensitive layer on the substrate; and forming a thin film transistor after forming the photosensitive member.
  • forming the photosensitive member further includes forming a first electrode before forming the photosensitive layer and forming a second electrode after forming the photosensitive layer;
  • forming the thin film transistor further includes forming an active layer and forming an interlayer insulating layer, the active layer being on the substrate The upper orthographic projection falls within the orthographic projection of the first electrode on the base substrate; the method further comprises: forming a buffer layer after forming the photosensitive member and forming the active layer; forming a layer penetrating the interlayer insulating layer and the buffer layer a via hole and a second via hole; forming a conductive film; and patterning the conductive film to form a conductive layer and a source and a drain of the thin film transistor, the source and the drain are respectively electrically connected to the active layer, the source and the drain
  • One of the first vias is electrically connected to the first electrode through a first via, and the conductive layer is electrically connected to the second electrode.
  • the first via and the second via are formed in the same patterning process, and the source, drain, and conductive layers are formed in the same patterning process.
  • FIG. 3C is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure. Referring to FIG. 3C, the method for fabricating the array substrate includes the following steps.
  • Step 100 forming a photosensitive member on the base substrate, the photosensitive member comprising a first electrode, a photosensitive layer and a second electrode which are sequentially stacked, the first electrode being closer to the substrate than the second electrode.
  • the first electrode may extend below the TFT to serve as a light shielding layer of the active layer of the TFT.
  • the forming process of the first electrode 31 may also include forming a first electrode film layer, and patterning the first electrode film layer to form the first electrode 31.
  • the forming process of the photosensitive member includes: first forming a first electrode 31 having a light shielding effect on the base substrate 1, and forming a PIN film layer by about 1 ⁇ m on the first electrode 31 of the light shielding by a chemical vapor deposition process, and then on the PIN film.
  • a transparent conductive second electrode layer is formed on the layer by sputtering, and then a pattern of the photosensitive layer 32 and the second electrode 33 of the photosensitive member 3 is formed by a wet etching process.
  • step 200 a thin film transistor 5 and a conductive layer 6 are formed on the photosensitive member.
  • the first electrode 31 is electrically connected to one of the drain 501 or the source 502 of the thin film transistor 5, and the second electrode 33 is electrically connected to the conductive layer 6.
  • the formation process of the thin film transistor 5 and the conductive layer 6 is performed, and the conductive layer 6 may be disposed in the same layer as the source/drain layer 55 of the thin film transistor 5 (as shown in FIG. 2A).
  • a buffer film layer is formed by chemical vapor deposition, and the material of the buffer film layer may be SiOx or SiNx. Then, an active thin film layer is formed and patterned to form a semiconductor pattern. Forming a gate insulating film layer and a gate film, and then performing a patterning process on the gate insulating film layer and the gate film to form a gate insulating layer 52 and a gate electrode 53.
  • the material of the gate insulating film layer may be SiOx
  • the gate film can be any metal material with good conductivity. Then, a region of the active layer 51 that is not covered by the gate electrode 53 and the gate insulating layer 52 is conductorized.
  • an interlayer insulating film is formed, and the material of the interlayer insulating film may be SiOx.
  • the interlayer insulating film is patterned to form a first via hole V01, a second via hole V02, a third via hole V03, and a fourth via hole V04, and the first via hole V01 and the second via hole V02 penetrate the gate
  • the thin film and the interlayer insulating film, the third via hole V03 and the fourth via hole V04 penetrate the interlayer insulating film.
  • a conductive material layer is formed and patterned to form the source drain layer 55 and the conductive layer 6, complete electrical connection between the source 502 and the active layer 51, electrical connection between the drain 501 and the active layer 51,
  • the first electrode 31 is electrically connected to the drain 501 of the thin film transistor 5, and the second electrode 33 is electrically connected to the conductive layer 6.
  • a subsequent passivation layer 7 can be formed to protect the thin film transistor 5. After this step, a structure as shown in FIG. 2A can be formed.
  • 4A-4K are schematic diagrams showing a method of fabricating an array substrate according to an embodiment of the present disclosure. A method for fabricating an array substrate according to an embodiment of the present disclosure will be described below with reference to FIGS. 4A-4K.
  • a first electrode 31 is formed on the base substrate 1.
  • a photosensitive film 320 and a second electrode film 330 are formed on the first electrode 31.
  • the photosensitive film 320 and the second electrode film 330 are patterned to form a photosensitive layer 32 and a second electrode 33.
  • a buffer film layer 40 is formed on the photosensitive layer 32 and the second electrode 33.
  • an active thin film layer 510 is formed on the buffer film layer 40.
  • the active thin film layer 510 is patterned to form the active layer 51.
  • a gate insulating layer 52 and a gate electrode 53 are formed on the active layer 51, and a region conductor of the active layer 51 not covered by the gate electrode 53 and the gate insulating layer 52 is formed by a self-alignment process. Chemical.
  • an interlayer insulating film 540 is formed on the gate insulating layer 52 and the gate electrode 53.
  • the interlayer insulating film 540 and the buffer film layer 40 are patterned to form a first via hole V01 and a second via hole V02, and the interlayer insulating film 540 is patterned to form a third via hole. V03 and fourth via V04.
  • a conductive material layer 56 is formed.
  • the conductive material layer 56 is patterned to form a source 502, a drain 501, and a conductive layer 6.
  • the drain 501 and the source 502 are electrically connected to the active layer 51 through the third via V03 and the fourth via V04, respectively, and the conductive layer 6 is electrically connected to the second electrode 33 through the second via V02.
  • the drain 501 is electrically connected to the first electrode 31 through the first via hole V01.
  • a passivation layer 7 is formed on the structure shown in FIG. 4K to obtain an array substrate having the structure shown in FIG. 2A.
  • the active layer 51 includes a channel region 510, a source region 512, and a drain region 511.
  • first via hole V01, the second via hole V02, the third via hole V03, and the fourth via hole V04 are formed in the same patterning process, but are not limited thereto.
  • the photosensitive member 3 is formed first, and then the thin film transistor 5 is formed on the photosensitive member 3.
  • the hydrogen element is prevented from affecting the thin film transistor 5 during the formation of the photosensitive member 3.
  • the source/drain layer pattern of the thin film transistor 5 can be It is formed by a single patterning process, which simplifies the manufacturing process.
  • the embodiment of the present disclosure further provides a display panel including the array substrate of the above embodiment.
  • An embodiment of the present disclosure further provides a display device including the display panel of any of the above embodiments.
  • the display device may be any product or component having a display function such as a mobile phone, a watch, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic paper, or the like.
  • a display function such as a mobile phone, a watch, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic paper, or the like.

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Abstract

提供一种阵列基板及其制作方法、显示面板和显示装置。该阵列基板包括：位于衬底基板(1)上的光敏部件(3)以及薄膜晶体管(5)，光敏部件(3)包括光敏层(32)；薄膜晶体管(5)位于光敏部件(3)远离衬底基板(1)的一侧。该阵列基板中，先形成光敏部件，再在光敏部件上形成薄膜晶体管，避免了光敏部件形成过程中氢元素对薄膜晶体管产生影响，薄膜晶体管的源漏层图案可以通过一次图形化处理形成，简化了制作工艺。

Description

阵列基板及其制作方法、显示面板和显示装置
相关申请的交叉引用
本专利申请要求于2018年4月12日递交的中国专利申请第201810327453.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板及其制作方法、显示面板和显示装置。
背景技术
目前，大尺寸的显示面板向高可靠性、高分辨率、高色域等方向发展，对背板制作工艺的要求也不断提高。
发明内容
本公开的实施例提供一种阵列基板及其制作方法、显示面板、显示装置，以解决阵列基板制作中，形成源漏层图案工艺复杂的问题。
本公开的至少一实施例提供一种阵列基板，包括：位于衬底基板上的光敏部件，所述光敏部件包括光敏层；以及薄膜晶体管，所述薄膜晶体管位于所述光敏部件远离所述衬底基板的一侧。
在本公开的一个或多个实施例中，所述光敏部件还包括第一电极和第二电极，所述第一电极、所述光敏层和所述第二电极层叠设置，并且所述第一电极比所述第二电极更靠近所述衬底基板；所述薄膜晶体管包括有源层，所述有源层的材料包括半导体；所述第一电极为遮光层，所述第一电极在所述衬底基板上的正投影完全覆盖所述有源层在所述衬底基板上的正投影。
在本公开的一个或多个实施例中，所述第二电极位于所述衬底基板和所述有源层之间。
在本公开的一个或多个实施例中，所述薄膜晶体管还包括源漏层，所述源漏层包括源极和漏极，所述源极和所述漏极分别与所述有源层电连接；所述源极和所述漏极在所述衬底基板上的正投影落入所述第一电极在所述衬底 基板上的正投影内。
在本公开的一个或多个实施例中，所述第一电极和所述源漏层分别位于不同的层，所述源极和所述漏极之一与所述第一电极电连接。
在本公开的一个或多个实施例中，所述源极和所述漏极之一与所述第一电极接触。
在本公开的一个或多个实施例中，阵列基板还包括导电层，所述导电层与所述第二电极电连接，所述导电层与所述源漏层位于同一层。
在本公开的一个或多个实施例中，阵列基板还包括层间绝缘层，所述层间绝缘层位于所述光敏部件的远离所述衬底基板的一侧，并且位于所述源极和所述漏极之间；所述导电层和所述源漏层与所述层间绝缘层的远离所述衬底基板的表面接触。
在本公开的一个或多个实施例中，阵列基板还包括位于所述有源层远离所述衬底基板一侧的依次设置的栅极绝缘层和栅极，所述栅极绝缘层和所述栅极在所述衬底基板上的正投影落入所述有源层在所述衬底基板上的正投影内。
在本公开的一个或多个实施例中，阵列基板还包括位于所述光敏部件和所述薄膜晶体管之间的缓冲层，所述源极或所述漏极通过贯穿所述缓冲层和所述层间绝缘层的第一过孔电连接，所述导电层通过贯穿所述缓冲层和所述层间绝缘层的第二过孔电连接。
在本公开的一个或多个实施例中，所述光敏层的材料包括PIN型半导体材料。
本公开的至少一实施例还提供一种显示面板，包括上述任一阵列基板。
本公开的至少一实施例还提供一种显示装置，包括上述任一显示面板。
本公开的至少一实施例还提供一种阵列基板的制作方法，包括：在衬底基板上形成光敏部件，形成所述光敏部件包括形成光敏层；以及形成薄膜晶体管，所述薄膜晶体管位于所述光敏部件远离所述衬底基板的一侧。
本公开的至少一实施例还提供一种阵列基板的制作方法，包括：形成光敏部件，形成所述光敏部件包括在衬底基板上形成光敏层；以及在形成所述光敏部件后，形成薄膜晶体管。
在本公开的一个或多个实施例中，形成所述光敏部件还包括在形成所述 光敏层之前形成第一电极以及在形成所述光敏层之后形成第二电极；形成所述薄膜晶体管还包括形成有源层和形成层间绝缘层，所述有源层在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影内；所述方法还包括：在形成所述光敏部件后以及形成所述有源层之前，形成缓冲层；形成贯穿所述层间绝缘层和所述缓冲层的第一过孔和第二过孔；形成导电薄膜；以及对所述导电薄膜进行构图形成导电层以及所述薄膜晶体管的源极和漏极，所述源极和漏极分别与所述有源层电连接，所述源极和漏极之一通过所述第一过孔与所述第一电极电连接，所述导电层与所述第二电极电连接。
在本公开的一个或多个实施例中，所述第一过孔和所述第二过孔在同一次构图工艺中形成，所述源极、漏极和所述导电层在同一次构图工艺中形成。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的结构示意图；
图2A为本公开一实施例提供的阵列基板的结构示意图；
图2B为本公开另一实施例提供的阵列基板的结构示意图；
图3A为本公开一实施例提供的阵列基板的制作方法流程图；
图3B为本公开一实施例提供的阵列基板的制作方法流程图；
图3C为本公开一实施例提供的阵列基板的制作方法流程图；以及
图4A～4K为本公开一实施例提供的阵列基板的制作方法的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获取的所有其他实施例，都属于本公开保护的范围。
目前主要采用补偿技术来提升显示面板(panel)的显示质量，采用在显示面板中内置光学传感器进行补偿。例如，将具有光电流传感功能的光敏部 件(例如，PIN)结合一个作为开关的薄膜晶体管(thin film transistor，TFT)，可以检测实时光学变化，再通过外部电路对显示面板进行调控。
图1为一种阵列基板的结构示意图。在顶栅型阵列基板中，为了避免作为开关的TFT的沟道受到光照影响，如图1所示，在基底01之上设置有遮光层02。例如，遮光层02可以采用任何具有遮光作用的金属导电薄膜进行图案化形成。如图1所示，遮光层02上设有开关TFT001，TFT001上设有光敏部件09。TFT001包括源漏层08、半导体有源层012和栅极06，源漏层08包括源极081和漏极082。光敏部件09包括第一电极091、光敏层090和第二电极092。
如图1所示。光敏层090形成在源漏层08之上，由于在制作光敏部件09时，会产生大量氢元素，氢元素对TFT的电学性能影响较大，因此在制作工艺中要避免氢元素沉积到TFT001上，这就需要进行两次图形化工艺形成源漏层08的图形，即在形成栅极06和缓冲层07(ILD)图案后，形成源漏层08，需先对源漏层08进行第一次图形化处理，该次图形化处理保留TFT的栅极06之上的源漏层的金属，防止在之后形成光敏层090过程中氢元素对TFT001造成影响。在形成光敏层090后，再对源漏层08进行第二次图形化处理，将TFT的栅极06上方的源漏层金属刻蚀掉，形成完整的源漏层图形，之后再形成钝化层010(PVX)，在钝化层010上形成过孔，在过孔处通过金属层011将光敏部件09与显示面板的外部信号连接。
发明人发现，上述过程中，形成源漏层图案要采用两步图形化的工艺，制作工艺复杂，影响产品的良率。
图2A为本公开一实施例提供的阵列基板的结构示意图。如图2A所示，本公开一实施例提供的阵列基板，包括：位于衬底基板1上的光敏部件3以及薄膜晶体管5，光敏部件3包括光敏层32；薄膜晶体管5位于光敏部件3远离衬底基板1的一侧。
本公开一实施例提供的阵列基板，薄膜晶体管5位于光敏部件3远离衬底基板1的一侧，形成薄膜晶体管5之前形成光敏层32，避免形成光敏层32的过程中产生的氢元素对薄膜晶体管5产生影响，并且薄膜晶体管的源极和漏极所在的层可以采用一步图案化工艺完成，简化工艺步骤。
例如，如图2A所示，阵列基板还包括源漏层55和导电层6。例如，导 电层6与第二电极33电连接，导电层6与源漏层55位于同一层。源漏层55包括漏极501和源极502，源极502和漏极501分别与有源层51电连接，源极502和漏极501在衬底基板1上的正投影落入第一电极31在衬底基板1上的正投影内。
例如，如图2A所示，第一电极31和源漏层55分别位于不同的层。第一电极31与漏极501和源极502之一电连接。本公开的实施例中，漏极501和源极502可互换，本公开的实施例以漏极501与第一电极31电连接为例进行说明。
例如，如图2A所示，该光敏部件3包括层叠设置的第一电极31、光敏层32和第二电极33，第一电极31比第二电极33更靠近衬底基板1。第一电极31与薄膜晶体管5的漏极501电连接，第二电极33与导电层6电连接。
例如，如图2A所示，薄膜晶体管5包括有源层51，有源层51的材料包括半导体；第一电极31为遮光层，第一电极31在衬底基板1上的正投影完全覆盖有源层51在衬底基板1上的正投影。第一电极31同时起到遮光作用，避免照射到有源层51上的光对薄膜晶体管5造成影响。例如，如图2A所示，第二电极33位于衬底基板1和有源层51之间。
可以理解的是，上述光敏部件3的第一电极31与薄膜晶体管5的源极或漏极电连接，第二电极33与导电层6电连接，导电层6可以与阵列基板的外围电路电连接，将具有光电流传感功能的光敏部件3结合一个作为开关的薄膜晶体管5形成可检测实时光学变化，并通过导电层6与外围电路连接，对光敏部件3进行调控，通过该种补偿技术提升显示质量。
本公开实施例的阵列基板，在衬底基板1上设有光敏部件3，在光敏部件3上设有薄膜晶体管5和导电层6。光敏部件3包括层叠设置的第一电极31、光敏层32和第二电极33，第一电极31靠近衬底基板1设置，将光敏部件3的第一电极31与薄膜晶体管5的漏极501或源极502之一电连接，光敏部件3的第二电极33与导电层6电连接。在制作过程中，先形成光敏部件3，再在光敏部件3上形成薄膜晶体管5，避免了光敏部件5形成过程中氢元素对薄膜晶体管5产生影响，薄膜晶体管5的源漏层55的图案可以通过一次图形化处理形成，简化了制作工艺。
如图2A所示，薄膜晶体管5还包括位于有源层51远离衬底基板1一侧 的依次设置的栅极绝缘层52和栅极53，栅极绝缘层52和栅极53在衬底基板1上的正投影落入有源层51在衬底基板1上的正投影内。例如，栅极53的材料包括金属，栅极绝缘层52的材料包括绝缘材料。
例如，如图2A所示，以上述薄膜晶体管5为顶栅结构的薄膜晶体管为例进行说明，但可以理解的是，在底栅结构中，本公开的实施例的结构也同样适用。即，在本公开的另一实施例提供的阵列基板中，将图2A中的顶栅结构的TFT替换为底栅结构的TFT。
上述第一电极31可以延伸至有源层51的下方，作为遮光层34，即，遮光层34第一电极31一体形成。如图2A所示，第一电极31或遮光层34在衬底基板1上的正投影覆盖薄膜晶体管5的有源层51在衬底基板1上的正投影，可以防止薄膜晶体管5的沟道受到衬底基板1下方的光照的影响，避免劣化薄膜晶体管的电学特性。
如图2A所示，遮光层34位于有源层51的正下方，遮光层34第一电极31一体形成。第一电极31同时起到遮光与光敏器件的一个电极的作用，也即遮光层34可以作为光敏器件3的一个电极。在制作工艺中，简化了工艺步骤，可以在衬底基板上形成遮光的电极层，通过一次图形化处理即形成了一体的遮光层34和第一电极31。
在第一电极31上形成有光敏层32，光敏层32的材料可以采用光敏材料，可以为PIN型半导体材料，其厚度可以为1μm左右。例如，光敏层32可采用通常的方法制作。在光敏层32之上形成有第二电极33，第二电极33的材料可以为透明的导电层材料如氧化铟锡(ITO)等。
上述光敏部件3的第一电极31、光敏层32和第二电极33的形成工艺可以包括如下步骤。步骤1)、在衬底基板上形成具有遮光作用的第一电极层；步骤2)、在第一电极层上采用化学气相沉积的工艺形成PIN膜层1μm左右，步骤3)、在PIN膜层上溅射形成透明导电的第二电极层，之后采用先湿刻再干刻的工艺形成光敏部件3的图形。
在形成光敏部件3后，再在其上进行形成薄膜晶体管5，薄膜晶体管5的制作工艺可以参考通常工艺，在此不再赘述。
例如，导电层6与薄膜晶体管5的漏极501同层设置，也即导电层6与薄膜晶体管5的源漏层55同层设置，导电层6的材料可以与源漏层55的材 料相同，导电层6和源漏层55的材料例如包括金属或合金材料。该结构可以简化制作工艺，经一步图形化同时形成源漏层55的图案和导电层6的图案。导电层6用于与阵列基板的外围电路连接，以对光敏部件3进行调控。
可以理解的是，如图1所示的阵列基板，由于光敏部件位于薄膜晶体管的远离衬底基板的一侧，光敏部件的光敏层的形成过程中产生的氢元素会对薄膜晶体管的电学特性产生影响，因此在形成光敏部件之前未对源漏层完全图形化，源漏薄膜层的位于薄膜晶体管有源层上方的部分被保留，而当形成光敏部件的光敏层后，再对源漏薄膜层进行第二次图形化，形成完整的源漏层图案。而本申请中，如图2A所示的阵列基板中，由于光敏部件3形成在薄膜晶体管5之前，在后续形成薄膜晶体管5时，不用考虑氢元素会对其造成影响，仅需一次图形化处理，形成源漏层图案即可。因此，本申请制作工艺更加简单，简化了薄膜晶体管的形成步骤。
例如，如图2A所示，在第一电极31与薄膜晶体管5的漏极501之间，也即在第一电极31与源漏层55之间形成有层叠的缓冲层4和层间绝缘层54，缓冲层4比层间绝缘层54更靠近衬底基板1，缓冲层4和层间绝缘层54完全覆盖光敏部件3。
在缓冲层4中设置有过孔V1，在层间绝缘层54中设置有过孔V2，过孔V1和过孔V2构成第一过孔V01，薄膜晶体管5的漏极501通过第一过孔V01与第一电极31电连接，同样，也实现了薄膜晶体管5的漏极501与遮光层34电连接，可以提高薄膜晶体管的电学特性。可以理解的是，过孔V1与过孔V2可以在形成源漏层55之前通过曝光刻蚀工艺形成，在形成源漏薄膜层的同时，将薄膜晶体管5的漏极501通过源漏薄膜层的部分金属材料与第一电极31电连接。例如，过孔V1和过孔V2可在同一构图工艺中形成。
同样的，在缓冲层4中还设置有过孔V3，在层间绝缘层54中还设置有过孔V4，过孔V3和过孔V4构成第二过孔V02，导电层6通过第二过孔V02与第二电极33电连接。例如，过孔V3和过孔V4可在同一构图工艺中形成。为了进一步简化工艺，过孔V1、过孔V2、过孔V3和过孔V4可在同一构图工艺中形成。例如，第一过孔V01贯穿缓冲层4和层间绝缘层54，第二过孔V02贯穿缓冲层4和层间绝缘层54，第一过孔V01和第二过孔V02可在同一构图工艺中形成。
例如，如图2A所示，层间绝缘层54位于光敏部件3的远离衬底基板1的一侧，并且位于源极502和漏极501之间；导电层6和源漏层55与层间绝缘层54的远离衬底基板1的表面接触。
例如，如图2A所示，源极502或漏极501通过贯穿缓冲层4和层间绝缘层54的第一过孔V01电连接，导电层6通过贯穿缓冲层4和层间绝缘层54的第二过孔V02电连接。
例如，如图2A所示，阵列基板还包括钝化层7，以对源极502、漏极501和导电层6起到保护作用。钝化层7可采用绝缘材料制作。
本公开实施例提供的阵列基板中，薄膜晶体管5与光敏部件3的电连接以及光敏部件3与阵列基板的外围电路的电连接，可以通过位于缓冲层4与层间绝缘层54的过孔以及位于过孔中的部分导电源漏薄膜层的材料实现，仅需一次曝光刻蚀，即可形成这四个过孔，并实现电连接。而图1所示的阵列基板中，源漏层的漏极或源极同时作为光敏部件的一个电极，而光敏部件的另一个电极需要通过位于其上的过孔，再通过导电金属与外围电路连接，且遮光层与源漏层的电连接需要另外的过孔来实现，这两个过孔需在两次曝光刻蚀工艺中形成，显然，与图1所示的阵列基板的制作工艺相比，如图2A所示的阵列基板的制作工艺在整体设计上更加简便。
上述仅以薄膜晶体管5为顶栅结构进行说明，可以理解的是，在底栅结构中，同样，可以采用类似的上述结构，在形成光敏部件3后，再形成薄膜晶体管5和导电层6，将薄膜晶体管5的源极和漏极中的任意一个与光敏部件3的第一电极31电连接，导电层6与光敏部件3的第二电极33电连接。同样可以简化阵列基板薄膜晶体管的源漏层图案的图形化工艺，其具体的结构与上述实施例类似，在此不再赘述。
图2B为本公开另一实施例提供的阵列基板的结构示意图。与图2A所示的结构相比，漏极501通过连接电极521与第一电极31相连。
图3A为本公开一实施例提供的阵列基板的制作方法流程图。本公开的至少一实施例还提供一种阵列基板的制作方法，包括：在衬底基板上形成光敏部件，形成光敏部件包括形成光敏层；以及形成薄膜晶体管，薄膜晶体管位于光敏部件远离衬底基板的一侧。
图3B为本公开一实施例提供的阵列基板的制作方法流程图。本公开的 至少一实施例还提供一种阵列基板的制作方法，包括：形成光敏部件，形成光敏部件包括在衬底基板上形成光敏层；以及在形成光敏部件后，形成薄膜晶体管。
例如，形成光敏部件还包括在形成光敏层之前形成第一电极以及在形成光敏层之后形成第二电极；形成薄膜晶体管还包括形成有源层和形成层间绝缘层，有源层在衬底基板上的正投影落入第一电极在衬底基板上的正投影内；方法还包括：在形成光敏部件后以及形成有源层之前，形成缓冲层；形成贯穿层间绝缘层和缓冲层的第一过孔和第二过孔；形成导电薄膜；以及对导电薄膜进行构图形成导电层以及薄膜晶体管的源极和漏极，源极和漏极分别与有源层电连接，源极和漏极之一通过第一过孔与第一电极电连接，导电层与第二电极电连接。
例如，第一过孔和第二过孔在同一次构图工艺中形成，源极、漏极和导电层在同一次构图工艺中形成。
图3C为本公开一实施例提供的阵列基板的制作方法流程图。参照图3C所示，该阵列基板的制作方法包括如下步骤。
步骤100，在衬底基板上形成光敏部件，该光敏部件包括依次层叠设置的第一电极、光敏层和第二电极，第一电极比第二电极更靠近衬底基板。
该第一电极可以延伸至TFT的下方以作为TFT的有源层的遮光层。例如，第一电极31的形成过程也可以包括形成第一电极薄膜层，对第一电极薄膜层进行构图以形成第一电极31。
例如，光敏部件的形成过程包括：先在衬底基板1上形成具有遮光作用的第一电极31，在遮光的第一电极31上通过化学气相沉积工艺形成PIN膜层1μm左右，再在PIN膜层上以溅射方式形成透明导电的第二电极层，之后再采用先湿刻再干刻的工艺形成光敏部件3的光敏层32和第二电极33的图形。
步骤200，在光敏部件上形成薄膜晶体管5和导电层6，第一电极31与薄膜晶体管5的漏极501或源极502之一电连接，第二电极33与导电层6电连接。
例如，在完成步骤100之后，再进行薄膜晶体管5以及导电层6的形成工艺，导电层6可以与薄膜晶体管5的源漏层55(如图2A所示)同层设置。
例如，在完成步骤100后，再化学气相沉积形成缓冲薄膜层，缓冲薄膜层的材料可以为SiOx或者SiNx。然后，形成有源薄膜层，并对其进行图形化形成半导体图案。再形成栅极绝缘薄膜层以及栅极薄膜，之后再对栅极绝缘薄膜层以及栅极薄膜进行一次图形化工艺以形成栅极绝缘层52和栅极53，栅极绝缘薄膜层的材料可以为SiOx，栅极薄膜可以为任何导电性好的金属材料。然后，对有源层51的未被栅极53及栅极绝缘层52覆盖的区域导体化。之后形成层间绝缘薄膜，层间绝缘薄膜的材料可以为SiOx。之后，对层间绝缘薄膜进行图形化，形成第一过孔V01、第二过孔V02、第三过孔V03和第四过孔V04，第一过孔V01和第二过孔V02贯穿栅极薄膜和层间绝缘薄膜，第三过孔V03和第四过孔V04贯穿层间绝缘薄膜。过孔完成后，形成导电材料层，并图形化处理，形成源漏层55和导电层6，完成源极502与有源层51的电连接、漏极501与有源层51的电连接、第一电极31与薄膜晶体管5的漏极501的电连接，以及第二电极33与导电层6的电连接。完成上述步骤后，就可以形成后续的钝化层7，以对薄膜晶体管5进行保护，完成该步骤后，可形成如图2A所示的结构。
图4A～4K为本公开一实施例提供的阵列基板的制作方法的示意图。以下结合图4A～4K对本公开一实施例提供的阵列基板的制作方法进行描述。
如图4A所示，在衬底基板1上形成第一电极31。
如图4B所示，在第一电极31上形成光敏薄膜320和第二电极薄膜330。
如图4C所示，对光敏薄膜320和第二电极薄膜330进行构图，形成光敏层32和第二电极33。
如图4D所示，在光敏层32和第二电极33上形成缓冲薄膜层40。
如图4E所示，在缓冲薄膜层40上形成有源薄膜层510。
如图4F所示，对有源薄膜层510进行构图形成有源层51。
如图4G所示，在有源层51上形成栅极绝缘层52和栅极53，采用自对准工艺，对有源层51的未被栅极53及栅极绝缘层52覆盖的区域导体化。
如图4H所示，在栅极绝缘层52和栅极53上形成层间绝缘薄膜540。
如图4I所示，对层间绝缘薄膜540和缓冲薄膜层40进行图形化，形成第一过孔V01和第二过孔V02，并对层间绝缘薄膜540进行图形化，形成第三过孔V03和第四过孔V04。
如图4J所示，形成导电材料层56。
如图4K所示，对导电材料层56图形化，形成源极502、漏极501和导电层6。
如图4K所示，漏极501和源极502分别通过第三过孔V03和第四过孔V04与有源层51电连接，导电层6通过第二过孔V02与第二电极33电连接，漏极501通过第一过孔V01与第一电极31电连接。
在图4K所示的结构上形成钝化层7，即可得到如图2A所示结构的阵列基板。
如图4G所示，自对准工艺后，有源层51包括沟道区510、源极区512和漏极区511。
例如，第一过孔V01、第二过孔V02、第三过孔V03和第四过孔V04在同一个构图工艺中形成，但不限于此。
上述阵列基板的制作方法，先形成光敏部件3，再在光敏部件3上形成薄膜晶体管5，避免了光敏部件3形成过程中氢元素对薄膜晶体管5产生影响，薄膜晶体管5的源漏层图案可以通过一次图形化处理形成，简化了制作工艺。
本公开实施例还提供了一种显示面板，包括上述实施例的阵列基板。
本公开实施例还提供了一种显示装置，包括上述任一实施例的显示面板。
例如，显示装置可以为手机、手表、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (19)

  1. 一种阵列基板，包括：
    位于衬底基板上的光敏部件，所述光敏部件包括光敏层；以及
    薄膜晶体管，所述薄膜晶体管位于所述光敏部件远离所述衬底基板的一侧。
  2. 根据权利要求1所述的阵列基板，其中，所述光敏部件还包括第一电极和第二电极，所述第一电极、所述光敏层和所述第二电极层叠设置，并且所述第一电极比所述第二电极更靠近所述衬底基板；
    所述薄膜晶体管包括有源层，所述有源层的材料包括半导体；
    所述第一电极为遮光层，所述第一电极在所述衬底基板上的正投影完全覆盖所述有源层在所述衬底基板上的正投影。
  3. 根据权利要求2所述的阵列基板，其中，所述第二电极位于所述衬底基板和所述有源层之间。
  4. 根据权利要求2或3所述的阵列基板，其中，所述薄膜晶体管还包括源漏层，所述源漏层包括源极和漏极，所述源极和所述漏极分别与所述有源层电连接；
    所述源极和所述漏极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影内。
  5. 根据权利要求4所述的阵列基板，其中，所述第一电极和所述源漏层分别位于不同的层，所述源极和所述漏极之一与所述第一电极电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述源极和所述漏极之一与所述第一电极接触。
  7. 根据权利要求4-6任一项所述的阵列基板，还包括导电层，其中，所述导电层与所述第二电极电连接，所述导电层与所述源漏层位于同一层。
  8. 根据权利要求7所述的阵列基板，还包括层间绝缘层，其中，所述层间绝缘层位于所述光敏部件的远离所述衬底基板的一侧，并且位于所述源极和所述漏极之间；所述导电层和所述源漏层与所述层间绝缘层的远离所述衬底基板的表面接触。
  9. 根据权利要求8所述的阵列基板，还包括位于所述有源层远离所述衬底基板一侧的依次设置的栅极绝缘层和栅极，其中，所述栅极绝缘层和所述 栅极在所述衬底基板上的正投影落入所述有源层在所述衬底基板上的正投影内。
  10. 根据权利要求8或9所述的阵列基板，还包括位于所述光敏部件和所述薄膜晶体管之间的缓冲层，其中，所述源极或所述漏极通过贯穿所述缓冲层和所述层间绝缘层的第一过孔电连接，所述导电层通过贯穿所述缓冲层和所述层间绝缘层的第二过孔电连接。
  11. 根据权利要求1-10任一项所述的阵列基板，其中，所述光敏层的材料包括PIN型半导体材料。
  12. 一种显示面板，包括权利要求1-11任一项所述的阵列基板。
  13. 一种显示装置，包括权利要求12所述的显示面板。
  14. 一种阵列基板的制作方法，包括：
    在衬底基板上形成光敏部件，形成所述光敏部件包括形成光敏层；以及
    形成薄膜晶体管，所述薄膜晶体管位于所述光敏部件远离所述衬底基板的一侧。
  15. 根据权利要求14所述的制作方法，其中，形成所述光敏部件还包括在形成所述光敏层之前形成第一电极以及在形成所述光敏层之后形成第二电极；
    形成所述薄膜晶体管还包括形成有源层和形成层间绝缘层，所述有源层在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影内；
    所述方法还包括：
    在形成所述光敏部件后以及形成所述有源层之前，形成缓冲层；
    形成贯穿所述层间绝缘层和所述缓冲层的第一过孔和第二过孔；
    形成导电薄膜；以及
    对所述导电薄膜进行构图形成导电层以及所述薄膜晶体管的源极和漏极，所述源极和漏极分别与所述有源层电连接，所述源极和漏极之一通过所述第一过孔与所述第一电极电连接，所述导电层与所述第二电极电连接。
  16. 根据权利要求15所述的制作方法，其中，所述第一过孔和所述第二过孔在同一次构图工艺中形成，所述源极、漏极和所述导电层在同一次构图工艺中形成。
  17. 一种阵列基板的制作方法，包括：
    形成光敏部件，形成所述光敏部件包括在衬底基板上形成光敏层；以及
    在形成所述光敏部件后，形成薄膜晶体管。
  18. 根据权利要求17所述的制作方法，其中，形成所述光敏部件还包括在形成所述光敏层之前形成第一电极以及在形成所述光敏层之后形成第二电极；
    形成所述薄膜晶体管还包括形成有源层和形成层间绝缘层，所述有源层在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影内；
    所述方法还包括：
    在形成所述光敏部件后以及形成所述有源层之前，形成缓冲层；
    形成贯穿所述层间绝缘层和所述缓冲层的第一过孔和第二过孔；
    形成导电薄膜；以及
    对所述导电薄膜进行构图形成导电层以及所述薄膜晶体管的源极和漏极，所述源极和漏极分别与所述有源层电连接，所述源极和漏极之一通过所述第一过孔与所述第一电极电连接，所述导电层与所述第二电极电连接。
  19. 根据权利要求18所述的制作方法，其中，所述第一过孔和所述第二过孔在同一次构图工艺中形成，所述源极、漏极和所述导电层在同一次构图工艺中形成。
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