WO2017028455A1 - 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 - Google Patents

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 Download PDF

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WO2017028455A1
WO2017028455A1 PCT/CN2015/099336 CN2015099336W WO2017028455A1 WO 2017028455 A1 WO2017028455 A1 WO 2017028455A1 CN 2015099336 W CN2015099336 W CN 2015099336W WO 2017028455 A1 WO2017028455 A1 WO 2017028455A1
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layer
active layer
drain
source
thin film
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PCT/CN2015/099336
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English (en)
French (fr)
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崔承镇
金宰弘
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京东方科技集团股份有限公司
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Priority to EP15901655.9A priority Critical patent/EP3340312B1/en
Priority to US15/518,973 priority patent/US10333002B2/en
Publication of WO2017028455A1 publication Critical patent/WO2017028455A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • At least one embodiment of the present invention is directed to a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device.
  • the display includes an array substrate on which thin film transistors arranged in a matrix are disposed, each of which functions as a switch for connecting data lines and pixels, and the on and off times are controlled by the gate lines.
  • the array substrate in the liquid crystal display includes a plurality of gate lines and a plurality of data lines intersecting vertically and horizontally, and the gate lines and the data lines define a plurality of pixels, for example, each of the pixels includes a thin film transistor and a pixel electrode.
  • the gate of the thin film transistor is electrically connected to the gate line
  • the source of the thin film transistor is electrically connected to the data line
  • the drain of the thin film transistor is electrically connected to the pixel electrode.
  • the etch barrier metal oxide thin film transistor is a common metal oxide thin film transistor, and the fabrication process is simple, and the etch barrier formed on the metal oxide active layer can be formed in the process of forming the source/drain electrodes.
  • the protective metal oxide active layer is not damaged, thereby improving the performance of the metal oxide thin film transistor.
  • the metal oxide thin film transistor may include a bottom gate structure and a top gate structure according to a positional relationship between the gate electrode and the active layer, that is, in the bottom gate structure, the gate is located under the metal oxide active layer, and the top gate structure The gate is located above the metal oxide active layer. Further, in the top gate structure, in order to prevent the metal oxide active layer from being received, a light shielding metal layer is further disposed under the metal oxide active layer.
  • At least one embodiment of the present invention provides a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device to minimize electrostatic discharge at a position of an active layer to be electrically connected to a source/drain ESD damage caused by (ESD).
  • ESD source/drain ESD damage caused by
  • At least one embodiment of the present invention provides a thin film transistor including: an active layer; an etch stop layer disposed on the active layer; a cap layer disposed on the etch stop layer,
  • the cover layer includes at least one of a conductive material layer, an opaque insulating layer, and an opaque semiconductor layer; and a source and a drain disposed on the cap layer, the source and the drain Electrically connected to the active layer.
  • At least one embodiment of the present invention also provides an array substrate including the above thin film transistor.
  • At least one embodiment of the present invention also provides a display device including the above array substrate.
  • At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, the method comprising: forming an active layer; forming an etch barrier layer, the etch stop layer being formed on the active layer; forming a cover a layer, the cap layer is formed on the etch barrier layer and includes at least one of a conductive material layer, an opaque insulating layer, and an opaque semiconductor layer; and a source and a drain are formed, A source and the drain are formed on the cap layer and are electrically connected to the active layer.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, the array substrate comprising a thin film transistor fabricated by the above method.
  • 1a is a schematic cross-sectional view of a metal oxide thin film transistor of a bottom gate structure
  • FIG. 1b is a schematic view showing exposure processing when the etch barrier layer of the thin film transistor shown in FIG. 1a is formed;
  • FIG. 1c is a schematic view showing the occurrence of electrostatic discharge during the exposure process of patterning the etch barrier film
  • FIG. 2a is a cross-sectional view of a thin film transistor according to Embodiment 1 of the present invention.
  • FIG. 2b is a cross-sectional view of still another thin film transistor according to Embodiment 1 of the present invention.
  • FIG. 2c is a cross-sectional view of another thin film transistor according to Embodiment 1 of the present invention.
  • 3a is a cross-sectional view of a thin film transistor according to a second embodiment of the present invention.
  • 3b is a cross-sectional view of still another thin film transistor according to Embodiment 2 of the present invention.
  • 3c is a cross-sectional view of another thin film transistor according to Embodiment 2 of the present invention.
  • FIG. 4a to 4f are diagrams for fabricating a thin film transistor as shown in FIG. 2a according to a third embodiment of the present invention. Schematic diagram of each step;
  • 5a to 5f are schematic views showing the steps of fabricating the thin film transistor shown in Figs. 2b and 2c according to the third embodiment of the present invention.
  • the thin film transistor includes a gate electrode 01, a gate insulating layer 02 disposed on the gate electrode 01, a metal oxide (eg, indium gallium zinc oxide) active layer 03 disposed on the gate insulating layer 02, and a setting
  • the etch stop layer 04 on the metal oxide active layer 03 and the source 05a and the drain 05b disposed on the etch stop layer 04, the source 05a and the drain 05b pass through the etch barrier layer 04, respectively.
  • the hole 04a and the via 04b are electrically connected to the active layer 03.
  • the manufacturing method of the thin film transistor shown in FIG. 1a includes the following steps S01 to S05, which are described in detail below.
  • Step S01 depositing a gate metal layer film, and forming a gate electrode 01 by one patterning process.
  • Step S02 depositing a gate insulating film on the gate electrode 01, and forming a gate insulating layer 02 and a via hole (not shown in FIG. 1a) in the gate insulating layer 02 by one patterning process.
  • Step S03 depositing a metal oxide thin film on the gate insulating layer 02, and forming the metal oxide active layer 03 by one patterning process.
  • Step S04 depositing an etch barrier film on the metal oxide active layer 03, and forming an etch barrier layer 04 and via holes 04a and via holes 04b in the etch barrier layer 04 by one patterning process.
  • Step S05 depositing a source/drain metal layer film on the etch barrier layer 04, and forming a source electrode 05a and a drain electrode 05b by one patterning process, so that the source electrode 05a and the drain electrode 05b pass through the via hole 04a and the via hole 04b, respectively.
  • the metal oxide active layer 03 is electrically connected.
  • step S04 patterning the etch barrier film generally includes: performing photolithography on the etch barrier film 04' as shown in FIG. 1b.
  • the glue 07 is exposed, and the exposure position corresponds to the positions 04a' and 04b' of the etch barrier film 04' to be formed with the via hole 04a and the via hole 04b (shown by a broken line in FIG. 1b); thereafter, by development, etching
  • the treatment is performed to form the etch barrier layer 04 and the via holes 04a and the via holes 04b in the etch barrier layer 04.
  • the etch barrier film 04' is usually made of a material such as silicon oxide, when the photoresist 07 is exposed, light can be transmitted through the etch barrier film 04' onto the metal oxide active layer 03, which results in The probability of occurrence of electrostatic discharge (referred to as ESD, as shown in FIG. 1c) at the position where the metal oxide active layer 03 is to be electrically connected to the source and the drain is greatly increased. This is because, during the exposure, the portion of the metal oxide active layer 03 to be electrically connected to the source and the drain (i.e., the first portion 03a and the second portion 03b, as indicated by the broken line in Fig.
  • ESD electrostatic discharge
  • the probability of light irradiation and conductorization is greatly increased, causing the metal oxide active layer 03 to easily generate a capacitance between the first portion 03a and the second portion 03b and the gate electrode 01, which can greatly increase the probability of occurrence of ESD.
  • the ESD easily causes a short circuit between the gate electrode 01 under the metal oxide active layer 03 and the source/drain electrodes 05a, 05b above the metal oxide active layer 03.
  • At least one embodiment of the present invention provides a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device.
  • a etch stop layer disposed on the active layer is provided with a cap layer including at least one of a conductive material layer, an opaque insulating layer, and an opaque semiconductor layer.
  • the ESD is generated even at the position of the active layer to be electrically connected to the source/drain, the conductive material
  • the material layer can also act as a dispersion current, thereby avoiding the occurrence of ESD at the position of the active layer to be electrically connected to the source/drain, thereby causing the metal layer under the active layer and the source and drain metal above the active layer.
  • an opaque insulating layer or an opaque semiconductor layer can prevent a portion of the active layer to be electrically connected to the source/drain from being irradiated by light to be conductorized, thereby reducing the active layer The probability of ESD occurring at a position to be electrically connected to the source/drain, thereby avoiding a short circuit between the metal layer under the active layer and the source/drain metal layer above the active layer.
  • the present embodiment provides a thin film transistor, as shown in FIG. 2a to FIG. 2c, the thin film transistor includes: an active layer 30; an etch stop layer 40 disposed on the active layer 30; and an etch stop layer 40 a cover layer 60 on the upper side (ie, disposed on a side of the etch stop layer 40 away from the active layer 30); and disposed on the cover layer 60 (ie, disposed on a side of the cover layer 60 away from the etch stop layer 40)
  • the source 50a and the drain 50b, and the source 50a and the drain 50b are electrically connected to the active layer 30.
  • the cover layer 60 comprises a layer of electrically conductive material, ie the material of the cover layer 60 comprises a conductive material.
  • the cap layer 60 can disperse the current, thereby Reduce ESD damage.
  • the layer of conductive material can be broken at the location of the channel region 33 of the active layer 30. Since the cap layer 60 includes a conductive material layer, by disconnecting the conductive material layer at the position of the channel region 33 of the active layer 30, the source electrode 50a and the drain electrode 50b can be prevented from being electrically connected together through the conductive material layer, thereby The active layer 30 is formed into a channel region 33.
  • 2a to 2c illustrate the case where the cover layer 60 is a conductive material layer. As shown in FIGS. 2a to 2c, the cap layer 60 is broken at the position where the channel region 33 of the active layer 30 is located.
  • this embodiment can also adopt other methods commonly used in the art to form the active region 30 into the channel region 33.
  • the material of the layer of electrically conductive material included in the cover layer 60 can comprise a metal or a conductive metal oxide.
  • the metal may include at least one or more of metals such as aluminum, copper, zirconium, molybdenum, and titanium.
  • the conductive metal oxide may include at least one or more of conductive metal oxides such as indium gallium zinc oxide, indium tin oxide, and indium zinc oxide.
  • the conductive layer included in the cover layer may also be made of other conductive materials.
  • the metal layer when the material of the conductive material layer includes a metal, that is, when the conductive material layer includes a metal layer, the metal layer may have a thickness of 300 to 1000 angstroms. This can be achieved by exposing the overlay In the process, light is prevented from being irradiated onto the active layer by the metal layer, so that the probability of occurrence of ESD at the position of the active layer to be electrically connected to the source and the drain can be further reduced.
  • the conductive material layer may be formed by a single patterning process with the source and the drain, and during the patterning process, the conductive material layer may be formed and formed.
  • the source and drain metal/drain film of the source and drain are simultaneously etched, or the conductive material layer is etched with the source and drain as masks, which saves the process and the mask.
  • the edge of the conductive material layer at the position of the channel region of the active layer may be adjacent to the source-facing drain-side edge and the drain-facing source in a direction perpendicular to the cap layer. The edges of the pole sides are roughly aligned.
  • the cover layer 60 is a layer of conductive material.
  • the edge 63 of the cover layer 60 at the channel region 33 of the active layer 30 can be sourced with the source.
  • the edge 51 of the 50a side facing the drain 50b is substantially aligned, and the edge 64 may be substantially aligned with the edge 52 of the drain 50b facing the source 50a side.
  • the cap layer 60 may include a first portion 61 between the source 50a and the etch stop layer 40 and a second portion 62 between the drain 50b and the etch stop layer 40, the first portion 61 and the second portion
  • the portion 62 is located between the positions of the active layer 30 electrically connected to the source 50a and the drain 50b, and the distance between the first portion 61 and the second portion 62 is equal to the distance between the source 50a and the drain 50b. . Since the edge of the pattern formed when the film is patterned is not necessarily perpendicular to the face on which the pattern is located, "equal" herein may mean “substantially equal.”
  • the source 50a and the drain 50b may be electrically connected to the active layer 30 through vias, respectively, as shown in FIG. 2a, the source 50a may pass through the first via 1 of the etch barrier 40.
  • the active layer 30 is electrically connected, and the drain 50b may be electrically connected to the active layer 30 through the second via 2 penetrating the etch barrier layer 40.
  • the source 50a and the drain 50b may also be electrically connected to the active layer 30 without via holes.
  • the orthographic projection of the etch stop layer 40 on the surface of the active layer 30 may be located in the region where the active layer 30 is located, and the active layer 30 has an extension to the etch barrier.
  • the first portion 31 and the second portion 32 outside the two side edges 41, 42 of the layer 40, both the first portion 31 and the second portion 32 are located outside the orthographic projection of the etch stop layer 40, and the source 50a is electrically connected to the first portion 31, the drain 50b is electrically connected to the second portion 32.
  • a metal structure 80, metal structure 80 is disposed under active layer 30
  • An insulating layer 90 is disposed between the active layer 30 and the portions of the active layer 30 electrically connected to the source 50a and the drain 50b, respectively, and the metal structure 80 is perpendicular to the plane of the metal structure 80. overlap.
  • the orthographic projections of the first via 1 and the second via 2 on the face of the metal structure 80 overlap the metal structure 80.
  • the thin film transistor further includes a gate 10, as shown in FIGS. 2a and 2b, the gate 10 may be under the active layer 30, that is, the thin film transistor may be a bottom gate structure, in which case The gate electrode 10 can serve as the metal structure 80 described above, and the gate insulating layer 20 can serve as the insulating layer 90.
  • the thin film transistor provided in this embodiment may also be a top gate structure.
  • the gate 10 may be located above the active layer 30.
  • a metal structure 80 may be disposed under the active layer 30, and the metal structure 80 may be a light shielding metal layer for preventing the thin film transistor.
  • the active layer 30 is exposed to light.
  • the present embodiment is particularly applicable to a thin film transistor in which the material of the active layer 30 includes a metal oxide material.
  • the active layer 30 may also employ other materials that are susceptible to a more severe ESD phenomenon in the case where light is received at a position where the source layer and the drain of the active layer 30 are electrically connected.
  • the material of the active layer includes a metal oxide
  • the material of the insulating layer in contact with the active layer may include silicon oxide, for example, the etch stop layer 40 and the gate insulating in FIGS. 2a and 2b.
  • Layer 20, etch stop layer 40 and insulating layer 90 of Figure 2c may be fabricated using a silicon oxide material.
  • the insulating layer in contact with the active layer may also be made of other materials commonly used in the art.
  • the thin film transistor provided in this embodiment is different from the thin film transistor provided in the first embodiment in that the cover layer 60 is an opaque insulating layer, that is, the cover layer 60 is made of an opaque insulating material, as shown in FIG. 3a to FIG. 3c. Shown.
  • the cap layer 60 is an insulating layer, it is located in the channel region (not shown) of the active layer 30.
  • the place can be continuous. That is, the cap layer 60 can form the channel region of the active layer 30 without being disconnected.
  • the opaque insulating layer may be a black resin material. Of course, it can also be other opaque insulating materials commonly used in the art.
  • the first embodiment and the second embodiment are respectively described by taking a cover layer as a conductive material layer and an opaque insulating layer as an example.
  • the cover layer is an opaque semiconductor layer
  • the opaque semiconductor layer may be made of materials commonly used in the art, such as silicon or other materials.
  • those skilled in the art can set the thickness of the opaque semiconductor layer as needed, as long as it is opaque.
  • the cover layer of the opaque semiconductor layer may be disposed in the thin film transistor and the cover layer in the thin film transistor provided in the first embodiment.
  • the setting method is similar, and will not be described here.
  • the present embodiment provides a method for fabricating a thin film transistor, the method comprising: forming an active layer; forming an etch stop layer, The etch stop layer is formed on the active layer; forming a cap layer formed on the etch barrier layer and including a conductive material layer; and forming a source and a drain, the source and the drain being formed in the cover The layer is electrically connected to the active layer.
  • forming the etch barrier layer and the cap layer may include the following steps S31 to S35, which are described in detail below.
  • Step S31 forming an etch barrier film, so that an etch barrier film is formed on the active layer.
  • the etch barrier film may be a patterned film.
  • the etch barrier film may be formed together with the active layer in a single patterning process, that is, a film layer of an active layer material (eg, a conductive metal oxide material) and an etch stop thereon may be formed. The film layer of the layer material is then simultaneously patterned to form the active layer and the etch stop film described above.
  • an active layer material eg, a conductive metal oxide material
  • the etch barrier film may also be a film that has not been patterned. That is, a film layer of an etch barrier material may be formed over the active layer as an etch barrier film after the active layer is formed.
  • Step S32 forming a cover film on the etch barrier film.
  • a cover film The material may comprise a metal or a conductive metal oxide.
  • Step S33 forming a photoresist film on the cover film, and exposing and developing the photoresist film to form a photoresist pattern.
  • Step S34 etching the cover film by using the photoresist pattern formed in step S33 as a mask to form a cover layer pattern.
  • Step S35 etching the etch barrier film by using the photoresist pattern formed in step S33 or the overlying layer pattern formed in step S34 as a mask to form an etch barrier layer.
  • the source and drain can be electrically connected to the active layer through vias in the etch barrier, respectively.
  • the forming the cap layer pattern in step S34 further includes: forming a first cap layer via and a second cap via in the cap layer pattern; forming an etch barrier layer in step S35 The method includes forming a first etch stop via via corresponding to the first cap via in the etch barrier and a second etch barrier via corresponding to the second cap via.
  • the first cap layer via and the first etch stop via form a first via
  • the second overlayer via and the second etch stop via constitute a second via
  • the source passes through the first via
  • the hole is electrically connected to the active layer
  • the drain is electrically connected to the active layer through the second via.
  • the source and drain may also be electrically connected to the active layer without vias.
  • the orthographic projection of the cover layer pattern on the surface of the active layer may be located within the region where the active layer is located; in step S35, etching is formed.
  • the barrier layer may have an orthographic projection of the etch stop layer on the surface of the active layer in a region where the active layer is located, and the active layer has a first portion and a portion other than the two side edges of the etch barrier layer Two parts.
  • the source may be electrically connected to the first portion of the active layer and the drain may be electrically connected to the second portion of the active layer.
  • a plurality of via holes are formed in the photoresist pattern or the orthographic projection of the photoresist pattern on the surface of the active layer is located.
  • the region of the active layer is located such that the overlay pattern formed in step S34 also has a via or orthographic projection within the region of the active layer.
  • the cover layer, the source and the drain may include steps S361 to S363, for example, the cover layer includes a conductive material layer. Introduction.
  • Step S361 forming a source/drain metal layer on the cover layer pattern after forming the etch barrier layer membrane.
  • Step S362 patterning the source/drain metal layer film to form a source and a drain.
  • Step S363 etching the cap layer pattern to break the cap layer pattern at a position between the source and the drain. It should be noted that the step S363 may also be performed in the same patterning process as described above with the step S362.
  • the manufacturing method provided by at least one example of the embodiment may include the following steps S41 to S45, which are described in detail below.
  • Step S41 The active layer 30 is formed as shown in FIG. 4a.
  • a thin film of an active layer material may be formed first, and then the thin film is patterned to form the active layer 30.
  • Step S42 forming an etch barrier film 40', and an etch barrier film 40' is formed on the active layer 30 as shown in FIG. 4a.
  • FIG. 4a is described by taking an example in which the etch barrier film 40' is formed after the active layer 30 is formed.
  • the etch barrier film 40' is substantially aligned with the edge of the active layer 30.
  • Step S43 forming a cover film 60' on the etch barrier film 40', as shown in FIG. 4a; patterning the cover film 60' to form a cover layer pattern 60" and a cover layer pattern 60"
  • the first cover layer via 60a and the second cover layer via 60b are as shown in FIG. 4c.
  • patterning the cover film 60' includes: forming a photoresist film 70' on the cover film 60', and exposing the photoresist film 70' to an exposure position corresponding to the active layer 30. a portion electrically connected to the source and the drain, as shown in FIG. 4a; thereafter, developing treatment is performed to remove the photoresist irradiated with light, thereby obtaining a photoresist pattern 70" and a plurality of photoresists located therein Via, as shown in FIG. 4b; thereafter, the cover film 60' is etched using the photoresist pattern 70" as a mask to form a capping layer pattern 60" and via holes 60a and 60b therein, as shown in FIG. 4c Shown.
  • Step S44 etching the etch barrier film 40 ′ by using the photoresist pattern 70 ′′ or the cap layer pattern 60 ′′ formed in the step S43 as a mask to form the etch barrier layer 40 and the etch barrier layer.
  • the barrier via 40a constitutes a first via 1, and the second cladding via 60b and the second etch barrier via 40b form a second via 2, as shown in Figure 4d.
  • the photoresist pattern 70" on the cap layer pattern 60" can be removed, as shown in FIG. 4e.
  • Step S45 forming a source/drain metal layer film 50' on the cap layer pattern 60", so that the source/drain metal layer film 50' covers the first via hole 1 and the second via hole 2, as shown in FIG. 4f;
  • the layer film 50' and the capping layer pattern 60" are subjected to a patterning process to form a source electrode 50a, a drain electrode 50b, and a capping layer 60.
  • the source electrode 50a is electrically connected to the active layer 30 through the first via hole 1, and the drain electrode 50b passes through
  • the second via 2 is electrically connected to the active layer 30, and the cap layer 60 is broken at the position of the channel region 33 of the active layer 30, as shown in Fig. 2a.
  • the manufacturing method provided by at least one example of the embodiment includes, for example, the following steps S51 to S55, which are described in detail below.
  • Step S51 The active layer 30 is formed as shown in FIG. 5a.
  • Step S52 forming an etch stop film 40' on the active layer 30, as shown in Fig. 5a.
  • Step S53 forming a cover film 60' on the etch barrier film 40', and patterning the cover film 60' to form a cover layer pattern 60" on the surface of the active layer
  • the orthographic projection is located within the area where the active layer 30 is located, as shown in Figure 5c.
  • patterning the cover film 60' includes: forming a photoresist film 70' on the cover film 60', and exposing the photoresist film 70' to a non-exposure position corresponding to the active layer 30.
  • the portion to be formed into the channel region, the rest is the exposure position, as shown in FIG. 5a; after that, development processing is performed to remove the photoresist irradiated with light, thereby obtaining a photoresist pattern 70", a photoresist pattern 70"
  • the orthographic projection on the surface of the active layer 30 is located in the region where the active layer 30 is located, as shown in FIG. 5b; thereafter, the cover film 60' is etched by using the photoresist pattern 70" as a mask to A cover layer pattern 60" is formed as shown in Figure 5c.
  • Step S54 etching the etch barrier film 40 ′ by using the photoresist pattern 70 ′′ or the cap layer pattern 60 ′′ formed in step S53 as a mask to form an etch barrier layer 40 to form an etch barrier layer.
  • the orthographic projection on the face of the active layer 30 is located in the region where the active layer 30 is located, and the active layer 30 has the first portion 31 and the second portion 32 outside the orthographic projection of the etch stop layer 40, such as Figure 5d is shown.
  • the photoresist pattern 70" on the cap layer pattern 60" can be removed, as shown in FIG. 5e.
  • Step S55 forming a source/drain metal layer film 50' on the cap layer pattern 60", as shown in FIG. 5f; patterning the source/drain metal layer film 50' and the cap layer pattern 60" to form a source 50a, a drain The pole 50b and the cover layer 60, the source 50a is connected to the active layer 30 through the first portion 31 of the active layer 30, and the drain 50b is electrically connected to the active layer 30 through the second portion 32 of the active layer 30, the cover layer 60 Disconnected at the location of the channel region 33 of the active layer 30, as shown in Figures 2b and 2c.
  • the method further includes: forming a gate electrode 10 and a gate insulating layer over the gate electrode 10 before forming the active layer 30.
  • Layer 20 A thin film transistor for a top gate structure, such as the thin film transistor shown in FIG. 2c, further comprising: forming a metal structure 80 and an insulating layer 90 over the metal structure 80 before forming the active layer 30; After the source 50a, the drain 50b, and the cap layer 60, a gate insulating layer 20 and a gate electrode 10 on the gate insulating layer 20 are formed on the source 50a and the drain 50b.
  • the present embodiment provides another method for fabricating a thin film transistor, comprising: forming an active layer; forming an etch barrier layer; An etch stop layer is formed on the active layer; a capping layer is formed on the etch stop layer and is an opaque insulating layer; and a source and a drain are formed, and the source and the drain are formed on the cap layer And electrically connected to the active layer.
  • the fabrication method provided in this embodiment is similar to the fabrication method provided in the third embodiment, except that the portion of the channel region of the corresponding active layer of the cover layer may not be etched, that is, the cover layer is in the trench of the active layer.
  • the location of the road zone can be continuous.
  • the manufacturing method provided in this embodiment may include the above steps S41 to S45; and the overlay layer pattern formed in step S43 is the overlay layer, and may not be covered in step S45.
  • the layer pattern is etched.
  • the fabrication method provided in this embodiment may include the above steps S51 to S55; and the overlay layer pattern formed in step S53 is the overlay layer, in step S55.
  • the cover layer pattern may not be etched.
  • This embodiment provides an array substrate and a manufacturing method thereof.
  • the array substrate provided in this embodiment includes the thin film transistor provided in the first embodiment or the second embodiment.
  • the array substrate may be an array substrate used in a liquid crystal display device.
  • the array substrate further includes a pixel electrode, and the pixel electrode may be electrically connected to a drain of the thin film transistor.
  • the array substrate may also be other types of array substrates such as an OLED (Organic Light Emitting Diode) array substrate.
  • the cover layer includes at least one of a conductive material layer and an opaque insulating layer, and therefore, the cover layer is formed during the process of forming the etch barrier layer
  • the current at the time of ESD generation can be dispersed and/or the portion of the active layer to be electrically connected to the source/drain can be prevented from being electrically guided, so that the cover layer can reduce ESD damage, for example, it can be avoided as much as possible
  • a short circuit occurs between the source/drain metal layer above the source layer and the metal layer (eg, the gate metal layer) under the active layer.
  • the array substrate provided in this embodiment includes the thin film transistor, and thus the array substrate also has a similar effect.
  • the array substrate includes a thin film transistor, and the thin film transistor is fabricated by the method provided in the third embodiment or the fourth embodiment.
  • the method for fabricating the array substrate further includes forming other film layers.
  • the array substrate for liquid crystal display further includes forming a pixel electrode layer.
  • the OLED array substrate further includes forming an anode layer, a cathode layer, and the like.
  • the third embodiment to the fifth embodiment only describe the manufacturing method of the thin film transistor and the manufacturing method of the array substrate by taking the cover layer as a conductive material layer or an opaque insulating layer as an example.
  • the cover layer is an opaque semiconductor layer
  • the fabrication method of the thin film transistor and the array substrate is similar to that of the third embodiment, and details are not described herein again.
  • This embodiment provides a display device including the array substrate provided in Embodiment 5.
  • the display device may include an array substrate and a counter substrate disposed opposite to each other, and the opposite substrate is, for example, a color filter substrate.
  • the display device may further include an array substrate Backlight for backlighting.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种薄膜晶体管及其制作方法、阵列基板及其制作方法以及显示装置。该薄膜晶体管包括：有源层（30）；设置在所述有源层（30）上的刻蚀阻挡层（40）；设置在所述刻蚀阻挡层（40）上的覆盖层（60），所述覆盖层（60）包括导电材料层、不透光的绝缘层和不透光的半导体层中的至少一种；以及设置在所述覆盖层（60）上的源极（50a）和漏极（50b），所述源极（50a）和所述漏极（50b）与所述有源层（30）电连接。该薄膜晶体管中的覆盖层（60）可以尽量减小有源层（30）的待与源/漏极（50a、50b）电连接的位置处发生ESD造成的ESD损害。

Description

薄膜晶体管及制作方法、阵列基板及制作方法和显示装置 技术领域
本发明的至少一个实施例涉及一种薄膜晶体管及制作方法、阵列基板及制作方法和显示装置。
背景技术
通常，显示器包括阵列基板，阵列基板上设置有呈矩阵排列的薄膜晶体管，每个薄膜晶体管作为一个连接数据线和像素的开关，开和关的时间由栅线控制。以液晶显示器为例，液晶显示器中的阵列基板包括横纵交叉的多条栅线和多条数据线，这些栅线和数据线限定多个像素，例如，每个像素包括薄膜晶体管和像素电极，例如，薄膜晶体管的栅极与栅线电连接，薄膜晶体管的源极与数据线电连接，薄膜晶体管的漏极与像素电极电连接。
目前，金属氧化物薄膜晶体管由于迁移率高、均一性好、透明、制作工艺简单等优点而备受关注。刻蚀阻挡型金属氧化物薄膜晶体管是一种常见的金属氧化物薄膜晶体管，其制作工艺简单，并且在金属氧化物有源层上形成的刻蚀阻挡层可以在形成源/漏电极的过程中保护金属氧化物有源层不被破坏，从而提高金属氧化物薄膜晶体管的性能。
根据栅极和有源层的位置关系，金属氧化物薄膜晶体管可以包括底栅结构和顶栅结构，即，在底栅结构中，栅极位于金属氧化物有源层的下方，在顶栅结构中，栅极位于金属氧化物有源层的上方。此外，在顶栅结构中，为避免金属氧化物有源层受光，在金属氧化物有源层下方还设置有遮光金属层。
发明内容
本发明的至少一个实施例提供了一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置，以尽量减小有源层的待与源/漏极电连接的位置处发生静电释放(ESD)造成的ESD损害。
本发明的至少一个实施例提供了一种薄膜晶体管，其包括：有源层；设置在所述有源层上的刻蚀阻挡层；设置在所述刻蚀阻挡层上的覆盖层，所述 覆盖层包括导电材料层、不透光的绝缘层和不透光的半导体层中的至少一种；以及设置在所述覆盖层上的源极和漏极，所述源极和所述漏极与所述有源层电连接。
本发明的至少一个实施例还提供了一种阵列基板，其包括上述薄膜晶体管。
本发明的至少一个实施例还提供了一种显示装置，其包括上述阵列基板。
本发明的至少一个实施例还提供了一种薄膜晶体管的制作方法，该方法包括：形成有源层；形成刻蚀阻挡层，所述刻蚀阻挡层形成在所述有源层上；形成覆盖层，所述覆盖层形成在所述刻蚀阻挡层上并且包括导电材料层、不透光的绝缘层和不透光的半导体层中的至少一种；以及形成源极和漏极，所述源极和所述漏极形成在所述覆盖层上并且与所述有源层电连接。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，所述阵列基板包括薄膜晶体管，所述薄膜晶体管采用上述方法制作。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为一种底栅结构的金属氧化物薄膜晶体管的剖视示意图；
图1b为制作图1a所示的薄膜晶体管的刻蚀阻挡层时进行曝光处理的示意图；
图1c为对刻蚀阻挡层薄膜进行图案化处理的曝光过程中发生静电释放的示意图；
图2a为本发明实施例一提供的一种薄膜晶体管的剖视示意图；
图2b为本发明实施例一提供的又一种薄膜晶体管的剖视示意图；
图2c为本发明实施例一提供的另一种薄膜晶体管的剖视示意图；
图3a为本发明实施例二提供的一种薄膜晶体管的剖视示意图；
图3b为本发明实施例二提供的又一种薄膜晶体管的剖视示意图；
图3c为本发明实施例二提供的另一种薄膜晶体管的剖视示意图；
图4a至图4f为本发明实施例三提供的制作如图2a所示的薄膜晶体管的 各步骤的示意图；
图5a至5f为本发明实施例三提供的制作如图2b和图2c所示的薄膜晶体管的各步骤的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1a为一种底栅结构的金属氧化物薄膜晶体管的剖视示意图。如图1a所示，该薄膜晶体管包括栅极01、设置在栅极01上的栅绝缘层02、设置在栅绝缘层02上的金属氧化物(例如氧化铟镓锌)有源层03、设置在金属氧化物有源层03上的刻蚀阻挡层04和设置在刻蚀阻挡层04上的源极05a和漏极05b，源极05a和漏极05b分别通过刻蚀阻挡层04中的过孔04a和过孔04b与有源层03电连接。
通常，图1a所示的薄膜晶体管的制作方法包括如下步骤S01至步骤S05，下面详细介绍这些步骤。
步骤S01：沉积栅金属层薄膜，并通过一次图案化处理形成栅极01。
步骤S02：在栅极01上沉积栅绝缘层薄膜，并通过一次图案化处理形成栅绝缘层02和位于栅绝缘层02中的过孔(图1a中未示出)。
步骤S03：在栅绝缘层02上沉积金属氧化物薄膜，并通过一次图案化处理形成金属氧化物有源层03。
步骤S04：在金属氧化物有源层03上沉积刻蚀阻挡层薄膜，并通过一次图案化处理形成刻蚀阻挡层04和位于刻蚀阻挡层04中的过孔04a和过孔04b。
步骤S05：在刻蚀阻挡层04上沉积源漏金属层薄膜，并通过一次图案化处理形成源极05a和漏极05b，使源极05a和漏极05b分别通过过孔04a和过孔04b与金属氧化物有源层03电连接。
在研究中，本申请的发明人注意到，在步骤S04中，对刻蚀阻挡层薄膜进行图案化处理通常包括：如图1b所示，对形成在刻蚀阻挡层薄膜04'上的光刻胶07进行曝光，曝光位置对应刻蚀阻挡层薄膜04'的待形成过孔04a和过孔04b的位置04a'和04b'(如图1b中的虚线所示)；之后，通过显影、刻蚀等处理，以形成刻蚀阻挡层04以及刻蚀阻挡层04中的过孔04a和过孔04b。
由于刻蚀阻挡层薄膜04'通常采用氧化硅等材料制作，在对光刻胶07进行曝光时，光线可透过刻蚀阻挡层薄膜04'照射到金属氧化物有源层03上，这导致金属氧化物有源层03的待与源极和漏极电连接的位置处发生静电释放(简称ESD，如图1c所示)的几率大大增加。这是因为：在曝光过程中，金属氧化物有源层03的待与源极和漏极电连接的部分(即第一部分03a和第二部分03b，如图1b中的虚线所示)因被光照射而导体化的几率大大增加，导致金属氧化物有源层03在第一部分03a和第二部分03b处容易与栅极01之间产生电容，该电容可大大提高ESD的发生几率。ESD容易导致金属氧化物有源层03下方的栅极01与金属氧化物有源层03上方的源/漏极05a、05b之间发生短路。
本发明的至少一个实施例提供了一种薄膜晶体管及其制作方法、阵列基板及其制作方法以及显示装置。在该薄膜晶体管中，设置于有源层上的刻蚀阻挡层上设置有覆盖层，该覆盖层包括导电材料层、不透光的绝缘层和不透光的半导体层中的至少一种。在形成刻蚀阻挡层及其中的过孔的图案化处理的曝光过程中，即使有源层的待与源/漏极电连接的位置处发生ESD，导电材 料层也可以起到分散电流的作用，从而尽量避免因有源层的待与源/漏极电连接的位置处发生ESD而导致有源层下方的金属层与有源层上方的源漏金属层之间发生短路的现象；不透光的绝缘层或不透光的半导体层可以避免有源层的待与源/漏极电连接的部分被光照射而导体化，从而降低有源层的待与源/漏极电连接的位置处发生ESD的几率，进而尽量避免有源层下方的金属层与有源层上方的源漏金属层之间发生短路的现象。
实施例一
本实施例提供了一种薄膜晶体管，如图2a至图2c所述，该薄膜晶体管包括：有源层30；设置在有源层30上的刻蚀阻挡层40；设置在刻蚀阻挡层40上(即设置在刻蚀阻挡层40的远离有源层30的一侧)的覆盖层60；以及设置在覆盖层60上(即设置在覆盖层60的远离刻蚀阻挡层40的一侧)的源极50a和漏极50b，源极50a和漏极50b与有源层30电连接。在本实施例中，覆盖层60包括导电材料层，即覆盖层60的材料包括导电材料。这样，在通过图案化处理形成刻蚀阻挡层的过程中，即使有源层30的待与源极50a和漏极50b电连接的位置处发生ESD，覆盖层60也可以将电流分散出去，从而减少ESD损害。
在至少一个示例中，导电材料层在有源层30的沟道区33所在位置处可以断开。由于覆盖层60包括导电材料层，通过使导电材料层在有源层30的沟道区33所在位置处断开，可以避免源极50a和漏极50b通过该导电材料层电连接在一起，从而使有源层30形成沟道区33。图2a至图2c以覆盖层60为导电材料层为例进行说明。如图2a至图2c所示，覆盖层60在有源层30的沟道区33所在的位置处断开。当然，本实施例也可以采用本领域常用的其它的使有源层30形成沟道区33的方式。
在至少一个示例中，覆盖层60包括的导电材料层的材料可以包括金属或导电金属氧化物。例如，金属可以包括铝、铜、锆、钼和钛等金属中的至少一种或几种。例如，导电金属氧化物可以包括氧化铟镓锌、氧化铟锡和氧化铟锌等导电金属氧化物中的至少一种或几种。当然，覆盖层包括的导电材料层也可以采用其它导电材料。
例如，导电材料层的材料包括金属时，即，导电材料层包括金属层时，该金属层的厚度可以为300～1000埃。这样可以实现在对覆盖层进行曝光的 过程中避免光线因透过该金属层而照射到有源层上，从而可以进一步降低有源层的待与源极和漏极电连接的位置处发生ESD的几率。
此外，无论导电材料层的材料包括金属还是金属氧化物材料，导电材料层都可以与源极和漏极通过一次图案化处理形成，在该图案化处理的过程中，导电材料层可以与形成与源极和漏极的源漏金属层薄膜同时刻蚀，或者以源极和漏极为掩膜对导电材料层进行刻蚀，这样可以节省工艺和掩模板。在这种情况下，沿垂直于覆盖层的方向，导电材料层的在有源层的沟道区所在位置处的边缘可以分别与源极的面向漏极一侧的边缘和漏极的面向源极一侧的边缘大致对齐。
例如，如图2a至图2c所示，覆盖层60为导电材料层，沿垂直于覆盖层60的方向，覆盖层60在有源层30的沟道区33所在处的边缘63可以与源极50a的面向漏极50b一侧的边缘51大致对齐，边缘64可以与漏极50b的面向源极50a一侧的边缘52大致对齐。也就是说，覆盖层60可以包括位于源极50a和刻蚀阻挡层40之间的第一部分61以及位于漏极50b和刻蚀阻挡层40之间的第二部分62，第一部分61和第二部分62都位于有源层30的与源极50a和漏极50b电连接的位置之间，并且第一部分61与第二部分62之间的距离与源极50a和漏极50b之间的距离相等。由于对薄膜进行图案化处理时形成的图案的边缘未必是完全垂直于该图案所在的面，因此，此处的“相等”可以是指“大致相等”。
在至少一个示例中，源极50a和漏极50b可以分别通过过孔与有源层30电连接，如图2a所示，源极50a可以通过贯穿刻蚀阻挡层40的第一过孔1与有源层30电连接，漏极50b可以通过贯穿刻蚀阻挡层40的第二过孔2与有源层30电连接。
在至少一个示例中，源极50a和漏极50b也可以不通过过孔与有源层30电连接。例如，如图2b和图2c所示，刻蚀阻挡层40在有源层30所在面上的正投影可以位于有源层30所在的区域内，有源层30具有分别伸出到刻蚀阻挡层40的两侧边缘41、42之外的第一部分31和第二部分32，第一部分31和第二部分32都位于刻蚀阻挡层40的正投影之外，源极50a电连接到第一部分31，漏极50b电连接到第二部分32。
在至少一个示例中，在有源层30下方设置有金属结构80，金属结构80 与有源层30之间设置有绝缘层90，并且有源层30的分别与源极50a和漏极50b电连接的部分都与该金属结构80在垂直于该金属结构80所在面的方向上交叠。
例如，在图2a所示情形中，第一过孔1和第二过孔2在金属结构80所在面上的正投影与金属结构80有重叠部分。
例如，在图2b和图2c所示情形中，在该薄膜晶体管中，有源层30的第一部分31和第二部分32在金属结构80所在面上的正投影都与金属结构80有重叠部分。
在至少一个示例中，薄膜晶体管还包括栅极10，如图2a和图2b所示，栅极10可以位于有源层30之下，即该薄膜晶体管可以为底栅结构，在这种情况下，该栅极10可以作为上述金属结构80，栅绝缘层20可以作为上述绝缘层90。当然，本实施例提供的薄膜晶体管也可以为顶栅结构。如图2c所示，栅极10可以位于有源层30之上，在这种情况下，在有源层30下方设置有金属结构80，金属结构80可以为遮光金属层，用于防止薄膜晶体管的有源层30受光。
由于有源层30的材料包括金属氧化物时，有源层30的待与源极和漏极电连接的部分在受光时导体化的几率大大增加，导致有源层30的待与源极和漏极电连接的位置处发生ESD的几率大大增加。因此，本实施例尤其适用于有源层30的材料包括金属氧化物材料的薄膜晶体管。当然，有源层30也可以采用其它的容易在有源层30的待与源极和漏极电连接的位置处受光情况下发生较严重的ESD现象的材料。
由于有源层的材料包括金属氧化物，为尽量避免影响其性能，与有源层接触的绝缘层的材料可以包括氧化硅，例如，图2a和图2b中的刻蚀阻挡层40和栅绝缘层20、图2c中的刻蚀阻挡层40和绝缘层90可以采用氧化硅材料制作。当然，与有源层接触的绝缘层也可以采用本领域常用的其它材料。
实施例二
本实施例提供的薄膜晶体管与实施例一提供的薄膜晶体管的区别在于：覆盖层60为不透光的绝缘层，即覆盖层60的材料为不透光的绝缘材料，如图3a至图3c所示。
由于覆盖层60为绝缘层，其在有源层30的沟道区(图中未标出)所在 处可以是连续的。即覆盖层60可以不断开即可形成有源层30的沟道区。
例如，该不透光的绝缘层可以为黑色树脂材料。当然，也可以是本领域常用的其它不透光的绝缘材料。
本实施例提供的薄膜晶体管的各组成部分的设置可参考实施例一中的相关描述，重复之处不再赘述。
上述实施例一和实施例二分别以覆盖层为导电材料层和不透光的绝缘层为例进行说明。当覆盖层为不透光的半导体层时，该不透光的半导体层可以采用本领域常用的材料，例如，硅或其它材料。当然，本领域技术人员可以根据需要对该不透光的半导体层的厚度进行设置，只要保证其不透光即可。此外，为了避免该覆盖层将源极和漏极电连接在一起，该为不透光的半导体层的覆盖层在薄膜晶体管中的设置方式可以与实施例一提供的薄膜晶体管中的覆盖层的设置方式类似，此处不再赘述。
实施例三
针对实施例一提供的薄膜晶体管，例如图2a至图2c所示的薄膜晶体管，本实施例提供了一种薄膜晶体管的制作方法，该制作方法包括：形成有源层；形成刻蚀阻挡层，该刻蚀阻挡层形成在有源层上；形成覆盖层，该覆盖层形成在刻蚀阻挡层上并且包括导电材料层；以及形成源极和漏极，该源极和该漏极形成在覆盖层上并且与有源层电连接。
例如，形成刻蚀阻挡层和覆盖层可以包括以下步骤S31至步骤S35，下面详细介绍这些步骤。
步骤S31：形成刻蚀阻挡层薄膜，使刻蚀阻挡层薄膜形成在有源层上。
在该步骤中，刻蚀阻挡层薄膜可以是经过图案化处理的薄膜。例如，刻蚀阻挡层薄膜可以与有源层在一次图案化处理中一起形成，也就是说，可以形成有源层材料(例如导电金属氧化物材料)的膜层和位于其上的刻蚀阻挡层材料的膜层，之后对二者同时进行图案化处理以形成有源层和上述刻蚀阻挡层薄膜。
或者，刻蚀阻挡层薄膜也可以是未经图案化处理的薄膜。即，可以在形成有源层之后，在有源层之上形成刻蚀阻挡层材料的膜层作为刻蚀阻挡层薄膜。
步骤S32：在刻蚀阻挡层薄膜上形成覆盖层薄膜。例如，覆盖层薄膜的 材料可以包括金属或导电金属氧化物。
步骤S33：在覆盖层薄膜上形成光刻胶薄膜，对光刻胶薄膜进行曝光、显影处理后形成光刻胶图案。
步骤S34：以步骤S33中形成的光刻胶图案为掩膜对覆盖层薄膜进行刻蚀，以形成覆盖层图案。
步骤S35：以步骤S33中形成的光刻胶图案或步骤S34中形成的覆盖层图案为掩膜，对刻蚀阻挡层薄膜进行刻蚀，以形成刻蚀阻挡层。
在至少一个示例中，源极和漏极可以分别通过刻蚀阻挡层中的过孔与有源层电连接。在这种情况下，例如，步骤S34中的形成覆盖层图案还包括：形成位于覆盖层图案中的第一覆盖层过孔和第二覆盖层过孔；步骤S35中的形成刻蚀阻挡层还包括形成位于刻蚀阻挡层中的对应第一覆盖层过孔的第一刻蚀阻挡层过孔和对应第二覆盖层过孔的第二刻蚀阻挡层过孔。例如，第一覆盖层过孔和第一刻蚀阻挡层过孔构成第一过孔，第二覆盖层过孔和第二刻蚀阻挡层过孔构成第二过孔，源极通过第一过孔与有源层电连接，漏极通过第二过孔与有源层电连接。
或者，在至少一个示例中，源极和漏极也可以不通过过孔与有源层电连接。在这种情况下，例如，在步骤S34中，形成覆盖层图案时可以使覆盖层图案在有源层所在面上的正投影位于有源层所在区域之内；在步骤S35中，形成刻蚀阻挡层时可以使刻蚀阻挡层在有源层所在面上的正投影位于有源层所在区域内，并且使有源层具有伸出刻蚀阻挡层的两侧边缘之外的第一部分和第二部分。在后续步骤中源极可以电连接到有源层的第一部分，漏极可以电连接到有源层的第二部分。
在上述示例中，可以通过调整步骤S33中对光刻胶薄膜进行曝光的位置，使在光刻胶图案中形成多个过孔或者使光刻胶图案在有源层所在面上的正投影位于有源层所在区域之内，从而使步骤S34中形成的覆盖层图案也相应地具有过孔或正投影位于有源层所在区域之内。
由于覆盖层包括导电材料层，为了形成有源层的沟道区，本实施例提供的薄膜晶体管的制作方法中，形成覆盖层、源极和漏极例如可以包括步骤S361～S363，下面进行详细介绍。
步骤S361：在形成刻蚀阻挡层之后，在覆盖层图案上形成源漏金属层薄 膜。
步骤S362：对源漏金属层薄膜进行图案化处理以形成源极和漏极。
步骤S363：对覆盖层图案进行刻蚀，以使覆盖层图案在源极和漏极之间的位置处断开。需要说明的是，该步骤S363也可以与步骤S362在上述同一次图案化处理过程中进行。
例如，针对图2a所示的薄膜晶体管，如图4a至图4f所示，本实施例的至少一个示例提供的制作方法可以包括如下步骤S41～步骤S45，下面详细介绍这些步骤。
步骤S41：形成有源层30，如图4a所示。
例如，可以先形成有源层材料(例如导电金属氧化物材料)的薄膜，之后对该薄膜进行图案化处理以形成有源层30。
步骤S42：形成刻蚀阻挡层薄膜40'，刻蚀阻挡层薄膜40'形成在有源层30上，如图4a所示。
刻蚀阻挡层薄膜40'的形成方式可参考上述步骤S31中的相关描述，重复之处不再赘述。图4a以刻蚀阻挡层薄膜40'在有源层30形成之后形成为例进行说明。当刻蚀阻挡层薄膜40'与有源层30通过同一次图案化处理形成时，刻蚀阻挡层薄膜40'与有源层30的边缘大致对齐。
步骤S43：在刻蚀阻挡层薄膜40'上形成覆盖层薄膜60'，如图4a所示；对覆盖层薄膜60'进行图案化处理，以形成覆盖层图案60”和位于覆盖层图案60”中的第一覆盖层过孔60a和第二覆盖层过孔60b，如图4c所示。
例如，对覆盖层薄膜60'进行图案化处理包括：在覆盖层薄膜60'上形成光刻胶薄膜70'，并对光刻胶薄膜70'进行曝光处理，曝光位置对应有源层30的待与源极和漏极电连接的部分，如图4a所示；之后，进行显影处理，去除被光照射到的光刻胶，从而得到光刻胶图案70”和位于其中的多个光刻胶过孔，如图4b所示；之后，以光刻胶图案70”为掩膜对覆盖层薄膜60'进行刻蚀，以形成覆盖层图案60”及其中的过孔60a和60b，如图4c所示。
步骤S44：以步骤S43中形成的光刻胶图案70”或覆盖层图案60”为掩膜，对刻蚀阻挡层薄膜40'进行刻蚀，以形成刻蚀阻挡层40以及位于刻蚀阻挡层40中的对应第一覆盖层过孔60a的第一刻蚀阻挡层过孔40a和对应第二覆盖层过孔60b的第二刻蚀阻挡层过孔40b，第一覆盖层过孔60a和第一刻蚀阻 挡层过孔40a构成第一过孔1，第二覆盖层过孔60b和第二刻蚀阻挡层过孔40b构成第二过孔2，如图4d所示。
在该步骤中，在形成刻蚀阻挡层40之后，可以去除覆盖层图案60”上的光刻胶图案70”，如图4e所示。
步骤S45：在覆盖层图案60”上形成源漏金属层薄膜50'，使源漏金属层薄膜50'覆盖第一过孔1和第二过孔2，如图4f所示；对源漏金属层薄膜50'和覆盖层图案60”进行一次图案化处理以形成源极50a、漏极50b和覆盖层60，源极50a通过第一过孔1与有源层30电连接，漏极50b通过第二过孔2与有源层30电连接，覆盖层60在有源层30的沟道区33所在位置处断开，如图2a所示。
针对图2b和图2c所示的薄膜晶体管，如图5a至图5f所示，本实施例的至少一个示例提供的制作方法例如包括如下步骤S51～步骤S55，下面详细介绍这些步骤。
步骤S51：形成有源层30，如图5a所示。
步骤S52：在有源层30上形成刻蚀阻挡层薄膜40'，如图5a所示。
步骤S53：在刻蚀阻挡层薄膜40'上形成覆盖层薄膜60'，对覆盖层薄膜60'进行图案化处理，以形成覆盖层图案60”，覆盖层图案60”在有源层所在面上的正投影位于有源层30所在区域之内，如图5c所示。
例如，对覆盖层薄膜60'进行图案化处理包括：在覆盖层薄膜60'上形成光刻胶薄膜70'，并对光刻胶薄膜70'进行曝光处理，非曝光位置对应有源层30的待形成沟道区的部分，其余为曝光位置，如图5a所示；之后，进行显影处理，去除被光照射到的光刻胶，从而得到光刻胶图案70”，光刻胶图案70”在有源层30所在面上的正投影位于有源层30所在区域之内，如图5b所示；之后，以光刻胶图案70”为掩膜对覆盖层薄膜60'进行刻蚀，以形成覆盖层图案60”，如图5c所示。
步骤S54：以步骤S53中形成的光刻胶图案70”或覆盖层图案60”为掩膜，对刻蚀阻挡层薄膜40'进行刻蚀，以形成刻蚀阻挡层40，使刻蚀阻挡层40在有源层30所在面上的正投影位于有源层30所在区域内，并且使有源层30具有位于刻蚀阻挡层40的正投影之外的第一部分31和第二部分32，如图5d所示。
在该步骤中，在形成刻蚀阻挡层40之后，可以去除覆盖层图案60”上的光刻胶图案70”，如图5e所示。
步骤S55：在覆盖层图案60”上形成源漏金属层薄膜50'，如图5f所示；对源漏金属层薄膜50'和覆盖层图案60”进行图案化处理以形成源极50a、漏极50b和覆盖层60，源极50a通过有源层30的第一部分31与有源层30连接，漏极50b通过有源层30的第二部分32与有源层30电连接，覆盖层60在有源层30的沟道区33所在位置处断开，如图2b和图2c所示。
当然，针对底栅结构的薄膜晶体管，例如图2a和图2b所示的薄膜晶体管，其制作方法还包括：在形成有源层30之前，形成栅极10和位于栅极10之上的栅绝缘层20。针对顶栅结构的薄膜晶体管，例如图2c所示的薄膜晶体管，其制作方法，还包括：在形成有源层30之前，形成金属结构80和位于金属结构80之上的绝缘层90；在形成源极50a、漏极50b和覆盖层60之后，在源极50a和漏极50b上形成栅绝缘层20和位于栅绝缘层20上的栅极10。
实施例四
针对实施例二提供的薄膜晶体管，例如图3a至图3c所示的薄膜晶体管，本实施例提供了另一种薄膜晶体管的制作方法，其包括：形成有源层；形成刻蚀阻挡层，刻蚀阻挡层形成在有源层上；形成覆盖层，覆盖层形成在刻蚀阻挡层上并且为不透光的绝缘层；以及形成源极和漏极，源极和漏极形成在覆盖层上并且与有源层电连接。
本实施例提供的制作方法与实施例三提供的制作方法类似，不同之处在于：可以不对覆盖层的对应有源层的沟道区的部分进行刻蚀，即覆盖层在有源层的沟道区所在位置处可以是连续的。
例如，对于图3a所示的薄膜晶体管，本实施例提供的制作方法可以包括上述步骤S41至步骤S45；并且，在步骤S43中形成的覆盖层图案即为覆盖层，在步骤S45中可以不对覆盖层图案进行刻蚀。
例如，对于图3b和图3c所示的薄膜晶体管，本实施例提供的制作方法可以包括上述步骤S51至步骤S55；并且，在步骤S53中形成的覆盖层图案即为覆盖层，在步骤S55中可以不对覆盖层图案进行刻蚀。
本实施例提供的制作方法可参考实施例三中的相关描述，重复之处不做 赘述。
实施例五
本实施例提供了一种阵列基板及其制作方法。
本实施例提供的阵列基板包括上述实施例一或实施例二提供的薄膜晶体管。
例如，该阵列基板可以为用于液晶显示装置中的阵列基板，在这种情况下，该阵列基板还包括像素电极，像素电极可以与薄膜晶体管的漏极电连接。当然，该阵列基板也可以为OLED(有机发光二极管)阵列基板等其它类型的阵列基板。
由于薄膜晶体管具有设置在刻蚀阻挡层上的覆盖层，该覆盖层包括导电材料层和不透光的绝缘层中的至少一种，因此，在制作刻蚀阻挡层的过程中，该覆盖层可分散发生ESD时的电流和/或起到避免有源层的待与源/漏极电连接的部分受光而导体化的作用，因而该覆盖层可以减小ESD损害，例如，可以尽量避免有源层上方的源漏金属层与有源层下方的金属层(例如栅金属层)之间发生短路。本实施例提供的阵列基板包括该薄膜晶体管，因而，该阵列基板也具有类似效果。
本实施例提供的阵列基板的制作方法中，该阵列基板包括薄膜晶体管，并且该薄膜晶体管采用上述实施例三或实施例四提供的方法制作。
当然，该阵列基板的制作方法还包括形成其它膜层，例如，用于液晶显示的阵列基板还包括形成像素电极层，例如，OLED阵列基板还包括形成阳极层和阴极层等。这些膜层可以采用本领域常用的方式形成，本实施例不做赘述。
以上实施例三至实施例五仅以覆盖层为导电材料层或不透光的绝缘层为例对薄膜晶体管的制作方法和阵列基板的制作方法进行说明。当覆盖层为不透光的半导体层时，薄膜晶体管和阵列基板的制作方法与实施例三类似，此处不再赘述。
实施例六
本实施例提供了一种显示装置，其包括实施例五提供的阵列基板。
例如，该显示装置可以包括相对设置的阵列基板与对置基板，该对置基板例如为彩膜基板。在一些实施例中，该显示装置还可以包括为阵列基板提 供背光的背光源。
例如，该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年8月20日递交的中国专利申请第201510516319.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种薄膜晶体管，包括：
    有源层；
    设置在所述有源层上的刻蚀阻挡层；
    设置在所述刻蚀阻挡层上的覆盖层，其中，所述覆盖层包括导电材料层、不透光的绝缘层和不透光的半导体层中的至少一种；以及
    设置在所述覆盖层上的源极和漏极，其中，所述源极和所述漏极与所述有源层电连接。
  2. 如权利要求1所述的薄膜晶体管，其中，所述覆盖层包括所述导电材料层或所述不透光的半导体层，所述有源层具有沟道区，所述覆盖层在所述有源层的所述沟道区所在的位置处断开。
  3. 如权利要求2所述的薄膜晶体管，其中，
    所述导电材料层的材料包括金属或导电金属氧化物。
  4. 如权利要求2所述的薄膜晶体管，其中，所述导电材料层包括金属层，并且所述金属层的厚度为300～1000埃。
  5. 如权利要求2-4任一项所述的薄膜晶体管，其中，沿垂直于所述覆盖层的方向，所述导电材料层或所述不透光的半导体层的在所述沟道区所在位置处的边缘分别与所述源极的面向所述漏极一侧的边缘和所述漏极的面向所述源极一侧的边缘对齐。
  6. 如权利要求1-5任一项所述的薄膜晶体管，其中，
    所述源极通过贯穿所述刻蚀阻挡层的第一过孔与所述有源层电连接，所述漏极通过贯穿所述刻蚀阻挡层的第二过孔与所述有源层电连接；或者
    所述刻蚀阻挡层在所述有源层所在面上的正投影位于所述有源层所在的区域内，且所述有源层具有分别伸出到所述刻蚀阻挡层的两侧边缘之外的第一部分和第二部分，所述源极电连接到所述第一部分，所述漏极电连接到所述第二部分。
  7. 如权利要求6所述的薄膜晶体管，其中，
    所述有源层下方设置有金属结构；
    所述第一过孔和所述第二过孔在所述金属结构所在面上的正投影与所述 金属结构有重叠部分，或者所述有源层的所述第一部分和所述第二部分在所述金属结构所在面上的正投影都与所述金属结构有重叠部分。
  8. 如权利要求7所述的薄膜晶体管，还包括栅极，其中，
    所述栅极位于所述有源层之下，所述金属结构包括所述栅极；或者
    所述栅极位于所述有源层之上，所述金属结构包括遮光金属层。
  9. 如权利要求1-8任一项所述的薄膜晶体管，其中，所述有源层的材料包括金属氧化物。
  10. 一种阵列基板，包括如权利要求1-9任一项所述的薄膜晶体管。
  11. 一种显示装置，包括如权利要求10所述的阵列基板。
  12. 一种薄膜晶体管的制作方法，包括：
    形成有源层；
    形成刻蚀阻挡层，其中，所述刻蚀阻挡层形成在所述有源层上；
    形成覆盖层，其中，所述覆盖层形成在所述刻蚀阻挡层上并且包括导电材料层、不透光的绝缘层和不透光的半导体层中的至少一种；以及
    形成源极和漏极，其中，所述源极和所述漏极形成在所述覆盖层上并且与所述有源层电连接。
  13. 如权利要求12所述的制作方法，其中，形成所述刻蚀阻挡层和所述覆盖层包括：
    形成刻蚀阻挡层薄膜，其中，所述刻蚀阻挡层薄膜形成在所述有源层上；
    在所述刻蚀阻挡层薄膜上形成覆盖层薄膜；
    在所述覆盖层薄膜上形成光刻胶薄膜，对所述光刻胶薄膜进行曝光、显影处理后形成光刻胶图案；
    以所述光刻胶图案为掩膜对所述覆盖层薄膜进行刻蚀，以形成覆盖层图案；以及
    以所述光刻胶图案或所述覆盖层图案为掩膜，对所述刻蚀阻挡层薄膜进行刻蚀，以形成所述刻蚀阻挡层。
  14. 如权利要求13所述的制作方法，其中，
    形成所述覆盖层图案还包括形成位于所述覆盖层图案中的第一覆盖层过孔和第二覆盖层过孔；
    形成所述刻蚀阻挡层还包括形成位于所述刻蚀阻挡层中的对应所述第一 覆盖层过孔的第一刻蚀阻挡层过孔和对应所述第二覆盖层过孔的第二刻蚀阻挡层过孔，
    其中，所述第一覆盖层过孔和所述第一刻蚀阻挡层过孔构成第一过孔，所述第二覆盖层过孔和所述第二刻蚀阻挡层过孔构成第二过孔，所述源极通过所述第一过孔与所述有源层电连接，所述漏极通过所述第二过孔与所述有源层电连接。
  15. 如权利要求13所述的制作方法，其中，
    形成所述覆盖层图案时使所述覆盖层图案在所述有源层所在面上的正投影位于所述有源层所在区域之内；
    形成所述刻蚀阻挡层时使所述有源层具有伸出所述刻蚀阻挡层的两侧边缘之外的第一部分和第二部分；
    其中，所述源极电连接到所述第一部分，所述漏极电连接到所述第二部分。
  16. 如权利要求13-15任一项所述的制作方法，其中，所述覆盖层包括所述导电材料层或所述不透光的半导体层；
    在形成所述刻蚀阻挡层之后，在所述覆盖层图案上形成源漏金属层薄膜；
    对所述源漏金属层薄膜进行图案化处理以形成所述源极和所述漏极；以及
    对所述覆盖层图案进行刻蚀，以使所述覆盖层图案在所述源极和所述漏极之间的位置处断开。
  17. 一种阵列基板的制作方法，其中，所述阵列基板包括薄膜晶体管，所述薄膜晶体管采用如权利要求12-16任一项所述的方法制作。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779203B (zh) * 2015-04-23 2017-11-28 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN105161519B (zh) * 2015-08-20 2018-03-27 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
CN106298954B (zh) * 2016-08-31 2020-02-04 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法
CN106601754A (zh) * 2016-12-06 2017-04-26 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制备方法、显示装置
CN107146818B (zh) 2017-06-27 2020-02-18 京东方科技集团股份有限公司 一种薄膜晶体管、其制作方法、阵列基板及显示装置
US10510899B2 (en) * 2017-08-07 2019-12-17 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor, thin film transistor manufacturing method and liquid crystal display panel
CN107579006B (zh) * 2017-09-13 2019-08-06 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制备方法
CN109634004A (zh) * 2018-11-12 2019-04-16 惠科股份有限公司 一种显示面板、制作方法和显示装置
CN109659313B (zh) * 2018-11-12 2021-04-02 惠科股份有限公司 一种阵列基板、阵列基板的制作方法和显示面板
CN112951924B (zh) * 2021-02-02 2022-07-12 Tcl华星光电技术有限公司 Tft器件及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3538088B2 (ja) * 1999-10-25 2004-06-14 Ｎｅｃ液晶テクノロジー株式会社 薄膜トランジスタおよびその製造方法
CN102646633A (zh) * 2011-11-28 2012-08-22 友达光电股份有限公司 阵列基板及其制作方法
CN104600123A (zh) * 2015-01-05 2015-05-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板及显示装置
CN105161519A (zh) * 2015-08-20 2015-12-16 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8558276B2 (en) * 2009-06-17 2013-10-15 Alpha And Omega Semiconductor, Inc. Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)
CN102569413A (zh) * 2011-12-13 2012-07-11 华映视讯（吴江）有限公司 薄膜晶体管及其制造方法
KR102023924B1 (ko) 2012-05-24 2019-09-23 엘지디스플레이 주식회사 산화물 박막 트랜지스터를 구비한 표시장치용 어레이기판 그리고 그 제조방법
KR101739636B1 (ko) * 2012-06-15 2017-05-24 소니 주식회사 표시 장치, 반도체 장치 및 표시 장치의 제조 방법
CN103915444B (zh) * 2013-04-10 2016-10-19 上海天马微电子有限公司 一种阵列基板及其制备方法、液晶显示面板
KR102080065B1 (ko) 2013-04-30 2020-04-07 엘지디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
KR102227474B1 (ko) * 2013-11-05 2021-03-15 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판, 유기발광표시장치 및 박막트랜지스터 어레이 기판의 제조 방법
DE102014201131A1 (de) * 2014-01-22 2015-07-23 Zf Friedrichshafen Ag Getriebevorrichtung mit einem Hydrauliksystem
US10032924B2 (en) * 2014-03-31 2018-07-24 The Hong Kong University Of Science And Technology Metal oxide thin film transistor with channel, source and drain regions respectively capped with covers of different gas permeability
CN104377247B (zh) 2014-11-24 2017-12-08 深圳市华星光电技术有限公司 薄膜晶体管、显示装置及薄膜晶体管的制造方法
US9495633B2 (en) * 2015-04-16 2016-11-15 Cylance, Inc. Recurrent neural networks for malware analysis

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3538088B2 (ja) * 1999-10-25 2004-06-14 Ｎｅｃ液晶テクノロジー株式会社 薄膜トランジスタおよびその製造方法
CN102646633A (zh) * 2011-11-28 2012-08-22 友达光电股份有限公司 阵列基板及其制作方法
CN104600123A (zh) * 2015-01-05 2015-05-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板及显示装置
CN105161519A (zh) * 2015-08-20 2015-12-16 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3340312A4 *

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