CN109659313B - 一种阵列基板、阵列基板的制作方法和显示面板 - Google Patents
一种阵列基板、阵列基板的制作方法和显示面板 Download PDFInfo
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Abstract
本发明公开了一种阵列基板、阵列基板的制作方法和显示面板。包括薄膜晶体管,所述薄膜晶体管包括衬底、第一金属层、绝缘层、半导体层、阻挡层、第二金属层、第一钝化层和像素电极;第一金属层,形成于所述衬底表面;绝缘层,覆盖在所述第一金属层表面;半导体层,覆盖在所述绝缘层表面;阻挡层,覆盖在所述半导体层和所述绝缘层表面;第二金属层,覆盖在所述阻挡层表面;所述第二金属层包括源极和漏极;第一钝化层覆盖在所述第二金属层表面;像素电极,设于第一钝化层上方;所述阻挡层上对应源极和漏极位置设有连接槽,所述连接槽一端连接源极与半导体层,另一端连接漏极与半导体层。刻蚀区域小,防止做薄绝缘层,引起画面异常。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种阵列基板、阵列基板的制作方法和显示面板。
背景技术
随着现代资讯科技的进步,在这些显示器中,由于液晶显示器(LCD,LiquidCrystal Display)及有机电激发光显示器(OELD或称为OLED,Organic Electro-luminescent Display)具有轻薄以及消耗功率低的优点,因此在市场中成为主流商品。范例性技术中刻蚀阻挡层存在两种薄膜晶体管结构,薄膜晶体管制程较为稳定,但薄膜晶体管面积较大,影响开口率;另一种是薄膜晶体管面积小的结构。
为了防止氧化铟镓锌背沟道的刻蚀损伤,薄膜晶体管面积虽小,容易出现刻蚀不均匀(蚀刻不干净或者过蚀刻),过蚀刻容易刻蚀到刻蚀阻挡层下面的绝缘层。
发明内容
为实现上述目的,本发明提供了一种阵列基板、阵列基板的制作方法和显示面板,来解决薄膜晶体管面积小的结构,来防止过刻蚀导致绝缘层做薄的的技术问题。
本发明还公开了一种阵列基板,包括薄膜晶体管,所述薄膜晶体管包括衬底、第一金属层、绝缘层、半导体层、阻挡层、第二金属层、第一钝化层和像素电极;第一金属层,形成于所述衬底表面;绝缘层,覆盖在所述第一金属层表面;半导体层,覆盖在所述绝缘层表面;阻挡层,覆盖在所述半导体层和所述绝缘层表面;第二金属层,覆盖在所述阻挡层表面;所述第二金属层包括源极和漏极;第一钝化层覆盖在所述第二金属层表面;像素电极,设于第一钝化层上方;所述阻挡层上对应源极和漏极位置设有连接槽,所述连接槽一端连接源极与半导体层,另一端连接漏极与半导体层。
可选的,所述连接槽包括第一连接槽与第二连接槽;所述第一连接槽与第二连接槽首尾相互连接,形成闭环的通槽结构。
可选的,所述第一连接槽的宽度等于第二连接槽的宽度,所述第一连接槽的长度等于第二连接槽的长度。
可选的,所述连接槽包括第一连接槽;所述第一连接槽连接所述源极与所述漏极形成开环的通槽结构。
可选的,所述连接槽的宽度范围为3-15μm。
可选的,所述薄膜晶体管包括色阻层,覆盖在第一钝化层表面;第二钝化层,覆盖在色阻层表面;所述像素电极覆盖在所述第二钝化层表面;接触孔,所述接触孔贯穿第一钝化层、色阻层与第二钝化层,所述像素电极通过所述接触孔与漏极连接。
可选的,所述薄膜晶体管包括接触孔,所述接触孔贯穿第一钝化层,所述像素电极通过接触孔与漏极连接。
本发明还公开了一种阵列基板的制作方法,所述制作方法包括:
在衬底上形成第一金属层和绝缘层;
在绝缘层上形成半导体层和阻挡层;
在阻挡层上形成连接槽;
在阻挡层上覆盖第二金属层;
在第二金属层上形成第一钝化层;
在第一钝化层形成像素电极;
在像素电极上形成接触孔,贯穿第一钝化层。
可选的,所述连接槽的制作方法包括:
涂布阻挡层材料;
在阻挡层上涂布光阻;
利用光罩进行对其曝光显影;
刻蚀得到连接槽。
本发明还公开了一种显示面板。显示面板包括上述的阵列基板。
相对于范例性的薄膜晶体管的面积虽小的方案来说,在干蚀刻刻蚀阻挡层那一层时,由于刻蚀阻挡层需蚀刻掉的面积过大,容易出现刻蚀不均匀(蚀刻不干净或者过蚀刻),过蚀刻容易刻蚀到刻蚀阻挡层下面的绝缘层,从而使绝缘层膜厚减薄,易漏电,而本申请中蚀刻区域较小,即防止了蚀刻不完全,又防止阻挡层过蚀刻损伤到绝缘层,引起画面异常等问题,对大尺寸且分辨率要求高的显示面板像素设计具有一定的优势。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解,其构成了说明书的一部分,用于例示本申请的实施方式,并与文字描述一起来阐释本申请的原理。显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。在附图中:
图1是本发明的其中一个实施例的薄膜晶体管连接槽的俯视图;
图2是本发明的其中一个实施例的薄膜晶体管连接槽AA’的剖视图;
图3是本发明的其中一个实施例的薄膜晶体管连接槽的俯视图;
图4是本发明的另一实施例的阻挡层C的俯视图;
图5是本发明的另一实施例的薄膜晶体管连接槽AA’的示意图;
图6是本发明的另一实施例的阵列基板制作方法的示意图;
图7是本发明的另一实施例的连接槽制作方法的示意图。
其中,100、显示面板;110、阵列基板;120、薄膜晶体管;121、衬底;122、第一金属层;123、绝缘层;124、半导体层;125、阻挡层;126、第二金属层;127、源极;128、漏极;129、像素电极;130、接触孔;131、第一钝化层;132、第二钝化层;133、色阻层;134、连接槽;135、第一连接槽;136、第二连接槽。
具体实施方式
需要理解的是,这里所使用的术语、公开的具体结构和功能细节,仅仅是为了描述具体实施例,是代表性的,但是本申请可以通过许多替换形式来具体实现,不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中,术语“第一”、“第二”仅用于描述目的,而不能理解为指示相对重要性,或者隐含指明所指示的技术特征的数量。由此,除非另有说明,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征;“多个”的含义是两个或两个以上。术语“包括”及其任何变形,意为不排他的包含,可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外,“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语,是基于附图所示的方位或相对位置关系描述的,仅是为了便于描述本申请的简化描述,而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。
此外,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,或是两个元件内部的连通。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本发明作进一步说明。
如图1至图2所示,本发明实施例公布了一种阵列基板110,包括薄膜晶体管120,薄膜晶体管120包括衬底121、第一金属层122、绝缘层123、半导体层124、阻挡层125、第二金属层126、第一钝化层131和像素电极129;第一金属层122,形成于衬底121表面;绝缘层123,覆盖在第一金属层122表面;半导体层124,覆盖在绝缘层123表面;阻挡层125,覆盖在半导体层124和绝缘层123表面;第二金属层126,覆盖在阻挡层125表面;第二金属层126包括源极127和漏极128;第一钝化层131覆盖在第二金属层126表面;像素电极129,设于第一钝化层131上方;阻挡层125上对应源极127和漏极128位置设有连接槽134,连接槽134一端连接源极127与半导体层124,另一端连接漏极128与半导体层124。
本案中,显示面板100适用于第一钝化层131上方紧贴像素电极129的面板,同样也适用于第一钝化层131上方还有其他层的面板,层层贴于表面,像素电极129设于第一钝化层131的上方,第一钝化层131上方不排除有其他层的可能性,第一金属层122为栅极,第二金属层126包括源极127和漏极128,对应源极127和漏极128位置设有连接槽,连接形成闭合通槽,连接半导体层127与源漏电极形成通路,只需对应闭合通槽处进行刻蚀,相对范例性的薄膜晶体管120尺寸面积小的来说,本案的蚀刻区域较小,其他区域依然保留阻挡层125,所以绝缘层123上还覆盖着阻挡层125,防止了阻挡层125过蚀刻损伤到绝缘层123,引起画面异常等问题,对大尺寸且分辨率要求高的面板像素设计具有一定的优势。
如图3至4所示,在一实施例中,连接槽134包括第一连接槽135与第二连接槽136;第一连接槽135与第二连接槽136首尾相互连接,形成闭环的通槽结构。
本案中,连接槽134包括第一连接槽135和第二连接槽136,互相连接形成一个闭合的四边形通槽,闭合通槽相对于范例性只有两个过孔来讲,范例性的过孔的尺寸会限制薄膜晶体管120的尺寸,而本申请的通槽的大小不会限制到薄膜晶体管120的大小,且外环形不会受限于薄膜晶体管120,就算通槽很大,也不会影响到薄膜晶体管120的尺寸。
如图4所示,在一实施例中,第一连接槽135的宽度等于第二连接槽136的宽度,第一连接槽135的长度等于第二连接槽136的长度。
本案中,第一连接槽135的宽度为W1,第二连接槽136的宽度为W2,通槽的宽度等于通孔的宽度,第一连接槽135的长度为L1,第二连接槽136的长度为L2,长度一致,整个连接槽形成闭合通槽,制程时不需要额外的调节,长宽一致,制程稳定,更不会因为通槽的整个宽度不一,造成电子的迁移率下降,影响源极127和漏极128的导通。
如图1所示,在一实施例中,连接槽134包括第一连接槽135;第一连接槽135连接源极127与漏极128形成开环的通槽结构。
本案中,通槽相对于上一实施方式来说,通槽的区域变小了,刻蚀区域对应通槽区域刻蚀,刻蚀区域相对更小了,其他区域除了通槽区域都覆盖着阻挡层125,刻蚀损伤下层的绝缘层123的几率就更小了,对绝缘层123的保护范围增大,减小过刻蚀引起的绝缘层123做薄的风险。
在一实施例中,连接槽的尺寸宽度范围为3-15μm。
本案中,故通槽的大小范围可以为3-15μm,尺寸再大薄膜晶体管120尺寸也不会影响,但是为了防止过蚀刻的问题,防止绝缘层123做薄,在此范围内比较合适。
如图2所示,在一实施例中,薄膜晶体管120包括色阻层133,覆盖在第一钝化层131表面;第二钝化层132,覆盖在色阻层133表面;像素电极129覆盖在第二钝化层132表面;接触孔130,接触孔130贯穿第一钝化层131、色阻层133与第二钝化层132,像素电极129通过接触孔130与漏极128连接。
本案中,色阻层133为红色阻层133,也可为蓝色阻和绿色组,第二钝化层132保护色阻层133,接触孔130贯穿第一钝化层131、色阻层133和第二钝化层132,像素电极129通过接触孔130与漏极128连接形成通路。
如图5所示,在一实施例中,薄膜晶体管120包括接触孔
130,第三接触孔130贯穿第一钝化层131,像素电极129通过第三接触孔130与漏极128连接。
本案中,第一钝化层131覆盖在第二金属层126上,第三接触孔130贯穿第一钝化层131,像素电极129通过第三接触孔130与漏极128连接,形成通路。
如图6所示,作为本发明的另一实施例,公开了一种阵列基板的制作方法。制作方法包括:
在衬底上形成第一金属层和绝缘层;
在绝缘层上形成半导体层和阻挡层;
在阻挡层上形成连接槽;
在阻挡层上覆盖第二金属层;
在第二金属层上形成第一钝化层;
在第一钝化层形成像素电极;
在像素电极上形成接触孔,贯穿第一钝化层。
如图6所示,在一实施例中,连接槽的制作方法包括:
涂布阻挡层材料;
在阻挡层上涂布光阻;
利用光罩进行对其曝光显影;
刻蚀得到连接槽。
如图2至4所示,作为本发明的另一实施例,公开了一种阵列基板110。包括薄膜晶体管120,薄膜晶体管120包括衬底121、第一金属层122、绝缘层123、半导体层124、阻挡层125、第二金属层126、第一钝化层131和像素电极129;第一金属层122,形成于衬底121表面;绝缘层123,覆盖在第一金属层122表面;半导体层124,覆盖在绝缘层123表面;阻挡层125,覆盖在半导体层124和绝缘层123表面;第二金属层126,覆盖在阻挡层125表面;第二金属层126包括源极127和漏极128;第一钝化层131覆盖在第二金属层126表面;像素电极129,设于第一钝化层131上方;阻挡层125上对应源极127和漏极128位置设有连接槽134,连接槽134包括第一连接槽135与第二连接槽136;第一连接槽135与第二连接槽136首尾相互连接,形成环形通槽,连接源极127、漏极128和半导体层124,第一连接槽135的宽度等于第二连接槽136的宽度,宽度范围为3-15μm。
本案中,环形通槽,由两个小连接槽组成,相对于范例性的薄膜晶体管120器件小的来讲,本案比范例性的刻蚀区域减小,范例性的刻蚀区域比较大,刻蚀区域大,容易出现刻蚀不均匀(蚀刻不干净或者过蚀刻),过蚀刻容易刻蚀到刻蚀阻挡层125下面的绝缘层123,从而使绝缘层123膜厚减薄,易漏电,而本申请中,蚀刻环形通槽,刻蚀区域较小,即防止了蚀刻不完全,又防止阻挡层125过蚀刻损伤到绝缘层123,引起画面异常等问题,对大尺寸且分辨率要求高的面板像素设计具有一定的优势。
如图1至7所示,作为本发明的另一实施例,公开了一种显示面板100。显示面板100包括上述的阵列基板110。
需要说明的是,本方案中涉及到的各步骤的限定,在不影响具体方案实施的前提下,并不认定为对步骤先后顺序做出限定,写在前面的步骤可以是在先执行的,也可以是在后执行的,甚至也可以是同时执行的,只要能实施本方案,都应当视为属于本发明的保护范围。
本发明的技术方案可以广泛用于各种显示面板,如TN型显示面板(全称为TwistedNematic,即扭曲向列型面板)、IPS型显示面板(In-Plane Switching,平面转换)、VA型显示面板(VerticaAignment,垂直配向技术),当然,也可以是其他类型的显示面板,如有机发光显示面板(organic light emitting diode,简称OLED显示面板),均可适用上述方案。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。
Claims (10)
1.一种阵列基板,其特征在于,包括薄膜晶体管,所述薄膜晶体管包括:
衬底;
第一金属层,形成于所述衬底表面;
绝缘层,覆盖在所述第一金属层表面;
半导体层,覆盖在所述绝缘层表面;
阻挡层,覆盖在所述半导体层和绝缘层表面;
第二金属层,覆盖在所述阻挡层表面;所述第二金属层包括源极和漏极;
第一钝化层覆盖在所述第二金属层表面;
像素电极,设于第一钝化层上方;
所述阻挡层上对应源极和漏极位置设有连接槽,所述连接槽一端连接源极与半导体层,另一端连接漏极与半导体层,所述源极通过连接槽与所述半导体层电连接;所述漏极通过连接槽与所述半导体层电连接;所述连接槽位于所述第二金属层与所述半导体层之间。
2.如权利要求1所述的一种阵列基板,其特征在于,所述连接槽包括第一连接槽与第二连接槽;
所述第一连接槽与第二连接槽首尾相互连接,形成闭环的通槽结构。
3.如权利要求2所述的一种阵列基板,其特征在于,所述第一连接槽的宽度等于第二连接槽的宽度,第一连接槽的长度等于第二连接槽的长度。
4.如权利要求1所述的一种阵列基板,其特征在于,所述连接槽包括第一连接槽;
所述第一连接槽连接所述源极与所述漏极形成开环的通槽结构。
5.如权利要求3所述的一种阵列基板,其特征在于,所述连接槽的宽度范围为3-15μm。
6.如权利要求1所述的一种阵列基板,其特征在于,所述薄膜晶体管包括色阻层,覆盖在第一钝化层表面;
第二钝化层,覆盖在所述色阻层表面;
所述像素电极覆盖在所述第二钝化层表面;
接触孔,所述接触孔贯穿第一钝化层、色阻层与第二钝化层,所述像素电极通过所述接触孔与漏极连接。
7.如权利要求1所述的一种阵列基板,其特征在于,所述薄膜晶体管包括接触孔,所述接触孔贯穿第一钝化层,所述像素电极通过接触孔与漏极连接。
8.一种阵列基板的制作方法,所述制作方法包括:
在衬底上形成第一金属层和绝缘层;
在绝缘层上形成半导体层和阻挡层;
在阻挡层上形成连接槽;
在阻挡层上覆盖第二金属层;
在第二金属层上形成第一钝化层;
在第一钝化层形成像素电极;
在像素电极上形成接触孔,贯穿第一钝化层;
其中,所述第二金属层包括源极和漏极,所述连接槽一端连接源极与半导体层,另一端连接漏极与半导体层,所述源极通过连接槽与所述半导体层电连接;所述漏极通过连接槽与所述半导体层电连接;所述连接槽位于所述第二金属层与所述半导体层之间。
9.如权利要求8所述的一种阵列基板的制作方法,其特征在于,所述连接槽的制作方法包括:
涂布阻挡层材料;
在阻挡层上涂布光阻;
利用光罩进行对其曝光显影;
刻蚀得到连接槽。
10.一种显示面板,其特征在于,包括如权利要求1至7任意一项所述的阵列基板。
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