CN105932024B - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

Info

Publication number
CN105932024B
CN105932024B CN201610293562.9A CN201610293562A CN105932024B CN 105932024 B CN105932024 B CN 105932024B CN 201610293562 A CN201610293562 A CN 201610293562A CN 105932024 B CN105932024 B CN 105932024B
Authority
CN
China
Prior art keywords
source electrode
data line
metal layer
layer
core material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610293562.9A
Other languages
English (en)
Other versions
CN105932024A (zh
Inventor
刘正
张治超
陈曦
张小祥
刘明悬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201610293562.9A priority Critical patent/CN105932024B/zh
Publication of CN105932024A publication Critical patent/CN105932024A/zh
Priority to US15/560,374 priority patent/US20180190795A1/en
Priority to PCT/CN2017/078272 priority patent/WO2017190567A1/zh
Application granted granted Critical
Publication of CN105932024B publication Critical patent/CN105932024B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • H01L29/458Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays

Abstract

本发明提供一种阵列基板,所述阵列基板被划分为多个像素单元,每个所述像素单元内均设置有薄膜晶体管,所述薄膜晶体管包括有源层、设置在所述有源层上的钝化层、源极和漏极,所述钝化层上形成有贯穿所述钝化层的源极过孔、贯穿所述钝化层的漏极过孔和与所述源极过孔相连通的数据线槽,所述源极设置在所述源极过孔中,以与所述有源层相连,所述漏极设置在所述漏极过孔中,以与所述有源层相连,所述数据线设置在所述数据线槽中,以与相对应的所述源极电连接。本发明还提供一种阵列基板的制造方法和一种显示装置。本发明提供一种具有新结构的阵列基板,并且,该阵列基板的有源层不再受制造工艺的限制。

Description

阵列基板及其制造方法和显示装置
技术领域
本发明涉及显示技术领域,具体地,涉及一种阵列基板、该阵列基板的制造方法和包括该阵列基板的显示装置。
背景技术
薄膜晶体管是应用于阵列基板中的重要开关元件,根据有源层材料的不同,可以将薄膜晶体管划分为氧化物薄膜晶体管和多晶硅薄膜晶体管。
在制作形成多晶硅薄膜晶体管时,形成了有源层之后,可以直接在有源层上方形成金属层,然后再对金属层进行湿刻构图工艺,从而可以获得源极和漏极。
在制作形成氧化物薄膜晶体管时,形成了有源层之后,需要在有源层上方形成刻蚀阻挡层,然后再形成源极和漏极。
随着电子产品的多样化,对阵列基板的结构多样化也提出了要求,因此,如何提供一种具有新结构、便于制造的薄膜晶体管成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板、该阵列基板的制造方法和显示装置,所述阵列基板具有一种新的结构,符合市场对阵列基板结构多样化的要求。
为了实现上述目的,作为本发明的一个方面,提供一种阵列基板,所述阵列基板被划分为多个像素单元,每个所述像素单元内均设置有薄膜晶体管,所述薄膜晶体管包括有源层、设置在所述有源层上的钝化层、源极和漏极,其中,所述钝化层上形成有贯穿所述钝化层的源极过孔、贯穿所述钝化层的漏极过孔和与所述源极过孔相连通的数据线槽,所述源极设置在所述源极过孔中,以与所述有源层相连,所述漏极设置在所述漏极过孔中,以与所述有源层相连,所述数据线设置在所述数据线槽中,以与相对应的所述源极电连接。
优选地,所述源极、所述漏极和所述数据线的上表面与所述钝化层的上表面平齐。
优选地,所述源极包括源极防扩散金属层和源极芯材,所述源极防扩散金属层位于所述源极芯材和所述源极过孔的外表面之间;
所述漏极包括漏极防扩散金属层和漏极芯材,所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间;
所述数据线包括数据线防扩散金属层和数据线芯材,所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间。
优选地,所述源极芯材、所述漏极芯材和所述数据线芯材均由铜制成,所述源极防扩散金属层、所述漏极防扩散金属层和所述数据线防扩散层均由钼或者钼合金制成。
优选地,所述阵列基板还包括设置在每个所述像素单元中的像素电极,所述像素电极形成在所述钝化层上,并与所述漏极电连接。
优选地,所述阵列基板还包括多个源极保护件和多个数据线上保护件,每个源极对应一个所述源极保护件,每条所述数据线对应一个所述数据线上保护件,所述源极保护件和所述数据线上保护件与所述像素电极同层设置,且材料相同。
优选地,所述有源层由氧化物制成。
优选地,所述阵列基板包括栅极、栅线和栅极绝缘层,所述栅极绝缘层设置在所述栅极所在的层和所述有源层之间,并位于所述有源层下方,所述阵列基板还包括多个数据线下保护件,所述数据线下保护件与所述有源层同层设置,每条所述数据线对应一个所述数据线下保护件,且所述数据线下保护件位于相对应的数据线的下方。
作为本发明的另一个方面,提供一种阵列基板的制作方法,其中,所述制造方法包括:
在衬底上形成包括有源层的图形,所述衬底被划分为多个像素单元,每个所述像素单元内均形成有所述有源层;
在包括有源层的图形上方形成钝化层;
在所述钝化层上形成源极过孔、漏极过孔和数据线槽,所述源极过孔和所述漏极过孔均贯穿所述钝化层,所述源极过孔和所述漏极过孔位于所述有源层上方,所述数据线槽与相对应的所述源极过孔相通;
形成包括源极、漏极和数据线的图形,其中,所述源极位于所述源极过孔中,所述漏极位于所述漏极过孔中,所述数据线位于所述数据线槽中,并与相应的所述源极电连接。
优选地,形成包括源极、漏极和数据线的图形的步骤包括:
形成金属层,所述金属层的部分材料落入所述源极过孔、所述漏极过孔和所述数据线槽中;
对所述金属层进行研磨,去除所述金属层中位于所述钝化层上表面上的部分,以使得所述金属层中所述源极过孔中的部分形成为所述源极、所述金属层中位于所述漏极过孔中的部分形成为所述漏极、所述金属层中位于所述数据线槽中的部分形成为所述数据线。
优选地,所述源极包括源极防扩散金属层和源极芯材,所述源极防扩散金属层位于所述源极芯材和所述源极过孔的外表面之间;
所述漏极包括漏极防扩散金属层和漏极芯材,所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间;
所述数据线包括数据线防扩散金属层和数据线芯材,所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间;
形成金属层的步骤包括:
形成防扩散金属层;
形成芯材金属层,其中,
对所述金属层进行研磨的步骤中,所述防扩散金属层位于所述源极过孔中的部分形成为所述源极防扩散金属层,所述芯材金属层位于所述源极过孔中的部分形成为所述源极芯材,所述防扩散金属层位于所述漏极过孔中的部分形成为所述漏极防扩散金属层,所述芯材金属层位于所述漏极过孔中的部分形成为所述漏极芯材,所述防扩散金属层位于所述数据线槽中的部分形成为所述数据线防扩散金属层,所述芯层金属层中位于所述数据线槽中的部分形成为所述数据线芯材。
优选地,所述防扩散金属层由钼或者钼合金制成,所述芯层金属层由铜制成。
优选地,在对所述金属层进行研磨的步骤中,利用化学机械研磨法对所述金属层进行研磨。
优选地,在对所述金属层进行研磨的步骤中,采用的研磨液包括研磨颗粒和水的混合物。
优选地,所述方法包括在化学研磨之后进行的:
形成包括像素电极、源极保护件、和数据线上保护件的图形的步骤,每个所述像素单元内均设置有一个所述像素电极,所述像素电极与所述漏极电连接,每个所述源极对应一个所述源极保护件,每条所述数据线对应一个所述数据线上保护件,所述源极保护件覆盖在所述源极的上方,所述数据线上保护件覆盖在所述数据线上方。
优选地,所述有源层由金属氧化物制成。
优选地,所述制造方法包括在衬底上形成包括有源层的图形的步骤之前进行的:
提供衬底,包括:
提供玻璃基板;
在所述玻璃基板上形成包括栅极和栅线的图形;
形成栅极绝缘层;
所述包括有源层的图形还包括多个数据线下保护件,每条所述数据线对应一个所述数据线下保护件,且所述数据线下保护件位于相对应的数据线的下方。
作为本发明的还一个方面,提供一种显示装置,所述显示装置包括阵列基板,其中,所述阵列基板为本发明所提供的上述阵列基板。
在制造本发明所提供的阵列基板时,形成了源极过孔、漏极过孔和数据线槽之后,直接在钝化层上设置金属层,金属层的材料可以落入源极过孔、漏极过孔和数据线槽中。接下来,利用研磨的方法将钝化层上方多余的金属打磨掉,源极过孔中残留的金属层材料形成为源极,漏极过孔中残留的金属层材料形成为漏极,数据线槽中残留的金属层材料形成为数据线。由此可知,在对金属层进行图形化时,无需用到掩模板,从而可以节约成本。
并且,在本发明所提供的阵列基板中,对形成有源层的具体材料并没有特殊的限制,既可以利用多晶硅材料制造有源层,也可以用氧化物(例如,IGZO)制造有源层。
本发明提供一种具有新结构的阵列基板,并且,该阵列基板的有源层不再受制造工艺的限制。
附图说明
附图是用来提供对本发明的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本发明,但并不构成对本发明的限制。在附图中:
图1是本发明所提供的阵列基板中,薄膜晶体管的剖视结构图;
图2是本发明所提供的阵列基板的一部分的俯视结构图;
图3是制造所述阵列基板时,形成了公共电极后的衬底;
图4是制造所述阵列基板时,形成了包括栅极的图形之后的衬底;
图5是制造所述阵列基板时,形成了包括有源层的图形之后的衬底;
图6是部分有源层图形的俯视图;
图7制造所述阵列基板时,在钝化层上形成源极过孔和漏极过孔的示意图;
图8是在制造阵列基板时,形成了金属层后的衬底;
图9是在制造阵列基板时,经过研磨步骤后的衬底。
附图标记说明
100:有源层 200:钝化层
300:金属层 310:源极
311:源极防扩散金属层 312:源极芯材
320:漏极 321:漏极防扩散金属层
322:漏极芯材 330:数据线
331:数据线防扩散金属层 332:数据线芯材
410:像素电极 420:源极保护层
500:公共电极 600:栅极
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明,并不用于限制本发明。
作为本发明的一个方面,提供一种阵列基板,所述阵列基板被划分为多个像素单元,每个所述像素单元内均设置有薄膜晶体管,所述薄膜晶体管包括有源层100、设置在该有源层100上的钝化层、源极310和漏极320,其中,钝化层100上形成有贯穿该钝化层100的源极过孔、贯穿该钝化层的漏极过孔100和与所述源极过孔相连通的数据线槽。源极310设置在所述源极过孔中,以与有源层100相连,漏极320设置在所述漏极过孔中,以与有源层100相连。如图2所示,数据线330设置在所述数据线槽中,以与相对应的源极310电连接。
本领域技术人员容易理解的是,图1中的薄膜晶体管部分是图2中A-A剖视图。并且,数据线与源极的对应关系也是本领域技术人员所公知的。作为本发明的一种实施方式,同一列像素单元中的薄膜晶体管的源极可以与同一条数据线相对应,当然,本发明并不限于此,数据线和源极也可以具有其他对应关系,这里不在一一列举。
在制造本发明所提供的阵列基板时,形成了源极过孔、漏极过孔和数据线槽之后,直接在钝化层200上设置金属层,金属层的材料可以落入源极过孔、漏极过孔和数据线槽中。接下来,利用研磨的方法将钝化层上方多余的金属打磨掉,源极过孔中残留的金属层材料形成为源极,漏极过孔中残留的金属层材料形成为漏极,数据线槽中残留的金属层材料形成为数据线。由此可知,在对金属层进行图形化时,无需用到掩模板,从而可以节约成本。
并且,在本发明所提供的阵列基板中,对形成有源层100的具体材料并没有特殊的限制,既可以利用多晶硅材料制造有源层100,也可以用氧化物(例如,IGZO)制造有源层100。
本发明提供一种具有新结构的阵列基板,并且,该阵列基板的有源层不再受制造工艺的限制。
为了便于利用研磨的方法获得所述阵列基板,作为本发明的一种优选实施方式,如图1所示,源极310、漏极320和所述数据线的上表面与钝化层200的上表面平齐。此处所用到的方位“上”是指图1中的上方。
本领域技术人员容易理解的是,在阵列基板中,源极、漏极以及数据线均是由金属材料制成。可以利用一种材料制成源极、漏极和数据线。也可以用多层不同金属材料形成的具有“堆叠结构”的金属层结构制成源极、漏极和数据线。其中,与钝化层200直接接触的一层金属可以用于防止其他层金属扩散。
具体地,如图1和图2所示,源极310包括源极防扩散金属层311和源极芯材312,源极防扩散金属层311位于源极芯材312和源极过孔的外表面之间。具体地,所述源极过孔的外表面包括所述源极过孔的侧壁和底壁,也就是说,源极防扩散金属层311直接与所述源极过孔的外表面相接触,防止形成源极芯材312的金属扩散。
漏极320包括漏极防扩散金属层321和漏极芯材322,漏极防扩散金属层321位于所述漏极过孔的外表面和漏极芯材322之间。具体地,所述漏极过孔的外表面包括所述漏极过孔的侧壁和底壁,也就是说,漏极防扩散金属层321直接与所述漏极过孔的外表面相接触,防止形成漏极芯材322的金属扩散。
如图2所示,数据线330包括数据线防扩散金属层331和数据线芯材332,数据线防扩散层331位于所述数据线槽的外表面和数据线芯材332之间。具体地,所述数据线槽的外表面包括所述数据线槽的侧壁和底壁,也就是说,数据线防扩散层331的直接与所述数据线槽的外表面相接触,防止形成数据线芯材332的金属扩散。
通常,利用导电性能较好的金属制成源极芯材312、漏极芯材312和数据线芯材332,优选地,源极芯材312、漏极芯材322和数据线芯材332均由铜制成。相应地,可以利用扩散性能较差的金属制成源极防扩散金属层311、漏极防扩散金属层321和数据线防扩散金属层331,优选地,源极防扩散金属层312、漏极防扩散金属层321和数据线防扩散层331均由钼或者钼合金制成。
本领域技术人员容易理解的是,所述阵列基板还包括设置在每个所述像素单元中的像素电极410,该像素电极410形成在钝化层200上,并与漏极320电连接。
如上所述,源极芯材312、漏极芯材322和数据线芯材332均由导电性能较好的材料制成。为了防止制作过程中源极芯材312和数据线芯材322被氧化,优选地,如图1所示,所述阵列基板还包括多个源极保护件420和多个数据线上保护件(未示出),每个源极对应一个源极保护件420,每条所述数据线对应一个所述数据线上保护件,所述源极保护件和所述数据线上保护件与像素电极410同层设置,且材料相同。
像素电极410由ITO制成,具有较好的抗氧化性能,从而可以对源极芯材和数据线芯材进行较好的保护。由于漏极芯材的上方覆盖有像素电极,因此,无需在漏极芯材上设置其他的保护层。
虽然在本发明中,对制成有源层100的材料并没有特殊的限制,优选地,有源层100由氧化物制成。具体地,有源层100可以由IGZO制成。
在本申请中,对薄膜晶体管的具体结构并没有特殊的限制,例如,所述薄膜晶体管可以具有底栅结构,如图中所示,所述阵列基板包括栅极600、栅线和栅极绝缘层,所述栅极绝缘层设置在所述栅极所在的层和所述有源层之间,并位于有源层100下方。如图2所示,所述阵列基板还包括多个数据线下保护件110,所述数据线下保护件110与所述有源层100同层设置,每条数据线330对应一个数据线下保护件110,且数据线下保护件110位于相对应的数据线330的下方。设置数据线下保护层的目的在于,防止刻蚀形成数据线槽时将数据下方的栅极绝缘层刻穿,从而可以避免栅线和数据线之间产生短路。
作为本发明的另一个方面,提供一种阵列基板的制作方法,其中,所述制造方法包括:
如图5所示,在衬底上形成包括有源层100的图形,所述衬底被划分为多个像素单元,每个所述像素单元内均形成有有源层100;
在包括有源层100的图形上方形成钝化层200,如图7所示;
在钝化层200上形成源极过孔310a、漏极过孔320a和数据线槽(未示出),源极过孔310a和漏极过孔320a均贯穿钝化层200,源极过孔310a和漏极过孔320a位于有源层100上方,如图7所示。其中,所述数据线槽与相对应的源极过孔310a相通;
形成包括源极310、漏极320和数据线的图形,其中,源极310位于所述源极过孔中,漏极320位于所述漏极过孔中,如图9所示。并且,所述数据线位于所述数据线槽中,并与相应的所述源极电连接。
利用本发明所提供的制造方法可以得到本发明所提供的上述阵列基板。
为了减少制造方法所用到的掩膜板的数量,并降低成本,优选地,形成包括源极、漏极和数据线的图形的步骤包括:
形成金属层300,该金属层300的部分材料落入所述源极过孔、所述漏极过孔中,如图8所示。并且,金属层300的部分材料还落入所述数据线槽中;
对金属层300进行研磨,去除金属层300中位于钝化层200上表面上的部分,以使得金属层300中所述源极过孔中的部分形成为源极310、金属层300中位于所述漏极过孔中的部分形成为漏极320、金属层300中位于所述数据线槽中的部分形成为所述数据线。
通过对金属层300进行研磨即可获得源极、漏极和数据线,从而可以减少制作方法中掩膜板的使用,降低制造方法的成本。
如上文中所述,作为本发明的一种优选实施方式,源极310包括源极防扩散金属层311和源极芯材312,源极防扩散金属层312位于源极芯材312和所述源极过孔的外表面之间。
漏极320包括漏极防扩散金属层321和漏极芯材322,漏极防扩散金属层321位于所述漏极过孔的外表面和漏极芯材322之间。
数据线330包括数据线防扩散金属层331和数据线芯材332,数据线防扩散层332位于所述数据线槽的外表面和数据线芯材332之间。
相应地,形成金属层300的步骤包括:
形成防扩散金属层300a;
形成芯材金属层300b。
对所述金属层进行研磨的步骤中,如图9所示,所述防扩散金属层位于所述源极过孔中的部分形成为源极防扩散金属层311,所述芯材金属层位于所述源极过孔中的部分形成为源极芯材312。所述防扩散金属层位于所述漏极过孔中的部分形成为漏极防扩散金属层321,所述芯材金属层位于所述漏极过孔中的部分形成为漏极芯材322。所述防扩散金属层位于所述数据线槽中的部分形成为数据线防扩散金属层331,所述芯层金属层中位于所述数据线槽中的部分形成为数据线芯材332。
优选地,所述防扩散金属层由钼或者钼合金制成,所述芯层金属层由铜制成。
为了提高掩膜效率,优选地,在对所述金属层进行研磨的步骤中,利用化学机械研磨法对所述金属层进行研磨。
优选地,在对所述金属层进行研磨的步骤中,采用的研磨液包括研磨颗粒和水的混合物,其中,研磨颗粒可以包括二氧化硅颗粒。除此之外,研磨液还可以包括调节研磨液流动性的添加剂等。
优选地,所述方法包括在化学研磨之后进行的:
形成包括像素电极、源极保护件、和数据线上保护件的图形的步骤,每个所述像素单元内均设置有一个所述像素电极,所述像素电极与所述漏极电连接,每个所述源极对应一个所述源极保护件,每条所述数据线对应一个所述数据线上保护件,所述源极保护件覆盖在所述源极的上方,所述数据线上保护件覆盖在所述数据线上方。
优选地,所述有源层由金属氧化物制成。
容易理解的是,所述制造方法包括在衬底上形成包括有源层的图形的步骤之前进行的:
提供衬底,包括:
提供玻璃基板;
在玻璃基板上形成包括栅极600和栅线的图形;
形成栅极绝缘层。
相应地,如图6所示,包括有源层的图形还包括多个数据线下保护件110,每条所述数据线对应一个数据线下保护件110,且数据线下保护件110位于相对应的数据线的下方。
在本发明中,衬底可以包括玻璃基板、形成在玻璃基板上的公共电极500、形成在玻璃基板上的包括栅极600的图形和覆盖包括栅极600的图形的栅极绝缘层。
因此,作为本发明的一种优选实施方式,提供衬底的步骤可以包括:
在玻璃基板上形成包括公共电极500的图形,如图3所示;
在玻璃基板上形成包括栅极600的图形,如图4所示;
在包括栅极600的图形和包括公共电极500的图形上方形成栅极绝缘层。
作为本发明的另一个方面,提供一种显示装置,所述显示装置包括阵列基板,其中,所述阵列基板为本发明所提供的上述阵列基板。
所述显示装置可以为:液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。

Claims (14)

1.一种阵列基板,所述阵列基板被划分为多个像素单元,每个所述像素单元内均设置有薄膜晶体管,所述薄膜晶体管包括有源层、设置在所述有源层上的钝化层、源极和漏极,其特征在于,所述钝化层上形成有贯穿所述钝化层的源极过孔、贯穿所述钝化层的漏极过孔和与所述源极过孔相连通的数据线槽,所述源极设置在所述源极过孔中,以与所述有源层相连,所述漏极设置在所述漏极过孔中,以与所述有源层相连,所述数据线设置在所述数据线槽中,以与相对应的所述源极电连接,
所述源极、所述漏极和所述数据线的上表面与所述钝化层的上表面平齐,所述源极、所述漏极和所述数据线是通过研磨工艺去除形成在所述钝化层上的金属材料位于所述钝化层的上表面以上的部分获得;
所述阵列基板包括栅极、栅线和栅极绝缘层,所述栅极绝缘层设置在所述栅极所在的层和所述有源层之间,并位于所述有源层下方,所述阵列基板还包括多个数据线下保护件,所述数据线下保护件与所述有源层同层设置,每条所述数据线对应一个所述数据线下保护件,且所述数据线下保护件位于相对应的数据线的下方。
2.根据权利要求1所述的阵列基板,其特征在于,所述源极包括源极防扩散金属层和源极芯材,所述源极防扩散金属层位于所述源极芯材和所述源极过孔的外表面之间;
所述漏极包括漏极防扩散金属层和漏极芯材,所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间;
所述数据线包括数据线防扩散金属层和数据线芯材,所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间。
3.根据权利要求2所述的阵列基板,其特征在于,所述源极芯材、所述漏极芯材和所述数据线芯材均由铜制成,所述源极防扩散金属层、所述漏极防扩散金属层和所述数据线防扩散层均由钼或者钼合金制成。
4.根据权利要求1至3中任意一项所述的阵列基板,其特征在于,所述阵列基板还包括设置在每个所述像素单元中的像素电极,所述像素电极形成在所述钝化层上,并与所述漏极电连接。
5.根据权利要求4所述的阵列基板,其特征在于,所述阵列基板还包括多个源极保护件和多个数据线上保护件,每个源极对应一个所述源极保护件,每条所述数据线对应一个所述数据线上保护件,所述源极保护件和所述数据线上保护件与所述像素电极同层设置,且材料相同。
6.根据权利要求1至3中任意一项所述的阵列基板,其特征在于,所述有源层由氧化物制成。
7.一种阵列基板的制造方法,其特征在于,所述制造方法包括:
在衬底上形成包括有源层的图形,所述衬底被划分为多个像素单元,每个所述像素单元内均形成有所述有源层;
在包括有源层的图形上方形成钝化层;
在所述钝化层上形成源极过孔、漏极过孔和数据线槽,所述源极过孔和所述漏极过孔均贯穿所述钝化层,所述源极过孔和所述漏极过孔位于所述有源层上方,所述数据线槽与相对应的所述源极过孔相通;
形成包括源极、漏极和数据线的图形,其中,所述源极位于所述源极过孔中,所述漏极位于所述漏极过孔中,所述数据线位于所述数据线槽中,并与相应的所述源极电连接,
形成包括源极、漏极和数据线的图形的步骤包括:
形成金属层,所述金属层的部分材料落入所述源极过孔、所述漏极过孔和所述数据线槽中;
对所述金属层进行研磨,去除所述金属层中位于所述钝化层上表面上的部分,以使得所述金属层中所述源极过孔中的部分形成为所述源极、所述金属层中位于所述漏极过孔中的部分形成为所述漏极、所述金属层中位于所述数据线槽中的部分形成为所述数据线;
所述制造方法还包括在衬底上形成包括有源层的图形的步骤之前进行的:
提供衬底,包括:
提供玻璃基板;
在所述玻璃基板上形成包括栅极和栅线的图形;
形成栅极绝缘层;
所述包括有源层的图形还包括多个数据线下保护件,每条所述数据线对应一个所述数据线下保护件,且所述数据线下保护件位于相对应的所述数据线的下方。
8.根据权利要求7所述的制造方法,其特征在于,所述源极包括源极防扩散金属层和源极芯材,所述源极防扩散金属层位于所述源极芯材和所述源极过孔的外表面之间;
所述漏极包括漏极防扩散金属层和漏极芯材,所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间;
所述数据线包括数据线防扩散金属层和数据线芯材,所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间;
形成金属层的步骤包括:
形成防扩散金属层;
形成芯材金属层,其中,
对所述金属层进行研磨的步骤中,所述防扩散金属层位于所述源极过孔中的部分形成为所述源极防扩散金属层,所述芯材金属层位于所述源极过孔中的部分形成为所述源极芯材,所述防扩散金属层位于所述漏极过孔中的部分形成为所述漏极防扩散金属层,所述芯材金属层位于所述漏极过孔中的部分形成为所述漏极芯材,所述防扩散金属层位于所述数据线槽中的部分形成为所述数据线防扩散金属层,所述芯材金属层中位于所述数据线槽中的部分形成为所述数据线芯材。
9.根据权利要求8所述的制造方法,其特征在于,所述防扩散金属层由钼或者钼合金制成,所述芯材 金属层由铜制成。
10.根据权利要求7所述的制造方法,其特征在于,在对所述金属层进行研磨的步骤中,利用化学机械研磨法对所述金属层进行研磨。
11.根据权利要求7所述的制造方法,其特征在于,在对所述金属层进行研磨的步骤中,采用的研磨液包括研磨颗粒和水的混合物。
12.根据权利要求7至11中任意一项所述的制造方法,其特征在于,所述方法包括在化学研磨之后进行的:
形成包括像素电极、源极保护件、和数据线上保护件的图形的步骤,每个所述像素单元内均设置有一个所述像素电极,所述像素电极与所述漏极电连接,每个所述源极对应一个所述源极保护件,每条所述数据线对应一个所述数据线上保护件,所述源极保护件覆盖在所述源极的上方,所述数据线上保护件覆盖在所述数据线上方。
13.根据权利要求7至11中任意一项所述的制造方法,其特征在于,所述有源层由金属氧化物制成。
14.一种显示装置,所述显示装置包括阵列基板,其特征在于,所述阵列基板为权利要求1至6中任意一项所述的阵列基板。
CN201610293562.9A 2016-05-05 2016-05-05 阵列基板及其制造方法和显示装置 Active CN105932024B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201610293562.9A CN105932024B (zh) 2016-05-05 2016-05-05 阵列基板及其制造方法和显示装置
US15/560,374 US20180190795A1 (en) 2016-05-05 2017-03-27 Array Substrate, Manufacturing Method Thereof, and Display Device
PCT/CN2017/078272 WO2017190567A1 (zh) 2016-05-05 2017-03-27 阵列基板及其制造方法和显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610293562.9A CN105932024B (zh) 2016-05-05 2016-05-05 阵列基板及其制造方法和显示装置

Publications (2)

Publication Number Publication Date
CN105932024A CN105932024A (zh) 2016-09-07
CN105932024B true CN105932024B (zh) 2019-05-24

Family

ID=56835114

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610293562.9A Active CN105932024B (zh) 2016-05-05 2016-05-05 阵列基板及其制造方法和显示装置

Country Status (3)

Country Link
US (1) US20180190795A1 (zh)
CN (1) CN105932024B (zh)
WO (1) WO2017190567A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105932024B (zh) * 2016-05-05 2019-05-24 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置
CN110534659B (zh) * 2018-05-23 2022-09-27 昆明申北科技有限公司 顶发光oled的阳极结构、显示装置及其制造方法
CN109659313B (zh) * 2018-11-12 2021-04-02 惠科股份有限公司 一种阵列基板、阵列基板的制作方法和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1819125A (zh) * 2005-03-22 2006-08-16 广辉电子股份有限公司 一种薄膜晶体管与液晶显示器的制造方法
CN1932599A (zh) * 2006-10-13 2007-03-21 友达光电股份有限公司 液晶显示器用基板的制作方法
CN101364572A (zh) * 2007-08-10 2009-02-11 群康科技(深圳)有限公司 薄膜晶体管基板制造方法
CN103018990A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种阵列基板和其制备方法、及液晶显示装置
CN103137630A (zh) * 2011-11-30 2013-06-05 三星显示有限公司 薄膜晶体管阵列基板、其制造方法以及有机发光显示设备
CN103715203A (zh) * 2013-12-26 2014-04-09 合肥京东方光电科技有限公司 阵列基板及其制造方法和显示装置
CN104766891A (zh) * 2015-03-18 2015-07-08 华南理工大学 一种薄膜晶体管的源漏电极及制备方法、薄膜晶体管及制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391780B1 (en) * 1999-08-23 2002-05-21 Taiwan Semiconductor Manufacturing Company Method to prevent copper CMP dishing
KR100846974B1 (ko) * 2006-06-23 2008-07-17 베이징 보에 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 Tft lcd 어레이 기판 및 그 제조 방법
TWI613824B (zh) * 2011-12-23 2018-02-01 半導體能源研究所股份有限公司 半導體裝置
CN105932024B (zh) * 2016-05-05 2019-05-24 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1819125A (zh) * 2005-03-22 2006-08-16 广辉电子股份有限公司 一种薄膜晶体管与液晶显示器的制造方法
CN1932599A (zh) * 2006-10-13 2007-03-21 友达光电股份有限公司 液晶显示器用基板的制作方法
CN101364572A (zh) * 2007-08-10 2009-02-11 群康科技(深圳)有限公司 薄膜晶体管基板制造方法
CN103137630A (zh) * 2011-11-30 2013-06-05 三星显示有限公司 薄膜晶体管阵列基板、其制造方法以及有机发光显示设备
CN103018990A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种阵列基板和其制备方法、及液晶显示装置
CN103715203A (zh) * 2013-12-26 2014-04-09 合肥京东方光电科技有限公司 阵列基板及其制造方法和显示装置
CN104766891A (zh) * 2015-03-18 2015-07-08 华南理工大学 一种薄膜晶体管的源漏电极及制备方法、薄膜晶体管及制备方法

Also Published As

Publication number Publication date
US20180190795A1 (en) 2018-07-05
CN105932024A (zh) 2016-09-07
WO2017190567A1 (zh) 2017-11-09

Similar Documents

Publication Publication Date Title
US9673300B2 (en) Semiconductor devices including a gate core and a fin active core and methods of fabricating the same
US9761593B2 (en) Semiconductor device
US9704865B2 (en) Semiconductor devices having silicide and methods of manufacturing the same
CN106920838A (zh) 半导体器件及其制造方法
US10319679B2 (en) Semiconductor device
JP2007250705A (ja) 半導体集積回路装置及びダミーパターンの配置方法
WO2014190702A1 (zh) 阵列基板及其制作方法、显示装置
CN105932024B (zh) 阵列基板及其制造方法和显示装置
WO2017118096A1 (zh) 显示基板及其制作方法、显示装置
TW201444053A (zh) 具有虛擬閘極及閘極的半導體裝置
US9356018B2 (en) Semiconductor devices and methods of fabricating the same
JP2009044004A (ja) 半導体装置およびその製造方法
CN111403423B (zh) 显示基板及其制备方法、显示面板和显示装置
CN103247531A (zh) 薄膜晶体管及其制作方法及显示器
CN107134459B (zh) 显示背板及其制作方法和显示装置
KR101661030B1 (ko) 시차를 둔 니켈 실리콘과 니켈 게르마늄 구조의 형성
CN106129063B (zh) 薄膜晶体管阵列基板及其制造方法
JP2012089772A (ja) 半導体装置の製造方法
CN105304566A (zh) 一种半导体器件及其制造方法、电子装置
TWI830244B (zh) 半導體裝置
KR101926362B1 (ko) 반도체 소자 제조 방법
CN108121933B (zh) 一种半导体器件及其制备方法、电子装置
CN106328546A (zh) 一种半导体器件及其制造方法、电子装置
US10381379B2 (en) Array substrate and manufacturing method thereof, and display device
US20120139058A1 (en) Power mos device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant