WO2020097998A1 - 阵列基板、阵列基板的制作方法和显示面板 - Google Patents

阵列基板、阵列基板的制作方法和显示面板 Download PDF

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Publication number
WO2020097998A1
WO2020097998A1 PCT/CN2018/118415 CN2018118415W WO2020097998A1 WO 2020097998 A1 WO2020097998 A1 WO 2020097998A1 CN 2018118415 W CN2018118415 W CN 2018118415W WO 2020097998 A1 WO2020097998 A1 WO 2020097998A1
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Prior art keywords
layer
connection groove
array substrate
connection
contact hole
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PCT/CN2018/118415
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English (en)
French (fr)
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宋振莉
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惠科股份有限公司
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Priority to US17/041,439 priority Critical patent/US11456322B2/en
Publication of WO2020097998A1 publication Critical patent/WO2020097998A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate, a method for manufacturing the array substrate, and a display panel.
  • liquid crystal displays LCD, Liquid
  • organic electroluminescent displays OELD or OLED, Organic-luminescent Display
  • LCD liquid crystal displays
  • OELD organic electroluminescent display
  • OLED Organic-luminescent Display
  • the thin film transistor process is relatively stable, but the large area of the thin film transistor affects the aperture ratio; the other is the structure with a small area of the thin film transistor.
  • the thin film transistor area is small, prone to uneven etching (etching is not clean or over-etching), over-etching is easy to etch to the insulating layer under the etch barrier.
  • the present application provides an array substrate, a method for manufacturing the array substrate, and a display panel, to solve the structure of a thin film transistor with a small area, so as to prevent the insulating layer from being thinned due to over-etching.
  • the present application also discloses an array substrate including a thin film transistor
  • the thin film transistor includes: a substrate, a first metal layer, an insulating layer, a semiconductor layer, a barrier layer, a second metal layer, a first passivation layer, and a pixel electrode; a first metal layer is provided on the surface of the substrate; An insulating layer covering the surface of the first metal layer; a semiconductor layer covering the surface of the insulating layer; a barrier layer covering the surfaces of the semiconductor layer and the insulating layer; a second metal layer covering the barrier The surface of the layer; the second metal layer includes a source and a drain; a first passivation layer covers the surface of the second metal layer; and, a pixel electrode is provided above the first passivation layer; wherein, the barrier A connection groove is provided on the layer corresponding to the positions of the source electrode and the drain electrode. One end of the connection groove connects the source electrode and the semiconductor layer, and the other end connects the drain electrode and the semiconductor layer.
  • connection slot includes a first connection slot and a second connection slot; the first connection slot and the second connection slot are connected end to end, and a closed-loop through slot structure is provided.
  • the width of the first connection groove is equal to the width of the second connection groove.
  • the length of the first connection groove is equal to the length of the second connection groove.
  • connection groove includes a first connection groove; the first connection groove connects the source electrode and the drain electrode to provide an open-loop through-groove structure.
  • the width of the connection groove ranges from 3 microns to 15 microns.
  • the thin film transistor includes a color resist layer, covering the surface of the first passivation layer;
  • the thin film transistor includes a contact hole, the contact hole penetrates the first passivation layer, and the pixel electrode is connected to the drain electrode through the contact hole.
  • the first metal layer is a gate.
  • the closed-loop through-groove structure is a quadrilateral through-groove.
  • the application also discloses a method for manufacturing an array substrate.
  • the method includes:
  • a semiconductor layer and a barrier layer are provided on the insulating layer;
  • a contact hole is provided on the pixel electrode, penetrating the first passivation layer.
  • the manufacturing method of the connection slot includes:
  • connection groove is obtained by etching.
  • the application also discloses a display panel.
  • the display panel includes an array substrate,
  • the array substrate includes a thin film transistor
  • the thin film transistor includes:
  • the first metal layer is provided on the surface of the substrate
  • a barrier layer covering the surface of the semiconductor layer and the insulating layer
  • the first passivation layer covers the surface of the second metal layer
  • the pixel electrode is provided above the first passivation layer
  • connection groove is provided on the barrier layer corresponding to the positions of the source electrode and the drain electrode, and one end of the connection groove connects the source electrode and the semiconductor layer, and the other end connects the drain electrode and the semiconductor layer.
  • connection slot includes a first connection slot and a second connection slot
  • the first connection slot and the second connection slot are connected end to end, and a closed-loop through slot structure is provided.
  • the width of the first connection groove is equal to the width of the second connection groove.
  • the length of the first connection slot is equal to the length of the second connection slot.
  • connection groove includes a first connection groove; the first connection groove connects the source electrode and the drain electrode to provide an open-loop through-groove structure.
  • the insulating layer is a gate oxide insulating layer.
  • the thin film transistor further includes a third contact hole, the third contact hole connects the source electrode and the semiconductor layer, and the second contact hole connects the drain electrode and the semiconductor to form a via.
  • the first contact hole, the second contact hole and the third contact hole have the same shape.
  • the barrier layer is etched by dry etching, because the area to be etched off by the etching barrier layer is too large, uneven etching is likely to occur (etching does not Clean or over-etched), over-etching is easy to etch to the insulating layer below the etch barrier layer, so that the thickness of the insulating layer is thinned and easy to leak, and the etching area in this application is small, which prevents incomplete etching It prevents the barrier layer from being overetched and damaged to the insulating layer, causing problems such as abnormal pictures, and has certain advantages for the pixel design of the display panel with a large size and high resolution.
  • FIG. 1 is a top view of a connection groove of a thin film transistor according to one embodiment of the present application.
  • FIG. 2 is a cross-sectional view of a thin film transistor connection groove AA 'according to one embodiment of the present application;
  • FIG. 3 is a top view of a connection groove of a thin film transistor according to one embodiment of the present application.
  • FIG. 4 is a top view of the barrier layer C according to one embodiment of the present application.
  • FIG. 5 is a schematic diagram of a thin film transistor connection groove AA 'according to one embodiment of the present application.
  • FIG. 6 is a schematic diagram of an array substrate manufacturing method according to one embodiment of the present application.
  • FIG. 7 is a schematic diagram of a method for manufacturing a connection slot according to one embodiment of the present application.
  • first and second are used only for descriptive purposes and cannot be understood as indicating relative importance, or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may expressly or implicitly include one or more of the features; “multiple” means two or more.
  • the term “comprising” and any variations thereof are meant to be non-exclusive and one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection It can also be an electrical connection; it can be directly connected, indirectly connected through an intermediary, or connected within two components.
  • an embodiment of the present application discloses an array substrate 110 including a thin film transistor 120.
  • the thin film transistor 120 includes a substrate 121, a first metal layer 122, an insulating layer 123, a semiconductor layer 124, and a barrier A layer 125, a second metal layer 126, a first passivation layer 131, and a pixel electrode 129; a first metal layer 122, which is provided on the surface of the substrate 121; an insulating layer 123, which covers the surface of the first metal layer 122; and a semiconductor layer 124, Covering the surface of the insulating layer 123; the barrier layer 125 covering the surfaces of the semiconductor layer 124 and the insulating layer 123; the second metal layer 126 covering the surface of the barrier layer 125; the second metal layer 126 includes the source electrode 127 and the drain electrode 128; A passivation layer 131 covers the surface of the second metal layer 126; the pixel electrode 129 is provided above the first passivation layer 131;
  • the display panel 100 is suitable for a panel close to the pixel electrode 129 above the first passivation layer 131, and is also applicable to a panel with other layers above the first passivation layer 131.
  • the layers are attached to the surface and the pixel electrode 129 is disposed above the first passivation layer 131.
  • the possibility of other layers is not excluded above the first passivation layer 131.
  • the first metal layer 122 is a gate
  • the second metal layer 126 includes a source 127 and a drain 128 , Corresponding to the source 127 and the drain 128 are provided with a connecting groove, and a closed through groove is connected to connect the semiconductor layer 127 and the source-drain electrode to form a path, and only needs to be etched corresponding to the closed through groove, as compared to the exemplary thin film transistor 120
  • the etching area in this case is small, and the barrier layer 125 is still reserved in other areas, so the insulating layer 123 is also covered with the barrier layer 125, which prevents the over-etching damage of the barrier layer 125 to the insulating layer 123, resulting in abnormal images
  • it has certain advantages for the design of large-size and high-resolution panel pixels.
  • connection groove 134 includes a first connection groove 135; the first connection groove 135 connects the source electrode 127 and the drain electrode 128 to provide an open-loop through-groove structure.
  • the area of the through-groove becomes smaller, the etching area corresponds to the etching of the through-groove area, the etching area is relatively smaller, and the other areas except the through-groove area are covered
  • the barrier layer 125 With the barrier layer 125, the chance of etching damage to the underlying insulating layer 123 is smaller, the protection range of the insulating layer 123 is increased, and the risk of thinning the insulating layer 123 due to over-etching is reduced.
  • the thin film transistor 120 includes a color resist layer 133 covering the surface of the first passivation layer 131; a second passivation layer 132 covering the surface of the color resist layer 133; and the pixel electrode 129 covering On the surface of the second passivation layer 132; a contact hole 130, the contact hole 130 penetrates the first passivation layer 131, the color resist layer 133 and the second passivation layer 132, and the pixel electrode 129 is connected to the drain electrode 128 through the contact hole 130.
  • the color resist layer 133 is a red resist layer 133 or a blue resist and a green group.
  • the second passivation layer 132 protects the color resist layer 133, and the contact hole 130 penetrates the first passivation layer 131 and the color resist layer 133 With the second passivation layer 132, the pixel electrode 129 is connected to the drain electrode 128 through the contact hole 130 to form a via.
  • connection slot 134 includes a first connection slot 135 and a second connection slot 136; the first connection slot 135 and the second connection slot 136 are connected to each other end to end, and a closed-loop through slot is provided structure.
  • the connection slot 134 includes a first connection slot 135 and a second connection slot 136, and a closed through slot is connected to each other.
  • the closed through slot has only two via holes relative to the exemplary one, and the size of the exemplary via hole may limit the film
  • the size of the transistor 120, and the size of the through groove of the present application will not be limited to the size of the thin film transistor 120, and the outer ring will not be limited to the thin film transistor 120, even if the through groove is large, it will not affect the thin film transistor 120 size.
  • the width of the first connection groove 135 is equal to the width of the second connection groove 136
  • the length of the first connection groove 135 is equal to the length of the second connection groove 136.
  • the width of the first connection groove 135 is W1
  • the width of the second connection groove 136 is W2
  • the width of the through groove is equal to the width of the through hole
  • the length of the first connection groove 135 is L1
  • the length of the second connection groove 136 is L2
  • the length is the same, the entire connection slot is provided with a closed through slot, no additional adjustment is required during the process, the length and width are consistent, the process is stable, and the mobility of the electrons will not be reduced due to the different width of the through slot, affecting the source electrode 127 and The drain 128 is turned on.
  • the size and width of the connection groove ranges from 3 ⁇ m to 15 ⁇ m. Therefore, the size of the through groove can be 3 ⁇ m to 15 ⁇ m, and the size of the thin film transistor 120 will not be affected. However, in order to prevent the over-etching problem and prevent the insulating layer 123 from being thin, it is more suitable within this range.
  • the closed channel structure is a quadrilateral channel. From the top view, it is seen that the two connecting grooves are provided with closed-loop quadrilateral vias.
  • the size of the quadrilateral closed via structure is not limited to the size of the thin film transistor 120, and the outer ring is not limited to the thin film transistor 120, even if the closed via structure is Very large, it will not affect the size of the thin film transistor 120.
  • an array substrate 110 is disclosed.
  • the thin film transistor 120 includes a substrate 121, a first metal layer 122, an insulating layer 123, a semiconductor layer 124, a barrier layer 125, a second metal layer 126, a first passivation layer 131 and a pixel electrode 129;
  • the first The metal layer 122 is provided on the surface of the substrate 121;
  • the insulating layer 123 covers the surface of the first metal layer 122;
  • the semiconductor layer 124 covers the surface of the insulating layer 123;
  • the barrier layer 125 covers the surfaces of the semiconductor layer 124 and the insulating layer 123;
  • the second metal layer 126 covers the surface of the barrier layer 125;
  • the second metal layer 126 includes the source electrode 127 and the drain electrode 128;
  • the first passivation layer 131 covers the surface of the second metal layer 126;
  • the pixel electrode 129 is provided on the first Above the passivation layer 131;
  • the connection layer 131 is provided on the
  • the connection groove 134 includes a first connection groove 135 and a second connection groove 136; the first connection groove 135 is connected to the second The grooves 136 are connected to each other end to end, and a ring-shaped through groove is provided to connect the source electrode 127, the drain electrode 128, and the semiconductor layer 124.
  • the width of the first connection groove 135 is equal to the width of the second connection groove 136, and the width ranges from 3 ⁇ m to 15 ⁇ m.
  • the ring-shaped through groove is composed of two small connection grooves.
  • this case is smaller than the exemplary etching area, and the exemplary etching area is relatively large.
  • the etching area is large, and uneven etching is easy to occur (etching is not clean or over-etching).
  • Over-etching is easy to etch to the insulating layer 123 under the etching barrier layer 125, so that the thickness of the insulating layer 123 is reduced, and leakage is easy.
  • the circular through-groove is etched, and the etching area is small, which prevents the etching from being incomplete, and prevents the barrier layer 125 from being over-etched and damaged to the insulating layer 123, causing problems such as abnormal pictures, and requires large size and high resolution.
  • the pixel design of the panel has certain advantages.
  • the thin film transistor 120 includes a contact hole 130, the third contact hole 130 penetrates the first passivation layer 131, and the pixel electrode 129 is connected to the drain electrode 128 through the third contact hole 130.
  • the first passivation layer 131 covers the second metal layer 126, the third contact hole 130 penetrates the first passivation layer 131, and the pixel electrode 129 is connected to the drain electrode 128 through the third contact hole 130 to form a via.
  • Production methods include:
  • a contact hole is provided on the pixel electrode, penetrating the first passivation layer.
  • the manufacturing method of the connection groove includes:
  • connection groove is obtained by etching.
  • a display panel 100 As shown in FIGS. 1 to 7, as another embodiment of the present application, a display panel 100 is disclosed.
  • the display panel 100 includes an array substrate 110 including: a thin film transistor 120, and the thin film transistor 120 includes:
  • the first metal layer 122 is provided on the surface of the substrate 121;
  • the insulating layer 123 covers the surface of the first metal layer 122;
  • the semiconductor layer 124 covers the surface of the insulating layer 123;
  • the barrier layer 125 covers the surfaces of the semiconductor layer 124 and the insulating layer 123;
  • the second metal layer 126 covers the surface of the barrier layer 125; the second metal layer 126 includes a source electrode and a drain electrode;
  • the first passivation layer 131 covers the surface of the second metal layer 126;
  • the pixel electrode 129 is disposed above the first passivation layer 131;
  • connection groove 134 is provided on the barrier layer 125 corresponding to the positions of the source electrode 127 and the drain electrode 128.
  • One end of the connection groove 134 connects the source electrode 128 and the semiconductor layer 124, and the other end connects the drain electrode 128 and the semiconductor layer 124.
  • the display panel 100 is suitable for a panel close to the pixel electrode 129 above the first passivation layer 131, and is also suitable for a panel with other layers above the first passivation layer 131.
  • the layers are attached to the surface and the pixel electrode 129 is disposed above the first passivation layer 131.
  • the possibility of other layers is not ruled out above the first passivation layer 131.
  • the first metal layer 122 is a gate.
  • the size and area are small In this case, the etched area is small, and the barrier layer 125 remains in other areas, so the insulating layer 123 is also covered with the barrier layer 125, which prevents the barrier layer 125 from being overetched and damaged to the insulating layer 123, causing problems such as abnormal pictures. And the panel pixel design with high resolution requirement has certain advantages.
  • connection slot 134 includes a first connection slot 135 and a second connection slot 136;
  • the first connection slot and the second connection slot are connected to each other end to end, and a closed-loop through slot structure is provided.
  • connection slot 134 includes a first connection slot 135 and a second connection slot 136, and a closed through slot is connected to each other.
  • the closed through slot has only two via holes relative to the exemplary one. The size will limit the size of the thin film transistor 120, and the size of the through slot of the present application will not be limited to the size of the thin film transistor 120.
  • the width of the first connection groove 135 is equal to the width of the second connection groove 136.
  • the width of the first connection groove 135 is W1
  • the width of the second connection groove 136 is W2
  • the width of the through groove is equal to the width of the through hole
  • the manufacturing process is stable, and it will not be caused by the different width of the through groove.
  • the mobility of electrons decreases, affecting the conduction of the source 127 and the drain 128.
  • the length of the first connection groove 135 is equal to the length of the second connection groove 136.
  • the length of the first connection groove 135 is L1
  • the length of the second connection groove 136 is L2.
  • the lengths are the same, and no additional adjustment is required during the manufacturing process.
  • connection groove 134 includes a first connection groove 135; the first connection groove 135 connects the source electrode 127 and the drain electrode 128 to provide an open-loop through-groove structure.
  • the area of the through groove becomes smaller, the etched area corresponds to the area of the through groove, and the etched area is relatively smaller.
  • the insulating layer is a gate oxide insulating layer, which is easy to block the mobility of electrons and has an excellent insulating effect.
  • the thin film transistor further includes a third contact hole, the third contact hole connects the source electrode and the semiconductor layer, and the second contact hole connects the drain electrode and the semiconductor to form a via.
  • the first contact hole, the second contact hole and the third contact hole have the same shape.
  • the range of electron migration is the same, and it will not cause the imbalance of electron transmission and damage the components because any one contact hole is too large.
  • the technical solution of the present application can be widely used in various display panels, such as TN type display panel (full name Twisted Nematic, namely twisted nematic panel), IPS type display panel (In-Plane Switching, plane conversion), VA type display
  • TN type display panel full name Twisted Nematic, namely twisted nematic panel
  • IPS type display panel In-Plane Switching, plane conversion
  • the panel (Vertical Alignment)
  • OLED display panel organic light emitting diode

Abstract

本申请公开了一种阵列基板、阵列基板的制作方法和显示面板。包括薄膜晶体管，薄膜晶体管包括衬底、第一金属层、绝缘层、半导体层、阻挡层、第二金属层、第一钝化层和像素电极；第二金属层包括源极和漏极；阻挡层上对应源极和漏极位置设有连接槽，连接槽一端连接源极与半导体层，另一端连接漏极与半导体层。

Description

阵列基板、阵列基板的制作方法和显示面板
本申请要求于2018年11月12日提交中国专利局，申请号为CN201811337216.1，申请名称为“一种阵列基板、阵列基板的制作方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、阵列基板的制作方法和显示面板。
背景技术
应当理解的是，这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着现代资讯科技的进步，在这些显示器中，由于液晶显示器(LCD，Liquid Crystal Display)及有机电激发光显示器(OELD或称为OLED，Organic Electro-luminescent Display)具有轻薄以及消耗功率低的优点，因此在市场中成为主流商品。范例性技术中刻蚀阻挡层存在两种薄膜晶体管结构，薄膜晶体管制程较为稳定，但薄膜晶体管面积较大，影响开口率；另一种是薄膜晶体管面积小的结构。
为了防止氧化铟镓锌背沟道的刻蚀损伤，薄膜晶体管面积虽小，容易出现刻蚀不均匀(蚀刻不干净或者过蚀刻)，过蚀刻容易刻蚀到刻蚀阻挡层下面的绝缘层。
申请内容
本申请提供了一种阵列基板、阵列基板的制作方法和显示面板，来解决薄膜晶体管面积小的结构，来防止过刻蚀导致绝缘层做薄。
本申请还公开了一种阵列基板，包括薄膜晶体管，
所述薄膜晶体管包括：衬底、第一金属层、绝缘层、半导体层、阻挡层、第二金属层、第一钝化层和像素电极；第一金属层，设置于所述衬底表面；绝缘层，覆盖在所述第一金属层表面；半导体层，覆盖在所述绝缘层表面；阻挡层，覆盖在所述半导体层和所述绝缘层表面；第二金属层，覆盖在所述阻挡层表面；所述第二金属层包括源极和漏极；第一钝化层覆盖在所述第二金属层表面；以及，像素电极，设于第一钝化层上方；其中，所述阻挡层上对应源极和漏极位置设有连接槽，所述连接槽一端连接源极与半导体层，另一端连接漏极与半导体层。
可选的，所述连接槽包括第一连接槽与第二连接槽；所述第一连接槽与第二连接槽首尾 相互连接，设置闭环的通槽结构。
可选的，所述第一连接槽的宽度等于第二连接槽的宽度。
可选的，所述第一连接槽的长度等于第二连接槽的长度。
可选的，所述连接槽包括第一连接槽；所述第一连接槽连接所述源极与所述漏极设置开环的通槽结构。
可选的，所述连接槽的宽度范围为3微米-15微米。
可选的，所述薄膜晶体管包括色阻层，覆盖在第一钝化层表面；
第二钝化层，覆盖在色阻层表面；所述像素电极覆盖在所述第二钝化层表面；接触孔，所述接触孔贯穿第一钝化层、色阻层与第二钝化层，所述像素电极通过所述接触孔与漏极连接。
可选的，所述薄膜晶体管包括接触孔，所述接触孔贯穿第一钝化层，所述像素电极通过接触孔与漏极连接。
可选的，所述第一金属层为栅极。
可选的，所述闭环的通槽结构为四边形通槽状。
本申请还公开了一种阵列基板的制作方法，所述制作方法包括：
在衬底上设置第一金属层和绝缘层；
在绝缘层上设置半导体层和阻挡层；
在阻挡层上设置连接槽；
在阻挡层上覆盖第二金属层；
在第二金属层上设置第一钝化层；
在第一钝化层设置像素电极；以及
在像素电极上设置接触孔，贯穿第一钝化层。
可选的，所述连接槽的制作方法包括：
涂布阻挡层材料；
在阻挡层上涂布光阻；
利用光罩进行对其曝光显影；以及
刻蚀得到连接槽。
本申请还公开了一种显示面板。显示面板包括阵列基板，
所述阵列基板包括薄膜晶体管，
所述薄膜晶体管包括：
衬底；
第一金属层，设置于所述衬底表面；
绝缘层，覆盖在所述第一金属层表面；
半导体层，覆盖在所述绝缘层表面；
阻挡层，覆盖在所述半导体层和绝缘层表面；
第二金属层，覆盖在所述阻挡层表面；所述第二金属层包括源极和漏极；
第一钝化层覆盖在所述第二金属层表面；以及
像素电极，设于第一钝化层上方；
其中，所述阻挡层上对应源极和漏极位置设有连接槽，所述连接槽一端连接源极与半导体层，另一端连接漏极与半导体层。
可选的，所述连接槽包括第一连接槽与第二连接槽；
所述第一连接槽与第二连接槽首尾相互连接，设置闭环的通槽结构。
可选的，所述第一连接槽的宽度等于第二连接槽的宽度。
可选的，第一连接槽的长度等于第二连接槽的长度。
可选的，所述连接槽包括第一连接槽；所述第一连接槽连接所述源极与所述漏极设置开环的通槽结构。
可选的，所述绝缘层为栅氧绝缘层。
可选的，所述薄膜晶体管还包括第三接触孔，所述第三接触孔连通源极与半导体层，与所述第二接触孔连接漏极与半导体，形成通路。
可选的，所述第一接触孔、第二接触孔与第三接触孔的形状相同。
相对于范例性的薄膜晶体管的面积虽小的方案来说，在干蚀刻刻蚀阻挡层那一层时，由于刻蚀阻挡层需蚀刻掉的面积过大，容易出现刻蚀不均匀(蚀刻不干净或者过蚀刻)，过蚀刻容易刻蚀到刻蚀阻挡层下面的绝缘层，从而使绝缘层膜厚减薄，易漏电，而本申请中蚀刻区域较小，即防止了蚀刻不完全，又防止阻挡层过蚀刻损伤到绝缘层，引起画面异常等问题，对大尺寸且分辨率要求高的显示面板像素设计具有一定的优势。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的其中一个实施例的薄膜晶体管连接槽的俯视图；
图2是本申请的其中一个实施例的薄膜晶体管连接槽AA’的剖视图；
图3是本申请的其中一个实施例的薄膜晶体管连接槽的俯视图；
图4是本申请的其中一个实施例的阻挡层C的俯视图；
图5是本申请的其中一个实施例的薄膜晶体管连接槽AA’的示意图；
图6是本申请的其中一个实施例的阵列基板制作方法的示意图；
图7是本申请的其中一个实施例的连接槽制作方法的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和实施例对本申请的说明。
如图1至图2所示，本申请一实施例公布了一种阵列基板110，包括薄膜晶体管120，薄膜晶体管120包括衬底121、第一金属层122、绝缘层123、半导体层124、阻挡层125、第二金属层126、第一钝化层131和像素电极129；第一金属层122，设置于衬底121表面；绝缘层123，覆盖在第一金属层122表面；半导体层124，覆盖在绝缘层123表面；阻挡层125，覆盖在半导体层124和绝缘层123表面；第二金属层126，覆盖在阻挡层125表面；第二金属层126包括源极127和漏极128；第一钝化层131覆盖在第二金属层126表面；像素电极129，设于第一钝化层131上方；阻挡层125上对应源极127和漏极128位置设有连接槽134，连接槽134一端连接源极127与半导体层124，另一端连接漏极128与半导体层124。
本方案中，显示面板100适用于第一钝化层131上方紧贴像素电极129的面板，同样也适用于第一钝化层131上方还有其他层的面板，层层贴于表面，像素电极129设于第一钝化层131的上方，第一钝化层131上方不排除有其他层的可能性，第一金属层122为栅极，第二金属层126包括源极127和漏极128，对应源极127和漏极128位置设有连接槽，连接设置闭合通槽，连接半导体层127与源漏电极形成通路，只需对应闭合通槽处进行刻蚀，相对范例性的薄膜晶体管120尺寸面积小的来说，本案的蚀刻区域较小，其他区域依然保留阻挡层125，所以绝缘层123上还覆盖着阻挡层125，防止了阻挡层125过蚀刻损伤到绝缘层123，引起画面异常等问题，对大尺寸且分辨率要求高的面板像素设计具有一定的优势。
如图1所示，在一实施例中，连接槽134包括第一连接槽135；第一连接槽135连接源极127与漏极128设置开环的通槽结构。
本方案中，通槽相对于上一实施方式来说，通槽的区域变小了，刻蚀区域对应通槽区域刻蚀，刻蚀区域相对更小了，其他区域除了通槽区域都覆盖着阻挡层125，刻蚀损伤下层的绝缘层123的几率就更小了，对绝缘层123的保护范围增大，减小过刻蚀引起的绝缘层123做薄的风险。
如图2所示，在一实施例中，薄膜晶体管120包括色阻层133，覆盖在第一钝化层131表面；第二钝化层132，覆盖在色阻层133表面；像素电极129覆盖在第二钝化层132表面；接触孔130，接触孔130贯穿第一钝化层131、色阻层133与第二钝化层132，像素电极129通过接触孔130与漏极128连接。
本方案中，色阻层133为红色阻层133，也可为蓝色阻和绿色组，第二钝化层132保护色阻层133，接触孔130贯穿第一钝化层131、色阻层133和第二钝化层132，像素电极129通过接触孔130与漏极128连接形成通路。
如图3至4所示，在一实施例中，连接槽134包括第一连接槽135与第二连接槽136；第一连接槽135与第二连接槽136首尾相互连接，设置闭环的通槽结构。连接槽134包括第一连接槽135和第二连接槽136，互相连接设置一个闭合的通槽，闭合通槽相对于范例性只有两个过孔来讲，范例性的过孔的尺寸会限制薄膜晶体管120的尺寸，而本申请的通槽的大小不会限制到薄膜晶体管120的大小，且外环形不会受限于薄膜晶体管120，就算通槽很大，也不会影响到薄膜晶体管120的尺寸。
如图4所示，在一实施例中，第一连接槽135的宽度等于第二连接槽136的宽度，第一连接槽135的长度等于第二连接槽136的长度。第一连接槽135的宽度为W1,第二连接槽136的宽度为W2,通槽的宽度等于通孔的宽度，第一连接槽135的长度为L1，第二连接槽136的长度为L2,长度一致，整个连接槽设置闭合通槽，制程时不需要额外的调节，长宽一致，制程稳定，更不会因为通槽的整个宽度不一，造成电子的迁移率下降，影响源极127和 漏极128的导通。
在一实施例中，连接槽的尺寸宽度范围为3μm-15μm。故通槽的大小范围可以为3μm-15μm，尺寸再大薄膜晶体管120尺寸也不会影响，但是为了防止过蚀刻的问题，防止绝缘层123做薄，在此范围内比较合适。
如图4所示，在一实施例中，闭合通槽结构为四边形通槽。从俯视图看是两个连接槽设置闭环的四边形通槽，四边形状闭合通槽结构的大小不会限制到薄膜晶体管120的大小，且外环形不会受限于薄膜晶体管120，就算闭合通槽结构很大，也不会影响到薄膜晶体管120的尺寸。
如图2至4所示，作为本申请的另一实施例，公开了一种阵列基板110。包括薄膜晶体管120，薄膜晶体管120包括衬底121、第一金属层122、绝缘层123、半导体层124、阻挡层125、第二金属层126、第一钝化层131和像素电极129；第一金属层122，设置于衬底121表面；绝缘层123，覆盖在第一金属层122表面；半导体层124，覆盖在绝缘层123表面；阻挡层125，覆盖在半导体层124和绝缘层123表面；第二金属层126，覆盖在阻挡层125表面；第二金属层126包括源极127和漏极128；第一钝化层131覆盖在第二金属层126表面；像素电极129，设于第一钝化层131上方；阻挡层125上对应源极127和漏极128位置设有连接槽134，连接槽134包括第一连接槽135与第二连接槽136；第一连接槽135与第二连接槽136首尾相互连接，设置环形通槽，连接源极127、漏极128和半导体层124，第一连接槽135的宽度等于第二连接槽136的宽度，宽度范围为3μm-15μm。
本方案中，环形通槽，由两个小连接槽组成，相对于范例性的薄膜晶体管120器件小的来讲，本案比范例性的刻蚀区域减小，范例性的刻蚀区域比较大，刻蚀区域大，容易出现刻蚀不均匀(蚀刻不干净或者过蚀刻)，过蚀刻容易刻蚀到刻蚀阻挡层125下面的绝缘层123，从而使绝缘层123膜厚减薄，易漏电，而本申请中，蚀刻环形通槽，刻蚀区域较小，即防止了蚀刻不完全，又防止阻挡层125过蚀刻损伤到绝缘层123，引起画面异常等问题，对大尺寸且分辨率要求高的面板像素设计具有一定的优势。
如图5所示，在一实施例中，薄膜晶体管120包括接触孔130，第三接触孔130贯穿第一钝化层131，像素电极129通过第三接触孔130与漏极128连接。第一钝化层131覆盖在第二金属层126上，第三接触孔130贯穿第一钝化层131，像素电极129通过第三接触孔130与漏极128连接，形成通路。
如图6所示，作为本申请的另一实施例，公开了一种阵列基板的制作方法。制作方法包括：
S61：在衬底上设置第一金属层和绝缘层；
S62：在绝缘层上设置半导体层和阻挡层；
S63：在阻挡层上设置连接槽；
S64：在阻挡层上覆盖第二金属层；
S65：在第二金属层上设置第一钝化层；
S66：在第一钝化层设置像素电极；以及
S67：在像素电极上设置接触孔，贯穿第一钝化层。
如图7所示，在一实施例中，连接槽的制作方法包括：
S71：涂布阻挡层材料；
S72：在阻挡层上涂布光阻；
S73：利用光罩进行对其曝光显影；以及
S74：刻蚀得到连接槽。
如图1至7所示，作为本申请的另一实施例，公开了一种显示面板100。显示面板100包括阵列基板110，阵列基板110包括：包括薄膜晶体管120，薄膜晶体管120包括：
衬底121；
第一金属层122，设置于衬底121表面；
绝缘层123，覆盖在第一金属层122表面；
半导体层124，覆盖在绝缘层123表面；
阻挡层125，覆盖在半导体层124和绝缘层123表面；
第二金属层126，覆盖在阻挡层125表面；第二金属层126包括源极和漏极；
第一钝化层131覆盖在第二金属层126表面；
像素电极129，设于第一钝化层131上方；
阻挡层125上对应源极127和漏极128位置设有连接槽134，连接槽134一端连接源极128与半导体层124，另一端连接漏极128与半导体层124。
本方案中，显示面板100适于第一钝化层131上方紧贴像素电极129的面板，同样也适用于第一钝化层131上方还有其他层的面板，层层贴于表面，像素电极129设于第一钝化层131的上方，第一钝化层131上方不排除有其他层的可能性，第一金属层122为栅极，相对范例性的薄膜晶体管120尺寸面积小的来说，本案的蚀刻区域较小，其他区域依然保留阻挡层125，所以绝缘层123上还覆盖着阻挡层125，防止了阻挡层125过蚀刻损伤到绝缘层123，引起画面异常等问题，对大尺寸且分辨率要求高的面板像素设计具有一定的优势。
在一实施例中，连接槽134包括第一连接槽135与第二连接槽136；
第一连接槽与第二连接槽首尾相互连接，设置闭环的通槽结构。
本方案中，连接槽134包括第一连接槽135和第二连接槽136，互相连接设置一个闭合的通槽，闭合通槽相对于范例性只有两个过孔来讲，范例性的过孔的尺寸会限制薄膜晶体管 120的尺寸，而本申请的通槽的大小不会限制到薄膜晶体管120的大小。
在一实施例中，第一连接槽135的宽度等于第二连接槽136的宽度。
本方案中，第一连接槽135的宽度为W1,第二连接槽136的宽度为W2,通槽的宽度等于通孔的宽度，制程稳定，更不会因为通槽的整个宽度不一，造成电子的迁移率下降，影响源极127和漏极128的导通。
在一实施例中，第一连接槽135的长度等于第二连接槽136的长度。
本方案中，第一连接槽135的长度为L1，第二连接槽136的长度为L2,长度一致，制程时不需要额外的调节。
在一实施例中，连接槽134包括第一连接槽135；第一连接槽135连接源极127与漏极128设置开环的通槽结构。
本方案中，通槽相对于上一实施方式来说，通槽的区域变小了，刻蚀区域对应通槽区域刻蚀，刻蚀区域相对更小了。
在一实施例中，绝缘层为栅氧绝缘层，易阻挡电子的迁移率，绝缘效果佳。
在一实施例中，薄膜晶体管还包括第三接触孔，第三接触孔连通源极与半导体层，与所述第二接触孔连接漏极与半导体，形成通路。
在一实施例中，第一接触孔、第二接触孔与第三接触孔的形状相同。电子迁移的范围一样，不会因为任意一个接触孔过大，造成电子传输失衡，损坏元器件。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Vertical Alignment，垂直配向技术)，当然，也可以是其他类型的显示面板，如有机发光显示面板(organic light emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种阵列基板，包括薄膜晶体管，
    所述薄膜晶体管包括：
    衬底；
    第一金属层，设置于所述衬底表面；
    绝缘层，覆盖在所述第一金属层表面；
    半导体层，覆盖在所述绝缘层表面；
    阻挡层，覆盖在所述半导体层和绝缘层表面；
    第二金属层，覆盖在所述阻挡层表面；所述第二金属层包括源极和漏极；
    第一钝化层覆盖在所述第二金属层表面；以及
    像素电极，设于第一钝化层上方；
    其中，所述阻挡层上对应源极和漏极位置设有连接槽，所述连接槽一端连接源极与半导体层，另一端连接漏极与半导体层。
  2. 如权利要求1所述的一种阵列基板，其中，所述连接槽包括第一连接槽与第二连接槽；
    所述第一连接槽与第二连接槽首尾相互连接，设置闭环的通槽结构。
  3. 如权利要求1所述的一种阵列基板，其中，所述第一连接槽的宽度等于第二连接槽的宽度。
  4. 如权利要求1所述的一种阵列基板，其中，第一连接槽的长度等于第二连接槽的长度。
  5. 如权利要求1所述的一种阵列基板，其中，所述连接槽包括第一连接槽；
    所述第一连接槽连接所述源极与所述漏极设置开环的通槽结构。
  6. 如权利要求3所述的一种阵列基板，其中，所述连接槽的宽度范围为3微米-15微米。
  7. 如权利要求1所述的一种阵列基板，其中，所述薄膜晶体管包括：
    色阻层，覆盖在第一钝化层表面；
    第二钝化层，覆盖在所述色阻层表面；
    所述像素电极覆盖在所述第二钝化层表面；以及
    接触孔，所述接触孔贯穿第一钝化层、色阻层与第二钝化层，所述像素电极通过所述接触孔与漏极连接。
  8. 如权利要求1所述的一种阵列基板，其中，所述薄膜晶体管包括接触孔，所述接触孔贯穿第一钝化层，所述像素电极通过接触孔与漏极连接。
  9. 如权利要求1所述的一种阵列基板，其中，所述第一金属层为栅极。
  10. 如权利要求2所述的一种阵列基板，其中，所述闭环的通槽结构为四边形通槽状。
  11. 一种阵列基板的制作方法，所述制作方法包括：
    在衬底上设置第一金属层和绝缘层；
    在绝缘层上设置半导体层和阻挡层；
    在阻挡层上设置连接槽；
    在阻挡层上覆盖第二金属层；
    在第二金属层上设置第一钝化层；
    在第一钝化层设置像素电极；以及
    在像素电极上设置接触孔，贯穿第一钝化层。
  12. 如权利要求8所述的一种阵列基板的制作方法，其中，所述连接槽的制作方法包括：
    涂布阻挡层材料；
    在阻挡层上涂布光阻；
    利用光罩进行对其曝光显影；以及
    刻蚀得到连接槽。
  13. 一种显示面板，包括阵列基板，
    所述阵列基板包括：包括薄膜晶体管；
    所述薄膜晶体管包括：
    衬底；
    第一金属层，设置于所述衬底表面；
    绝缘层，覆盖在所述第一金属层表面；
    半导体层，覆盖在所述绝缘层表面；
    阻挡层，覆盖在所述半导体层和绝缘层表面；
    第二金属层，覆盖在所述阻挡层表面；所述第二金属层包括源极和漏极；
    第一钝化层覆盖在所述第二金属层表面；以及
    像素电极，设于第一钝化层上方；
    其中，所述阻挡层上对应源极和漏极位置设有连接槽，所述连接槽一端连接源极与半导体层，另一端连接漏极与半导体层。
  14. 如权利要求13所述的一种显示面板，其中，所述连接槽包括第一连接槽与第二连接槽；
    所述第一连接槽与第二连接槽首尾相互连接，设置闭环的通槽结构。
  15. 如权利要求13所述的一种显示面板，其中，所述第一连接槽的宽度等于第二连接 槽的宽度。
  16. 如权利要求13所述的一种显示面板，其中，第一连接槽的长度等于第二连接槽的长度。
  17. 如权利要求13所述的一种显示面板，其中，所述连接槽包括第一连接槽；所述第一连接槽连接所述源极与所述漏极设置开环的通槽结构。
  18. 如权利要求13所述的显示面板，其中，所述绝缘层为栅氧绝缘层。
  19. 如权利要求13所述的显示面板，其中，所述薄膜晶体管还包括第三接触孔，所述第三接触孔连通源极与半导体层，与所述第二接触孔连接漏极与半导体，形成通路。
  20. 如权利要求18所述的显示面板，其中，所述第一接触孔、第二接触孔与第三接触孔的形状相同。
PCT/CN2018/118415 2018-11-12 2018-11-30 阵列基板、阵列基板的制作方法和显示面板 WO2020097998A1 (zh)

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