WO2021104050A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2021104050A1
WO2021104050A1 PCT/CN2020/128766 CN2020128766W WO2021104050A1 WO 2021104050 A1 WO2021104050 A1 WO 2021104050A1 CN 2020128766 W CN2020128766 W CN 2020128766W WO 2021104050 A1 WO2021104050 A1 WO 2021104050A1
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Prior art keywords
substrate
layer
electrode
orthographic projection
display
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PCT/CN2020/128766
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English (en)
French (fr)
Inventor
韩影
林奕呈
徐攀
张星
高展
闫光
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京东方科技集团股份有限公司
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Priority to US17/418,814 priority Critical patent/US20220123083A1/en
Publication of WO2021104050A1 publication Critical patent/WO2021104050A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to a display substrate, a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • the brightness of the display screen generally has a problem of unevenness, which affects the user experience. Therefore, it is necessary to perform brightness compensation on the display panel to make the brightness of the display screen of the display panel uniform.
  • At least one embodiment of the present disclosure provides a display substrate, the display substrate including a substrate, a light emitting device located on the substrate, and an optical compensation structure;
  • the optical compensation structure includes a photo sensor, a transistor, and a capacitor, and the photo sensor is electrically connected to the transistor and the capacitor, respectively;
  • the photosensor includes a first electrode, a photosensitive layer on the side of the first electrode facing away from the substrate, and a second electrode on the side of the photosensitive layer facing away from the substrate;
  • the transistor includes a source electrode , A drain electrode, a gate electrode and an active layer;
  • the capacitor includes a first electrode plate and a second electrode plate located on a side of the first electrode plate away from the substrate;
  • the orthographic projection of the source electrode on the substrate and the orthographic projection of the drain electrode on the substrate do not overlap with the orthographic projection of the first electrode plate on the substrate. Both the orthographic projection of the source electrode on the substrate and the orthographic projection of the drain electrode on the substrate overlap with the orthographic projection of the first electrode on the substrate.
  • the orthographic projection of the active layer on the substrate overlaps the orthographic projection of the photosensitive layer on the substrate.
  • the orthographic projection of the active layer on the substrate is within the projection of the photosensitive layer on the substrate.
  • the source electrode, the drain electrode and the first electrode plate are located on the same layer.
  • the first electrode and the second electrode plate are located on the same layer.
  • the display substrate further includes an insulating layer located on a side of the photosensor close to the substrate, and the insulating layer includes a first passivation layer, which is located away from the first passivation layer.
  • the transistor is located on a side of the insulating layer close to the substrate, the insulating layer is provided with a contact hole, and the first electrode and the source electrode are electrically connected through the contact hole .
  • the material of the planarization layer is one of a silicon-glass bonding structure material and a resin.
  • the material of the planarization layer is a silicon-glass bonding structure material
  • the second passivation layer covers the surface of the planarization layer facing away from the substrate and the planarization layer The sidewall of the layer.
  • the orthographic projection of the photosensor on the substrate is within the orthographic projection of the planarization layer on the substrate.
  • the orthographic projection of the photosensitive layer on the substrate is within the orthographic projection of the first electrode on the substrate.
  • the orthographic projection of the second electrode on the substrate is within the orthographic projection of the photosensitive layer on the substrate.
  • the light emitting device is located on a side of the photosensor away from the substrate, the light emitting device includes an anode, an insulating layer is provided between the second electrode and the anode, and the insulating Through holes are provided on the layer;
  • the display substrate further includes a lead, the lead and the anode are located on the same layer, and one end of the lead is electrically connected to the second electrode through the through hole.
  • the display substrate further includes a color filter layer, the color filter layer is located between the light-emitting device and the photoelectric sensor, and the orthographic projection of the color filter layer on the substrate and the The orthographic projection of the photoelectric sensor on the substrate has no overlap.
  • At least one embodiment of the present disclosure provides a display panel including the above-mentioned display substrate.
  • At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of a structure of a display substrate provided by an exemplary embodiment of the present disclosure
  • Fig. 2 is a circuit diagram of an optical compensation structure provided by an exemplary embodiment of the present disclosure
  • FIG. 3 is a cross-sectional view of a display substrate provided by an exemplary embodiment of the present disclosure
  • FIG. 4 is another cross-sectional view of a display substrate provided by an exemplary embodiment of the present disclosure.
  • Fig. 5 is a circuit diagram of a pixel circuit provided by an exemplary embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of another structure of a display substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view of a partial structure of a display substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 8 is a diagram of the positional relationship between a color film layer and a photoelectric sensor according to an exemplary embodiment of the present disclosure
  • FIG. 9 is a diagram of the positional relationship between the color film layer and the photoelectric sensor provided by an exemplary embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a manufacturing method of a display substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view of a first intermediate structure of a display substrate provided by an exemplary embodiment of the present disclosure
  • FIG. 12 is a cross-sectional view of a second intermediate structure of a display substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view of a third intermediate structure of a display substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 14 is another cross-sectional view of the third intermediate structure of the display substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 15 is a cross-sectional view of a fourth intermediate structure of a display substrate provided by an exemplary embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of performing secondary exposure according to an exemplary embodiment of the present disclosure.
  • FIG. 17 is a cross-sectional view of a fifth intermediate structure of a display substrate provided by an exemplary embodiment of the present disclosure.
  • first, second, third, etc. may be used in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as second information, and similarly, the second information may also be referred to as first information.
  • word “if” as used herein can be interpreted as "when” or “when” or "in response to determination”.
  • the embodiment of the present disclosure provides a display substrate.
  • the display substrate 100 includes a substrate 10, a light emitting device 21 and an optical compensation structure 30 on the substrate 10.
  • the optical compensation structure 30 includes a photo sensor 31, a transistor 32 and a capacitor 33.
  • the photoelectric sensor 31 is used to collect the intensity of the light emitted by the light-emitting device 21. 3 and 4, the photosensor 31 includes a first electrode 311, a photosensitive layer 312 located on the side of the first electrode 311 away from the substrate 10, and a photosensitive layer 312 located away from the substrate 10 One side of the second electrode 313.
  • the transistor 32 includes an active layer 321, a gate electrode 322, a drain electrode 323 and a source electrode 324.
  • the capacitor 33 includes a first electrode plate 331 and a second electrode plate 332 located on a side of the first electrode plate 331 away from the substrate 10.
  • the orthographic projection of the source electrode 324 of the transistor 32 on the substrate 10 and the orthographic projection of the drain electrode 323 of the transistor 32 on the substrate 10 are the same as the first plate of the capacitor 33
  • the orthographic projection of 331 on the substrate 10 does not overlap, the orthographic projection of the source electrode 324 of the transistor 32 on the substrate 10 and the drain electrode 323 of the transistor 32 on the substrate 10
  • the orthographic projection of the first electrode 311 of the photoelectric sensor 31 on the substrate 10 overlaps.
  • the optical compensation structure 30 collects the intensity of the light emitted by the light-emitting device 21 to compensate the brightness of the light-emitting device 21, so that the luminous intensity of each light-emitting device 21 in the display substrate is consistent, and the display substrate The brightness of the display screen is uniform everywhere; because the optical compensation structure 30 directly obtains the brightness difference of each light-emitting device 21 and compensates, it can solve the problem of uneven brightness caused by various factors, and the electrical compensation can only solve the threshold voltage and mobility Compared with the solution that causes the problem of uneven brightness, the solution provided by the embodiments of the present disclosure performs brightness compensation more comprehensively.
  • the orthographic projection of the source electrode 324 of the transistor 32 on the substrate 10 and the orthographic projection of the drain electrode 323 on the substrate 10 do not overlap with the orthographic projection of the first plate 331 of the capacitor 33 on the substrate 10.
  • the source electrode 324, the drain electrode 323, and the first electrode plate 331 can be formed in the same layer, and the source electrode 324, the drain electrode 323 and the first electrode plate 331 can be formed in the same process, which helps simplify the manufacturing process.
  • the orthographic projection of the source electrode 324 on the substrate 10 and the orthographic projection of the drain electrode 323 on the substrate 10 overlap with the orthographic projection of the first electrode 311 on the substrate, which can save space on the display substrate.
  • the orthographic projection of the active layer 321 of the transistor 32 on the substrate 10 overlaps the orthographic projection of the photosensitive layer 312 of the photosensor 31 on the substrate 10.
  • the orthographic projection of the active layer 321 of the transistor 32 on the substrate 10 overlaps with the orthographic projection of the photosensor 31 on the substrate 10, which can save the space of the display substrate.
  • the projection and the orthographic projection of the photoelectric sensor 31 on the substrate 10 do not overlap, when the total area of the orthographic projection of the active layer 321 and the photoelectric sensor 31 on the substrate is constant, the light of the photoelectric sensor 31 can be received. Setting the surface to be larger helps to improve the detection accuracy of the photoelectric sensor 31.
  • the orthographic projection of the active layer 321 of the transistor 32 on the substrate 10 is within the orthographic projection of the photosensitive layer 312 of the photosensor 31 on the substrate 10. This arrangement can save the space of the display substrate to the greatest extent.
  • the source electrode 324 and the drain electrode 323 of the transistor 32 and the first plate 331 of the capacitor 33 are located on the same layer.
  • the source electrode 324, the drain electrode 323 and the first electrode plate 331 are located on the same layer, which means that the source electrode 324, the drain electrode 323 and the first electrode plate 331 have the same material and are formed at the same time. That is, the source electrode 324, the drain electrode 323, and the first electrode plate 331 can be formed in the same process, which helps simplify the manufacturing process.
  • the first electrode 311 of the photosensor 31 and the second electrode plate 332 of the capacitor 33 are located on the same layer.
  • the first electrode 311 and the second electrode plate 332 are located on the same layer, which means that the first electrode 311 and the second electrode plate 332 have the same material and are formed at the same time. That is, the first electrode 311 and the second electrode plate 332 can be formed in the same process, which helps simplify the manufacturing process.
  • FIG. 2 shows a schematic diagram of a circuit formed by connecting the photosensor 31, the transistor 32, and the capacitor 33 in the optical compensation structure.
  • the capacitor 33 is connected in parallel with the photoelectric sensor 31, that is, one plate of the capacitor 33 is electrically connected to the input end of the photoelectric sensor 31, and the other plate of the capacitor 33 is electrically connected to the output end of the photoelectric sensor 32;
  • the input terminal of the sensor 31 is connected to the high-level power line of the external power supply, the output terminal of the photoelectric sensor 31 is electrically connected to the source electrode 324 of the transistor 32, the drain electrode 323 of the transistor 32 is electrically connected to the chip, and the gate electrode 322 of the transistor 32 is connected to the switch Signal line.
  • the setting of the capacitor 33 is beneficial to the brightness detection and compensation under high gray scale.
  • the display substrate 100 is an OLED display substrate.
  • the pixel 20 of the display substrate 100 further includes a pixel circuit 22 for driving the light-emitting device 21, and the pixel circuit 22 and the light-emitting device 21 are electrically connected.
  • FIG. 5 shows a schematic diagram of the structure of the pixel circuit 22.
  • the pixel circuit is a 3T1C circuit, including three transistors and one capacitor.
  • the gate of the transistor T1 is connected to the scan line, the first end of the transistor T1 is connected to the data line, the second end of the transistor T1 is electrically connected to the gate of the transistor T2; the first end of the transistor T2 is electrically connected to the high level, and the transistor T2
  • the second end of the transistor T3 is electrically connected to the light emitting device 21; the gate of the transistor T3 is connected to the scan line, the first end of the transistor T3 is electrically connected to the second end of the transistor T2, and the second end of the transistor T3 is connected to the reset signal line; One end is connected to the gate of the transistor T2, and the other end is connected to the second end of the transistor T2.
  • the pixel circuit 22 can also be a 2T1C circuit (including two transistors and one capacitor), a 7T1C circuit (including seven transistors and one capacitor), a 7T2C circuit (including seven transistors and two capacitors), etc.
  • the photosensor 31 is located on the light emitting side of the light emitting device 21 to obtain the luminous intensity of the light emitting device 21.
  • the display substrate 100 provided by the embodiment of the present disclosure may be a bottom-emitting display substrate, and the light emitted by the light-emitting structure 20 is emitted through the substrate 10. As shown in FIG. 1, the light emitting device 21 can be divided into a first area 201 and a second area 202. The orthographic projection of the first area 201 on the substrate 10 and the photoelectric sensor 31 in the optical compensation structure 30 are on the substrate 10.
  • the orthographic projection of the photosensor 31 in the optical compensation structure 30 on the substrate 10 falls within the orthographic projection of the second region 202 on the substrate 10, and the second region 202 of the light emitting device 21 emits The light part is received by the photosensor 31, and the light emitted by the first region 201 of the light emitting device 21 exits through the substrate 10.
  • the light-emitting device 21 includes an anode 211, an organic layer 212 located on the side of the anode 211 away from the substrate 10, and a cathode 213 located on the side of the organic layer 212 away from the substrate 10.
  • the display substrate 100 is a bottom-emitting display substrate
  • the material of the anode 211 is a light-transmitting material.
  • the photosensor 31 is a photodiode.
  • the photodiode has a fast response speed and a more stable operation.
  • the display substrate 100 further includes an insulating layer 110 located on the side of the photosensor 21 close to the substrate 10, and the insulating layer 110 includes a first passivation layer 105 located on the first passivation layer.
  • the planarization layer 106 on the side of the planarization layer 106 away from the substrate 10 and the second passivation layer 107 on the side of the planarization layer 106 away from the substrate 10.
  • the planarization layer 106 can ensure that the bottom of the photosensor 21 is flat, and help reduce the dark current of the photosensor 31.
  • the orthographic projection of the photosensor 31 on the substrate 10 is within the orthographic projection of the planarization layer 106 on the substrate 10.
  • the orthographic projection of the photosensor 31 on the substrate 10 is within the orthographic projection of the planarization layer 106 on the substrate 10, which refers to the first electrode 311, the photosensitive layer 312, and the second electrode 313 of the photosensor 31 on the substrate 10.
  • the above orthographic projections are all located within the orthographic projection of the planarization layer 106 on the substrate 10.
  • the planarization layer 106 can prevent the ambient light from being incident on the photosensor 31 and cause interference to the signals detected by the photosensor 31, which helps to improve the signal-to-noise ratio.
  • the orthographic projection of the photosensitive layer 312 of the photoelectric sensor 31 on the substrate 10 is within the orthographic projection of the first electrode 311 on the substrate 10.
  • Such a configuration can prevent the interference of ambient light on the photosensitive layer 312, and improve the signal-to-noise ratio of the signal received by the photoelectric sensor 31.
  • the distance between the sidewall of the photosensitive layer 312 and the sidewall of the first electrode 311 is d3, and the range of d3 may be [1 ⁇ m, 3 ⁇ m].
  • the value of d3 can be 2 ⁇ m.
  • the orthographic projection of the second electrode 313 on the substrate 10 is within the orthographic projection of the photosensitive layer 312 on the substrate 10. This arrangement helps to reduce the dark current of the photoelectric sensor 31.
  • the distance between the sidewall of the photosensitive layer 312 and the sidewall of the second electrode 313 is d1, and the range of d1 may be [0.5 ⁇ m, 2.5 ⁇ m].
  • the value of d1 may be 1.5 ⁇ m.
  • the planarization layer 106 is located only under the photosensor 31, and the area of the orthographic projection of the planarization layer 106 on the substrate 10 is smaller than the area of the substrate 10.
  • the material of the planarization layer 106 may be SOG (Silicon On Glass, silicon-glass bonding structure) material.
  • SOG Silicon On Glass, silicon-glass bonding structure
  • the planarization layer 106 made of SOG material can make the bottom of the photoelectric sensor 31 better.
  • the distance between the sidewall of the planarization layer 106 and the sidewall of the first electrode 311 is d2, and the range of d2 may be [2 ⁇ m, 4 ⁇ m].
  • the value of d2 can be 3 ⁇ m.
  • the second passivation layer 107 covers the walls of the planarization layer 106 away from the substrate 10 and the sidewalls of the planarization layer 106. In this way, the second passivation layer 107 can prevent the SOG material from contaminating the equipment chamber during the preparation of subsequent film layers, such as the respective film layers of the photoelectric sensor 31; and, the second passivation layer 107 can avoid the preparation of the first electrode of the photoelectric sensor 31
  • the SOG material contaminates the sidewall of the photosensor 31 and causes the problem of high dark current of the photosensor 31.
  • the orthographic projection of the first electrode 311 on the substrate 10 is located on the orthographic projection of the planarization layer 106 on the substrate 10, which can avoid silicon in the SOG material. The risk of film exposure caused by volatilization.
  • the planarization layer 106 is a film layer deposited on the entire surface, that is, the projection of the planarization layer 106 on the substrate 10 covers the substrate 10.
  • the planarization layer 106 is a film layer deposited on the entire surface, compared with the structure in which the planarization layer 106 is located only under the light-emitting device 21, the height difference between the first region 211 and the second region 212 of the light-emitting device 21 can be reduced.
  • the climbing difficulty of the anode 211, the organic layer 212 and the cathode 213 is reduced, and the risk of the anode 211, the organic layer 212 and the cathode 213 being broken is reduced.
  • the photoelectric sensor 31 can be reduced when preparing the photoelectric sensor 31.
  • the amount of photoresist used in the exposure and development process, the photoresist and metal residues remaining on the sidewall of the photoelectric sensor 31 are less, no secondary exposure is required, which helps to reduce the number of masks used and the process complexity
  • the planarization layer 106 is a film layer deposited on the entire surface, which is beneficial to block the influence on the transistor 32 in the process of preparing the photosensor 31, thereby reducing the bright spots of the panel and improving the display effect.
  • the material of the planarization layer 106 is resin.
  • the light transmittance of the resin is relatively high, and the light emitted by the light emitting device 21 can be emitted through the planarization layer 106.
  • the second passivation layer 107 covers the planarization layer 106.
  • the second passivation layer 107 can prevent the planarization layer 106 from being over-etched and etched to the planarization layer 106 during the preparation of the first electrode 311 of the photosensor 31 and protect the planarization layer 106.
  • the transistor 32 is located on the side of the insulating layer 110 close to the substrate 10, the insulating layer 110 is provided with a contact hole 1100, and the first electrode 311 of the photosensor 31 is connected to the substrate 10.
  • the source electrode 324 of the transistor 32 is electrically connected through the contact hole 1100 on the insulating layer 110.
  • an insulating layer 109 is provided between the second electrode 313 of the photosensor 31 and the anode 211, and a through hole 1090 is provided on the insulating layer 109.
  • the display substrate 100 further includes a lead 40, the lead 40 and the anode 211 are located on the same layer, one end of the lead 40 is electrically connected to the second electrode 313 through the through hole 1090 on the insulating layer 109, The other end is electrically connected to the chip, and the chip performs optical compensation on the light-emitting device according to the received signal.
  • the lead 40 may be directly electrically connected to the chip or indirectly electrically connected to the chip through other devices.
  • the lead 40 and the anode 211 are located in the same layer, that is, the material of the lead 40 and the anode 211 are the same, and the two are formed at the same time, the anode 211 and the lead 40 can be formed in the same process, which helps to simplify the preparation of the display substrate 10 Craft.
  • the material of the insulating layer 109 may be resin.
  • the second plate 332 of the capacitor 33 and the first electrode 311 of the photosensor 31 are the same conductive block, that is, the conductive block is used as the first electrode 311 of the photosensor 31 and also The second electrode plate 332 as the capacitor 33 and the first electrode plate 331 form the capacitor 33.
  • the second plate 332 of the capacitor 33 and the photo sensor 31 may also be different conductive blocks.
  • the display substrate 100 may further include a light-shielding layer 101 between the substrate 10 and the active layer 321 of the transistor 32, and a light-shielding layer 101 between the light-shielding layer 101 and the active layer 321.
  • the buffer layer 102, the gate insulating layer 103 between the active layer 321 and the gate 322, the interlayer dielectric layer 104 between the gate 322 and the source electrode 324, and the second electrode 313 and the insulating layer 109 The third passivation layer 108 of, and the pixel defining layer 41 between the lead 40 and the anode 211, the pixel defining layer 41 is provided with a pixel opening, the pixel opening exposes a part of the anode 211, and the organic layer 212 is at least partially located in the pixel opening.
  • the projection of the light shielding layer 101 on the substrate 10 roughly coincides with the orthographic projection of the active layer 321 on the substrate 10.
  • the display substrate further includes a color filiter (CF) layer 50.
  • the display substrate is bottom-emitting, the color film layer 50 is located between the light-emitting device 21 and the photosensor 31, and the color film layer 50 is on the substrate 10. There is no overlap between the orthographic projection and the orthographic projection of the photoelectric sensor 31 on the substrate 10.
  • the display substrate may be top-emitting, the color film layer is located on the side of the light-emitting device 21 away from the substrate 10, and the orthographic projection of the color film layer on the substrate does not overlap with the projection of the photoelectric sensor on the substrate. Stacked.
  • the orthographic projection of the color film layer 50 on the substrate 10 and the orthographic projection of the photoelectric sensor 31 on the substrate do not overlap, and the light emitted by the light-emitting device received by the photoelectric sensor does not pass through the color film layer, which enables the photoelectric sensor to detect The accuracy of the data is higher, and the effect is better when the optical compensation is performed based on the data detected by the photoelectric sensor 31.
  • the photosensor 31 is a photodiode.
  • the photodiode has a fast response speed and a more stable operation.
  • the display substrate includes a plurality of light-emitting structures, and each light-emitting structure may be provided with an optical compensation structure on a side close to the substrate.
  • Figure 8 shows the positional relationship diagram of the color film layer 50 and the photoelectric sensor 31 in this case. See Figure 8. Different fillings represent color films of different colors.
  • Figure 8 shows the color film of four pixels. The color film of each pixel corresponds to four optical compensation structures, that is, each light-emitting structure is correspondingly provided with an optical compensation structure. At the same time, there is no overlap between the orthographic projection of the color film layer 50 on the substrate and the projection of the photoelectric sensor 31 on the substrate.
  • two or more adjacent light-emitting devices may share an optical compensation structure.
  • four light-emitting devices of the display substrate can share an optical compensation structure, and the optical compensation structure is used to detect the light-emitting brightness of the four light-emitting devices.
  • FIG. 9 shows the positional relationship diagram of the color filter layer 50 and the photoelectric sensor 31 in this case. The difference from FIG. 8 is that the four light-emitting structures are provided with an optical compensation structure corresponding to each other. This arrangement can reduce the number of optical compensation structures in the display substrate and help reduce the complexity of the structure.
  • the embodiment of the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a substrate 10, a light emitting device 21 and an optical compensation structure 30 on the substrate 10.
  • the optical compensation structure 30 includes a photo sensor, a transistor, and a capacitor.
  • the photoelectric sensor includes a first electrode, a photosensitive layer and a second electrode.
  • the transistor includes an active layer, a source electrode, a gate electrode, and a drain electrode.
  • the capacitor includes a first electrode plate and a second electrode plate.
  • the method for preparing the display substrate includes the following steps 110 to 180.
  • step 110 a substrate is provided.
  • the substrate 10 may be a flexible substrate or a rigid substrate.
  • the flexible substrate may be a transparent substrate prepared from one or more of PET (polyethylene terephthalate), PI (polyimide), PC (polycarbonate), and the like.
  • the rigid substrate may be, for example, a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate.
  • step 120 an active layer is formed on the substrate.
  • the preparation method further includes: forming a light-shielding layer 101 on the substrate 10, and forming a buffer layer 102 on the side of the light-shielding layer 101 away from the substrate 10.
  • the active layer 321 is located on the side of the buffer layer 102 away from the substrate 10.
  • the orthographic projection of the active layer 321 on the substrate 10 is within the orthographic projection of the light shielding layer 101 on the substrate 10.
  • step 120 the first intermediate structure as shown in FIG. 11 can be obtained.
  • a gate electrode, a source electrode, and a drain electrode are formed on the side of the active layer away from the substrate.
  • the source electrode and the drain electrode are electrically connected to the active layer, and the gate electrode is insulated from the active layer.
  • Step 130 can be achieved by the following processes: forming an active layer 321 on the side of the buffer layer 102 away from the substrate 10; forming a gate insulating layer 103 on the side of the active layer 321 away from the substrate 10; A gate electrode 322 is formed on the side away from the substrate 10; an interlayer dielectric layer 104 is formed on the side of the gate electrode 322 away from the substrate 10; a through hole is formed on the interlayer dielectric layer 104, and the through hole is in the orthographic projection of the substrate 10 Located in the orthographic projection of the active layer 331 on the substrate 10; the source electrode 324, the drain electrode 323 and the first plate 331 of the capacitor 33 are formed on the side of the interlayer dielectric layer 104 away from the substrate 10. The source electrode 324 and The drain electrodes 323 are in contact with the active layer 321 through corresponding through holes, respectively.
  • a second intermediate structure as shown in FIG. 12 can be obtained.
  • an insulating layer is formed on the side of the source electrode away from the substrate.
  • the insulating layer includes a first passivation layer, a planarization layer located on the side of the first passivation layer away from the substrate, and a planarization layer located away from the substrate.
  • a contact hole is opened on the insulating layer, and the orthographic projection of the contact hole on the substrate is located within the orthographic projection of the source electrode on the substrate.
  • step 140 a schematic diagram of the third intermediate structure as shown in FIG. 13 or FIG. 14 can be obtained.
  • the area of the orthographic projection of the planarization layer 106 on the substrate 10 is smaller than the area of the substrate 10.
  • the orthographic projection of the planarization layer 106 on the substrate 10 covers the substrate 10.
  • a first electrode and a second electrode are formed on the side of the insulating layer away from the substrate.
  • the first electrode is electrically connected to the source electrode through the contact hole on the planarization layer.
  • a photosensitive layer is formed on the side of the photosensitive layer, and a second electrode is formed on the side of the photosensitive layer away from the substrate.
  • the projection of at least one of the first electrode, the photosensitive layer and the second electrode on the substrate is intersected by the projection of the active layer on the substrate. Stacked.
  • FIG. 15 only shows that the area of the orthographic projection of the planarization layer 106 on the substrate 10 is smaller than the area of the substrate 10 as an example, and the case where the orthographic projection of the planarization layer 106 on the substrate 10 covers the substrate 10 is no longer performed. Signal.
  • the orthographic projections of the first electrode 311, the photosensitive layer 312 and the second electrode 313 on the substrate 10 are all located within the orthographic projection of the planarization layer 106 on the substrate 10.
  • the orthographic projection of the photosensitive layer 312 on the substrate 10 is within the orthographic projection of the first electrode 311 on the substrate 10.
  • the orthographic projection of the second electrode 313 on the substrate 10 is within the orthographic projection of the photosensitive layer 312 on the substrate 10.
  • the second plate 332 of the capacitor 33 and the first electrode 311 of the photosensor 31 are the same conductive block, that is, the conductive block is used as the first electrode 311 of the photosensor 31 and also The second electrode plate 332 as the capacitor 33 and the first electrode plate 331 form the capacitor 33.
  • the second plate 332 of the capacitor 33 and the photo sensor 31 may also be different conductive blocks.
  • the orthographic projection of the active layer 321 of the transistor 32 on the substrate 10 is within the projection of the photosensor 31 on the substrate 10. That is, the orthographic projection of the active layer 321 of the transistor 32 on the substrate falls within the set of orthographic projections of the first electrode 311, the photosensitive layer 312, and the second electrode 313 on the substrate. With this arrangement, the space of the display substrate can be saved to the greatest extent, so as to increase the light-emitting area of the display substrate.
  • a conductive layer is first deposited on the entire surface of the photosensitive layer 312 away from the substrate 10, and then the conductive layer is patterned to form the first electrode 311.
  • an exposure and development process may be used to pattern the conductive layer.
  • the amount of photoresist applied is increased to avoid that the photoresist at the sidewalls of the photosensitive layer 312 is thinner due to the large height difference between the conductive layer and the planarization layer 106.
  • over-etching occurs.
  • the sidewalls of the passivation layer 107 and the walls away from the substrate 10 will be caused.
  • the photoresist and conductive layer remain on the walls of, the sidewalls of the photosensitive layer 312, and the walls away from the substrate 10.
  • the area can be exposed twice.
  • a mask may be used to cover the conductive layer on the side facing away from the substrate 10, and the through holes on the mask correspond to the areas where the photoresist and the conductive layer remain, and the holes are provided on the mask. exposure.
  • the amount of photoresist 51 on the side of the planarization layer 106 is relatively large, and the distance d4 between the through hole on the mask 52 and the sidewall of the planarization layer 106 can be 2 ⁇ m to ensure that the photoresist 51 is removed completely during the second exposure.
  • step 160 an anode and a lead are formed on the side of the second electrode away from the substrate.
  • the preparation method may further include: forming a third passivation layer 108 on the side of the second electrode 313 away from the substrate 10, and forming an insulating layer 109 on the side of the third passivation layer 108 away from the substrate 10.
  • the third passivation layer 108 and the insulating layer 109 are respectively provided with through holes 1081 and 1091 communicating with each other.
  • the through holes on the third passivation layer 108 and the through holes on the insulating layer 109 can be formed at the same time in the same step.
  • the second electrode is located on the side of the insulating layer 109 away from the substrate. Through this process, an intermediate structure as shown in FIG. 17 can be obtained.
  • the lead 40 formed in step 160 is electrically connected to the second electrode 313 through the through hole 1081 on the third passivation layer 108 and the through hole 1091 on the insulating layer 109.
  • a pixel defining layer is formed on the side of the anode away from the substrate, and a pixel opening is opened on the pixel defining layer, and the pixel opening exposes a part of the anode.
  • step 180 an organic layer is formed on the side of the anode away from the substrate, and a cathode is formed on the side of the organic layer away from the substrate.
  • step 180 a display substrate as shown in FIG. 3 or FIG. 4 can be obtained.
  • the display substrate includes an optical compensation structure that collects the intensity of light emitted by the light-emitting device, and compensates the brightness of the light-emitting device, so that the luminous intensity of each light-emitting device in the display substrate is consistent, and then Make the brightness of the display screen of the display substrate uniform; because the optical compensation structure directly obtains the brightness difference of each light-emitting device and compensates, it can solve the problem of uneven brightness caused by various factors, and the electrical compensation can only solve the threshold voltage and migration Compared with the solution to the problem of uneven brightness caused by the rate, the solution provided by the embodiment of the present disclosure performs brightness compensation more comprehensively.
  • the source electrode of the transistor, the drain electrode of the transistor, and the first electrode plate of the capacitor are formed at the same time, and the first electrode of the photosensor and the second electrode plate of the capacitor are formed at the same time, which helps to simplify the manufacturing process.
  • the orthographic projection of the active layer of the transistor on the substrate overlaps the orthographic projection of the photoelectric sensor on the substrate, which can save the space of the display substrate.
  • the size of the display substrate is fixed, the total light emission of the light-emitting device can be increased. The area helps to improve the display effect.
  • the present disclosure also provides a display panel, which includes the display substrate provided in any of the above-mentioned embodiments.
  • the display panel may also include an encapsulation layer, a polarizer, a glass cover plate, etc.
  • the embodiment of the present disclosure also provides a display device.
  • the display device includes a casing and the above-mentioned display panel, and the display panel is covered on the casing.
  • the display device in this embodiment may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, and so on.

Abstract

一种显示基板（100）、显示面板及显示装置。显示基板（100）包括衬底（10）、位于衬底（10）上的发光器件（21）及光学补偿结构（30）。光学补偿结构（30）包括光电传感器（31）、晶体管（32）和电容（33），光电传感器（31）分别与晶体管（32）和电容（33）电连接。光电传感器（31）包括第一电极（311）、位于第一电极（311）背离衬底（10）的一侧的感光层（312）、以及位于感光层（312）背离衬底（10）的一侧的第二电极（313）；晶体管（32）包括源电极（324）、漏电极（323）、栅电极（322）及有源层（321）；电容（33）包括第一极板（331）及位于第一极板（331）背离衬底（10）的一侧的第二极板（332）。源电极（324）在衬底（10）上的正投影及漏电极（323）在衬底（10）上的正投影均与第一极板（331）在衬底（10）上的正投影无交叠，源电极（324）在衬底（10）上的正投影及漏电极（323）在衬底（10）上的正投影均与第一电极（311）在衬底（10）上的正投影有交叠。

Description

显示基板、显示面板及显示装置
本申请要求于2019年11月26日提交的申请号为201911171911.X、发明名称为“显示基板、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及一种显示基板、显示面板及显示装置。
背景技术
近年来，基于有机发光二极管(Organic Light Emitting Diode，OLED)的显示装置因具有自发光、视角广、发光效率高、色域广、工作电压低、面板薄等优点，成为国内外热门的显示产品。
显示面板制备完成后，显示画面的亮度一般存在不均一的问题，影响用户的使用体验。因此，需要对显示面板进行亮度补偿，以使显示面板的显示画面各处的亮度均一。
发明内容
本公开的至少一实施例提供了一种显示基板，所述显示基板包括衬底、位于所述衬底上的发光器件及光学补偿结构；
所述光学补偿结构包括光电传感器、晶体管和电容，所述光电传感器分别与所述晶体管和所述电容电连接；
所述光电传感器包括第一电极、位于第一电极背离所述衬底的一侧的感光层、以及位于所述感光层背离所述衬底的一侧的第二电极；所述晶体管包括源电极、漏电极、栅电极及有源层；所述电容包括第一极板及位于所述第一极板背离所述衬底的一侧的第二极板；
所述源电极在所述衬底上的正投影及所述漏电极在所述衬底上的正投影均与所述第一极板在所述衬底上的正投影无交叠，所述源电极在所述衬底上的正投影及所述漏电极在所述衬底上的正投影均与所述第一电极在所述衬底上的正投影有交叠。
在一个实施例中，所述有源层在所述衬底上的正投影与所述感光层在所述衬底上的正投影有交叠。
在一个实施例中，所述有源层在所述衬底上的正投影位于所述感光层在所述衬底上的投影内。
在一个实施例中，所述源电极、所述漏电极与所述第一极板位于同一层。
在一个实施例中，所述第一电极与所述第二极板位于同一层。
在一个实施例中，所述显示基板还包括位于所述光电传感器靠近所述衬底的一侧的绝缘层，所述绝缘层包括第一钝化层、位于所述第一钝化层背离所述衬底一侧的平坦化层、以及位于所述平坦化层背离所述衬底一侧的第二钝化层。
在一个实施例中，所述晶体管位于所述绝缘层靠近所述衬底的一侧，所述绝缘层上设置有接触孔，所述第一电极与所述源电极通过所述接触孔电连接。
在一个实施例中，所述平坦化层的材料为硅-玻璃键合结构材料和树脂中的一种。
在一个实施例中，所述平坦化层的材料为硅-玻璃键合结构材料，所述第二钝化层包覆所述平坦化层背离所述衬底一侧的表面及所述平坦化层的侧壁。
在一个实施例中，所述光电传感器在所述衬底上的正投影位于所述平坦化层在所述衬底上的正投影内。
在一个实施例中，所述感光层在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内。
在一个实施例中，所述第二电极在所述衬底上的正投影位于所述感光层在所述衬底上的正投影内。
在一个实施例中，所述发光器件位于所述光电传感器背离所述衬底的一侧，所述发光器件包括阳极，所述第二电极与所述阳极之间设有绝缘层，所述绝缘层上设置有通孔；
所述显示基板还包括引线，所述引线与所述阳极位于同一层，所述引线的一端通过所述通孔与所述第二电极电连接。
在一个实施例中，所述显示基板还包括彩膜层，所述彩膜层位于所述发光器件与所述光电传感器之间，所述彩膜层在所述衬底上的正投影与所述光电传感器在所述衬底上的正投影无交叠。
本公开的至少一实施例提供了一种显示面板，所述显示面板包括上述的显示基板。
本公开的至少一实施例提供了一种显示装置，所述显示装置包括上述的显示面板。
附图说明
图1是本公开一示例性实施例提供的显示基板的一种结构示意图；
图2是本公开一示例性实施例提供的光学补偿结构的电路图；
图3是本公开一示例性实施例提供的显示基板的一种剖视图；
图4是本公开一示例性实施例提供的显示基板的另一种剖视图；
图5是本公开一示例性实施例提供的一种像素电路的电路图；
图6是本公开一示例性实施例提供的显示基板的另一种结构示意图；
图7是本公开一示例性实施例提供的显示基板的部分结构的剖视图；
图8是本公开一示例性实施例提供的彩膜层和光电传感器的位置关系图；
图9是本公开一示例性实施例提供的彩膜层和光电传感器的位置关系图；
图10是本公开一示例性实施例提供的显示基板的制备方法的流程图；
图11是本公开一示例性实施例提供的显示基板的第一中间结构的剖视图；
图12是本公开一示例性实施例提供的显示基板的第二中间结构的剖视图；
图13是本公开一示例性实施例提供的显示基板的第三中间结构的一种剖视图；
图14是本公开一示例性实施例提供的显示基板的第三中间结构的另一种剖视图；
图15是本公开一示例性实施例提供的显示基板的第四中间结构的剖视图；
图16是本公开一示例性实施例提供的进行二次曝光的示意图；
图17是本公开一示例性实施例提供的显示基板的第五中间结构的剖视图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本公开相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
在本公开使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本 公开。在本公开和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本公开可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本公开范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
下面结合附图，对本公开的一些实施例作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
本公开实施例提供了一种显示基板。参见图1，所述显示基板100包括衬底10、位于所述衬底10上的发光器件21及光学补偿结构30。
参见图2，所述光学补偿结构30包括光电传感器31、晶体管32和电容33。所述光电传感器31用于采集所述发光器件21发出光的强度。参见图3及图4，所述光电传感器31包括第一电极311、位于第一电极311背离所述衬底10的一侧的感光层312、以及位于所述感光层312背离所述衬底10的一侧的第二电极313。所述晶体管32包括有源层321、栅电极322、漏电极323及源电极324。所述电容33包括第一极板331及位于所述第一极板331背离所述衬底10的一侧的第二极板332。
所述晶体管32的源电极324在所述衬底10上的正投影、及所述晶体管32的漏电极323在所述衬底10上的正投影，均与所述电容33的第一极板331在所述衬底10上的正投影无交叠，所述晶体管32的源电极324在所述衬底10上的正投影、及所述晶体管32的漏电极323在所述衬底10上的正投影，均所述光电传感器31的第一电极311在所述衬底10上的正投影有交叠。
本公开实施例提供的显示基板，光学补偿结构30采集所述发光器件21发出光的强度，以对发光器件21进行亮度补偿，使显示基板内各发光器件21的发光强度一致，进而使显示基板的显示画面各处亮度均一；由于光学补偿结构30直接获取各个发光器件21的亮度差异并进行补偿，可解决多方面因素导致的亮度不均一的问题，与电学补偿仅能解决阈值电压及迁移率引起的亮度不均一问题的方案相比，本公开实施例提供的方案进行亮度补偿时，补偿更全面。晶 体管32的源电极324在衬底10上的正投影、及漏电极323在衬底10上的正投影均与电容33的第一极板331在衬底10上的正投影无交叠，则源电极324、漏电极323及第一极板331可做在同一层，源电极324、漏电极323及第一极板331可在同一工序中形成，有助于简化制备工艺。源电极324在衬底10上的正投影、及漏电极323在衬底10上的正投影均与第一电极311在衬底上的正投影有交叠，可节省显示基板的空间。
在一个实施例中，所述晶体管32的有源层321在所述衬底10上的正投影与所述光电传感器31的感光层312在所述衬底10上的正投影有交叠。晶体管32的有源层321在衬底10上的正投影与光电传感器31在衬底10上的正投影有交叠，可节省显示基板的空间，与有源层321在衬底10上的正投影与光电传感器31在衬底10上的正投影无交叠的方案相比，有源层321与光电传感器31在衬底上的正投影的总面积一定时，可将光电传感器31的光接受面设置得更大，有助于提升光电传感器31检测的精确度。
可选地，所述晶体管32的有源层321在所述衬底10上的正投影位于所述光电传感器31的感光层312在所述衬底10上的正投影内。如此设置，可在最大程度上节省显示基板的空间。
在一个实施例中，晶体管32的源电极324、漏电极323与电容33的第一极板331位于同一层。源电极324、漏电极323与第一极板331位于同一层指的是，源电极324、漏电极323与第一极板331材料相同，且同时形成。也即是，源电极324、漏电极323与第一极板331可在同一工序中形成，有助于简化制备工艺。
在一个实施例中，光电传感器31的第一电极311与电容33的第二极板332位于同一层。第一电极311与第二极板332位于同一层指的是，第一电极311与第二极板332材料相同，且同时形成。也即是，第一电极311与第二极板332可在同一工序中形成，有助于简化制备工艺。
图2所示为光学补偿结构中光电传感器31、晶体管32及电容33连接而成的电路的示意图。如图2所示，电容33与光电传感器31并联，也即电容33的一个极板与光电传感器31的输入端电连接，电容33的另一个极板与光电传感器32的输出端电连接；光电传感器31的输入端连接外部电源的高电平电源线，光电传感器31的输出端与晶体管32的源电极324电连接，晶体管32的漏电极323与芯片电连接，晶体管32的栅电极322连接开关信号线。电容33的设置有利于高灰阶下的亮度检测及补偿。
在一个实施例中，显示基板100为OLED显示基板。显示基板100的像素20还包括用于驱动发光器件21的像素电路22，像素电路22和发光器件21电连接。
图5所示为像素电路22的一种结构示意图。参见图5，像素电路为3T1C电路，包括三个晶体管及一个电容。晶体管T1的栅极连接扫描线，晶体管T1的第一端与数据线连接，晶体管T1的第二端与晶体管T2的栅极电连接；晶体管T2的第一端与高电平电连接，晶体管T2的第二端与发光器件21电连接；晶体管T3的栅极连接扫描线，晶体管T3的第一端与晶体管T2的第二端电连接，晶体管T3的第二端连接复位信号线；电容C的一端连接晶体管T2的栅极，另一端连接晶体管T2的第二端。在其他实施例中，像素电路22还可为2T1C电路(包括两个晶体管及一个电容)、7T1C电路(包括七个晶体管及一个电容)、7T2C电路(包括七个晶体管及两个电容)等。
光电传感器31位于发光器件21的出光侧，获取发光器件21的发光强度。本公开实施例提供的显示基板100可以是底发光显示基板，发光结构20发出的光通过衬底10出射。如图1所示，发光器件21可分为第一区201及第二区202，第一区201在衬底10上的正投影与光学补偿结构30中的光电传感器31在衬底10上的正投影无交叠，且光学补偿结构30中的光电传感器31在衬底10上的正投影落在第二区202在衬底10上的正投影内，发光器件21的第二区202发出的光部分被光电传感器31接收，发光器件21的第一区201发出的光通过衬底10出射。
参见图3和图4，发光器件21包括阳极211、位于阳极211背离衬底10一侧的有机层212及位于有机层212背离衬底10一侧的阴极213。图示实施例中，显示基板100为底发光显示基板，阳极211的材料为透光材料。
在一个实施例中，光电传感器31为光电二极管。光电二极管反应速度快，工作更稳定。
在一个实施例中，所述显示基板100还包括位于所述光电传感器21靠近所述衬底10的一侧的绝缘层110，绝缘层110包括第一钝化层105、位于第一钝化层105背离衬底10一侧的平坦化层106、以及位于平坦化层106背离衬底10一侧的第二钝化层107。平坦化层106可保证光电传感器21的底部平坦，有助于降低光电传感器31的暗电流。
在一个实施例中，所述光电传感器31在所述衬底10上的正投影位于所述 平坦化层106在所述衬底10上的正投影内。光电传感器31在衬底10上的正投影位于平坦化层106在衬底10上的正投影内，指的是光电传感器31的第一电极311、感光层312及第二电极313在衬底10上的正投影均位于平坦化层106在衬底10上的正投影内。如此设置，平坦化层106可避免环境光入射至光电传感器31而对光电传感器31检测的信号造成干扰，有助于提升信噪比。
在一个实施例中，所述光电传感器31的感光层312在所述衬底10上的正投影位于所述第一电极311在所述衬底10上的正投影内。如此设置，可防止环境光对感光层312的干扰，提高光电传感器31接收到的信号的信噪比。参见图7，感光层312的侧壁与第一电极311的侧壁之间的距离为d3，d3的范围可为[1μm，3μm]。可选的，d3的值可为2μm。
在一个实施例中，所述第二电极313在所述衬底10上的正投影位于所述感光层312在所述衬底10上的正投影内。如此设置，有助于降低光电传感器31的暗电流。参见图7，感光层312的侧壁与第二电极313的侧壁之间的距离为d1，d1的范围可为[0.5μm，2.5μm]。可选的，d1的值可为1.5μm。
在一个实施例中，参见图3，平坦化层106仅位于光电传感器31下方，平坦化层106在衬底10上的正投影的面积小于衬底10的面积。平坦化层106的材料可为SOG(Silicon On Glass，硅-玻璃键合结构)材料。采用SOG材料制备的平坦化层106可使得光电传感器31底部的平坦度更好。参见图7，平坦化层106的侧壁与第一电极311的侧壁之间的距离为d2，d2的范围可为[2μm，4μm]。可选的，d2的值可为3μm。
在一个实施例中，平坦化层106的材料为SOG材料时，第二钝化层107包覆平坦化层106背离衬底10的壁及平坦化层106的侧壁。如此，第二钝化层107可避免后续膜层例如光电传感器31的各个膜层制备过程中SOG材料污染设备腔室；并且，第二钝化层107可避免在制备光电传感器31的第一电极311时过刻而刻蚀到平坦化层106，导致SOG材料污染光电传感器31的侧壁而造成光电传感器31的暗电流较高的问题。
在一个实施例中，平坦化层106的材料为SOG材料时，第一电极311在衬底10上的正投影位于平坦化层106在衬底10上的正投影，可避免SOG材料中的硅挥发时造成的暴膜风险。
在另一个实施例中，参见图4，所述平坦化层106为整面沉积的膜层，也即是平坦化层106在衬底10上的投影覆盖衬底10。平坦化层106为整面沉积的膜 层时，与平坦化层106仅位于发光器件21下方的结构相比，可降低发光器件21的第一区211与第二区212之间的高度差，减小阳极211、有机层212及阴极213的攀爬难度，降低阳极211、有机层212及阴极213发生断裂的风险。并且，与平坦化层106仅位于发光器件21下方的结构相比，由于发光器件21的第一区201与第二区202之间的高度差较小，在制备光电传感器31时，可减小曝光显影工艺过程中使用的光刻胶的用量，光电传感器31的侧壁上残留的光刻胶及金属残留较少，无需进行二次曝光，有助于减少使用的掩膜板数目及工艺复杂度；此外，平坦化层106为整面沉积的膜层，有利于阻挡制备光电传感器31的过程中对晶体管32的影响，进而可以减少面板亮点，提升显示效果。
示例性地，平坦化层106的材料为树脂。树脂的透光率较高，发光器件21发出的光可通过平坦化层106而出射。
在一个实施例中，平坦化层106为整面沉积的膜层时，第二钝化层107覆盖平坦化层106。第二钝化层107可避免在制备光电传感器31的第一电极311时过刻而刻蚀到平坦化层106，保护平坦化层106。
在一个实施例中，所述晶体管32位于所述绝缘层110靠近所述衬底10的一侧，所述绝缘层110上设置有接触孔1100，所述光电传感器31的第一电极311与所述晶体管32的源电极324通过所述绝缘层110上的接触孔1100电连接。
在一个实施例中，所述光电传感器31的第二电极313与所述阳极211之间设有绝缘层109，所述绝缘层109上设置有通孔1090。所述显示基板100还包括引线40，所述引线40与所述阳极211位于同一层，所述引线40的一端通过所述绝缘层109上的通孔1090与所述第二电极313电连接，另一端与芯片电连接，芯片根据接收到的信号对发光器件进行光学补偿。引线40可直接与芯片电连接，或者通过其他器件与芯片间接电连接。引线40与阳极211位于同一层，也即是，引线40与阳极211的材料相同，且二者同时形成，则阳极211与引线40可在同一工序中形成，有助于简化显示基板10的制备工艺。绝缘层109的材料可为树脂。
图示实施例中，电容33的第二极板332与光电传感器31的第一电极311为同一个导电块，也即是，该导电块既用作光电传感器31的第一电极311，同时也作为电容33的第二极板332，与第一极板331构成电容33。在其他实施例中，电容33的第二极板332与光电传感器31也可为不同的导电块。
在一个实施例中，参见图3与图4，显示基板100还可包括位于衬底10与 晶体管32的有源层321之间的遮光层101、位于遮光层101与有源层321之间的缓冲层102、位于有源层321与栅极322之间的栅极绝缘层103、位于栅极322与源电极324之间的层间介质层104、位于第二电极313与绝缘层109之间的第三钝化层108、及位于引线40与阳极211之间的像素限定层41，像素限定层41上设有像素开口，像素开口暴露部分阳极211，有机层212至少部分位于像素开口内。遮光层101在衬底10上的投影与有源层321在衬底10上的正投影大致重合。
参见图6，显示基板还包括彩膜(color filiter，CF)层50。图6所示的实施例中，显示基板为底发光，所述彩膜层50位于所述发光器件21与所述光电传感器31之间，所述彩膜层50在所述衬底10上的正投影与所述光电传感器31在所述衬底10上的正投影无交叠。在其他实施例中，显示基板可为顶发光，彩膜层位于发光器件21背离衬底10的一侧，且彩膜层在衬底上的正投影与光电传感器在衬底上的投影无交叠。如此，彩膜层50在衬底10上的正投影与光电传感器31在衬底上的正投影无交叠，则光电传感器接收的发光器件发出的光未经过彩膜层，可使得光电传感器检测的数据精确度较高，进而根据光电传感器31检测到的数据进行光学补偿时，效果更好。
在一个实施例中，光电传感器31为光电二极管。光电二极管反应速度快，工作更稳定。
在一个实施例中，显示基板包括多个发光结构，每一发光结构靠近衬底的一侧可均对应设置有一个光学补偿结构。图8所示是这种情况下，彩膜层50和光电传感器31的位置关系图，参见图8，不同填充代表不同颜色的彩膜，图8中示出了四个像素的彩膜，四个像素的彩膜对应四个光学补偿结构，也即每一发光结构对应设置有一个光学补偿结构。同时，彩膜层50在衬底上的正投影与光电传感器31在衬底上的投影无交叠。
在其他实施例中，相邻的两个或两个以上的发光器件可共用一个光学补偿结构。例如显示基板的四个发光器件可共用一个光学补偿结构，光学补偿结构用于检测四个发光器件的发光亮度。图9所示是这种情况下，彩膜层50和光电传感器31的位置关系图，与图8的区别在于，四个发光结构对应设置有一个光学补偿结构。如此设置，可减少显示基板中光学补偿结构的数量，有助于降低结构复杂度。
本公开实施例还提供了一种显示基板的制备方法，显示基板包括衬底10、 位于所述衬底10上的发光器件21及光学补偿结构30。所述光学补偿结构30包括光电传感器、晶体管和电容。光电传感器包括第一电极、感光层及第二电极。晶体管包括有源层、源电极、栅电极及漏电极。电容包括第一极板与第二极板。
参见图10，所述显示基板的制备方法包括如下步骤110至步骤180。
在步骤110中，提供衬底。
在一个实施例中，衬底10可以是柔性衬底或刚性衬底。柔性衬底可以由PET(聚对苯二甲酸乙二醇酯)、PI(聚酰亚胺)、PC(聚碳酸酯)等中的一种或多种制备得到的透明衬底。刚性衬底例如可以是玻璃衬底、石英衬底或者塑料衬底等透明衬底。
在步骤120中，在衬底上形成有源层。
在步骤120之前，所述制备方法还包括：在衬底10上形成遮光层101，以及在遮光层101背离衬底10的一侧形成缓冲层102。有源层321位于缓冲层102背离衬底10的一侧。有源层321在衬底10上的正投影位于遮光层101在衬底10上的正投影内。
通过步骤120可得到如图11所示的第一中间结构。
在步骤130中，在有源层背离衬底的一侧形成栅电极、源电极及漏电极，源电极及漏电极与有源层电连接，栅电极与有源层绝缘。
步骤130可通过如下过程实现：在缓冲层102背离衬底10的一侧形成有源层321；在有源层321背离衬底10的一侧形成栅极绝缘层103；在栅极绝缘层103背离衬底10的一侧形成栅电极322；在栅电极322背离衬底10的一侧形成层间介质层104；在层间介质层104上形成通孔，通孔在衬底10的正投影位于有源层331在衬底10上的正投影内；在层间介质层104背离衬底10的一侧形成源电极324、漏电极323及电容33的第一极板331，源电极324与漏电极323分别通过对应的通孔与有源层321接触。通过步骤130可得到如图12所示的第二中间结构。
在步骤140中，在源电极背离衬底的一侧形成绝缘层，绝缘层包括第一钝化层、位于第一钝化层背离衬底一侧的平坦化层及位于平坦化层背离衬底一侧的第二钝化层，在绝缘层上开设接触孔，所述接触孔在衬底上的正投影位于所述源电极在衬底上的正投影内。
通过步骤140可得到如图13或图14所示的第三中间结构的示意图。图13所示的第三中间结构中，平坦化层106在衬底10上的正投影的面积小于衬底10 的面积。图14所示的第三中间结构中，平坦化层106在衬底10上的正投影覆盖衬底10。
在步骤150中，在绝缘层背离衬底的一侧形成第一电极及第二极板，第一电极通过平坦化层上的接触孔与源电极电连接，在第一电极背离衬底的一侧形成感光层，在感光层背离衬底的一侧形成第二电极，第一电极、感光层及第二电极中至少一个在衬底上的投影与有源层在衬底上的投影有交叠。
通过步骤150可得到如图15所示的第四中间结构。图15仅以平坦化层106在衬底10上的正投影的面积小于衬底10的面积为例进行示意，平坦化层106在衬底10上的正投影覆盖衬底10的情况不再进行示意。
参见图15，第一电极311、感光层312及第二电极313在衬底10上的正投影均位于平坦化层106在衬底10上的正投影内。感光层312在衬底10上的正投影位于第一电极311在衬底10上的正投影内。第二电极313在衬底10上的正投影位于感光层312在衬底10上的正投影内。
图示实施例中，电容33的第二极板332与光电传感器31的第一电极311为同一个导电块，也即是，该导电块既用作光电传感器31的第一电极311，同时也作为电容33的第二极板332，与第一极板331构成电容33。在其他实施例中，电容33的第二极板332与光电传感器31也可为不同的导电块。
在一个实施例中，晶体管32的有源层321在衬底10上的正投影位于光电传感器31在衬底10上的投影内。也即是，晶体管32的有源层321在衬底上的正投影落在第一电极311、感光层312及第二电极313在衬底上的正投影的集合内。如此设置，可在最大程度上节省显示基板的空间，以提高显示基板的发光面积。
在形成第二电极313时，首先在感光层312背离衬底10的一侧整面沉积导电层，之后对导电层进行图形化形成第一电极311。在一个实施例中，可采用曝光显影工艺对导电层进行图形化处理。在曝光显影工艺中，涂布的光刻胶的量加大，以避免由于导电层与平坦化层106之间的高度差较大，而导致感光层312侧壁处的光刻胶较薄，在刻蚀导电层的过程中出现过度刻蚀的情况。
但是，由于光刻胶的厚度增大，若采用常规的紫外光照量进行曝光，会导致钝化层107的侧壁及背离衬底10的壁、第一电极311的侧壁及背离衬底10的壁、感光层312的侧壁及背离衬底10的壁有光刻胶及导电层残留。为了避免光刻胶及导电层残留，可对该区域进行二次曝光。示例性地，可采用掩膜板罩 设在导电层背离衬底10的一侧，掩膜板上的通孔与光刻胶及导电层残留的区域对应，通过掩膜板上的开孔进行曝光。参见图16，光刻胶51在平坦化层106侧部的量较多，掩膜板52上的通孔与平坦化层106的侧壁之间的距离d4可为2μm，以保证光刻胶51在二次曝光时去除比较彻底。
在步骤160中，在第二电极背离衬底的一侧形成阳极及引线。
在步骤160之前，制备方法还可包括：在第二电极313背离衬底10的一侧形成第三钝化层108，在第三钝化层108背离衬底10的一侧形成绝缘层109，在第三钝化层108及绝缘层109上分别开设互相连通的通孔1081、1091，第三钝化层108上的通孔与绝缘层109上的通孔可在同一步骤中同时形成。第二电极位于绝缘层109背离衬底的一侧。通过该过程可得到如图17所示的中间结构。步骤160中形成的引线40通过第三钝化层108上的通孔1081及绝缘层109上的通孔1091与第二电极313电连接。
在步骤170中，在阳极背离衬底的一侧形成像素限定层，在像素限定层上开设像素开口，像素开口暴露部分阳极。
在步骤180中，在阳极背离衬底的一侧形成有机层，在有机层背离衬底的一侧形成阴极。
通过步骤180可得到如图3或者图4所示的显示基板。
本公开实施例提供的显示基板的制备方法，显示基板包括光学补偿结构，光学补偿结构采集发光器件发出光的强度，对发光器件进行亮度补偿，使显示基板内各发光器件的发光强度一致，进而使显示基板的显示画面各处亮度均一；由于光学补偿结构直接获取各个发光器件的亮度差异并进行补偿，可解决多方面因素导致的亮度不均一的问题，与电学补偿仅能解决阈值电压及迁移率引起的亮度不均一问题的方案相比，本公开实施例提供的方案进行亮度补偿时，补偿更全面。光学补偿结构中晶体管的源电极、晶体管的漏电极与电容的第一极板同时形成，光电传感器的第一电极与电容的第二极板同时形成，有助于简化制备工艺。晶体管的有源层在衬底上的正投影与光电传感器在衬底上的正投影有交叠，可节省显示基板的空间，显示基板的尺寸一定的情况下，可增大发光器件的总发光面积，有助于提升显示效果。
对于方法实施例而言，由于其基本对应于产品的实施例，所以相关细节及有益效果的描述参见产品实施例的部分说明即可，不再进行赘述。
本公开还提供了一种显示面板，显示面板包括上述任一实施例提供的显示 基板。显示面板还可包括封装层、偏光片、玻璃盖板等。
本公开实施例还提供了一种显示装置。所述显示装置包括壳体及上述的显示面板，显示面板覆盖在壳体上。
本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (16)

  1. 一种显示基板，所述显示基板包括：
    衬底；
    位于所述衬底上的发光器件及光学补偿结；
    所述光学补偿结构包括光电传感器、晶体管和电容，所述光电传感器分别与所述晶体管和所述电容电连接；
    所述光电传感器包括第一电极、位于第一电极背离所述衬底的一侧的感光层、以及位于所述感光层背离所述衬底的一侧的第二电极；所述晶体管包括源电极、漏电极、栅电极及有源层；所述电容包括第一极板及位于所述第一极板背离所述衬底的一侧的第二极板；
    所述源电极在所述衬底上的正投影及所述漏电极在所述衬底上的正投影均与所述第一极板在所述衬底上的正投影无交叠，所述源电极在所述衬底上的正投影及所述漏电极在所述衬底上的正投影均与所述第一电极在所述衬底上的正投影有交叠。
  2. 根据权利要求1所述的显示基板，其中，所述有源层在所述衬底上的正投影与所述感光层在所述衬底上的正投影有交叠。
  3. 根据权利要求2所述的显示基板，其中，所述有源层在所述衬底上的正投影位于所述感光层在所述衬底上的投影内。
  4. 根据权利要求1至3任一项所述的显示基板，其中，所述源电极、所述漏电极与所述第一极板位于同一层。
  5. 根据权利要求1至4任一项所述的显示基板，其中，所述第一电极与所述第二极板位于同一层。
  6. 根据权利要求1至5任一项所述的显示基板，其中，所述显示基板还包括：
    位于所述光电传感器靠近所述衬底的一侧的绝缘层，所述绝缘层包括第一钝化层、位于所述第一钝化层背离所述衬底一侧的平坦化层、以及位于所述平坦化层背离所述衬底一侧的第二钝化层。
  7. 根据权利要求6所述的显示基板，其中，所述晶体管位于所述绝缘层靠近所述衬底的一侧，所述绝缘层上设置有接触孔，所述第一电极与所述源电极通过所述接触孔电连接。
  8. 根据权利要求6所述的显示基板，其中，所述平坦化层的材料为硅-玻璃键合结构材料和树脂中的一种。
  9. 根据权利要求8所述的显示基板，其中，所述平坦化层的材料为硅-玻璃键合结构材料，所述第二钝化层包覆所述平坦化层背离所述衬底一侧的表面及所述平坦化层的侧壁。
  10. 根据权利要求6所述的显示基板，其中，所述光电传感器在所述衬底上的正投影位于所述平坦化层在所述衬底上的正投影内。
  11. 根据权利要求1至10任一项所述的显示基板，其中，所述感光层在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影内。
  12. 根据权利要求1至11任一项所述的显示基板，其中，所述第二电极在所述衬底上的正投影位于所述感光层在所述衬底上的正投影内。
  13. 根据权利要求1至12任一项所述的显示基板，其中，所述发光器件位于所述光电传感器背离所述衬底的一侧，所述发光器件包括阳极，所述第二电极与所述阳极之间设有绝缘层，所述绝缘层上设置有通孔；
    所述显示基板还包括引线，所述引线与所述阳极位于同一层，所述引线的一端通过所述通孔与所述第二电极电连接。
  14. 根据权利要求1至13任一项所述的显示基板，其中，所述显示基板还包括彩膜层，所述彩膜层位于所述发光器件与所述光电传感器之间，所述彩膜层在所述衬底上的正投影与所述光电传感器在所述衬底上的正投影无交叠。
  15. 一种显示面板，所述显示面板包括权利要求1至14任一项所述的显示基板。
  16. 一种显示装置，所述显示装置包括权利要求15所述的显示面板。
PCT/CN2020/128766 2019-11-26 2020-11-13 显示基板、显示面板及显示装置 WO2021104050A1 (zh)

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