CN108336100A - 一种阵列基板及其制备方法、显示面板、显示装置 - Google Patents
一种阵列基板及其制备方法、显示面板、显示装置 Download PDFInfo
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Abstract
本发明公开一种阵列基板,包括:形成在衬底基板上的光敏部件,及形成在所述光敏部件远离所述衬底基板一侧的薄膜晶体管和导电层;所述光敏部件包括层叠设置的第一电极、光敏层和第二电极,所述第一电极靠近所述衬底基板设置;所述第一电极与所述薄膜晶体管的第一极电连接,所述第二电极与所述导电层电连接;其中,所述第一极为所述薄膜晶体管的源极或漏极。本发明实施例的阵列基板,在制备过程中,先形成光敏部件,再在光敏部件上形成薄膜晶体管,避免了光敏部件形成过程中氢元素对薄膜晶体管产生影响,薄膜晶体管的源漏层图案可以通过一次图形化处理形成,简化了制备工艺。
Description
技术领域
本发明涉及显示技术领域,特别是涉及一种阵列基板及其制备方法、显示面板、显示装置。
背景技术
目前,大尺寸的显示面板向高可靠性、高分辨率、高色域等方向发展,对背板制备工艺的要求也不断提高,目前主要采用补偿技术来提升显示面板(panel)的显示质量,采用光学传感器内置在panel上进行补偿,具体的将具有光电流传感功能的光敏部件(PIN)结合一个作为开关的薄膜晶体管(TFT),可以检测实时光学变化,再通过外部电路对显示面板进行调控。
现有的顶栅型阵列基板的结构,在制作工艺中,为了避免上述TFT开关的沟道受到光照影响,如图1所示,在基底1'之上设置有遮光层2',遮光层2'可以采用任何具有遮光作用的金属导电薄膜进行图案化形成。如图1所示结构,光敏部件9'形成在源漏层之上,由于在制作光敏部件9'时,会产生大量氢元素,氢元素对TFT的电学性能影响较大,因此在制作工艺中要避免氢元素沉积到TFT上,这就需要进行两次图形化工艺形成源漏层的图形,即在形成栅极层6'之上的缓冲层7'(ILD)图案后,形成源漏层8',需先对源漏层8'进行第一次图形化处理,该次图形化处理保留TFT的栅极层6'之上的源漏层金属,防止在之后形成光敏部件9'过程中氢元素对TFT造成影响。在形成光敏部件9'后,再对源漏层8'进行第二次图形化处理,将TFT的栅极层6'上方的源漏层金属刻蚀掉,形成完整的源漏层图形,之后再形成钝化层10'(PVX),在钝化层10'上形成过孔,在过孔处通过金属层11'将光敏部件9'与panel的外部信号连接。
上述过程中,形成源漏层图案要采用两步图形化的工艺,制作工艺复杂,影响产品的良率。
发明内容
本发明提供了一种阵列基板及其制备方法、显示面板、显示装置,以解决现有技术中阵列基板制作中,形成源漏层图案工艺复杂的问题。
第一方面,本发明提供一种阵列基板,包括:
形成在衬底基板上的光敏部件,及形成在所述光敏部件远离所述衬底基板一侧的薄膜晶体管和导电层;
所述光敏部件包括层叠设置的第一电极、光敏层和第二电极,所述第一电极靠近所述衬底基板设置;所述第一电极与所述薄膜晶体管的第一极电连接,所述第二电极与所述导电层电连接;其中,所述第一极为所述薄膜晶体管的源极或漏极。
可选地,所述第一电极为遮光层,所述第一电极覆盖所述薄膜晶体管的有源层在所述衬底基板上的正投影。
可选地,所述导电层与所述薄膜晶体管的第一极同层设置。
可选地,所述薄膜晶体管为顶栅结构。
可选地,所述第一电极与所述第一极之间形成有层叠的缓冲层和绝缘层,所述缓冲层靠近所述衬底基板设置,在所述缓冲层上设置有第一过孔,所述绝缘层上设置有第二过孔,所述第一极通过所述第一过孔、所述第二过孔与所述第一电极电连接。
可选地,在所述缓冲层上还设置有第三过孔,所述绝缘层上还设置有第四过孔,所述导电层通过所述第三过孔、所述第四过孔与所述第二电极电连接。
可选地,所述光敏层的材料为PIN型半导体材料。
第二方面,本发明还提供了一种阵列基板的制备方法,包括:
在衬底基板上形成光敏部件,所述光敏部件包括依次层叠设置的第一电极、光敏层和第二电极,所述第一电极靠近所述衬底基板设置;
在所述光敏部件上形成薄膜晶体管和导电层,其中,所述第一电极与所述薄膜晶体管的第一极电连接,所述第二电极与所述导电层电连接,所述第一极为所述薄膜晶体管的源极或漏极。
第三方面,本发明还提供了一种显示面板,包括上述阵列基板。
第四方面,本发明还提供了一种显示装置,包括上述显示面板。
与现有技术相比,本发明实施例具有以下优点:
本发明实施例的阵列基板,在衬底基板上形成有光敏部件,在光敏部件上形成有薄膜晶体管和导电层,其中,光敏部件包括层叠设置的第一电极、光敏层和第二电极,第一电极靠近衬底基板设置,将光敏部件的第一电极与薄膜晶体管的第一极电连接,光敏部件的第二电极与导电层电连接。在制备过程中,先形成光敏部件,再在光敏部件上形成薄膜晶体管,避免了光敏部件形成过程中氢元素对薄膜晶体管产生影响,薄膜晶体管的源漏层图案可以通过一次图形化处理形成,简化了制备工艺。
附图说明
图1所示为现有技术的阵列基板的结构示意图;
图2所示为本发明实施例的阵列基板的结构示意图;
图3所示为本发明实施例的阵列基板的制备方法流程图;
图4a~e所示为阵列基板在制备过程中形成的层结构示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获取的所有其他实施例,都属于本发明保护的范围。
如图2所示,本发明实施例的阵列基板包括形成在衬底基板1上的光敏部件3,以及形成在光敏部件3远离衬底基板1一侧的薄膜晶体管5和导电层6。
该光敏部件3包括层叠设置的第一电极31、光敏层32和第二电极33,其中第一电极31靠近衬底基板1设置。第一电极31与薄膜晶体管5的第一极电连接,第二电极33与导电层6电连接。上述第一极为薄膜晶体管5的源极或漏极。
可以理解的是,上述光敏部件3的第一电极31与薄膜晶体管5的源极或漏极电连接,第二电极33与导电层6电连接,导电层6可以与阵列基板的外围电路电连接,将具有光电流传感功能的光敏部件3结合一个开关的薄膜晶体管5形成可检测实时光学变化,并通过导电层6与外围电路连接后,对光敏部件进行调控,通过该种补偿技术提升显示质量。
本发明实施例的阵列基板,在衬底基板1上形成有光敏部件3,在光敏部件3上形成有薄膜晶体管5和导电层6,其中,光敏部件3包括层叠设置的第一电极31、光敏层32和第二电极33,第一电极31靠近衬底基板1设置,将光敏部件3的第一电极31与薄膜晶体管5的第一极电连接,光敏部件3的第二电极33与导电层6电连接。在制备过程中,先形成光敏部件3,再在光敏部件3上形成薄膜晶体管5,避免了光敏部件5形成过程中氢元素对薄膜晶体管5产生影响,薄膜晶体管5的源漏层图案可以通过一次图形化处理形成,简化了制备工艺。
具体的,如图2所示,以上述薄膜晶体管5为顶栅结构的薄膜晶体管为例进行说明,但可以理解的是,在底栅结构中,本发明的结构也同样适用。
上述第一电极31可以为遮光层,并且第一电极31覆盖薄膜晶体管5的有源层51在衬底基板1上的正投影,可以防止薄膜晶体管5的沟道受到衬底基板1下方的光照的影响,劣化薄膜晶体管的电学特性。
第一电极31同时起到遮光与光敏器件的一个电极的作用,也即遮光层可以作为光敏器件3的一个电极。在制备工艺中,简化了工艺步骤,可以在衬底基板上形成遮光的电极层,通过一次图形化处理即形成了遮光层和第一电极。
在第一电极31上形成有光敏层32,光敏层32的具体材料可以为PIN型半导体材料,其厚度可以为1um左右。在光敏层32之上形成有第二电极33,第二电极33的材料可以为透明的导电层材料如ITO等。
上述光敏部件3的第一电极31、光敏层32和第二电极33具体的形成工艺可以为如下过程:在衬底基板上沉积具有遮光作用的第一电极层,在第一电极层上采用化学气相沉积的工艺沉积PIN膜层1um左右,再在PIN膜层上溅射沉积透明导电的第二电极层,之后再采用先湿刻再干刻的工艺形成光敏部件3的图形。
在形成光敏部件3后,再在其上进行形成薄膜晶体管5,薄膜晶体管5的制备工艺可以参考现有工艺,在此不再赘述。
进一步的,导电层6与薄膜晶体管5的第一极同层设置,也即导电层6与薄膜晶体管5的源漏层55同层设置,导电层6的材料可以与源漏层55的材料相同。该结构可以简化制作工艺,经一步图形化同时形成源漏层55的图案和导电层6的图案。导电层6用于与阵列基板的外围电路连接,以对光敏部件3进行调控。
可以理解的是,现有技术中,由于光敏部件5位于薄膜晶体管3的上方,光敏部件5的形成过程中产生的氢元素会对薄膜晶体管5的电学特性产生影响,因此在形成光敏部件5之前未对源漏层完全图形化,薄膜晶体管有源层上方的源漏层保留,而当形成光敏部件后,再对源漏层进行第二次图形化,形成完整的源漏层图案。而本申请中,由于光敏部件5形成在薄膜晶体管3之前,在后续形成薄膜晶体管3时,不用考虑氢元素会对其造成影响,仅需一次图形化处理,形成源漏层图案即可。因此,本申请制作工艺更加简单,简化了薄膜晶体管的形成步骤。
具体的,在上述第一电极31与薄膜晶体管5的第一极之间,也即在第一电极31与源漏层55之间形成有层叠的缓冲层4和绝缘层54,其中,缓冲层4靠近衬底基板1设置,缓冲层4和绝缘层54完全覆盖光敏部件3。
在缓冲层4上设置有第一过孔,在绝缘层54上设置有第二过孔,薄膜晶体管5的第一极通过第一过孔、第二过孔与第一电极31电连接,同样,也实现了薄膜晶体管5的第一极与遮光层的电连接,可以提高薄膜晶体管的电学特性。可以理解的是,第一过孔与第二过孔可以在形成源漏层之前通过曝光刻蚀工艺形成,在沉积源漏层的同时,将薄膜晶体管5的第一电极通过源漏层金属材料与第一电极31电连接。
同样的,在绝缘层4上还设置有第三过孔,在绝缘层54上还设置有第四过孔,导电层6通过第三过孔、第四过孔与第二电极电连接。
本发明实施例的薄膜晶体管5与光敏部件3的电连接以及光敏部件3与阵列基板的外围电路的电连接,可以通过位于缓冲层4与绝缘层54的过孔以及位于过孔中导电的源漏层材料实现,仅需一次曝光刻蚀,即可形成这四个过孔,并实现电连接。而现有技术中,参照图1所示,源漏层同时作为光敏部件的一个电极,而光敏部件的另一个电极需要通过位于其上的过孔,再通过导电金属与外围电路连接,且遮光层与源漏层的电连接需要另外的过孔来实现,这两个过孔需在两次曝光刻蚀工艺中形成,显然,与本申请相比,工艺较为复杂。本申请的方案,在Array工艺的整体设计上更加简便。
上述仅以薄膜晶体管5为顶栅结构进行说明,可以理解的是,在底栅结构中,同样,可以采用类似的上述结构,在形成光敏部件3后,再形成薄膜晶体管5和导电层6,将薄膜晶体管5的源、漏极的任意一个电极与光敏部件3的第一电极31电连接,导电层6与光敏部件的第二电极33电连接。同样可以简化阵列基板薄膜晶体管的源漏层图案的图形化工艺,其具体的结构与上述实施例类似,在此不再赘述。
本发明实施例还提供了一种阵列基板的制备方法,参照图3所示,包括如下步骤:
步骤100,在衬底基板上形成光敏部件,该光敏部件包括依次层叠设置的第一电极、光敏层和第二电极,第一电极靠近衬底基板设置。
该第一电极具体可以为遮光层,其具体形成过程可以先在衬底基板1上形成具有遮光作用的第一电极层,在遮光的导电层上通过化学气相沉积工艺沉积PIN膜层1um左右,再在PIN膜层上溅射沉积透明导电的第二电极层,之后再采用先湿刻再干刻的工艺形成光敏部件3的图形。其形成过程的层结构示意图参照图4a~b所示。
步骤200,在光敏部件上形成薄膜晶体管和导电层,其中,第一电极层与薄膜晶体管的第一极电连接,第二电极与导电层电连接,第一极为薄膜晶体管的源极或漏极。
在完成步骤100之后,再进行薄膜晶体管5以及导电层6的形成工艺,导电层6可以与薄膜晶体管5的源漏层同层设置。
具体的,在完成步骤100后,再化学气相沉积缓冲层4,缓冲层的材料可以为SiOx或者SiNx;再沉积有源层51,并图形化形成沟道;再制作栅极绝缘层52以及栅极金属53,栅极绝缘层52的材料可以为SiOx,栅极金属53可以为任何导电性好的金属材料,之后再一次图形化形成栅极绝缘层52以及栅极金属53的图案,上述过程中形成的层结构示意图参照图4c~e。之后沉积绝缘层54,绝缘层54的材料可以为SiOx,在沉积绝缘层54之前,需要对有源层51未被栅极金属53及栅极绝缘层52覆盖的区域导体化,之后再形成了绝缘层54后,对其进行图形化,形成导电层6,并形成第一过孔、第二过孔、第三过孔、第四过孔,过孔完成后,沉积有源层55,并图形化处理,完成第一电极31与薄膜晶体管5的第一极的电连接,以及第二电极33与导电层6的电连接。完成上述步骤后,就可以沉积后续的钝化层7,以对薄膜晶体管5进行保护,完成该步骤后,形成如图2所示的结构。
上述阵列基板的制备方法,先形成光敏部件3,再在光敏部件3上形成薄膜晶体管5,避免了光敏部件3形成过程中氢元素对薄膜晶体管5产生影响,薄膜晶体管5的源漏层图案可以通过一次图形化处理形成,简化了制备工艺。
本发明实施例还提供了一种显示面板,包括上述实施例的阵列基板。
本发明实施例还提供了一种显示装置,包括上述实施例的显示面板,显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
本说明书中的各个实施例均采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似的部分互相参见即可。对于系统实施例而言,由于其与方法实施例基本相似,所以描述的比较简单,相关之处参见方法实施例的部分说明即可。
尽管已描述了本发明的优选实施例,但本领域内的技术人员一旦得知了基本创造性概念,则可对这些实施例做出另外的变更和修改。所以,所附权利要求意欲解释为包括优选实施例以及落入本发明实施例范围的所有变更和修改。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以权利要求的保护范围为准。
Claims (10)
1.一种阵列基板,其特征在于,包括:
形成在衬底基板上的光敏部件,及形成在所述光敏部件远离所述衬底基板一侧的薄膜晶体管和导电层;
所述光敏部件包括层叠设置的第一电极、光敏层和第二电极,所述第一电极靠近所述衬底基板设置;所述第一电极与所述薄膜晶体管的第一极电连接,所述第二电极与所述导电层电连接;其中,所述第一极为所述薄膜晶体管的源极或漏极。
2.根据权利要求1所述的阵列基板,其特征在于,所述第一电极为遮光层,所述第一电极覆盖所述薄膜晶体管的有源层在所述衬底基板上的正投影。
3.根据权利要求2所述的阵列基板,其特征在于,所述导电层与所述薄膜晶体管的第一极同层设置。
4.根据权利要求3所述的阵列基板,其特征在于,所述薄膜晶体管为顶栅结构。
5.根据权利要求3所述的阵列基板,其特征在于,所述第一电极与所述第一极之间形成有层叠的缓冲层和绝缘层,所述缓冲层靠近所述衬底基板设置,在所述缓冲层上设置有第一过孔,所述绝缘层上设置有第二过孔,所第一极通过所述第一过孔、所述第二过孔与所述第一电极电连接。
6.根据权利要求5所述的阵列基板,其特征在于,在所述缓冲层上还设置有第三过孔,所述绝缘层上还设置有第四过孔,所述导电层通过所述第三过孔、所述第四过孔与所述第二电极电连接。
7.根据权利要求1至6任一项所述的阵列基板,其特征在于,所述光敏层的材料为PIN型半导体材料。
8.一种阵列基板的制备方法,其特征在于,包括:
在衬底基板上形成光敏部件,所述光敏部件包括依次层叠设置的第一电极、光敏层和第二电极,所述第一电极靠近所述衬底基板设置;
在所述光敏部件上形成薄膜晶体管和导电层,其中,所述第一电极与所述薄膜晶体管的第一极电连接,所述第二电极与所述导电层电连接,所述第一极为所述薄膜晶体管的源极或漏极。
9.一种显示面板,其特征在于,包括权利要求1至7任一项所述的阵列基板。
10.一种显示装置,其特征在于,包括权利要求9所述的显示面板。
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