CN103681488A - 阵列基板及其制作方法,显示装置 - Google Patents
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Abstract
本发明涉及显示技术领域,公开了一种阵列基板制作方法,包括在衬底基板上形成包括薄膜晶体管、栅极引线及数据线引线的图形,栅极引线和数据线引线位于PAD区;形成绝缘间隔层,第一透明电极及钝化层的图形,使阵列基板对应的PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,并在对应栅极引线和数据线引线对应区域分别形成第一过孔和第二过孔,以暴露出栅极引线和数据线引线;形成包括第二透明电极、第一连接电极和第二连接电极的图形,使第一连接电极通过第一过孔连接栅极引线,第二连接电极通过第二过孔连接数据线引线。本发明还公开了一种阵列基板及显示装置。本发明使得PAD区在形成的连接电极能够与相应的信号引线充分接触。
Description
技术领域
本发明涉及显示技术领域,特别涉及一种阵列基板及其制作方法,显示装置。
背景技术
近年来随着人们对显示效果的要求提高,液晶显示器的PPI(Pixels per inch,每英寸所拥有像素数目)不断提高,这就要求显示屏内部单位面积上排布更多的像素,相应地有更多的布线。这样在各层金属间的电容及电阻会随之成倍增加,因此引起的时间延迟及功耗的增加就变得更为明显,严重影响客户使用,同现在提倡的节能环保相悖。为了降低金属层间的电容需要采用更低介电常数、更厚的绝缘材料,现传统的采用化学气相沉积(Chemical Vapor Deposition,CVD)方式制备的无机绝缘材料若要增加其厚度,对生产成本及工艺的要求会非常高,特别是在刻蚀时带来的技术难题是很难克服的,同时工艺的时间会大大增加,这样对产量会有很大影响,降低了企业的竞争力,为此选用有机绝缘材料具有生产工艺简单,成本较低,易于调整厚度,对降低功耗有很明显的效果,同时还降低公共电极的负载,对改善greenish(显示偏绿现象)不良有很明显的效果。
如图1和图2所示,示出了阵列基板的PAD区(显示区域外围的布线区域)的层次结构示意图,图1中由下至上依次为:衬底基板1、栅极引线2、栅绝缘层3,钝化层71、有机绝缘层8及其上过孔、像素电极9(电极材料为ITO)、光刻胶11。由于有机绝缘膜厚度是相对于其它层的10倍,这个厚度在外围PAD区走线的过孔处产生一个较深的坑,这样在随后的像素电极9曝光制作图形时,由于较厚的有机绝缘膜,会导致第一层透明电极的光刻胶在垂直光照时照射不充分,在孔的底部(如图1所示中虚线椭圆框所示的区域)有部分光刻胶残留,后续湿刻过程中会在孔内有部分ITO残留。如图2所示,刻蚀像素电极9后沉积第二钝化层72,然后刻蚀过孔处的第二钝化层72和栅绝缘层3。在刻蚀像素电极9时残留的ITO导致后面在刻蚀栅绝缘层3时只有部分刻透,比设计的第一连接电极12(连接栅金属层的连接电极,与公共电极同时形成,电极材料为ITO)与栅极引线2接触面积大大减小,在后面第一连接电极12沉积后接触不充分,会带来屏的亮线高发及异常点灯等不良,不利于产品的不良检测,及良率的提高,若在外围走线处去除有机绝缘膜会由于膜层段差过大导致后面成盒工序配向膜取向(rubbing)时产生异常,造成产品后面画面显示不均。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是:如何使第二层透明电极沉积后接触不充分,且不会产生取向异常。
(二)技术方案
为解决上述技术问题,本发明提供了一种阵列基板制作方法,包括步骤:
在衬底基板上形成包括薄膜晶体管、栅极引线及数据线引线的图形,所述栅极引线和数据线引线位于PAD区;
形成绝缘间隔层,第一透明电极及钝化层的图形,使所述阵列基板对应的PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,并在对应栅极引线和数据线引线对应区域分别形成第一过孔和第二过孔,以暴露出所述栅极引线和数据线引线;
形成包括第二透明电极、第一连接电极和第二连接电极的图形,使所述第一连接电极通过所述第一过孔连接所述栅极引线,所述第二连接电极通过所述第二过孔连接所述数据线引线。
其中,所述形成绝缘间隔层,第一透明电极及钝化层的图形,使所述阵列基板对应的PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,并在对应栅极引线和数据线引线对应区域分别形成第一过孔和第二过孔,以暴露出所述栅极引线和数据线引线的步骤具体包括:
形成绝缘材料薄膜,通过构图工艺去除所述第一透明电极与薄膜晶体管的漏极连接区域、所述栅极引线区域及数据线引线区域的绝缘材料薄膜,以分别形成连接过孔、第一子过孔和第二子过孔的图形,且使得PAD区的绝缘材料薄膜的厚度小于其它区域的绝缘材料薄膜的厚度,以形成所述绝缘间隔层;
通过构图工艺在非PAD区形成所述第一透明电极的图形,且所述第一透明电极通过所述连接过孔连接薄膜晶体管的漏极;
形成钝化层,通过构图工艺分别在所述第一子过孔和第二子过孔对应区域继续刻蚀,直到分别暴露出所述栅极引线和数据线引线,以形成所述第一过孔和第二过孔。
其中,所述阵列基板对应的PAD区的绝缘间隔层厚度为其它区域的绝缘间隔层厚度的一半。
其中,所述绝缘间隔层为有机材料制成。
本发明还提供了一种阵列基板,包括形成在衬底基板上的薄膜晶体管、第一透明电极、第二透明电极、栅极引线及数据线引线,所述栅极引线及数据线引线位于PAD区,还包括位于薄膜晶体管、栅极引线及数据线引线上方的绝缘间隔层,所述第一透明电极位于所述绝缘件间隔层之上的非PAD区,且连接所述薄膜晶体管的漏极,第二透明电极位于第一透明电极上方,两者之间间隔有钝化层,且在所述PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,所述绝缘间隔层对应PAD区形成有第一过孔和第二过孔,绝缘间隔层上方还形成有与所述第二透明电极位于同一层的第一连接电极和第二连接电极,所述第一连接电极和第二连接电极分别通过第一过孔和第二过孔连接所述栅极引线和数据线引线。
其中,所述PAD区的绝缘间隔层厚度为其它区域的绝缘间隔层厚度的一半。
其中,所述第一透明电极连接所述薄膜晶体管的漏极。
本发明还提供了一种显示装置,包括上述的阵列基板。
(三)有益效果
本发明的阵列基板制作方法使得显示外围区(PAD)形成厚度较薄的绝缘间隔层,使得PAD区在形成的连接电极能够与相应的信号引线充分接触,同时不会导致在后续rubbing时产生rubbing mura(取向不良),提高产品检出率。
附图说明
图1是现有技术的阵列基板的PAD区刻蚀像素电极的示意图;
图2是在阵列基板的PAD区形成第一连接电极后的示意图;
图3是本发明实施例的制作方法中,形成绝缘间隔层后的示意图;
图4是在图3的基础上形成像素电极的示意图;
图5是在图4的基础上形成钝化层的示意图;
图6是在图5的基础上形成公共电极、第一连接电极和第二连接电极的示意图;
图7是图6中第一过孔处的放大示意图。
具体实施方式
下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
如图3~6所示,本实施例的阵列基板制作方法流程包括:
步骤一,在衬底基板1上形成包括薄膜晶体管TFT、栅极引线21及数据线引线61的图形,所述栅极引线21和数据线引线61位于PAD区;在基板1上形成包括栅线及薄膜晶体管(TFT)的层次结构。其中,TFT形成在非PAD区(即显示区)包括:栅极2、栅绝缘层3、有源层4及源极5及漏极6。栅极引线21与栅极2同层形成,数据线引线61与源极5和漏极6同层形成。
步骤二,形成绝缘间隔层,第一透明电极及钝化层的图形,使阵列基板对应的PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,并在对应栅极引线和数据线引线对应区域分别形成第一过孔和第二过孔,以暴露出栅极引线和数据线引线。该步骤具体包括:
形成绝缘材料薄膜(在形成绝缘材料薄膜之前通常还形成一层钝化层71),通过构图工艺(通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺,本实施例中,具体采用半色调掩膜板Half Tonemask)去除所述第一透明电极与薄膜晶体管的漏极连接区域、所述栅极引线21区域及数据线引线61区域的绝缘材料薄膜(若形成钝化层71,也去除相应区域的钝化层71),以分别形成连接过孔14、第一子过孔15′和第二子过孔16′的图形,且使得PAD区的绝缘材料薄膜的厚度小于其它区域的绝缘材料薄膜的厚度,以形成所述绝缘间隔层8。所述间隔绝缘膜能够增加像素电极和源漏极之间的距离,进而减少寄生电容,降低功耗。形成绝缘间隔层8后的图形如图3所示,PAD区A的绝缘间隔层8的厚度h2小于其它区域的绝缘间隔层8的厚度h1。本实施例中,为了尽量减小高PPI阵列基板中各层导电层的电容及电阻,非PAD区的绝缘间隔层8的厚度优选为绝缘间隔层8采用有机绝缘材料。
形成绝缘间隔层8之后,通过构图工艺在非PAD区形成所述第一透明电极的图形。如图4所示,本实施例中,第一透明电极为像素电极9,该像素电极9通过连接过孔14连接薄膜晶体管的漏极6。本实施例中,形成像素电极9的过程为:
在形成有绝缘间隔层8之后的基板表面沉积一层ITO薄膜,即第一子过孔15′和第二子过孔16′中也沉积有ITO。通过构图工艺形成图4中像素电极9的图形,在该构图工艺中,由于PAD区的绝缘间隔层8厚度较小,第一子过孔15′和第二子过孔16′的深度较浅,其中光刻胶能够得到充分曝光被去除,因此在刻蚀第一子过孔15′和第二子过孔16′中的ITO时不会像图2中残留一部分ITO。优选地,在形成绝缘间隔层8时,使得h2的高度为h1的一半,这样能使光刻胶充分曝光,不容易残留ITO,也便于采用Half Tone mask实现,同时兼具改善rubbing mura,若厚度差异过大(如:2um以上),则容易产生rubbingmura。
如图5所示,形成像素电极9之后,在其上形成一定厚度的钝化层72(),通过构图工艺分别在所述第一子过孔15′和第二子过孔16′对应区域继续刻蚀,直到分别暴露出栅极引线21和数据线引线61,以形成所述第一过孔15和第二过孔16。
步骤三,形成包括第二透明电极、第一连接电极和第二连接电极的图形,使所述第一连接电极通过所述第一过孔连接所述栅极引线,所述第二连接电极通过所述第二过孔连接所述数据线引线。如图6所示,该步骤具体包括:
在钝化层72上形成ITO薄膜,公共构图工艺形成图6中所示的第二透明电极、第一连接电极12和第二连接电极13。本实施例中,第二透明电极为公共电极10(公共电极10连接公共电极线,公共电极线与栅极2及栅极引线21同时形成,图中未示出)。第一连接电极12通过第一过孔15连接栅极引线21,第二连接电极13通过第二过孔16连接数据线引线61,最终形成如图6所示的阵列基板。
由于在步骤二中第一子过孔15′和第二子过孔16′中不会残留制作像素电极9时的ITO,如图7所示,因此能够保证第一连接电极12和第二连接电极13分别与栅极引线21和数据线引线61有足够的接触面积,从而降低了显示装置的亮线高发及异常点灯等不良。
本发明还提供了一种按上述方法制成的阵列基板,如图6所示,包括形成在衬底基板上的薄膜晶体管、第一透明电极、第二透明电极、栅极引线21及数据线引线61。栅极引线21及数据线引线61位于PAD区,还包括位于薄膜晶体管、栅极引线21及数据线引线61上方的绝缘间隔层8(薄膜晶体管、栅极引线21及数据线引线61和绝缘间隔层8之间通常还形成有钝化层71)。所述第一透明电极位于所述绝缘件间隔层8之上的非PAD区,第一透明电极为像素电极9,且连接所述薄膜晶体管的漏极6。第二透明电极为公共电极10,位于像素电极9上方,两者之间间隔有钝化层72,且在所述PAD区的绝缘间隔层8的厚度小于其它区域的绝缘间隔层8的厚度,绝缘间隔层8对应PAD区形成有第一过孔15和第二过孔16,绝缘间隔层8上方还形成有与所述公共电极10位于同一层的第一连接电极12和第二连接电极13,第一连接电极12和第二连接电极13分别通过第一过孔15和第二过孔16连接栅极引线21和数据线引线61。
其中,所述PAD区的绝缘间隔层8厚度为其它区域的绝缘间隔层8厚度的一半。
本发明还提供了一种显示装置,包括上述的阵列基板。该显示装置可以为:液晶面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明,而并非对本发明的限制,有关技术领域的普通技术人员,在不脱离本发明的精神和范围的情况下,还可以做出各种变化和变型,因此所有等同的技术方案也属于本发明的范畴,本发明的专利保护范围应由权利要求限定。
Claims (9)
1.一种阵列基板制作方法,其特征在于,包括步骤:
在衬底基板上形成包括薄膜晶体管、栅极引线及数据线引线的图形,所述栅极引线和数据线引线位于PAD区;
形成绝缘间隔层,第一透明电极及钝化层的图形,使所述阵列基板对应的PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,并在对应栅极引线和数据线引线对应区域分别形成第一过孔和第二过孔,以暴露出所述栅极引线和数据线引线;
形成包括第二透明电极、第一连接电极和第二连接电极的图形,使所述第一连接电极通过所述第一过孔连接所述栅极引线,所述第二连接电极通过所述第二过孔连接所述数据线引线。
2.如权利要求1所述的阵列基板制作方法,其特征在于,所述形成绝缘间隔层,第一透明电极及钝化层的图形,使所述阵列基板对应的PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,并在对应栅极引线和数据线引线对应区域分别形成第一过孔和第二过孔,以暴露出所述栅极引线和数据线引线的步骤具体包括:
形成绝缘材料薄膜,通过构图工艺去除所述第一透明电极与薄膜晶体管的漏极连接区域、所述栅极引线区域及数据线引线区域的绝缘材料薄膜,以分别形成连接过孔、第一子过孔和第二子过孔的图形,且使得PAD区的绝缘材料薄膜的厚度小于其它区域的绝缘材料薄膜的厚度,以形成所述绝缘间隔层;
通过构图工艺在非PAD区形成所述第一透明电极的图形,且所述第一透明电极通过所述连接过孔连接薄膜晶体管的漏极;
形成钝化层,通过构图工艺分别在所述第一子过孔和第二子过孔对应区域继续刻蚀,直到分别暴露出所述栅极引线和数据线引线,以形成所述第一过孔和第二过孔。
3.如权利要求2所述的阵列基板制作方法,其特征在于,所述阵列基板对应的PAD区的绝缘间隔层厚度为其它区域的绝缘间隔层厚度的一半。
4.如权利要求2所述的阵列基板制作方法,其特征在于,非PAD区的绝缘间隔层厚度为
5.如权利要求1~4中任一项所述的阵列基板制作方法,其特征在于,所述绝缘间隔层为有机材料制成。
6.一种阵列基板,包括形成在衬底基板上的薄膜晶体管、第一透明电极、第二透明电极、栅极引线及数据线引线,所述栅极引线及数据线引线位于PAD区,还包括位于薄膜晶体管、栅极引线及数据线引线上方的绝缘间隔层,所述第一透明电极位于所述绝缘间隔层之上的非PAD区,第二透明电极位于第一透明电极上方,两者之间间隔有钝化层,其特征在于,且在所述PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度,所述绝缘间隔层对应PAD区形成有第一过孔和第二过孔,绝缘间隔层上方还形成有与所述第二透明电极位于同一层的第一连接电极和第二连接电极,所述第一连接电极和第二连接电极分别通过第一过孔和第二过孔连接所述栅极引线和数据线引线。
7.如权利要求6所述的阵列基板,其特征在于,所述PAD区的绝缘间隔层厚度为其它区域的绝缘间隔层厚度的一半。
8.如权利要求6所述的阵列基板,其特征在于,所述第一透明电极连接所述薄膜晶体管的漏极。
9.一种显示装置,其特征在于,包括如权利要求6~8中任一项所述的阵列基板。
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CN104701383A (zh) * | 2015-03-24 | 2015-06-10 | 京东方科技集团股份有限公司 | 薄膜晶体管和阵列基板及其制作方法、显示装置 |
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CN104701383B (zh) * | 2015-03-24 | 2018-09-11 | 京东方科技集团股份有限公司 | 薄膜晶体管和阵列基板及其制作方法、显示装置 |
CN105448936A (zh) * | 2016-01-04 | 2016-03-30 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN105448936B (zh) * | 2016-01-04 | 2019-07-23 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN105511188A (zh) * | 2016-02-01 | 2016-04-20 | 昆山龙腾光电有限公司 | 阵列基板和阵列基板的制作方法以及液晶显示装置 |
CN105957867A (zh) * | 2016-04-28 | 2016-09-21 | 京东方科技集团股份有限公司 | 阵列基板母板及其制作方法、显示装置 |
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CN106353937A (zh) * | 2016-11-28 | 2017-01-25 | 京东方科技集团股份有限公司 | 阵列基板、阵列基板的制造方法和显示装置 |
CN106353937B (zh) * | 2016-11-28 | 2020-11-24 | 京东方科技集团股份有限公司 | 阵列基板、阵列基板的制造方法和显示装置 |
CN108388057A (zh) * | 2018-03-16 | 2018-08-10 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板 |
CN108388057B (zh) * | 2018-03-16 | 2020-09-29 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板 |
WO2020186989A1 (zh) * | 2019-03-19 | 2020-09-24 | 京东方科技集团股份有限公司 | 基板及其制作方法、触控显示装置 |
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US20160027799A1 (en) | 2016-01-28 |
US9570473B2 (en) | 2017-02-14 |
WO2015090000A1 (zh) | 2015-06-25 |
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