CN105957867A - 阵列基板母板及其制作方法、显示装置 - Google Patents
阵列基板母板及其制作方法、显示装置 Download PDFInfo
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- CN105957867A CN105957867A CN201610274032.XA CN201610274032A CN105957867A CN 105957867 A CN105957867 A CN 105957867A CN 201610274032 A CN201610274032 A CN 201610274032A CN 105957867 A CN105957867 A CN 105957867A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/038—Macromolecular compounds which are rendered insoluble or differentially wettable
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/039—Macromolecular compounds which are photodegradable, e.g. positive electron resists
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/30—Imagewise removal using liquid means
- G03F7/32—Liquid compositions therefor, e.g. developers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0037—Production of three-dimensional images
Abstract
本发明提供了一种阵列基板母板及其制作方法、显示装置,属于显示技术领域。其中,阵列基板母板的制作方法,至少包括在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形,所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度,深孔为贯穿至少两层绝缘层的过孔,所述制作方法包括:在绝缘层上形成第二导电图形之前,减小第一区域所述绝缘层的厚度,所述第二导电图形通过贯穿所述绝缘层的过孔结构与位于所述绝缘层下的第一导电图形连接。通过本发明的技术方案,在阵列基板上形成不同显示产品的膜层图形时,能够避免出现Mura不良。
Description
技术领域
本发明涉及显示技术领域,特别是指一种阵列基板母板及其制作方法、显示装置。
背景技术
MMG(Multi Mode Group,多显示模式组)产品即是在同一张衬底基板上,同时形成两种或两种以上显示产品的图形,这样可以提高衬底基板的利用率,降低投入成本。目前如图1所示的43MMG产品已经量产,43MMG产品是在同一张衬底基板上形成43英寸的ADS显示产品和18.5英寸的HADS显示产品的图形。
对于43英寸的ADS(高级超维场转换)显示产品和18.5英寸的HADS(高开口率高级超维场转换)显示产品来说,43英寸的ADS显示产品的深孔密度小于18.5英寸的HADS显示产品的深孔密度,其中,深孔为贯穿至少两层绝缘层的过孔,由于在深孔处容易出现凹陷,导致在MMG产品的阵列基板上涂覆配向膜时,配向膜容易在深孔处易发生扩散不均,导致最终的显示产品出现显示Mura(不均匀)的问题。
发明内容
本发明要解决的技术问题是提供一种阵列基板母板及其制作方法、显示装置,在阵列基板上形成不同显示产品的膜层图形时,能够避免出现Mura不良。
为解决上述技术问题,本发明的实施例提供技术方案如下:
一方面,提供一种阵列基板母板的制作方法,至少包括在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形,所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度,深孔为贯穿至少两层绝缘层的过孔,所述制作方法包括:
在绝缘层上形成第二导电图形之前,减小第一区域所述绝缘层的厚度,所述第二导电图形通过贯穿所述绝缘层的过孔结构与位于所述绝缘层下的第一导电图形连接。
进一步地,所述制作方法具体包括:
形成所述第一导电图形;
形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构;
减小第一区域所述绝缘层的厚度;
在所述绝缘层上形成所述第二导电图形。
进一步地,所述形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构,减小第一区域所述绝缘层的厚度,在所述绝缘层上形成所述第二导电图形包括:
在形成有第一导电图形的衬底基板上形成所述绝缘层;
在所述绝缘层上涂覆正性光刻胶,利用灰色调掩膜板对所述正性光刻胶进行曝光,所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形,所述完全透光图形对应用以形成所述过孔结构的区域,所述部分透光图形对应所述第一区域除所述过孔结构之外的区域,所述完全不透光图形对应所述第二区域除所述过孔结构之外的区域;
对正性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域;
对光刻胶完全去除区域的绝缘层进行刻蚀,形成贯穿所述绝缘层的所述过孔结构;
去除光刻胶部分保留区域的正性光刻胶,对光刻胶部分保留区域的绝缘层进行刻蚀,减小光刻胶部分保留区域的绝缘层的厚度。
进一步地,所述形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构,减小第一区域所述绝缘层的厚度,在所述绝缘层上形成所述第二导电图形包括:
在形成有第一导电图形的衬底基板上形成所述绝缘层;
在所述绝缘层上涂覆负性光刻胶,利用灰色调掩膜板对所述负性光刻胶进行曝光,所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形,所述完全不透光图形对应用以形成所述过孔结构的区域,所述部分透光图形对应所述第一区域除所述过孔结构之外的区域,所述完全透光图形对应所述第二区域除所述过孔结构之外的区域;
对负性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域;
对光刻胶完全去除区域的绝缘层进行刻蚀,形成贯穿所述绝缘层的所述过孔结构;
去除光刻胶部分保留区域的负性光刻胶,对光刻胶部分保留区域的绝缘层进行刻蚀,减小光刻胶部分保留区域的绝缘层的厚度。
进一步地,第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极,第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线,第一区域的所述绝缘层为钝化层。
进一步地,所述制作方法具体包括:
提供一衬底基板;
在所述衬底基板的第一区域形成像素电极;
在形成有所述像素电极的衬底基板的第一区域形成薄膜晶体管的栅极;
在形成有所述栅极的衬底基板的第一区域形成栅绝缘层;
在第一区域的所述栅绝缘层上形成有源层;
在形成有所述有源层的衬底基板的第一区域形成薄膜晶体管的源极和漏极;
在形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域形成包括有所述过孔结构的钝化层的图形,所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔,其中,所述第二过孔还贯穿所述栅绝缘层;
在第一区域的所述钝化层上形成导电连接线,所述导电连接线通过所述第一过孔与所述漏极连接,通过所述第二过孔与所述像素电极连接。
进一步地,所述导电连接线为采用透明导电层制成。
进一步地,所述导电连接线与阵列基板第一区域的公共电极为通过一次构图工艺同时形成。
本发明实施例还提供了一种阵列基板母板,所述阵列基板母板至少包括形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形,所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度,深孔为贯穿至少两层绝缘层的过孔,所述阵列基板包括位于绝缘层下的第一导电图形和位于所述绝缘层上的第二导电图形,所述第二导电图形通过贯穿所述绝缘层的过孔结构与所述第一导电图形连接,其中,第一区域的所述绝缘层的厚度小于第二区域所述绝缘层的厚度。
进一步地,第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极,第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线,第一区域的所述绝缘层为钝化层。
进一步地,所述阵列基板具体包括:
衬底基板;
位于所述衬底基板的第一区域的像素电极;
位于形成有所述像素电极的衬底基板的第一区域的薄膜晶体管的栅极;
位于形成有所述栅极的衬底基板的第一区域的栅绝缘层;
位于第一区域的所述栅绝缘层上的有源层;
位于形成有所述有源层的衬底基板的第一区域的薄膜晶体管的源极和漏极;
位于形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域的包括有所述过孔结构的钝化层的图形,所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔,其中,所述第二过孔还贯穿所述栅绝缘层;
位于第一区域的所述钝化层上的导电连接线,所述导电连接线通过所述第一过孔与所述漏极连接,通过所述第二过孔与所述像素电极连接。
进一步地,所述导电连接线与阵列基板第一区域的公共电极为同层同材料设置。
本发明实施例还提供了一种显示装置,包括如上所述的第一显示产品。
本发明的实施例具有以下有益效果:
上述方案中,在阵列基板上形成不同显示产品的膜层图形时,在不增加构图工艺的前提下,减小深孔密度比较大的显示产品的绝缘层的厚度,进而减小该显示产品过孔的深度,这样之后在阵列基板上涂覆配向膜时,能够提高配向膜在过孔处的扩散效果,从而避免出现Mura不良。
附图说明
图1为MMG产品的结构示意图;
图2为本发明实施例对光刻胶进行曝光的示意图;
图3为本发明实施例对光刻胶进行显影后的示意图;
图4为本发明实施例刻蚀出过孔后的示意图;
图5为本发明实施例对光刻胶进行灰化后的示意图;
图6为本发明实施例对钝化层进行减薄后的示意图;
图7为本发明实施例形成第二透明导电层后的示意图。
附图标记
1 衬底基板 2 第一透明导电层 3 栅绝缘层 4 有源层
5 源漏金属层 6 钝化层 7 光刻胶 8 灰色调掩膜板
9 完全透光图形 10 部分透光图形 11 第二透明导电层
12 第一过孔 13 第二过孔 14 栅金属层
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
现有43MMG产品中,18.5英寸的HADS显示产品的薄膜晶体管的漏极和像素电极之间是通过深孔搭接的,即18.5英寸的HADS显示产品每一亚像素区域内都设置有一深孔,因此,18.5英寸的HADS显示产品的深孔密度明显比43英寸的ADS显示产品的深孔密度大,由于在深孔处容易出现凹陷,导致在MMG产品的阵列基板上涂覆配向膜时,配向膜容易在深孔处易发生扩散不均,导致最终的显示产品出现显示Mura的问题。
为了解决上述问题,本发明的实施例提供一种阵列基板母板及其制作方法、显示装置,在阵列基板母板上形成不同显示产品的膜层图形时,能够避免出现Mura不良。
实施例一
本实施例提供一种阵列基板母板的制作方法,至少包括在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形,所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度,深孔为贯穿至少两层绝缘层的过孔,所述制作方法包括:
在绝缘层上形成第二导电图形之前,减小第一区域所述绝缘层的厚度,所述第二导电图形通过贯穿所述绝缘层的过孔结构与位于所述绝缘层下的第一导电图形连接。
本实施例中,在阵列基板上形成不同显示产品的膜层图形时,在不增加构图工艺的前提下,减小深孔密度比较大的显示产品的绝缘层的厚度,进而减小该显示产品过孔的深度,这样之后在阵列基板上涂覆配向膜时,能够提高配向膜在过孔处的扩散效果,从而避免出现显示Mura的问题。
进一步地,所述制作方法具体包括:
形成所述第一导电图形;
形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构;
减小第一区域所述绝缘层的厚度;
在所述绝缘层上形成所述第二导电图形。
具体实施例中,可以通过灰色调掩膜板或半色调掩膜板曝光实现减小第一区域绝缘层的厚度。
进一步地,在利用正性光刻胶进行光刻工艺时,所述形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构,减小第一区域所述绝缘层的厚度,在所述绝缘层上形成所述第二导电图形包括:
在形成有第一导电图形的衬底基板上形成所述绝缘层;
在所述绝缘层上涂覆正性光刻胶,利用灰色调掩膜板对所述正性光刻胶进行曝光,所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形,所述完全透光图形对应用以形成所述过孔结构的区域,所述部分透光图形对应所述第一区域除所述过孔结构之外的区域,所述完全不透光图形对应所述第二区域除所述过孔结构之外的区域;
对正性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域;
对光刻胶完全去除区域的绝缘层进行刻蚀,形成贯穿所述绝缘层的所述过孔结构;
去除光刻胶部分保留区域的正性光刻胶,对光刻胶部分保留区域的绝缘层进行刻蚀,减小光刻胶部分保留区域的绝缘层的厚度。
进一步地,在利用负性光刻胶进行光刻工艺时,所述形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构,减小第一区域所述绝缘层的厚度,在所述绝缘层上形成所述第二导电图形包括:
在形成有第一导电图形的衬底基板上形成所述绝缘层;
在所述绝缘层上涂覆负性光刻胶,利用灰色调掩膜板对所述负性光刻胶进行曝光,所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形,所述完全不透光图形对应用以形成所述过孔结构的区域,所述部分透光图形对应所述第一区域除所述过孔结构之外的区域,所述完全透光图形对应所述第二区域除所述过孔结构之外的区域;
对负性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域;
对光刻胶完全去除区域的绝缘层进行刻蚀,形成贯穿所述绝缘层的所述过孔结构;
去除光刻胶部分保留区域的负性光刻胶,对光刻胶部分保留区域的绝缘层进行刻蚀,减小光刻胶部分保留区域的绝缘层的厚度。
进一步地,第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极,第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线,第一区域的所述绝缘层为钝化层。
进一步地,所述制作方法具体包括:
提供一衬底基板;
在所述衬底基板的第一区域形成像素电极;
在形成有所述像素电极的衬底基板的第一区域形成薄膜晶体管的栅极;
在形成有所述栅极的衬底基板的第一区域形成栅绝缘层;
在第一区域的所述栅绝缘层上形成有源层;
在形成有所述有源层的衬底基板的第一区域形成薄膜晶体管的源极和漏极;
在形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域形成包括有所述过孔结构的钝化层的图形,所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔,其中,所述第二过孔还贯穿所述栅绝缘层;
在第一区域的所述钝化层上形成导电连接线,所述导电连接线通过所述第一过孔与所述漏极连接,通过所述第二过孔与所述像素电极连接。
进一步地,为了不影响显示,导电连接线为采用透明导电层制成。
进一步地,所述导电连接线与阵列基板第一区域的公共电极为通过一次构图工艺同时形成,这样可以减少阵列基板的构图次数,提高阵列基板的生产效率,降低阵列基板的生产成本。
本实施例形成的阵列基板母板与彩膜基板对盒后形成一个大的显示面板,之后对显示面板进行切割即可形成多个43英寸的ADS显示产品和多个18.5英寸的HADS显示产品。
实施例二
本实施例提供了一种阵列基板母板,所述阵列基板母板至少包括形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形,所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度,深孔为贯穿至少两层绝缘层的过孔,所述阵列基板包括位于绝缘层下的第一导电图形和位于所述绝缘层上的第二导电图形,所述第二导电图形通过贯穿所述绝缘层的过孔结构与所述第一导电图形连接,其中,第一区域的所述绝缘层的厚度小于第二区域所述绝缘层的厚度。
本实施例中,在阵列基板上形成不同显示产品的膜层图形时,深孔密度比较大的显示产品的绝缘层的厚度比较小,进而该显示产品过孔的深度也比较小,这样之后在阵列基板上涂覆配向膜时,能够提高配向膜在过孔处的扩散效果,从而避免出现Mura不良。
进一步地,第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极,第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线,第一区域的所述绝缘层为钝化层。
进一步地,所述阵列基板具体包括:
衬底基板;
位于所述衬底基板的第一区域的像素电极;
位于形成有所述像素电极的衬底基板的第一区域的薄膜晶体管的栅极;
位于形成有所述栅极的衬底基板的第一区域的栅绝缘层;
位于第一区域的所述栅绝缘层上的有源层;
位于形成有所述有源层的衬底基板的第一区域的薄膜晶体管的源极和漏极;
位于形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域的包括有所述过孔结构的钝化层的图形,所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔,其中,所述第二过孔还贯穿所述栅绝缘层;
位于第一区域的所述钝化层上的导电连接线,所述导电连接线通过所述第一过孔与所述漏极连接,通过所述第二过孔与所述像素电极连接。
进一步地,所述导电连接线与阵列基板第一区域的公共电极为同层同材料设置。这样,导电连接线与阵列基板的公共电极可以通过一次构图工艺同时形成,这样可以减少阵列基板的构图次数,提高阵列基板的生产效率,降低阵列基板的生产成本。
实施例三
本实施例提供了一种显示装置,包括如上所述的第一区域。所述显示装置可以为:液晶面板、液晶电视、液晶显示器、数码相框、手机、平板电脑、导航仪、电子纸等任何具有显示功能的产品或部件。
实施例四
下面以43MMG产品为例,对本发明的阵列基板母板的制作方法进行进一步介绍。43MMG产品的阵列基板母板的制作方法为:形成第一透明导电层的图形-形成栅金属层的图形-形成源漏金属层的图形-形成钝化层-形成第二透明导电层的图形,本实施例是在原有阵列基板的制作工艺流程不变的前提下,利用半色调掩膜板或灰色调掩膜板对钝化层进行曝光,再通过刻蚀灰化等手段使得18.5英寸的HADS显示产品的钝化层厚度小于43英寸的ADS显示产品的钝化层厚度,从而在不增加构图工艺的前提下,减小18.5英寸的HADS显示产品的钝化层过孔的深度。具体地,本实施例的阵列基板母板的制作方法具体包括以下步骤:
步骤1、提供一衬底基板1,在衬底基板1上沉积第一透明导电层2,通过构图工艺形成第一透明导电层2的图形;
其中,衬底基板1可为玻璃基板或石英基板。具体地,可以在衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的第一透明导电层2,第一透明导电层2可以选用ITO。在第一透明导电层2上涂覆光刻胶,进行曝光、显影,刻蚀第一透明导电层2,并剥离光刻胶,形成第一透明导电层2的图形,第一透明导电层2的图形包括43英寸的ADS显示产品的公共电极和18.5英寸的HADS显示产品的像素电极。
步骤2、在经过步骤1的衬底基板1上形成栅金属层14的图形;
具体地,可以在经过步骤2的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的栅金属层14,栅金属层14可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金。栅金属层14可以是单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。在栅金属层14上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,使光刻胶形成光刻胶未保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于栅金属层14的图形所在区域,光刻胶未保留区域对应于上述图形以外的区域;进行显影处理,光刻胶未保留区域的光刻胶被完全去除,光刻胶保留区域的光刻胶厚度保持不变;通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属层,剥离剩余的光刻胶,形成栅金属层14的图形,栅金属层14的图形包括43英寸的ADS显示产品的栅线、薄膜晶体管的栅极和18.5英寸的HADS显示产品的栅线、薄膜晶体管的栅极。
步骤3、在经过步骤2的衬底基板1上形成栅绝缘层3和有源层4的图形;
具体地,可以采用等离子体增强化学气相沉积(PECVD)方法,在经过步骤2的衬底基板1上沉积厚度约为的栅绝缘层3,其中,栅绝缘层3的材料可以选用氧化物、氮化物或者氮氧化物,栅绝缘层3可以为单层、双层或多层结构。具体地,栅绝缘层3可以采用SiNx,SiOx或Si(ON)x。
在栅绝缘层3上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的半导体层,在半导体层上涂覆光刻胶,进行曝光、显影,刻蚀半导体层,并剥离光刻胶,形成由半导体层组成的有源层4的图形,有源层4的图形包括43英寸的ADS显示产品的有源层和18.5英寸的HADS显示产品的有源层。
步骤4、在经过步骤3的衬底基板1上形成源漏金属层5的图形;
具体地,可以在经过步骤3的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的源漏金属层5,源漏金属层5可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金。源漏金属层5可以是单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。在源漏金属层5上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,使光刻胶形成光刻胶未保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于源漏金属层5的图形所在区域,光刻胶未保留区域对应于上述图形以外的区域;进行显影处理,光刻胶未保留区域的光刻胶被完全去除,光刻胶保留区域的光刻胶厚度保持不变;通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属薄膜,剥离剩余的光刻胶,形成源漏金属层5的图形,源漏金属层5的图形包括43英寸的ADS显示产品的数据线、薄膜晶体管的源极、漏极和18.5英寸的HADS显示产品的数据线、薄膜晶体管的源极、漏极。
步骤5、在经过步骤4的衬底基板1上形成包括有过孔结构的钝化层6的图形,过孔结构包括有对应18.5英寸的HADS显示产品的漏极的第一过孔和对应18.5英寸的HADS显示产品的像素电极的第二过孔,第二过孔还贯穿栅绝缘层3;
具体地,如图2所示,在经过步骤4的衬底基板1上沉积钝化层6,在钝化层6上涂覆光刻胶7,利用灰色调掩膜板8对光刻胶7进行曝光,灰色调掩膜板8包括部分透光图形10、完全透光图形9和完全不透光图形(未图示),完全透光图形9对应用以形成过孔结构的区域,部分透光图形10对应第一区域除过孔结构之外的区域,完全不透光图形对应第二区域除过孔结构之外的区域,其中,第一区域为18.5英寸的HADS显示产品所在区域,第二区域为43英寸的ADS显示产品所在区域。
如图3所示,对光刻胶7进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域(未图示)。
如图4所示,对光刻胶完全去除区域的钝化层6进行刻蚀,形成贯穿钝化层6的过孔结构,在图4所示的第一区域中,过孔结构包括对应18.5英寸的HADS显示产品的漏极的第一过孔12和对应18.5英寸的HADS显示产品的像素电极的第二过孔13,第一过孔12贯穿钝化层6,第二过孔13贯穿钝化层6和栅绝缘层3;
如图5所示,通过灰化工艺去除光刻胶部分保留区域和光刻胶完全保留区域的光刻胶7,使得光刻胶部分保留区域的光刻胶7完全去除,光刻胶完全保留区域的光刻胶7的厚度也得以减薄。
如图6所示,对光刻胶部分保留区域的钝化层6进行刻蚀,通过精确控制刻蚀时间,减小光刻胶部分保留区域的钝化层6的厚度,进而减小第一过孔12和第二过孔13的深度,减少第一过孔12和第二过孔13处段差,避免Mura不良。此时,由于光刻胶完全保留区域仍然保留有光刻胶7,因此,光刻胶完全保留区域的钝化层6的厚度不会减小,即最终使得第一区域的钝化层6的厚度小于第二区域的钝化层6的厚度。
步骤6、在经过步骤5的衬底基板1上形成第二透明导电层11,对第二透明导电层11进行构图形成第二透明导电层11的图形。
具体地,如图7所示,可以在经过步骤5的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的第二透明导电层11,第二透明导电层11可以选用ITO。在第二透明导电层11上涂覆光刻胶,进行曝光、显影,刻蚀第二透明导电层11,并剥离光刻胶,形成第二透明导电层11的图形,第二透明导电层11的图形包括导电连接线、43英寸的ADS显示产品的像素电极和18.5英寸的HADS显示产品的公共电极,对于18.5英寸的HADS显示产品而言,导电连接线通过第一过孔12与薄膜晶体管的漏极连接,通过第二过孔13与像素电极连接,这样通过导电连接线即可实现薄膜晶体管的漏极与像素电极之间的电连接。
经过上述步骤1-6即可制作得到如图7所示的阵列基板,本实施例在保持原有阵列基板的制作工艺流程不变的情况下,利用半色调掩膜板或灰色调掩膜板对钝化层进行曝光,使得18.5英寸的HADS显示产品的钝化层厚度小于43英寸的ADS显示产品的钝化层厚度,从而在不增加构图工艺的前提下,减小18.5英寸的HADS显示产品的钝化层过孔的深度,这样之后在阵列基板上涂覆配向膜时,能够提高配向膜在过孔处的扩散效果,从而避免出现Mura不良。
以上所述是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (13)
1.一种阵列基板母板的制作方法,至少包括在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形,所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度,深孔为贯穿至少两层绝缘层的过孔,其特征在于,所述制作方法包括:
在绝缘层上形成第二导电图形之前,减小第一区域所述绝缘层的厚度,所述第二导电图形通过贯穿所述绝缘层的过孔结构与位于所述绝缘层下的第一导电图形连接。
2.根据权利要求1所述的阵列基板母板的制作方法,其特征在于,所述制作方法具体包括:
形成所述第一导电图形;
形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构;
减小第一区域所述绝缘层的厚度;
在所述绝缘层上形成所述第二导电图形。
3.根据权利要求2所述的阵列基板母板的制作方法,其特征在于,所述形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构,减小第一区域所述绝缘层的厚度,在所述绝缘层上形成所述第二导电图形包括:
在形成有第一导电图形的衬底基板上形成所述绝缘层;
在所述绝缘层上涂覆正性光刻胶,利用灰色调掩膜板对所述正性光刻胶进行曝光,所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形,所述完全透光图形对应用以形成所述过孔结构的区域,所述部分透光图形对应所述第一区域除所述过孔结构之外的区域,所述完全不透光图形对应所述第二区域除所述过孔结构之外的区域;
对正性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域;
对光刻胶完全去除区域的绝缘层进行刻蚀,形成贯穿所述绝缘层的所述过孔结构;
去除光刻胶部分保留区域的正性光刻胶,对光刻胶部分保留区域的绝缘层进行刻蚀,减小光刻胶部分保留区域的绝缘层的厚度。
4.根据权利要求2所述的阵列基板母板的制作方法,其特征在于,所述形成覆盖所述第一导电图形的绝缘层,并形成贯穿所述绝缘层的过孔结构,减小第一区域所述绝缘层的厚度,在所述绝缘层上形成所述第二导电图形包括:
在形成有第一导电图形的衬底基板上形成所述绝缘层;
在所述绝缘层上涂覆负性光刻胶,利用灰色调掩膜板对所述负性光刻胶进行曝光,所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形,所述完全不透光图形对应用以形成所述过孔结构的区域,所述部分透光图形对应所述第一区域除所述过孔结构之外的区域,所述完全透光图形对应所述第二区域除所述过孔结构之外的区域;
对负性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域;
对光刻胶完全去除区域的绝缘层进行刻蚀,形成贯穿所述绝缘层的所述过孔结构;
去除光刻胶部分保留区域的负性光刻胶,对光刻胶部分保留区域的绝缘层进行刻蚀,减小光刻胶部分保留区域的绝缘层的厚度。
5.根据权利要求3或4所述的阵列基板母板的制作方法,其特征在于,第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极,第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线,第一区域的所述绝缘层为钝化层。
6.根据权利要求5所述的阵列基板母板的制作方法,其特征在于,所述制作方法具体包括:
提供一衬底基板;
在所述衬底基板的第一区域形成像素电极;
在形成有所述像素电极的衬底基板的第一区域形成薄膜晶体管的栅极;
在形成有所述栅极的衬底基板的第一区域形成栅绝缘层;
在第一区域的所述栅绝缘层上形成有源层;
在形成有所述有源层的衬底基板的第一区域形成薄膜晶体管的源极和漏极;
在形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域形成包括有所述过孔结构的钝化层的图形,所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔,其中,所述第二过孔还贯穿所述栅绝缘层;
在第一区域的所述钝化层上形成导电连接线,所述导电连接线通过所述第一过孔与所述漏极连接,通过所述第二过孔与所述像素电极连接。
7.根据权利要求5所述的阵列基板母板的制作方法,其特征在于,所述导电连接线为采用透明导电层制成。
8.根据权利要求7所述的阵列基板母板的制作方法,其特征在于,所述导电连接线与阵列基板第一区域的公共电极为通过一次构图工艺同时形成。
9.一种阵列基板母板,所述阵列基板母板至少包括形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形,所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度,深孔为贯穿至少两层绝缘层的过孔,其特征在于,所述阵列基板包括位于绝缘层下的第一导电图形和位于所述绝缘层上的第二导电图形,所述第二导电图形通过贯穿所述绝缘层的过孔结构与所述第一导电图形连接,其中,第一区域的所述绝缘层的厚度小于第二区域所述绝缘层的厚度。
10.根据权利要求9所述的阵列基板母板,其特征在于,第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极,第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线,第一区域的所述绝缘层为钝化层。
11.根据权利要求10所述的阵列基板母板,其特征在于,所述阵列基板具体包括:
衬底基板;
位于所述衬底基板的第一区域的像素电极;
位于形成有所述像素电极的衬底基板的第一区域的薄膜晶体管的栅极;
位于形成有所述栅极的衬底基板的第一区域的栅绝缘层;
位于第一区域的所述栅绝缘层上的有源层;
位于形成有所述有源层的衬底基板的第一区域的薄膜晶体管的源极和漏极;
位于形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域的包括有所述过孔结构的钝化层的图形,所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔,其中,所述第二过孔还贯穿所述栅绝缘层;
位于第一区域的所述钝化层上的导电连接线,所述导电连接线通过所述第一过孔与所述漏极连接,通过所述第二过孔与所述像素电极连接。
12.根据权利要求10所述的阵列基板母板,其特征在于,所述导电连接线与阵列基板第一区域的公共电极为同层同材料设置。
13.一种显示装置,其特征在于,包括如权利要求9-12中任一项所述的第一显示产品。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107204344A (zh) * | 2017-05-23 | 2017-09-26 | 深圳市华星光电技术有限公司 | Tft阵列基板结构 |
WO2017185830A1 (zh) * | 2016-04-28 | 2017-11-02 | 京东方科技集团股份有限公司 | 阵列基板母板及其制作方法、显示装置 |
CN108598039A (zh) * | 2018-04-28 | 2018-09-28 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示装置 |
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WO2020088082A1 (zh) * | 2018-10-30 | 2020-05-07 | 京东方科技集团股份有限公司 | 显示基板母板及其制作方法 |
CN111477120A (zh) * | 2020-05-21 | 2020-07-31 | 京东方科技集团股份有限公司 | 一种显示母板及其分离方法和制作方法、显示面板 |
CN113741071A (zh) * | 2021-08-31 | 2021-12-03 | 惠科股份有限公司 | 显示面板的制造方法及显示面板 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101452933A (zh) * | 2008-12-30 | 2009-06-10 | 电子科技大学 | Bcd半导体器件及其制造方法 |
CN202421681U (zh) * | 2011-10-17 | 2012-09-05 | 京东方科技集团股份有限公司 | 像素单元、阵列基板、液晶面板及显示装置 |
CN103681488A (zh) * | 2013-12-16 | 2014-03-26 | 合肥京东方光电科技有限公司 | 阵列基板及其制作方法,显示装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100646783B1 (ko) | 1999-11-23 | 2006-11-17 | 삼성전자주식회사 | 액정 표시 장치용 박막 트랜지스터 기판 및 그 제조 방법 |
WO2004053816A1 (ja) * | 2002-12-10 | 2004-06-24 | Semiconductor Energy Laboratory Co., Ltd. | 発光装置およびその作製方法 |
CN102097389B (zh) | 2011-01-12 | 2013-11-06 | 深圳市联德合微电子有限公司 | 一种ldmos、集成该ldmos的半导体器件及其制造方法 |
KR20150008590A (ko) * | 2013-07-15 | 2015-01-23 | 삼성디스플레이 주식회사 | 표시 기판 및 표시 기판의 제조 방법 |
JP2016143606A (ja) * | 2015-02-04 | 2016-08-08 | セイコーエプソン株式会社 | 有機el装置、及び電子機器 |
CN105957867B (zh) | 2016-04-28 | 2018-12-18 | 京东方科技集团股份有限公司 | 阵列基板母板及其制作方法、显示装置 |
-
2016
- 2016-04-28 CN CN201610274032.XA patent/CN105957867B/zh active Active
-
2017
- 2017-01-11 WO PCT/CN2017/070833 patent/WO2017185830A1/zh active Application Filing
- 2017-01-11 US US15/544,562 patent/US10504943B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101452933A (zh) * | 2008-12-30 | 2009-06-10 | 电子科技大学 | Bcd半导体器件及其制造方法 |
CN202421681U (zh) * | 2011-10-17 | 2012-09-05 | 京东方科技集团股份有限公司 | 像素单元、阵列基板、液晶面板及显示装置 |
CN103681488A (zh) * | 2013-12-16 | 2014-03-26 | 合肥京东方光电科技有限公司 | 阵列基板及其制作方法,显示装置 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017185830A1 (zh) * | 2016-04-28 | 2017-11-02 | 京东方科技集团股份有限公司 | 阵列基板母板及其制作方法、显示装置 |
US10504943B2 (en) | 2016-04-28 | 2019-12-10 | Boe Technology Group Co., Ltd. | Method for manufacturing an array substrate motherboard |
CN107204344A (zh) * | 2017-05-23 | 2017-09-26 | 深圳市华星光电技术有限公司 | Tft阵列基板结构 |
CN108598039A (zh) * | 2018-04-28 | 2018-09-28 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示装置 |
CN108598039B (zh) * | 2018-04-28 | 2020-11-24 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示装置 |
WO2020088082A1 (zh) * | 2018-10-30 | 2020-05-07 | 京东方科技集团股份有限公司 | 显示基板母板及其制作方法 |
US11227839B2 (en) | 2018-10-30 | 2022-01-18 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate motherboard and method for manufacturing the same |
CN110364426A (zh) * | 2019-07-29 | 2019-10-22 | 昆山国显光电有限公司 | 显示面板母板及其制备方法 |
CN111477120A (zh) * | 2020-05-21 | 2020-07-31 | 京东方科技集团股份有限公司 | 一种显示母板及其分离方法和制作方法、显示面板 |
CN111477120B (zh) * | 2020-05-21 | 2022-07-05 | 京东方科技集团股份有限公司 | 一种显示母板及其分离方法和制作方法、显示面板 |
CN113741071A (zh) * | 2021-08-31 | 2021-12-03 | 惠科股份有限公司 | 显示面板的制造方法及显示面板 |
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