WO2020088082A1 - 显示基板母板及其制作方法 - Google Patents

显示基板母板及其制作方法 Download PDF

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Publication number
WO2020088082A1
WO2020088082A1 PCT/CN2019/103715 CN2019103715W WO2020088082A1 WO 2020088082 A1 WO2020088082 A1 WO 2020088082A1 CN 2019103715 W CN2019103715 W CN 2019103715W WO 2020088082 A1 WO2020088082 A1 WO 2020088082A1
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WIPO (PCT)
Prior art keywords
display panel
film
marking
pattern
substrate
Prior art date
Application number
PCT/CN2019/103715
Other languages
English (en)
French (fr)
Inventor
杜丽丽
龙跃
周宏军
宋二龙
曾超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020564869A priority Critical patent/JP2022503370A/ja
Priority to US16/649,787 priority patent/US11227839B2/en
Priority to EP19856415.5A priority patent/EP3876028A4/en
Publication of WO2020088082A1 publication Critical patent/WO2020088082A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate mother board and a method for manufacturing the same.
  • a plurality of display substrates are fabricated on one display substrate mother board, that is, one substrate includes a plurality of display panel regions, and each display panel region is provided with all the functional film patterns of the display substrate. After all the display substrates are manufactured, they are cut into multiple independent display substrates through a cutting process.
  • the existing mark patterns are small-area thin-film patterns. The small-area mark patterns are easy to fall off and are washed into the display panel area of the substrate, which affects the performance of the product and even causes the product to not work normally.
  • an embodiment of the present disclosure provides a method for manufacturing a display substrate motherboard, the display substrate motherboard including a substrate, the substrate including at least two display panel regions, each The periphery of the display panel area has a marking area.
  • the manufacturing method includes: forming a first film in the marking area; and performing a patterning process on the first film to form a plurality of marking patterns.
  • the mark pattern is a via formed on the first film.
  • the manufacturing method further includes: forming a second film in the display panel area of the substrate; and performing a patterning process on the second film to form the second film Pattern, wherein the forming of the first thin film in the marking area and the forming of the second thin film in the display panel area of the substrate include: simultaneously forming the first thin film and the first thin film through a film forming process using the same material Two films.
  • the step of performing a patterning process on the first film and the second film includes: using a masking plate to perform a patterning process on the second film and the corresponding on the display panel area at the same time Pattern the first film in the marked area to form the pattern of the second film and the marked pattern on the first film, and use the mask to sequentially sequence the second film and the corresponding The first film in the marking area is subjected to a patterning process; wherein, the formed marking pattern includes: at least one first marking pattern on one side of the display panel area and at least one second marking pattern on the opposite side, The marking area between two adjacent display panel areas has a first marking pattern and a second marking pattern, according to the first marking pattern and the position corresponding to the position of the marking area between the adjacent two display panel areas The offset amount of the two-mark pattern relative to the set distance to obtain the patterning process performed on the second films of the two adjacent display panel areas Exposure offset.
  • the display substrate mother board is an organic electroluminescent display substrate mother board;
  • the patterning process of the second thin film to form the pattern of the second thin film includes: The two thin films are subjected to a patterning process to form a flat layer or a pixel defining layer of the mother substrate of the organic electroluminescent display substrate.
  • the display substrate motherboard is a liquid crystal display substrate motherboard;
  • the patterning process of the second film to form the pattern of the second film includes: The patterning process forms a flat layer of the mother board of the liquid crystal display substrate.
  • the material of the first film and the second film is photoresist.
  • the patterning process of the second thin film to form the pattern of the second thin film includes: performing the second thin film in at least one display panel area of the substrate In the patterning process, the mask plate and the display panel area are aligned through the mark pattern, and the second thin film is patterned using the mask plate.
  • an embodiment of the present disclosure also provides a display substrate motherboard, including: a substrate, the substrate including at least two display panel regions, each of which has a periphery A marking area; and a first film located in the marking area, the first film includes a plurality of marking patterns, and the marking patterns are vias formed in the first film.
  • the display substrate mother board further includes: a second film disposed on the substrate, the second film being located in the display panel area.
  • the first film and the second film are the same film.
  • the mark pattern includes at least one first mark pattern on one side of the display panel area and at least one second mark pattern on the opposite side, adjacent two There are a first marking graphic and a second marking graphic between the display panel areas, so as to set relative to the first marking graphic and the second marking graphic corresponding to the position between the two adjacent display panel areas
  • the distance offset can obtain the exposure offset in the patterning process performed on the first thin films of the two adjacent display panel regions.
  • the vertical projection line segment on the side of the substrate of the first marking pattern located on the periphery of the display panel area and the corresponding second marking pattern at least partially coincide, and the position corresponding to The first connection line between the center of the first marking pattern and the center of the second marking pattern extends substantially in the first direction;
  • the substrate includes two display panel areas adjacent in the first direction, the two display panels
  • the second connection line of the center of the area is parallel to the first connection line, and the distance between the centers of the two display panel areas and the center of the first marking pattern on the opposite sides of a display panel area and corresponding positions
  • the distance between the centers of the second marking patterns is substantially the same, and the set distance is zero.
  • the first marking pattern and the second marking pattern located on opposite sides of the display panel area and corresponding to the positions, with the display panel area perpendicular to the first connection line
  • the central axis is substantially symmetrically distributed.
  • the shapes and aperture sizes of the first marking pattern and the second marking pattern are substantially the same.
  • the substrate includes at least four display panel regions, and the at least four display panel regions are substantially matrix-distributed.
  • the display substrate motherboard is an organic electroluminescence display substrate motherboard;
  • the second thin film is a flat layer or pixel definition layer of the organic electroluminescence display substrate motherboard.
  • the display substrate motherboard is a liquid crystal display substrate motherboard; the second film is a flat layer of the liquid crystal display substrate motherboard.
  • the marking pattern is a regularly shaped via.
  • the via hole includes at least one of a square hole, a cross-shaped hole, and a triangular hole.
  • the marking pattern is an irregularly shaped via.
  • an embodiment of the present disclosure also provides a method for obtaining the exposure offset during the manufacturing process of the display substrate motherboard described in the first aspect, including: The offset of the first marking pattern and the second marking pattern corresponding to the position of the marking area between the two display panel areas relative to the set distance, to obtain the composition of the second film of the two adjacent display panel areas Exposure offset in the process.
  • FIG. 1 and FIG. 2 show the manufacturing process of a mark pattern on a substrate in the related art for obtaining exposure offsets of two adjacent display panel areas;
  • FIG. 3 shows the formation principle of the mark pattern between two adjacent display panel areas in FIG. 2;
  • FIG. 4 shows a schematic diagram of a mark pattern on a substrate used to obtain exposure offsets of two adjacent display panel areas falling off in the related art
  • 5 and 7 show the manufacturing process of the mark pattern on the substrate for obtaining the exposure offset of the two adjacent display panel areas in the embodiment of the present disclosure
  • FIG. 6 shows a schematic structural diagram of a substrate when two adjacent display panel areas have no exposure offset in the embodiment of the present disclosure
  • FIG. 8 shows the formation principle of the mark pattern between two adjacent display panel areas in FIG. 7.
  • a plurality of display substrates are fabricated on one display substrate mother board, that is, one substrate includes a plurality of display panel regions, and each display panel region is provided with all the functional film patterns of the display substrate. After all the display substrates are manufactured, they are cut into multiple independent display substrates through a cutting process.
  • the existing marking pattern is a thin-area thin film pattern, and its shape may be a cross shape, a ring shape, a square shape, or the like. The small-area marking pattern is easy to fall off, and is washed into the display panel area of the substrate, which affects the performance of the product and even causes the product to not work properly.
  • a substrate needs to be exposed multiple times.
  • Each exposure of the mask is called a shot.
  • the offset of the two shots in the same substrate is Stitch Mark, Stitch
  • the distribution of Mark on the substrate / mask and the exposure relationship between shot and shot are as follows.
  • the Stitch Marks of the upper and left borders of the mask plate can be displayed on a display panel area 200 ′ of the substrate 100 ′ (each The display panel area 200 'is used to form a display substrate mother board).
  • a large ring-shaped first marking pattern 1' as shown in the upper left of FIG. 1 is exposed on the flat layer / pixel defining layer 10 'around the bottom of the mask.
  • the Stitch Mark of the bezel and the right bezel can expose a small square second mark pattern 2 'as shown in the lower left of FIG.
  • the specific principle of obtaining the offset of two shots is as follows: As shown in FIG. 3, between two adjacent display panel areas 200 ', the Stitch Mark on the flat layer / pixel defining layer 10' can be obtained in the previous shot
  • the second marking pattern 2 '(for example, 15um) with a small square shape as shown in FIG. 3 and the first marking pattern 1' (for example, inner diameter: 7.5um with a large ring shape as shown in FIG. 3 can be obtained by a subsequent shot , Outer diameter: 20um)
  • the resulting small ring for example, inner diameter: 7.5um, outer diameter: 15um
  • the small area island type (ring, small square) is very easy to fall off. After being dropped, it is washed by the rinse liquid to the backplane circuit or the light-emitting pixel area, which will affect the light emission, which will Affect the product yield, as shown in Figure 4.
  • the present application provides a method for manufacturing a display substrate mother board, the display substrate mother board includes a substrate, and the substrate includes at least two display panel regions, and each of the display panel regions With a marked area, the manufacturing method includes:
  • the mark pattern is a via formed on the first film.
  • the marking pattern of the mother board of the display substrate manufactured by the above manufacturing method is a via formed in the film, rather than a small-area island type thin film pattern, thereby overcoming the possibility of the marking pattern falling off, and further ensuring the reliability and yield of the product.
  • the present disclosure also provides a display substrate mother board made by the manufacturing method described above, the display substrate mother board including a first film located in the marked area, the first film including a substrate A plurality of mark patterns, the mark patterns are vias formed on the first film.
  • the size of the mask plate for exposing the thin film on the display substrate mother board is small, therefore, one display substrate mother board
  • the multiple display panel areas need multiple exposure processes using a mask to complete the production of the same functional thin film pattern.
  • the same functional thin film pattern is a pixel electrode, a gate electrode, a source electrode, or a drain electrode of a thin film transistor in all display panel areas.
  • a mark pattern is made around the display panel area, and the offset of the two exposures is obtained by the mark pattern.
  • the technical solution of the present disclosure is specifically described by taking a mask to expose only a thin film in one display panel area at a time.
  • the technical solution of the present disclosure is only introduced as an example, and the technical solution of the present disclosure is also applicable to the case where a mask plate exposes the thin films of at least two adjacent display panel regions at a time.
  • only The at least two adjacent display panel areas are regarded as a larger display panel area, which is the same as or similar to the technical solution of exposing a film of only one display panel area by one mask at a time, and is not detailed here. Narrate.
  • the two exposures before and after in this embodiment refer to: two exposure processes when the same functional thin film pattern is produced in two adjacent display panel areas.
  • the patterning process for the display panel area refers to the patterning process for the thin film in the display panel area.
  • the patterning process includes using a mask to expose the thin film in the display panel area.
  • the display substrate motherboard in this embodiment includes a substrate 100, and the substrate 100 includes at least two display panel regions 200, and each display panel region 200 has a marking region 201 on the periphery.
  • a first film 10 is formed in the marking area 201, and a patterning process is performed on the first film 10 to form a pattern including a plurality of marking patterns, and the marking pattern is a via 101 formed in the first film 10;
  • a second film 20 is formed in the display panel area 200, and a patterning process is performed on the second film 20 to form a pattern of the second film 20.
  • forming the first film 10 in the marking area 201 and forming the second film 20 in the display panel area 200 include:
  • the first thin film 10 and the second thin film 20 are simultaneously formed by using the same material in one film forming process.
  • the first film 10 and the second film 20 are the same film, to simplify the manufacturing process and reduce the cost.
  • the materials of the first thin film 10 and the second thin film 20 can be photoresist, and the via 101 (marking pattern) and the pattern of the second thin film 20 can be formed on the first thin film 10 only through the exposure process To further simplify the manufacturing process.
  • the step of performing a patterning process on the first film 10 and the second film 20 includes:
  • a patterning process is used to pattern the second film 20 of the display panel area 200 and the first film 10 of the corresponding marking area 201 at a time using a masking plate to form the pattern of the second film 20 and the first film 10 Mark pattern on the top, and use the mask to sequentially perform a patterning process on the second film 20 of all display panel areas 200 and the first film 10 of the corresponding mark area 201;
  • the marking patterns formed by the above steps include: at least one first marking pattern 11 on one side of the display panel area 200 and at least one second marking pattern 12 on the opposite side, between two adjacent display panel areas 200
  • the first marking pattern 11 and the second marking pattern 12 are provided to offset the relative distance between the first marking pattern 11 and the second marking pattern 12 corresponding to the position between the two adjacent display panel regions 200
  • the amount of exposure offset in the patterning process performed on the second films of the two adjacent display panel regions 200 is obtained.
  • the above manufacturing method uses the mark pattern corresponding to the position between two adjacent display panel areas to obtain the exposure offset in the composition process of the two adjacent display panel areas, because the mark pattern is an Holes, rather than small-area island-shaped thin film patterns, effectively overcome the possibility of marking patterns falling off, further ensuring the reliability and yield of the product.
  • the method for obtaining the exposure offset during the manufacturing process of the display substrate motherboard described above includes:
  • the offset of the first marking pattern and the second marking pattern which are located between the two adjacent display panel areas and the corresponding positions, with respect to the set distance, obtain the first The exposure offset in the patterning process performed by the two films.
  • the offset amount (ie, the exposure offset) of the mark pattern located at the periphery of the two adjacent display panel regions 200 and corresponding to the position relative to the set distance can be used to obtain the two adjacent display panel regions The amount of exposure shift in the patterning process performed by the second film 20 of 200.
  • the distribution rules of the marking patterns on the periphery of all the display panel regions 200 are the same, so by setting the distance between two adjacent display panel regions 200 The set distance between the first marking pattern 11 and the second marking pattern 12 between two adjacent display panel regions 200 may be set.
  • the mark pattern formed on the periphery of the two display panel regions 200 through the exposure process also shifts.
  • the offset amount that is, the exposure offset amount
  • the exposure offset amount of the first mark pattern 11 and the second mark pattern 12 located between the two adjacent display panel areas 200 and corresponding to the position relative to the set distance the offset offset in the patterning process performed by the second films 20 of the two adjacent display panel regions 200.
  • the exposure offset can be quickly and accurately obtained the exposure offset of the two adjacent display panel areas.
  • the positions of the first marking patterns 11 and the second marking patterns 12 located on opposite sides of the same display panel area 200 are provided in one-to-one correspondence.
  • a plurality of mark patterns are provided on one side of the display panel area 200, there are multiple sets of first mark patterns 11 and second mark patterns 12 located between two adjacent display panel areas 200 and corresponding to positions.
  • the offset of the first mark pattern 11 and the second mark pattern 12 corresponding to the group position relative to the set distance can improve the accuracy of the acquired exposure offset in the composition process of the two adjacent display panel regions 200.
  • the positions of the first marking patterns 11 located on one side of the display panel area 200 may correspond to the positions of the two second marking patterns 12 located on the opposite side.
  • the one mark pattern 11 and the second mark pattern 12 can acquire two sets of offsets with respect to the set distance, thereby further improving the accuracy of the acquired exposure offsets in the composition process of the two adjacent display panel regions 200.
  • first marking pattern and the second marking pattern that are located between two adjacent display panel regions and correspond to positions is not limited to the above two.
  • one first marking pattern and three second marking patterns may be set to correspond to each other, or a first marking pattern between two adjacent display panel areas and a plurality of second marking patterns at corresponding positions
  • the set distance of the center of is zero, which will not be enumerated here one by one, and all belong to the protection scope of the embodiments of the present disclosure.
  • the marking pattern may be a via hole 101 with a regular shape, a square hole as shown in FIGS. 7 and 9, a cross-shaped hole as shown in FIG. 10, and a triangular hole as shown in FIG. 11.
  • the marking pattern may also be other regularly shaped vias 101, which will not be listed here one by one.
  • the marking pattern may be an irregularly shaped via 101.
  • the marking pattern is set to a via hole 101 with a regular shape, so that the first marking pattern 11 and the second marking pattern 12 located between two adjacent display panel areas 200 and corresponding to positions are conveniently obtained The offset from the set distance.
  • the shape and size of all the marking patterns on the periphery of the display panel area 200 are set to be the same, and the corresponding position between the two adjacent display panel areas 200 and corresponding positions can be obtained according to the same reference point on the outline of the marking pattern
  • the offset of the two mark patterns further facilitates obtaining the offset of the two mark patterns relative to the set distance, as shown in FIG. 7 and FIG. 8.
  • the set distance between the first marking pattern and the second marking pattern that are located between two adjacent display panel areas and correspond to positions can be arbitrarily set according to need, and can be a value greater than zero (without exposure offset, The first marking pattern 11 and the second marking pattern 12 located between the two adjacent display panel areas and corresponding to the positions are staggered), or may be less than zero (in the absence of exposure offset, The first marking patterns 11 and the second marking patterns 12 corresponding to each other between the display panel areas partially overlap), or equal to zero (in the absence of an exposure offset, between two adjacent display panel areas 200) The center of the first marking pattern 11 and the second marking pattern 12 corresponding to and corresponding to the position coincide, as shown in FIG. 6).
  • setting the set distance equal to zero makes it easier to obtain the deviation of the first mark pattern 11 and the second mark pattern 12 between the two adjacent display panel areas 200 and corresponding positions relative to the set distance Displacement.
  • the shape and size of all the marking patterns on the periphery of the display panel area 200 are set to be the same, and the set distance is equal to zero, according to the same reference point on the outline of the marking pattern Obtaining the distance between the same reference points on the contour lines of the first and second marking patterns 11 and 12 located between the two adjacent display panel areas 200 and corresponding to the position is the offset from the set distance the amount. For example, when all the marking patterns on the periphery of the display panel area 200 are square holes of the same size, the positions of the first marking pattern 11 and the second marking pattern 12 between the two adjacent display panel areas 200 and corresponding positions The distance between the vertices at the same position (for example, the upper right vertex in FIG. 7) is the offset from the set distance.
  • the positions of the first marking patterns 11 and the second marking patterns 12 located on the periphery of the display panel area 200 correspond to each other, and the first marking patterns corresponding to the positions
  • the first line connecting the center of 11 and the center of the second mark pattern 12 extends in the first direction, as shown in the X direction in FIG. 7.
  • the substrate 100 includes two display panel regions 200 adjacent in the first direction, and the second connection line in the center of the two display panel regions 200 is parallel to the first connection line (that is, the two adjacent display panels
  • the panel areas 200 are arranged along the first direction), the distance between the centers of the two display panel areas 200 and the center of the first marking pattern 11 and the second marks corresponding to the positions on opposite sides of a display panel area 200
  • the distance between the centers of the graphics 12 is the same, and the set distance is zero, that is, when there is no exposure offset, the first marking graphics 11 and the The two-mark patterns 12 coincide, as shown in FIG. 6.
  • all the marking patterns around the periphery of the display panel area 200 are set to a regular shape with the same shape and size, so as to facilitate obtaining the first marking patterns 11 located between the two adjacent display panel areas 200 and corresponding to the positions.
  • the offset of the second marking pattern 12 from the set distance is set to a regular shape with the same shape and size, so as to facilitate obtaining the first marking patterns 11 located between the two adjacent display panel areas 200 and corresponding to the positions.
  • the vertex at the upper right corner of the mark shape is set as a reference point, by acquiring the first position corresponding to the position between two adjacent display panel areas 200
  • the offset of the upper right corner of the mark pattern 11 and the second mark pattern 12 relative to the set distance can be obtained as the exposure offset in the composition process of the two display panel regions 200, which can be decomposed
  • the offset in the second direction perpendicular to the first direction is y.
  • first marking pattern and the second marking pattern located on opposite sides of a display panel area and corresponding to the position may, but are not limited to, the central axis of the display panel area perpendicular to the first connection line be substantially Upper symmetrical distribution.
  • first mark patterns corresponding to positions one to one on opposite sides of the display panel area multiple sets of first mark patterns and second marks corresponding to one position to one position can be formed between two adjacent display panel areas
  • the graphic is convenient for obtaining the offset of the first marking graphic and the second marking graphic corresponding to the position with respect to the set distance, and setting the first marking graphic and the second marking graphic corresponding to each group in one-to-one position can improve the accuracy.
  • the two adjacent display panel regions are arranged along the first direction, and the adjacent two display panel regions arranged along the second direction perpendicular to the first direction have the same technical solutions as described above.
  • the substrate includes at least four display panel regions distributed substantially in a matrix along the first direction and the second direction, the corresponding technical solution is a combination of the two, which will not be described in detail here.
  • the first thin film 10 used to prepare the marking pattern in this embodiment may be the same thin film as the second thin film 20 of the display panel area 200, and are simultaneously manufactured by the same material through one film forming process.
  • the display panel area of the organic electroluminescence display substrate motherboard includes each functional film layer and pixel of the organic electroluminescence diode Definition layer, flat layer, etc.
  • the second film 20 in this embodiment may be a pixel defining layer or a flat layer of the mother substrate of the organic electroluminescent display substrate, and the first film 10 used to prepare the marking pattern may pass through the same material as the pixel defining layer or the flat layer once The film-forming process is produced simultaneously. Since the thickness of the flat layer and the pixel defining layer is thick, a flat surface can be provided, so that the opening ends of the via hole 101 are in the same plane, which is beneficial to accurately obtain the exposure offset.
  • the display panel area of the liquid crystal display substrate motherboard includes each functional film layer of a thin film transistor, a flat layer, a pixel electrode, and the like.
  • the second thin film 20 in this embodiment may be a flat layer of the mother board of the liquid crystal display substrate, and the first thin film 10 used for preparing the marking pattern may be manufactured at the same time using the same material as the flat layer through a film forming process. Since the thickness of the flat layer is thick, a flat surface can be provided, so that the opening ends of the via 101 are in the same plane, which is beneficial to accurately obtain the exposure offset.
  • the method for manufacturing the marking pattern of the display substrate mother board specifically includes:
  • a flat layer 10 is deposited on the substrate 100.
  • the flat layer 10 is made of a positive photoresist, and a patterning process is applied to a display panel area 200 and the flat area 10 of the marking area located on the periphery of the display panel area using a masking plate. It is formed by exposure and development, and the first mark pattern 11 and the second mark pattern 12, the first mark pattern 11 and the second mark pattern 12 on opposite sides of the display panel area 200 are formed on the flat layer 10 of the mark area
  • the first marking pattern 11 and the second marking pattern 12 on opposite sides of the display panel area 200 are shown in FIG. 7.
  • the exposure of the two adjacent display panel areas 200 has an offset, so that the first and second marking patterns 11 and 12 corresponding to the positions between the two adjacent display panel areas 200 are relatively set The distance is shifted, wherein the set distance is zero. Therefore, when there is no exposure offset, the first marking pattern 11 and the second marking pattern 12 located between the two adjacent display panel areas 200 and corresponding in position coincide, as shown in FIG. 6.
  • the above-mentioned embodiment specifically introduces the technical scheme of the present disclosure by taking a mark pattern for obtaining the offset of the two exposure processes of the adjacent two display panel regions as an example.
  • the mark patterns provided by the various embodiments of the present disclosure may also be alignment mark patterns, and the mask plate and the display panel area are aligned through the alignment mark patterns to perform a patterning process on the display panel area.
  • the patterning process of the second film 20 to form a pattern of the second film 20 includes:
  • the mask plate and the display panel area 200 are aligned through the marking patterns 11 and 12, and the mask plate is used A patterning process is performed on the second film 20.
  • marking graphics of the present disclosure may also be marking graphics with other functions.

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Abstract

一种显示基板母板及其制作方法。通过设置显示基板母板上的标记图形为薄膜上形成的过孔，而不是小面积孤岛型的薄膜图形，从而克服了标记图形脱落的可能，进一步保证产品的可靠性和良率。

Description

显示基板母板及其制作方法
相关申请的交叉引用
本申请主张在2018年10月30日在中国提交的中国专利申请号No.201811279971.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，特别是涉及一种显示基板母板及其制作方法。
背景技术
对于显示基板的生产线，是在一张显示基板母板上制作多个显示基板，即，一张基板包括多个显示面板区域，每一显示面板区域设置有显示基板的所有功能薄膜图形。在所有显示基板制作完成后，再通过切割工艺切割成多个独立的显示基板。在显示基板母板的制作过程中，需要在显示面板区域的周边上制作一些标记图形，用于对位、获取曝光偏移量等。现有的标记图形是小面积的薄膜图形，小面积的标记图形极易脱落，被冲洗到基板的显示面板区域，影响产品的性能，甚至导致产品不能正常工作。
发明内容
在第一个方面中，本公开文本实施例提供了一种显示基板母板的制作方法，所述显示基板母板包括衬底，所述衬底上包括至少两个显示面板区域，每一所述显示面板区域的外围具有标记区域，所述制作方法包括：在所述标记区域中形成第一薄膜；以及对所述第一薄膜进行构图工艺，以形成多个标记图形。所述标记图形为所述第一薄膜上形成的过孔。
根据本公开文本的一些可行实施例，所述制作方法还包括：在所述衬底的显示面板区域中形成第二薄膜；以及对所述第二薄膜进行构图工艺，以形成所述第二薄膜的图形，其中，所述在标记区域中形成第一薄膜和在所述衬底的显示面板区域中形成第二薄膜，包括：利用同一材料通过一次成膜工艺 同时形成所述第一薄膜和第二薄膜。
根据本公开文本的一些可行实施例，对所述第一薄膜和第二薄膜进行构图工艺的步骤，包括：利用一掩膜板采用一次构图工艺同时对所述显示面板区域的第二薄膜和对应的标记区域的第一薄膜进行构图，形成所述第二薄膜的图形，以及位于所述第一薄膜上的标记图形，并利用该掩膜板依次对所有显示面板区域的第二薄膜和对应的标记区域的第一薄膜进行构图工艺；其中，形成的所述标记图形包括：位于所述显示面板区域的一侧的至少一个第一标记图形和相对的另一侧的至少一个第二标记图形，相邻的两个显示面板区域之间的标记区域具有第一标记图形和第二标记图形，以根据位于相邻的两个显示面板区域之间标记区域的且位置对应的第一标记图形和第二标记图形相对设定距离的偏移量，获取对该两个相邻的显示面板区域的第二薄膜进行的构图工艺中的曝光偏移量。
根据本公开文本的一些可行实施例，所述显示基板母板为有机电致发光显示基板母板；所述对第二薄膜进行构图工艺形成所述第二薄膜的图形，包括：对所述第二薄膜进行构图工艺，形成所述有机电致发光显示基板母板的平坦层或像素界定层。
根据本公开文本的一些可行实施例，所述显示基板母板为液晶显示基板母板；所述对第二薄膜进行构图工艺形成所述第二薄膜的图形，包括：对所述第二薄膜进行构图工艺，形成所述液晶显示基板母板的平坦层。
根据本公开文本的一些可行实施例，所述第一薄膜和第二薄膜的材料为光刻胶。
根据本公开文本的一些可行实施例，所述对所述第二薄膜进行构图工艺，形成所述第二薄膜的图形，包括：在所述衬底的至少一个显示面板区域中的第二薄膜进行构图工艺时，通过所述标记图形对掩膜板和显示面板区域进行对位，利用所述掩膜板对所述第二薄膜进行构图工艺。
在第二个方面中，本公开文本实施例还提供了一种显示基板母板，包括：衬底，所述衬底上包括至少两个显示面板区域，每一所述显示面板区域的外围具有标记区域；以及位于所述标记区域的第一薄膜，所述第一薄膜包括多个标记图形，所述标记图形为所述第一薄膜上形成的过孔。
根据本公开文本的一些可行实施例，所述显示基板母板还包括：设置在所述衬底上的第二薄膜，所述第二薄膜位于所述显示面板区域中。
根据本公开文本的一些可行实施例，所述第一薄膜和所述第二薄膜为同一薄膜。
根据本公开文本的一些可行实施例，所述标记图形包括位于所述显示面板区域的一侧的至少一个第一标记图形和位于相对的另一侧的至少一个第二标记图形，相邻的两个显示面板区域之间具有第一标记图形和第二标记图形，以根据位于相邻的两个显示面板区域显示面板区域之间的且位置对应的第一标记图形和第二标记图形相对设定距离的偏移量能够获取对该两个相邻的显示面板区域的第一薄膜进行的构图工艺中的曝光偏移量。
根据本公开文本的一些可行实施例，位于所述显示面板区域外围的第一标记图形和位置对应的第二标记图形在所述衬底的侧面上的垂直投影线段至少部分重合，且位置对应的第一标记图形的中心和第二标记图形的中心的第一连线实质上沿第一方向延伸；所述衬底包括在第一方向上相邻的两个显示面板区域，该两个显示面板区域的中心的第二连线与所述第一连线平行，该两个显示面板区域的中心之间的距离与位于一显示面板区域的相对两侧且位置对应的第一标记图形的中心和第二标记图形的中心之间的距离实质上相同，所述设定距离为零。
根据本公开文本的一些可行实施例，位于所述显示面板区域的相对两侧的且位置对应的第一标记图形和第二标记图形，以该显示面板区域的垂直于所述第一连线的中心轴实质上对称分布。
根据本公开文本的一些可行实施例，所述第一标记图形和第二标记图形的形状和孔径尺寸实质上相同。
根据本公开文本的一些可行实施例，所述衬底包括至少四个显示面板区域，所述至少四个显示面板区域呈实质上矩阵分布。
根据本公开文本的一些可行实施例，所述显示基板母板为有机电致发光显示基板母板；所述第二薄膜为所述有机电致发光显示基板母板的平坦层或像素界定层。
根据本公开文本的一些可行实施例，所述显示基板母板为液晶显示基板 母板；所述第二薄膜为所述液晶显示基板母板的平坦层。
根据本公开文本的一些可行实施例，所述标记图形为规则形状的过孔。
根据本公开文本的一些可行实施例，所述过孔包括：方形孔、十字形孔、三角形孔中至少一种。
根据本公开文本的一些可行实施例，所述标记图形为不规则形状的过孔。
在第三个方面中，本公开文本实施例还提供了一种获取在第一个方面中所述的显示基板母板的制作过程中的曝光偏移量的方法，包括：根据位于相邻的两个显示面板区域之间标记区域的且位置对应的第一标记图形和第二标记图形相对设定距离的偏移量，获取对该两个相邻的显示面板区域的第二薄膜进行的构图工艺中的曝光偏移量。
附图说明
为了更清楚地说明本公开文本实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1和图2表示相关技术中基板上的用于获取相邻两个显示面板区域的曝光偏移量的标记图形的制作过程；
图3表示图2中位于相邻两个显示面板区域之间的标记图形的形成原理；
图4表示相关技术中基板上的用于获取相邻两个显示面板区域的曝光偏移量的标记图形发生脱落的示意图；
图5和图7表示本公开文本实施例中基板上的用于获取相邻两个显示面板区域的曝光偏移量的标记图形的制作过程；
图6表示本公开文本实施例中相邻两个显示面板区域无曝光偏移量时基板的结构示意图；
图8表示图7中位于相邻两个显示面板区域之间的标记图形的形成原理；以及
图9至图12表示本公开文本的实施例中基板的不同结构示意图。
具体实施方式
对于显示基板的生产线，是在一张显示基板母板上制作多个显示基板，即，一张基板包括多个显示面板区域，每一显示面板区域设置有显示基板的所有功能薄膜图形。在所有显示基板制作完成后，再通过切割工艺切割成多个独立的显示基板。在显示基板母板的制作过程中，需要在显示面板区域的周边上制作一些标记图形，用于对位、获取曝光偏移量等。现有的标记图形是小面积的薄膜图形，其形状可以为十字型、环形、正方形等。小面积的标记图形极易脱落，被冲洗到基板的显示面板区域，影响产品的性能，甚至导致产品不能正常工作。
具体的，在小尺寸的显示基板母板的生产过程中，会在一张基板上制作多个显示基板母板，制作完成后，通过切割工艺切割成多个独立的显示基板母板。由于掩膜板的尺寸小于基板的尺寸，所以一张基板需要分多次曝光，掩膜板每曝光一次称为一个shot，同一张基板中判断两个shot曝光偏移量的是Stitch Mark，Stitch Mark在基板/掩膜板上的分布以及shot与shot之间的曝光关系如下所述。
所述掩膜板的四周各分布6组Stitch Mark，结合图1和图2所示，掩膜板的上边框和左边框的Stitch Mark可在基板100＇的一个显示面板区域200＇(每一显示面板区域200＇用于形成一个显示基板母板)周边的平坦层/像素界定层10＇上曝光出如图1左上方所示的大环形的第一标记图形1＇，掩膜板的下边框和右边框的Stitch Mark可在基板100＇的一个显示面板区域200＇周边的平坦层/像素界定层10＇上曝光出如图1左下方所示的小正方形的第二标记图形2＇，两次shot存在交叠，使得位于相邻的两个显示面板区域200＇的且位置对应的第一标记图形1＇和第二标记图形2＇组合成的小环形的第三标记图形3＇，结合图3所示。
获取两次shot的偏移量的具体原理为：如图3所示，相邻的两个显示面板区域200＇之间，平坦层/像素界定层10＇上的Stitch Mark在前一次shot能够得到形状如图3所示的小正方形的第二标记图形2＇(例如，15um)，后一次shot能够得到形状如图3所示的大环形的第一标记图形1＇(例如，内径： 7.5um，外径：20um)，当小正方形和大环形的位置对应时，最终形成的小环形(例如，内径：7.5um，外径：15um)，通过量取小环形孔的水平孔径d＇就可以判断两次shot的偏移量。当两次shot的偏移量为零时，d＝15-7.5＝7.5um。
但是，平坦层/像素界定层因为本身材质原因，小面积孤岛型(环形、小正方形)存在时极易脱落，脱落后被冲洗液冲到背板电路或发光像素区，会影响发光，进而会影响产品良率，如图4所示。
为了解决上述技术问题，本申请提供一种显示基板母板的制作方法，所述显示基板母板包括衬底，所述衬底上包括至少两个显示面板区域，每一所述显示面板区域外围具有标记区域，所述制作方法包括：
在衬底所述标记区域中形成第一薄膜；以及
对所述第一薄膜进行构图工艺，以形成包括多个标记图形，
其中，所述标记图形为所述第一薄膜上形成的过孔。
通过上述制作方法制得的显示基板母板的标记图形为薄膜上形成的过孔，而不是小面积孤岛型的薄膜图形，从而克服了标记图形脱落的可能，进一步保证产品的可靠性和良率。
相应地，本公开文本还提供一种如上所述的制作方法制得的显示基板母板，所述显示基板母板包括位于所述标记区域的第一薄膜，所述第一薄膜包括衬底上的多个标记图形，所述标记图形为所述第一薄膜上形成的过孔。
下面将结合附图和实施例，对本公开文本的具体实施方式作进一步详细描述。以下实施例用于说明本公开文本，但不用来限制本公开文本的范围。
由于显示基板母板的尺寸较大，受到曝光精度和成本的限制，用于对所述显示基板母板上的薄膜进行曝光的掩膜板的尺寸较小，因此，一张显示基板母板上的多个显示面板区域需要利用掩膜板进行多次曝光工艺才能完成相同功能薄膜图形的制作。以所述显示基板母板为液晶显示基板母板为例，所述相同功能薄膜图形为所有显示面板区域的像素电极、薄膜晶体管的栅电极、源电极或漏电极等。
为了获取对相邻两个显示面板区域的前后两次曝光工艺的偏移量，会在显示面板区域的周边制作标记图形，通过该标记图形来获取两次曝光的偏移量。
本实施例中，以一张掩膜板一次仅对一个显示面板区域的薄膜进行曝光为例来具体介绍本公开文本的技术方案。仅是为了举例来介绍本公开文本的技术方案，本公开文本的技术方案也适用于一张掩膜板一次对至少两个相邻的显示面板区域的薄膜进行曝光的情形，此时，只需将该至少两个相邻的显示面板区域看作是一个面积更大的显示面板区域，与一张掩膜板一次仅对一个显示面板区域的薄膜进行曝光的技术方案相同或相似，不再详述。
需要说明的是，本实施例中前后两次曝光是指：在相邻两个显示面板区域制作相同功能薄膜图形时的两次曝光工艺。
以下内容中关于对显示面板区域进行构图工艺均是指对显示面板区域内的薄膜进行构图工艺，所述构图工艺包括利用掩膜板对显示面板区域内的薄膜进行曝光工艺。
结合图5和图7所示，本实施例中的显示基板母板包括衬底100，衬底100包括至少两个显示面板区域200，每一显示面板区域200的外围具有标记区域201。
本实施例中显示基板母板的制作方法包括：
在标记区域201中形成第一薄膜10，对第一薄膜10进行构图工艺，形成包括多个标记图形的图形，所述标记图形为第一薄膜10上形成的过孔101；
在显示面板区域200中形成第二薄膜20，对所述第二薄膜20进行构图工艺，形成所述第二薄膜20的图形。
其中，所述在标记区域201中形成第一薄膜10和在显示面板区域200中形成第二薄膜20，包括：
利用同一材料通过一次成膜工艺同时形成第一薄膜10和所述第二薄膜20。
即，第一薄膜10和所述第二薄膜20为同一薄膜，以简化制作工艺，降低成本。
进一步地，第一薄膜10和所述第二薄膜20的材料可以为光刻胶，仅通过曝光工艺就可以在第一薄膜10上形成过孔101(标记图形)，以及第二薄膜20的图形，进一步简化制作工艺。
其中，对所述第一薄膜10和第二薄膜20进行构图工艺的步骤，包括：
利用一掩膜板采用一次构图工艺同时对显示面板区域200的第二薄膜20和对应的标记区域201的第一薄膜10进行构图，形成所述第二薄膜20的图形，以及位于第一薄膜10上的标记图形，并利用该掩膜板依次对所有显示面板区域200的第二薄膜20和对应的标记区域201的第一薄膜10进行构图工艺；
上述步骤形成的标记图形包括：位于显示面板区域200的一侧的至少一个第一标记图形11和相对的另一侧的至少一个第二标记图形12，相邻的两个显示面板区域200之间具有第一标记图形11和第二标记图形12，以根据位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12相对设定距离的偏移量，获取对该两个相邻的显示面板区域200的第二薄膜进行的构图工艺中的曝光偏移量。
上述制作方法利用位于相邻的两个显示面板区域之间的位置对应的标记图形来获取该两个相邻的显示面板区域的构图工艺中的曝光偏移量，由于标记图形为薄膜中的过孔，而不是小面积孤岛型的薄膜图形，从而有效地克服了标记图形脱落的可能，进一步保证产品的可靠性和良率。
本实施例中，获取如上所述的显示基板母板的制作过程中的曝光偏移量的方法包括：
根据位于相邻的两个显示面板区域之间标记区域的且位置对应的第一标记图形和第二标记图形相对设定距离的偏移量，获取对该两个相邻的显示面板区域的第二薄膜进行的构图工艺中的曝光偏移量。
本公开文本的各个实施例所提供的技术方案其获取对相邻的两个显示面板区域200的前后两次曝光工艺的偏移量的具体的原理为：
由于显示面板区域200与其外围的标记图形利用同一掩膜板制得，则相邻两个显示面板区域200的构图工艺中的曝光偏移量与形成位于该相邻两个显示面板区域200外围的且位置对应的标记图形的构图工艺中的曝光偏移量相同。因此，可以利用位于该相邻两个显示面板区域200外围的且位置对应的标记图形相对设定距离的偏移量(即曝光偏移量)，来获取对该两个相邻的显示面板区域200的第二薄膜20进行的构图工艺中的曝光偏移量。
另外，由于所有显示面板区域200外围的标记图形利用同一掩膜板制得， 因此，所有显示面板区域200外围的标记图形的分布规则相同，由此通过设置相邻两个显示面板区域200的距离可以设置位于相邻两个显示面板区域200之间的第一标记图形11和第二标记图形12的设定距离。当相邻的两个显示面板区域200的曝光存在偏移量时，通过曝光工艺在两个显示面板区域200的外围形成的标记图形也会发生偏移。因此，根据位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12相对设定距离的偏移量(即曝光偏移量)，能够获取对该两个相邻的显示面板区域200的第二薄膜20进行的构图工艺中的曝光偏移量。
通过利用位于相邻的两个显示面板区域之间的且位置对应的标记图形相对设定距离的偏移量，来获取对该两个相邻的显示面板区域的第二薄膜进行的构图工艺中的曝光偏移量，由于距离较近，能够比较快速、准确地获取相邻的两个显示面板区域的曝光偏移量。
可选的，如图7所示，设置位于同一显示面板区域200的相对两侧的第一标记图形11和第二标记图形12的位置一一对应。当显示面板区域200的一侧设置多个标记图形时，位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12具有多组，通过测量多组位置对应的第一标记图形11和第二标记图形12相对设定距离的偏移量，能够提高获取的相邻的两个显示面板区域200的构图工艺中的曝光偏移量的精度。
如图12所示，也可以设置位于显示面板区域200的一侧的第一标记图形11与位于相对的另一侧的两个第二标记图形12的位置对应，由此一组位置对应的第一标记图形11和第二标记图形12能够获取两组相对设定距离的偏移量，进一步提高获取的两个相邻的显示面板区域200的构图工艺中的曝光偏移量的精度。
当然，位于相邻的两个显示面板区域之间的且位置对应的第一标记图形和第二标记图形的组合关系并不局限于上述两种。例如，还可以设置一个第一标记图形和三个第二标记图形的位置对应，或位于相邻的两个显示面板区域之间的一第一标记图形与位于位置对应的多个第二标记图形的中心的设定距离为零，在此不再一一列举，其都属于本公开文本实施例的保护范围。
其中，所述标记图形可以为规则形状的过孔101，如图7和图9所示的 方形孔，如图10所示的十字形孔，如图11所示的三角形孔。当然，所述标记图形还可以为其它规则形状的过孔101，在此不再一一列举。或者，所述标记图形也可以为不规则形状的过孔101。
作为一个可选的示例，设置所述标记图形为规则形状的过孔101，方便获取位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12的相对设定距离的偏移量。
进一步地，设置显示面板区域200外围的所有标记图形的形状和尺寸相同，根据标记图形的轮廓线上的同一参考点就可以获取位于相邻的两个显示面板区域200之间的且位置对应的两个标记图形的偏移量，进一步方便获取这两个标记图形相对设定距离的偏移量，结合图7和图8所示。
位于相邻的两个显示面板区域之间的且位置对应的第一标记图形和第二标记图形的设定距离可以根据需要任意设置，可以为大于零的值(在无曝光偏移量时，位于相邻的两个显示面板区域之间的且位置对应的第一标记图形11和第二标记图形12错开)，也可以小于零的值(在无曝光偏移量时，位于相邻的两个显示面板区域之间的且位置对应的第一标记图形11和第二标记图形12部分交叠)，或等于零(在无曝光偏移量时，位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12的中心重合，如图6所示)。
本实施例中，设置所述设定距离等于零，更方便获取位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12相对设定距离的偏移量。
作为一个可选的示例，如图7所示，设置显示面板区域200外围的所有标记图形的形状和尺寸相同，且所述设定距离等于零，根据标记图形的轮廓线上的同一参考点就可以获取位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12的轮廓线上的同一参考点之间的距离即为相对设定距离的偏移量。例如，当显示面板区域200外围的所有标记图形均为尺寸相同的正方形孔时，位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12的同一位置的顶点(例如，如图7中的右上顶点)之间的距离即为相对设定距离的偏移量。
需要说明的是，本实施例中关于方位的描述，如：左、右、上、下，均是以附图中的方向来定义，仅是为了便于描述，不具有其它限定意义。
在一个具体的实施方式中，结合图5和图7所示，设置位于显示面板区域200外围的第一标记图形11和第二标记图形12的位置一一对应，且位置对应的第一标记图形11的中心和第二标记图形12的中心的第一连线沿第一方向延伸，如图7所示的X方向。
衬底100包括在第一方向上相邻的两个显示面板区域200，该两个显示面板区域200的中心的第二连线与所述第一连线平行(即该相邻的两个显示面板区域200沿第一方向排布)，该两个显示面板区域200的中心之间的距离与位于一显示面板区域200的相对两侧且位置对应的第一标记图形11的中心和第二标记图形12的中心之间的距离相同，所述设定距离为零，即，在无曝光偏移量时，位于该两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12重合，参见图6所示。
如图7所示，如果该两个显示面板区域200的构图工艺中存在曝光偏移量，由于显示面板区域200与其外围的标记区域201利用同一掩膜板进行曝光工艺，因此，形成位于该两个显示面板区域200外围的标记图形的构图工艺中也存在曝光偏移量。也就是说，位于该两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12不再重合，发生偏移。可以通过所述第一标记图形11和第二标记图形12在第一方向(如图7所示的X方向)上的第一偏移量x和与所述第一方向垂直的第二方向(如图7所示的Y方向)上的第二偏移量y，来获取该两个显示面板区域200的构图工艺中的曝光偏移量，即在第一方向上的偏移量为x，在与第一方向垂直的第二方向上的偏移量为y。
该实施方式中，设置显示面板区域200外围的所有标记图形为形状和尺寸相同的规则形状，以方便获取位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12的相对设定距离的偏移量。
如图7所示，以标记图形为正方形的孔为例，设定标记图形的右上角的顶点为参考点，通过获取位于相邻的两个显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12的右上角的顶点相对设定距离的偏 移量，即可获取该两个显示面板区域200的构图工艺中的曝光偏移量，该曝光偏移量可以分解为在第一方向上的偏移量为x，在与第一方向垂直的第二方向上的偏移量为y。
其中，位于一显示面板区域的相对两侧的且位置对应的第一标记图形和第二标记图形，可以但并不局限于以该显示面板区域的垂直于所述第一连线的中心轴实质上对称分布。
上述具体实施方式通过在显示面板区域的相对两侧设置位置一一对应的标记图形，能够在相邻的两个显示面板区域之间形成多组位置一一对应的第一标记图形和第二标记图形，便于获取位置对应的第一标记图形和第二标记图形相对设定距离的偏移量，而且设置多组位置一一对应的第一标记图形和第二标记图形，能够提高精度。
上述具体实施方式中相邻两个显示面板区域沿第一方向排布，至于沿与第一方向垂直的第二方向排布的相邻两个显示面板区域，其对应的技术方案与上述相同。当所述衬底包括沿第一方向和第二方向，呈实质上矩阵分布的至少四个显示面板区域时，其对应的技术方案是上述两者的结合，在此不再详述。
为了简化制作工艺，本实施例中用于制备标记图形的第一薄膜10可以与显示面板区域200的第二薄膜20为同一薄膜，利用同一材料通过一次成膜工艺同时制得。
例如，当本实施例中的显示基板母板为有机电致发光显示基板母板时，所述有机电致发光显示基板母板的显示面板区域包括有机电致发光二极管的各功能膜层、像素界定层、平坦层等。
本实施例中的第二薄膜20可以为有机电致发光显示基板母板的像素界定层或平坦层，用于制备标记图形的第一薄膜10可以与像素界定层或平坦层利用同一材料通过一次成膜工艺同时制得。由于平坦层和像素界定层的厚度较厚，能够提供平坦表面，使得过孔101的开口端位于同一平面内，有利于准确获取曝光偏移量。
同样地，当本实施例中的显示基板母板为液晶显示基板母板时，所述液晶显示基板母板的显示面板区域包括薄膜晶体管的各功能膜层、平坦层、像 素电极等。
本实施例中的第二薄膜20可以为液晶显示基板母板的平坦层，用于制备标记图形的第一薄膜10可以与平坦层利用同一材料通过一次成膜工艺同时制得。由于平坦层的厚度较厚，能够提供平坦表面，使得过孔101的开口端位于同一平面内，有利于准确获取曝光偏移量。
以显示基板母板为有机电致发光显示基板母板为例，本实施例中，所述显示基板母板的标记图形的制作方法具体包括：
首先，在衬底100上沉积平坦层10，平坦层10由正性光刻胶制得，利用掩膜板采用一次构图工艺同时对一显示面板区域200和位于其外围的标记区域的平坦层10进行曝光，显影后形成，在标记区域的平坦层10上形成位于该显示面板区域200的相对两侧的第一标记图形11和第二标记图形12，第一标记图形11和第二标记图形12为平坦层10上的过孔101，如图5所示；
然后，利用同一掩膜板采用一次构图工艺同时对相邻的另一显示面板区域200和位于其外围的标记区域的平坦层10进行曝光，显影后形成，在标记区域的平坦层10上形成位于该显示面板区域200的相对两侧的第一标记图形11和第二标记图形12，如图7所示。这两个相邻的显示面板区域200的曝光存在偏移量，使得位于这两个相邻的显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12相对设定距离发生偏移，其中，所述设定距离为零。因此，在无曝光偏移量时，位于这两个相邻的显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12重合，如图6所示。在有曝光偏移量时，位于这两个相邻的显示面板区域200之间的且位置对应的第一标记图形11和第二标记图形12在第一方向上的第一偏移量x＝20um和与所述第一方向垂直的第二方向上的第二偏移量y＝20um，即为这两个相邻的显示面板区域200的曝光偏移量，如图8所示。
至此完成标记图形的制作，至于有机电致发光显示基板母板的其它功能膜层图形的制作方法在此不再一一详述。
上述实施例以用于获取对相邻的两个显示面板区域的前后两次曝光工艺的偏移量的标记图形为例来具体介绍了本公开文本的技术方案。
本公开文本各个实施例所提供的标记图形还可以为对位标记图形，通过 所述对位标记图形对掩膜板和显示面板区域进行对位，以对所述显示面板区域进行构图工艺。具体为：所述对所述第二薄膜20进行构图工艺，形成所述第二薄膜20的图形，包括：
在所述衬底的至少一个显示面板区域200中的第二薄膜20进行构图工艺时，通过所述标记图形11、12对掩膜板和显示面板区域200进行对位，利用所述掩膜板对所述第二薄膜20进行构图工艺。
当然，本公开文本的标记图形也可以为具有其他功能的标记图形。
以上所述仅是本公开文本的一些实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开文本的保护范围。

Claims (21)

  1. 一种显示基板母板的制作方法，所述显示基板母板包括衬底，所述衬底上包括至少两个显示面板区域，每一所述显示面板区域的外围具有标记区域，所述制作方法包括：
    在所述标记区域中形成第一薄膜；以及
    对所述第一薄膜进行构图工艺，以形成多个标记图形，
    其中，所述标记图形为所述第一薄膜上形成的过孔。
  2. 根据权利要求1所述的制作方法，其中，所述制作方法还包括：
    在所述衬底的显示面板区域中形成第二薄膜；以及
    对所述第二薄膜进行构图工艺，以形成所述第二薄膜的图形，
    其中，所述在标记区域中形成第一薄膜和在所述衬底的显示面板区域中形成第二薄膜，包括：
    利用同一材料通过一次成膜工艺同时形成所述第一薄膜和第二薄膜。
  3. 根据权利要求2所述的制作方法，其中，对所述第一薄膜和第二薄膜进行构图工艺的步骤，包括：
    利用一掩膜板采用一次构图工艺同时对所述显示面板区域的第二薄膜和对应的标记区域的第一薄膜进行构图，形成所述第二薄膜的图形，以及位于所述第一薄膜上的标记图形，并利用该掩膜板依次对所有显示面板区域的第二薄膜和对应的标记区域的第一薄膜进行构图工艺；
    其中，形成的所述标记图形包括：位于所述显示面板区域的一侧的至少一个第一标记图形和相对的另一侧的至少一个第二标记图形，相邻的两个显示面板区域之间的标记区域具有第一标记图形和第二标记图形，以根据位于相邻的两个显示面板区域之间标记区域的且位置对应的第一标记图形和第二标记图形相对设定距离的偏移量，获取对该两个相邻的显示面板区域的第二薄膜进行的构图工艺中的曝光偏移量。
  4. 根据权利要求2或3所述的制作方法，其中，所述显示基板母板为有机电致发光显示基板母板；
    所述对第二薄膜进行构图工艺形成所述第二薄膜的图形，包括：
    对所述第二薄膜进行构图工艺，形成所述有机电致发光显示基板母板的平坦层或像素界定层。
  5. 根据权利要求2或3所述的制作方法，其中，所述显示基板母板为液晶显示基板母板；
    所述对第二薄膜进行构图工艺形成所述第二薄膜的图形，包括：
    对所述第二薄膜进行构图工艺，形成所述液晶显示基板母板的平坦层。
  6. 根据权利要求2至5中任一项所述的制作方法，其中，所述第一薄膜和第二薄膜的材料为光刻胶。
  7. 根据权利要求2至6中任一项所述的制作方法，其中，所述对所述第二薄膜进行构图工艺，形成所述第二薄膜的图形，包括：
    在所述衬底的至少一个显示面板区域中的第二薄膜进行构图工艺时，通过所述标记图形对掩膜板和显示面板区域进行对位，利用所述掩膜板对所述第二薄膜进行构图工艺。
  8. 一种显示基板母板，包括：
    衬底，所述衬底上包括至少两个显示面板区域，每一所述显示面板区域的外围具有标记区域；以及
    位于所述标记区域的第一薄膜，所述第一薄膜包括多个标记图形，所述标记图形为所述第一薄膜上形成的过孔。
  9. 根据权利要求8所述的显示基板母板，其中，所述显示基板母板还包括：
    设置在所述衬底上的第二薄膜，所述第二薄膜位于所述显示面板区域中。
  10. 根据权利要求9所述的显示基板母板，其中，所述第一薄膜和所述第二薄膜为同一薄膜。
  11. 根据权利要求9或10所述的显示基板母板，其中，所述标记图形包括位于所述显示面板区域的一侧的至少一个第一标记图形和位于相对的另一侧的至少一个第二标记图形，相邻的两个显示面板区域之间具有第一标记图形和第二标记图形，以根据位于相邻的两个显示面板区域显示面板区域之间的且位置对应的第一标记图形和第二标记图形相对设定距离的偏移量能够获取对该两个相邻的显示面板区域的第一薄膜进行的构图工艺中的曝光偏移量。
  12. 根据权利要求11所述的显示基板母板，其中，位于所述显示面板区域外围的第一标记图形和位置对应的第二标记图形在所述衬底的侧面上的垂直投影线段至少部分重合，且位置对应的第一标记图形的中心和第二标记图形的中心的第一连线实质上沿第一方向延伸；
    所述衬底包括在第一方向上相邻的两个显示面板区域，该两个显示面板区域的中心的第二连线与所述第一连线平行，该两个显示面板区域的中心之间的距离与位于一显示面板区域的相对两侧且位置对应的第一标记图形的中心和第二标记图形的中心之间的距离实质上相同，所述设定距离为零。
  13. 根据权利要求12所述的显示基板母板，其中，位于所述显示面板区域的相对两侧的且位置对应的第一标记图形和第二标记图形，以该显示面板区域的垂直于所述第一连线的中心轴实质上对称分布。
  14. 根据权利要求13所述的显示基板母板，其中，所述第一标记图形和第二标记图形的形状和孔径尺寸实质上相同。
  15. 根据权利要求13所述的显示基板母板，其中，所述衬底包括至少四个显示面板区域，所述至少四个显示面板区域呈实质上矩阵分布。
  16. 根据权利要求9至15中任一项所述的显示基板母板，其中，所述显示基板母板为有机电致发光显示基板母板；
    所述第二薄膜为所述有机电致发光显示基板母板的平坦层或像素界定层。
  17. 根据权利要求9至15中任一项所述的显示基板母板，其中，所述显示基板母板为液晶显示基板母板；
    所述第二薄膜为所述液晶显示基板母板的平坦层。
  18. 根据权利要求8至17中任一项所述的显示基板母板，其中，所述标记图形为规则形状的过孔。
  19. 根据权利要求18所述的显示基板母板，其中，所述过孔包括：方形孔、十字形孔、三角形孔中至少一种。
  20. 根据权利要求8至17中任一项所述的显示基板母板，其中，所述标记图形为不规则形状的过孔。
  21. 一种获取权利要求3至7中任一项所述的显示基板母板的制作过程中的曝光偏移量的方法，包括：
    根据位于相邻的两个显示面板区域之间标记区域的且位置对应的第一标记图形和第二标记图形相对设定距离的偏移量，获取对该两个相邻的显示面板区域的第二薄膜进行的构图工艺中的曝光偏移量。
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