WO2017185830A1 - 阵列基板母板及其制作方法、显示装置 - Google Patents

阵列基板母板及其制作方法、显示装置 Download PDF

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Publication number
WO2017185830A1
WO2017185830A1 PCT/CN2017/070833 CN2017070833W WO2017185830A1 WO 2017185830 A1 WO2017185830 A1 WO 2017185830A1 CN 2017070833 W CN2017070833 W CN 2017070833W WO 2017185830 A1 WO2017185830 A1 WO 2017185830A1
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WIPO (PCT)
Prior art keywords
region
insulating layer
pattern
forming
layer
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PCT/CN2017/070833
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English (en)
French (fr)
Inventor
王静
郭会斌
丁向前
白金超
刘耀
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/544,562 priority Critical patent/US10504943B2/en
Publication of WO2017185830A1 publication Critical patent/WO2017185830A1/zh

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • G03F7/0037—Production of three-dimensional images

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate mother board, a manufacturing method thereof, and a display device.
  • the technical problem to be solved by the present disclosure is to provide an array substrate mother board, a manufacturing method thereof, and a display device, which can avoid the occurrence of Mura defects when forming a film layer pattern of different display products on the array substrate.
  • a method of fabricating an array substrate motherboard includes forming a film layer pattern of a first display product in a first region of the substrate substrate and forming a film layer pattern of the second display product in a second region of the substrate substrate.
  • the deep density of the first display product is greater than the deep hole density of the second display product, and the deep hole is a via hole penetrating at least two insulating layers.
  • Forming a film layer pattern of the first display product in the first region of the base substrate and forming a film layer pattern of the second display product in the second region of the base substrate includes:
  • the via structure of the insulating layer is connected to the first conductive pattern under the insulating layer.
  • the forming a film layer pattern of the first display product in the first region of the base substrate and forming the film layer pattern of the second display product in the second region of the substrate substrate specifically includes:
  • the second conductive pattern is formed on the insulating layer.
  • the second conductive pattern includes:
  • a positive photoresist on the insulating layer and exposing the positive photoresist by using a gray tuned mask comprising a partially transparent pattern, a completely transparent pattern, and a complete An opaque pattern, the completely transparent pattern corresponding to an area for forming the via structure, wherein the partial light transmission pattern corresponds to an area of the first area except the via structure, the The light transmissive pattern corresponds to a region of the second region other than the via structure;
  • a photoresist partial retention region, a photoresist completely removed region, and a photoresist completely reserved region are formed;
  • the positive photoresist in the remaining portion of the photoresist is removed, and the insulating layer in the remaining portion of the photoresist is etched to reduce the thickness of the insulating layer in the remaining portion of the photoresist.
  • the second conductive pattern includes:
  • the gray mask includes a partially transparent pattern, a completely transparent pattern, and a complete well a light pattern, the completely opaque pattern corresponding to an area for forming the via structure, the partial light transmission pattern corresponding to an area of the first area except the via structure, the complete light transmission
  • the graphic corresponds to an area of the second area other than the via structure
  • the negative photoresist in the remaining portion of the photoresist is removed, and the insulating layer in the remaining portion of the photoresist is etched to reduce the thickness of the insulating layer in the remaining portion of the photoresist.
  • the first conductive pattern located in the first region includes a drain of a thin film transistor and a pixel electrode, and the second conductive pattern located in the first region is associated with the drain and the pixel electrode
  • the electrically connected connecting wires respectively connected to the first region are a passivation layer.
  • the forming the film layer pattern of the first display product in the first region of the base substrate further includes:
  • a conductive connection line is formed on the passivation layer of the first region, the conductive connection line is connected to the drain through the first via hole, and is connected to the pixel electrode through the second via hole.
  • the conductive connection line and the common electrode located in the first region are simultaneously formed by one patterning process.
  • An embodiment of the present disclosure further provides an array substrate mother board, the array substrate mother board comprising at least a film layer pattern of a first display product formed on a first region of the substrate substrate and a second layer formed on the second region of the substrate substrate The film pattern of the product is displayed.
  • the deep density of the first display product is greater than the deep hole density of the second display product, and the deep hole is a via hole penetrating at least two insulating layers.
  • the film layer pattern of the first display product formed on the first region of the base substrate and the film layer pattern of the second display product formed on the second region of the base substrate include a first conductive pattern under the insulating layer and located at the a second conductive pattern on the insulating layer, the second conductive pattern being connected to the first conductive pattern by a via structure penetrating the insulating layer, wherein a thickness of the insulating layer of the first region is smaller than a second The thickness of the insulating layer in the region.
  • the first conductive pattern of the first region includes a drain of the thin film transistor and the pixel electrode
  • the second conductive pattern of the first region is a conductive connection line respectively connected to the drain and the pixel electrode
  • the insulating layer of the first region is a passivation layer.
  • the film layer pattern of the first display product specifically includes:
  • a pixel electrode located in a first region of the base substrate
  • a gate of a thin film transistor located in a first region of the base substrate on which the pixel electrode is formed;
  • a gate insulating layer located in a first region of the base substrate on which the gate electrode is formed
  • a pattern of a passivation layer including the via structure in a first region of a base substrate on which a source and a drain of the thin film transistor are formed, the via structure including a portion corresponding to the drain a via and a second via corresponding to the pixel electrode, wherein the second via further penetrates the gate insulating layer;
  • the conductive connection line is connected to the drain through the first via hole, and is connected to the pixel electrode through the second via hole.
  • the conductive connection line is disposed in the same layer as the common electrode located in the first region.
  • Embodiments of the present invention also provide a display device including the first display product as described above.
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising:
  • the density of the deep holes of the second display product is a second density, and the second density is less than the first density
  • each of the deep holes is a through hole penetrating through at least two insulating layers
  • forming a film layer pattern of the first display product in the first region of the base substrate and forming a film layer pattern of the second display product in the second region of the substrate substrate comprises:
  • a portion of the first conductive pattern located in the first region includes: a drain of the thin film transistor and a pixel electrode; and a portion of the second conductive pattern located in the first region includes: and the drain a conductive connection line connecting the pole and the pixel electrode respectively.
  • the portion of the second conductive pattern located in the first region further includes: a common electrode of the first display product.
  • the thickness of the insulating layer of the display product having a relatively large deep hole density is reduced without increasing the patterning process, thereby reducing the display product.
  • the depth of the holes so that when the alignment film is coated on the array substrate, the diffusion effect of the alignment film at the via holes can be improved, thereby avoiding the occurrence of Mura defects.
  • Figure 1 is a schematic structural view of an MMG product
  • FIG. 2 is a schematic view showing exposure of a photoresist according to an embodiment of the present disclosure
  • FIG. 3 is a schematic view of the photoresist after developing the embodiment of the present disclosure
  • FIG. 4 is a schematic view of the embodiment of the present disclosure after etching a via hole
  • FIG. 5 is a schematic view showing the photoresist after ashing according to an embodiment of the present disclosure
  • FIG. 6 is a schematic view showing a thinning of a passivation layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic view of the second transparent conductive layer after forming an embodiment of the present disclosure.
  • the 43MMG product shown in Fig. 1 has been mass-produced, and the 43MMG product is a 43-inch ADS (Advanced Super-Dimensional Field Conversion) display product and 18.5-inch HADS (high aperture ratio) on the same substrate. Advanced Superdimensional Field Conversion) displays the graphics of the product.
  • ADS Advanced Super-Dimensional Field Conversion
  • HADS high aperture ratio
  • the 43-inch ADS display has a deep hole density of HADS display products with a deep hole density of less than 18.5 inches, with deep holes running through at least two layers of insulation. Through hole.
  • the drain and the pixel electrode of the thin film transistor of the 18.5 inch HADS display product are overlapped by deep holes, that is, the 18.5 inch HADS display product is provided in each sub-pixel region. Deep holes, therefore, the 18.5-inch HADS display product has a deep hole density that is significantly higher than that of the 43-inch ADS display product. Due to the easy sag at the deep hole, the alignment film is coated on the array substrate of the MMG product. When the alignment film is liable to spread unevenly at the deep hole, the final display product has a problem of displaying Mura.
  • an embodiment of the present disclosure provides an array substrate mother board, a manufacturing method thereof, and a display device.
  • a film layer pattern of different display products is formed on an array substrate mother board, Mura defects can be avoided.
  • Some embodiments of the present disclosure provide a method for fabricating an array substrate, comprising at least forming a film layer pattern of a first display product in a first region of the substrate substrate and forming a second region in the substrate substrate.
  • the film pattern of the second display product, the deep density of the first display product is greater than the deep hole density of the second display product, and the deep hole is a via hole penetrating at least two insulating layers.
  • the manufacturing method includes:
  • the thickness of the insulating layer of the display product having a relatively large deep hole density is reduced without increasing the patterning process, thereby reducing the display product.
  • the depth of the vias so that when the alignment film is coated on the array substrate, the diffusion effect of the alignment film at the via holes can be improved, thereby avoiding the problem of displaying Mura.
  • the manufacturing method specifically includes:
  • the second conductive pattern is formed on the insulating layer.
  • the thickness of the first region insulating layer can be reduced by exposure to a gray tone mask or a halftone mask.
  • the insulating layer covering the first conductive pattern is formed, and a via structure penetrating the insulating layer is formed to reduce the insulation of the first region
  • the thickness of the layer, forming the second conductive pattern on the insulating layer comprises:
  • a positive photoresist on the insulating layer and exposing the positive photoresist by using a gray tuned mask comprising a partially transparent pattern, a completely transparent pattern, and a complete An opaque pattern, the completely transparent pattern corresponding to an area for forming the via structure, wherein the partial light transmission pattern corresponds to an area of the first area except the via structure, the The light transmissive pattern corresponds to a region of the second region other than the via structure;
  • a photoresist partial retention region, a photoresist completely removed region, and a photoresist completely reserved region are formed;
  • the positive photoresist in the remaining portion of the photoresist is removed, and the insulating layer in the remaining portion of the photoresist is etched to reduce the thickness of the insulating layer in the remaining portion of the photoresist.
  • the insulating layer covering the first conductive pattern is formed, and a via structure penetrating the insulating layer is formed to reduce the insulation of the first region
  • the thickness of the layer, forming the second conductive pattern on the insulating layer comprises:
  • the gray mask includes a partially transparent pattern, a completely transparent pattern, and a complete An opaque pattern, the completely opaque pattern corresponding to a region for forming the via structure, the partial light transmission pattern corresponding to the region of the first region except the via structure, the complete The light transmissive pattern corresponds to a region of the second region other than the via structure;
  • the negative photoresist in the remaining portion of the photoresist is removed, and the insulating layer in the remaining portion of the photoresist is etched to reduce the thickness of the insulating layer in the remaining portion of the photoresist.
  • the first conductive pattern of the first region includes a drain of the thin film transistor and the pixel electrode
  • the second conductive pattern of the first region is a conductive connection line respectively connected to the drain and the pixel electrode
  • the insulating layer of the first region is a passivation layer.
  • the manufacturing method specifically includes:
  • a conductive connection line is formed on the passivation layer of the first region, the conductive connection line is connected to the drain through the first via hole, and is connected to the pixel electrode through the second via hole.
  • the conductive connection line is made of a transparent conductive layer.
  • the conductive connection line and the common electrode of the first area of the array substrate are simultaneously formed by one patterning process, which can reduce the number of patterning of the array substrate, improve the production efficiency of the array substrate, and reduce the production cost of the array substrate.
  • the array substrate mother board formed in this embodiment forms a large display panel with the color film substrate, and then the display panel is cut to form a plurality of 43-inch ADS display products and a plurality of 18.5-inch HADS display products.
  • Some embodiments of the present disclosure provide an array substrate mother board, the array substrate mother board including at least a film layer pattern of a first display product formed on a first region of the substrate substrate and a second layer formed on the second region of the substrate substrate Displaying a film pattern of the product, the deep hole density of the first display product is greater than the deep hole density of the second display product, the deep hole is a via hole penetrating at least two insulating layers, and the array substrate comprises an insulation a first conductive pattern under the layer and a second conductive pattern on the insulating layer, the second conductive pattern being connected to the first conductive pattern by a via structure penetrating the insulating layer, wherein the first region The thickness of the insulating layer is smaller than the thickness of the insulating layer in the second region.
  • the thickness of the insulating layer of the display product having a relatively large deep hole density is relatively small, and the depth of the via hole of the display product is also relatively small, so that When the alignment film is coated on the array substrate, the diffusion effect of the alignment film at the via holes can be improved, thereby avoiding the occurrence of Mura defects.
  • the array substrate specifically includes:
  • a gate of a thin film transistor located in a first region of the base substrate on which the pixel electrode is formed;
  • a gate insulating layer located in a first region of the base substrate on which the gate electrode is formed
  • a pattern of a passivation layer including the via structure in a first region of a base substrate on which a source and a drain of the thin film transistor are formed, the via structure including a portion corresponding to the drain a via and a second via corresponding to the pixel electrode, wherein the second via further penetrates the gate insulating layer;
  • the conductive connection line is disposed in the same layer and the same material as the common electrode of the first region of the array substrate. In this way, the conductive connection line and the common electrode of the array substrate can be simultaneously formed by one patterning process, which can reduce the number of patterning of the array substrate, improve the production efficiency of the array substrate, and reduce the production cost of the array substrate.
  • the display device may be any product or component having a display function such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, a navigator, an electronic paper, or the like.
  • the method for fabricating the array substrate mother board of the present disclosure will be further described below by taking the 43MMG product as an example.
  • the method for fabricating an array substrate mother board of a 43MMG product comprises: forming a pattern of a first transparent conductive layer - forming a pattern of a gate metal layer - forming a pattern of a source/drain metal layer - forming a passivation layer - forming a pattern of the second transparent conductive layer,
  • the passivation layer is exposed by using a halftone mask or a gray tone mask, and the 18.5 inch HADS is made by etching and ashing.
  • a thickness of about one layer may be deposited on the base substrate 1 subjected to the step 1 by magnetron sputtering, thermal evaporation or other film formation methods.
  • the gate metal layer 14, the gate metal layer 14 may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals.
  • the gate metal layer 14 may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo or the like.
  • the thickness of the engraved adhesive remains unchanged; the gate metal layer of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the gate metal layer 14, and the pattern of the gate metal layer 14 includes 43 inches.
  • the ADS shows the gate line of the product, the gate of the thin film transistor, and the gate line of the 18.5-inch HADS display product, the gate of the thin film transistor.
  • Step 3 forming a pattern of the gate insulating layer 3 and the active layer 4 on the substrate 1 through the step 2;
  • a plasma enhanced chemical vapor deposition (PECVD) method may be employed to deposit a thickness on the substrate 1 through the step 2
  • the gate insulating layer 3 may be SiNx, SiOx or Si(ON)x.
  • a thickness on the gate insulating layer 3 by magnetron sputtering, thermal evaporation or other film formation method.
  • a semiconductor layer, coated with a photoresist on the semiconductor layer exposed, developed, etched the semiconductor layer, and stripped of the photoresist to form a pattern of the active layer 4 composed of the semiconductor layer, the pattern of the active layer 4 including The active layer of the 43-inch ADS display product and the active layer of the 18.5-inch HADS display product.
  • Step 4 forming a pattern of the source/drain metal layer 5 on the substrate 1 through the step 3;
  • a thickness of about one layer may be deposited on the base substrate 1 subjected to the step 3 by magnetron sputtering, thermal evaporation or other film formation method.
  • the source/drain metal layer 5, the source/drain metal layer 5 may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals.
  • the source/drain metal layer 5 may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo or the like.
  • a layer of photoresist is coated on the source/drain metal layer 5, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist remains.
  • the region corresponds to the region where the pattern of the source/drain metal layer 5 is located, and the photoresist unretained region corresponds to the region other than the above-mentioned pattern; the development process is performed, the photoresist in the unretained region of the photoresist is completely removed, and the photoresist retention region is completely removed.
  • the thickness of the photoresist remains unchanged; the source-drain metal film of the unretained region of the photoresist is completely etched away by the etching process, and the remaining photoresist is stripped to form a pattern of the source/drain metal layer 5, and the source/drain metal layer 5
  • the graphics include the data lines of the 43-inch ADS display product, the source and drain of the thin film transistor, and the data lines of the 18.5-inch HADS display product, the source and drain of the thin film transistor.
  • Step 5 Form a pattern including a passivation layer 6 having a via structure on the base substrate 1 subjected to the step 4, the via structure including a first via having a drain corresponding to a 18.5 inch HADS display product and a corresponding 18.5 The inch of the HADS shows the second via of the pixel electrode of the product, the second via also penetrates the gate insulating layer 3;
  • a passivation layer 6 is deposited on the substrate 1 through the step 4, a photoresist 7 is coated on the passivation layer 6, and a photoresist 7 is applied to the photoresist layer 8 by using the gray mask.
  • the gray tone mask 8 includes a partially transparent pattern 10, a completely transparent pattern 9 and a completely opaque pattern, and the completely transparent pattern 9 corresponds to a region for forming a via structure, and the partial light transmission pattern 10 corresponds to the first An area other than the via structure, the completely opaque pattern corresponding to the area of the second area except the via structure,
  • the first area is the area where the 18.5-inch HADS display product is located, and the second area is the area where the 43-inch ADS display product is located.
  • the photoresist 7 is developed to form a photoresist portion remaining region, a photoresist completely removed region, and a photoresist completely remaining region (not shown).
  • the passivation layer 6 in the completely removed region of the photoresist is etched to form a via structure penetrating through the passivation layer 6.
  • the via structure includes a corresponding 18.5.
  • the first via 12 of the drain of the inch of the HADS display product and the second via 13 of the pixel electrode of the 18.1 inch HADS display product, the first via 12 penetrating the passivation layer 6, and the second via 13 is blunt Layer 6 and gate insulating layer 3;
  • the photoresist 7 in the photoresist remaining portion and the photoresist completely remaining region is removed by an ashing process, so that the photoresist 7 in the photoresist remaining region is completely removed, and the photoresist is completely retained.
  • the thickness of the photoresist 7 in the region is also reduced.
  • the passivation layer 6 in the remaining portion of the photoresist is etched, and the thickness of the passivation layer 6 in the remaining portion of the photoresist portion is reduced by precisely controlling the etching time, thereby reducing the first
  • the depth of the via 12 and the second via 13 reduces the difference between the first via 12 and the second via 13 to avoid poor Mura.
  • the thickness of the passivation layer 6 in the completely remaining region of the photoresist is not reduced, that is, the passivation layer 6 of the first region is finally made.
  • the thickness is smaller than the thickness of the passivation layer 6 of the second region.
  • a thickness of about one layer may be deposited by magnetron sputtering, thermal evaporation, or other film formation method on the substrate 1 through step 5.
  • the second transparent conductive layer 11 and the second transparent conductive layer 11 may be made of ITO. Applying a photoresist on the second transparent conductive layer 11, performing exposure, development, etching the second transparent conductive layer 11, and stripping the photoresist to form a pattern of the second transparent conductive layer 11, the second transparent conductive layer 11
  • the pattern consists of a conductive connection line, a pixel electrode of a 43-inch ADS display product, and a common electrode of a 18.5-inch HADS display product.
  • the conductive connection line passes through the first via 12 and the thin film transistor.
  • the drain connection is connected to the pixel electrode through the second via hole 13, so that the electrical connection between the drain of the thin film transistor and the pixel electrode can be realized by the conductive connection line.
  • an array substrate as shown in FIG. 7 can be obtained.
  • a halftone mask or a gray mask is used while maintaining the manufacturing process of the original array substrate.
  • the passivation layer was exposed such that the 18.5 inch HADS display product had a passivation layer thickness of less than 43 inches for the passivation layer thickness of the ADS display product, thereby reducing the 18.5 inch HADS display product without increasing the patterning process.
  • the passivation layer has a depth of the via holes, so that when the alignment film is coated on the array substrate, the diffusion effect of the alignment film at the via holes can be improved, thereby avoiding the occurrence of Mura defects.

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Abstract

一种阵列基板母板及其制作方法、显示装置。阵列基板母板的制作方法至少包括在衬底基板（1）的第一区域形成第一显示产品的膜层图形和在衬底基板（1）的第二区域形成第二显示产品的膜层图形，第一显示产品的深孔密度大于第二显示产品的深孔密度，深孔为贯穿至少两层绝缘层的过孔。制作方法具体包括：在绝缘层上形成第二导电图形之前，减小第一区域绝缘层的厚度，第二导电图形通过贯穿绝缘层的过孔结构与位于绝缘层下的第一导电图形连接。

Description

阵列基板母板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2016年4月28日在中国提交的中国专利申请号No.201610274032.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是指一种阵列基板母板及其制作方法、显示装置。
背景技术
MMG(Multi Mode Group，多显示模式组)产品即是在同一张衬底基板上，同时形成两种或两种以上显示产品的图形，这样可以提高衬底基板的利用率，降低投入成本。然而，在同一张阵列基板上形成不同显示产品的膜层图形时，易出现显示Mura(不均匀)的问题。
发明内容
本公开要解决的技术问题是提供一种阵列基板母板及其制作方法、显示装置，在阵列基板上形成不同显示产品的膜层图形时，能够避免出现Mura不良。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种阵列基板母板的制作方法，包括在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形，所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度，深孔为贯穿至少两层绝缘层的过孔。所述在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形包括：
在绝缘层上形成第二导电图形之前，减小第一区域所述绝缘层的厚度；在所述绝缘层上形成所述第二导电图形，并使得所述第二导电图形通过贯穿 所述绝缘层的过孔结构与位于所述绝缘层下的第一导电图形连接。
进一步地，所述在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形具体包括：
形成所述第一导电图形；
形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构；
减小第一区域所述绝缘层的厚度；
在所述绝缘层上形成所述第二导电图形。
进一步地，所述形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构，减小第一区域所述绝缘层的厚度，在所述绝缘层上形成所述第二导电图形包括：
在形成有第一导电图形的衬底基板上形成所述绝缘层；
在所述绝缘层上涂覆正性光刻胶，利用灰色调掩膜板对所述正性光刻胶进行曝光，所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形，所述完全透光图形对应用以形成所述过孔结构的区域，所述部分透光图形对应所述第一区域除所述过孔结构之外的区域，所述完全不透光图形对应所述第二区域除所述过孔结构之外的区域；
对正性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域；
对光刻胶完全去除区域的绝缘层进行刻蚀，形成贯穿所述绝缘层的所述过孔结构；
去除光刻胶部分保留区域的正性光刻胶，对光刻胶部分保留区域的绝缘层进行刻蚀，减小光刻胶部分保留区域的绝缘层的厚度。
进一步地，所述形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构，减小第一区域所述绝缘层的厚度，在所述绝缘层上形成所述第二导电图形包括：
在形成有第一导电图形的衬底基板上形成所述绝缘层；
在所述绝缘层上涂覆负性光刻胶，利用灰色调掩膜板对所述负性光刻胶进行曝光，所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透 光图形，所述完全不透光图形对应用以形成所述过孔结构的区域，所述部分透光图形对应所述第一区域除所述过孔结构之外的区域，所述完全透光图形对应所述第二区域除所述过孔结构之外的区域；
对负性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域；
对光刻胶完全去除区域的绝缘层进行刻蚀，形成贯穿所述绝缘层的所述过孔结构；
去除光刻胶部分保留区域的负性光刻胶，对光刻胶部分保留区域的绝缘层进行刻蚀，减小光刻胶部分保留区域的绝缘层的厚度。
进一步地，位于所述第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极，位于所述第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线，位于所述第一区域的所述绝缘层为钝化层。
进一步地，所述在衬底基板的第一区域形成第一显示产品的膜层图形还包括：
在所述衬底基板的第一区域形成像素电极；
在形成有所述像素电极的衬底基板的第一区域形成薄膜晶体管的栅极；
在形成有所述栅极的衬底基板的第一区域形成栅绝缘层；
在第一区域的所述栅绝缘层上形成有源层；
在形成有所述有源层的衬底基板的第一区域形成薄膜晶体管的源极和漏极；
在形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域形成包括有所述过孔结构的钝化层的图形，所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔，其中，所述第二过孔还贯穿所述栅绝缘层；
在第一区域的所述钝化层上形成导电连接线，所述导电连接线通过所述第一过孔与所述漏极连接，通过所述第二过孔与所述像素电极连接。
进一步地，所述导电连接线为采用透明导电层制成。
进一步地，所述导电连接线与位于所述第一区域的公共电极为通过一次构图工艺同时形成。
本公开实施例还提供了一种阵列基板母板，所述阵列基板母板至少包括形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形，所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度，深孔为贯穿至少两层绝缘层的过孔。所述形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形包括位于绝缘层下的第一导电图形和位于所述绝缘层上的第二导电图形，所述第二导电图形通过贯穿所述绝缘层的过孔结构与所述第一导电图形连接，其中，第一区域的所述绝缘层的厚度小于第二区域所述绝缘层的厚度。
进一步地，第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极，第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线，第一区域的所述绝缘层为钝化层。
进一步地，所述第一显示产品的膜层图形具体包括：
位于所述衬底基板的第一区域的像素电极；
位于形成有所述像素电极的衬底基板的第一区域的薄膜晶体管的栅极；
位于形成有所述栅极的衬底基板的第一区域的栅绝缘层；
位于第一区域的所述栅绝缘层上的有源层；
位于形成有所述有源层的衬底基板的第一区域的薄膜晶体管的源极和漏极；
位于形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域的包括有所述过孔结构的钝化层的图形，所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔，其中，所述第二过孔还贯穿所述栅绝缘层；
位于第一区域的所述钝化层上的导电连接线，所述导电连接线通过所述第一过孔与所述漏极连接，通过所述第二过孔与所述像素电极连接。
进一步地，所述导电连接线与位于第一区域的公共电极为同层同材料设置。
本发明实施例还提供了一种显示装置，包括如上所述的第一显示产品。
本发明实施例还提供了一种阵列基板母板的制作方法，包括：
在衬底基板的第一区域形成第一显示产品的膜层图形，且所述第一显示产品的深孔的密度为第一密度；和
在所述衬底基板的第二区域形成第二显示产品的膜层图形，所述第二显示产品的深孔的密度为第二密度，所述第二密度小于所述第一密度；
其中，每个所述深孔为贯穿至少两层绝缘层的过孔；
其中，在所述衬底基板的第一区域形成第一显示产品的膜层图形和在所述衬底基板的第二区域形成第二显示产品的膜层图形包括：
在所述衬底基板上形成第一导电图形；
形成覆盖所述第一导电图形的绝缘层，并按照所述第一密度在所述绝缘层位于所述第一区域中的部分上形成过孔，并按照所述第二密度在所述绝缘层位于所述第二区域中的部分上形成过孔；
减小所述绝缘层位于所述第一区域中的部分的厚度使得位于所述第一区域中的所述过孔的深度小于位于所述第二区域中的所述过孔的深度；
在所述绝缘层上形成所述第二导电图形，使得所述第二导电图形位于所述第一区域中的部分通过位于所述第一区域中的所述过孔与所述第一导电图形位于所述第一区域中的部分连接，并使得所述第二导电图形位于所述第二区域中的部分通过位于所述第二区域中的所述过孔与所述第一导电图形位于所述第二区域中的部分连接。
进一步地，所述第一导电图形位于所述第一区域中的部分包括：薄膜晶体管的漏极和像素电极；所述第二导电图形位于所述第一区域中的部分包括：与所述漏极和所述像素电极分别连接的导电连接线。
进一步地，所述第二导电图形位于所述第一区域中的部分还包括：所述第一显示产品的公共电极。
本发明本公开的实施例具有以下有益效果：
上述方案中，在阵列基板上形成不同显示产品的膜层图形时，在不增加构图工艺的前提下，减小深孔密度比较大的显示产品的绝缘层的厚度，进而减小该显示产品过孔的深度，这样之后在阵列基板上涂覆配向膜时，能够提高配向膜在过孔处的扩散效果，从而避免出现Mura不良。
附图说明
图1为MMG产品的结构示意图；
图2为本公开实施例对光刻胶进行曝光的示意图；
图3为本公开实施例对光刻胶进行显影后的示意图；
图4为本公开实施例刻蚀出过孔后的示意图；
图5为本公开实施例对光刻胶进行灰化后的示意图；
图6为本公开实施例对钝化层进行减薄后的示意图；
图7为本公开实施例形成第二透明导电层后的示意图。
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
在相关技术中，如图1所示的43MMG产品已经量产，43MMG产品是在同一张衬底基板上形成43英寸的ADS(高级超维场转换)显示产品和18.5英寸的HADS(高开口率高级超维场转换)显示产品的图形。
对于43英寸的ADS显示产品和18.5英寸的HADS显示产品来说，43英寸的ADS显示产品的深孔密度小于18.5英寸的HADS显示产品的深孔密度，其中，深孔为贯穿至少两层绝缘层的过孔。
具体地，在上述43MMG产品中，18.5英寸的HADS显示产品的薄膜晶体管的漏极和像素电极之间是通过深孔搭接的，即18.5英寸的HADS显示产品每一亚像素区域内都设置有一深孔，因此，18.5英寸的HADS显示产品的深孔密度明显比43英寸的ADS显示产品的深孔密度大，由于在深孔处容易出现凹陷，导致在MMG产品的阵列基板上涂覆配向膜时，配向膜容易在深孔处易发生扩散不均，导致最终的显示产品出现显示Mura的问题。
为了解决上述问题，本公开的实施例提供一种阵列基板母板及其制作方法、显示装置，在阵列基板母板上形成不同显示产品的膜层图形时，能够避免出现Mura不良。
本公开一些实施例提供一种阵列基板母板的制作方法，至少包括在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成 第二显示产品的膜层图形，所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度，深孔为贯穿至少两层绝缘层的过孔。具体地，所述制作方法包括：
在绝缘层上形成第二导电图形之前，减小第一区域所述绝缘层的厚度，所述第二导电图形通过贯穿所述绝缘层的过孔结构与位于所述绝缘层下的第一导电图形连接。
本实施例中，在阵列基板上形成不同显示产品的膜层图形时，在不增加构图工艺的前提下，减小深孔密度比较大的显示产品的绝缘层的厚度，进而减小该显示产品过孔的深度，这样之后在阵列基板上涂覆配向膜时，能够提高配向膜在过孔处的扩散效果，从而避免出现显示Mura的问题。
进一步地，所述制作方法具体包括：
形成所述第一导电图形；
形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构；
减小第一区域所述绝缘层的厚度；
在所述绝缘层上形成所述第二导电图形。
具体实施例中，可以通过灰色调掩膜板或半色调掩膜板曝光实现减小第一区域绝缘层的厚度。
进一步地，在利用正性光刻胶进行光刻工艺时，所述形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构，减小第一区域所述绝缘层的厚度，在所述绝缘层上形成所述第二导电图形包括：
在形成有第一导电图形的衬底基板上形成所述绝缘层；
在所述绝缘层上涂覆正性光刻胶，利用灰色调掩膜板对所述正性光刻胶进行曝光，所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形，所述完全透光图形对应用以形成所述过孔结构的区域，所述部分透光图形对应所述第一区域除所述过孔结构之外的区域，所述完全不透光图形对应所述第二区域除所述过孔结构之外的区域；
对正性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域；
对光刻胶完全去除区域的绝缘层进行刻蚀，形成贯穿所述绝缘层的所述过孔结构；
去除光刻胶部分保留区域的正性光刻胶，对光刻胶部分保留区域的绝缘层进行刻蚀，减小光刻胶部分保留区域的绝缘层的厚度。
进一步地，在利用负性光刻胶进行光刻工艺时，所述形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构，减小第一区域所述绝缘层的厚度，在所述绝缘层上形成所述第二导电图形包括：
在形成有第一导电图形的衬底基板上形成所述绝缘层；
在所述绝缘层上涂覆负性光刻胶，利用灰色调掩膜板对所述负性光刻胶进行曝光，所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形，所述完全不透光图形对应用以形成所述过孔结构的区域，所述部分透光图形对应所述第一区域除所述过孔结构之外的区域，所述完全透光图形对应所述第二区域除所述过孔结构之外的区域；
对负性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域；
对光刻胶完全去除区域的绝缘层进行刻蚀，形成贯穿所述绝缘层的所述过孔结构；
去除光刻胶部分保留区域的负性光刻胶，对光刻胶部分保留区域的绝缘层进行刻蚀，减小光刻胶部分保留区域的绝缘层的厚度。
进一步地，第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极，第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线，第一区域的所述绝缘层为钝化层。
进一步地，所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板的第一区域形成像素电极；
在形成有所述像素电极的衬底基板的第一区域形成薄膜晶体管的栅极；
在形成有所述栅极的衬底基板的第一区域形成栅绝缘层；
在第一区域的所述栅绝缘层上形成有源层；
在形成有所述有源层的衬底基板的第一区域形成薄膜晶体管的源极和漏 极；
在形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域形成包括有所述过孔结构的钝化层的图形，所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔，其中，所述第二过孔还贯穿所述栅绝缘层；
在第一区域的所述钝化层上形成导电连接线，所述导电连接线通过所述第一过孔与所述漏极连接，通过所述第二过孔与所述像素电极连接。
进一步地，为了不影响显示，导电连接线为采用透明导电层制成。
进一步地，所述导电连接线与阵列基板第一区域的公共电极为通过一次构图工艺同时形成，这样可以减少阵列基板的构图次数，提高阵列基板的生产效率，降低阵列基板的生产成本。
本实施例形成的阵列基板母板与彩膜基板对盒后形成一个大的显示面板，之后对显示面板进行切割即可形成多个43英寸的ADS显示产品和多个18.5英寸的HADS显示产品。
本公开一些实施例提供了一种阵列基板母板，所述阵列基板母板至少包括形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形，所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度，深孔为贯穿至少两层绝缘层的过孔，所述阵列基板包括位于绝缘层下的第一导电图形和位于所述绝缘层上的第二导电图形，所述第二导电图形通过贯穿所述绝缘层的过孔结构与所述第一导电图形连接，其中，第一区域的所述绝缘层的厚度小于第二区域所述绝缘层的厚度。
本实施例中，在阵列基板上形成不同显示产品的膜层图形时，深孔密度比较大的显示产品的绝缘层的厚度比较小，进而该显示产品过孔的深度也比较小，这样之后在阵列基板上涂覆配向膜时，能够提高配向膜在过孔处的扩散效果，从而避免出现Mura不良。
进一步地，第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极，第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线，第一区域的所述绝缘层为钝化层。
进一步地，所述阵列基板具体包括：
衬底基板；
位于所述衬底基板的第一区域的像素电极；
位于形成有所述像素电极的衬底基板的第一区域的薄膜晶体管的栅极；
位于形成有所述栅极的衬底基板的第一区域的栅绝缘层；
位于第一区域的所述栅绝缘层上的有源层；
位于形成有所述有源层的衬底基板的第一区域的薄膜晶体管的源极和漏极；
位于形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域的包括有所述过孔结构的钝化层的图形，所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔，其中，所述第二过孔还贯穿所述栅绝缘层；
位于第一区域的所述钝化层上的导电连接线，所述导电连接线通过所述第一过孔与所述漏极连接，通过所述第二过孔与所述像素电极连接。
进一步地，所述导电连接线与阵列基板第一区域的公共电极为同层同材料设置。这样，导电连接线与阵列基板的公共电极可以通过一次构图工艺同时形成，这样可以减少阵列基板的构图次数，提高阵列基板的生产效率，降低阵列基板的生产成本。
本公开一些实施例提供了一种显示装置，包括如上所述的第一区域。所述显示装置可以为：液晶面板、液晶电视、液晶显示器、数码相框、手机、平板电脑、导航仪、电子纸等任何具有显示功能的产品或部件。
下面以43MMG产品为例，对本公开的阵列基板母板的制作方法进行进一步介绍。43MMG产品的阵列基板母板的制作方法包括：形成第一透明导电层的图形-形成栅金属层的图形-形成源漏金属层的图形-形成钝化层-形成第二透明导电层的图形，本实施例是在原有阵列基板的制作工艺流程不变的前提下，利用半色调掩膜板或灰色调掩膜板对钝化层进行曝光，再通过刻蚀灰化等手段使得18.5英寸的HADS显示产品的钝化层厚度小于43英寸的 ADS显示产品的钝化层厚度，从而在不增加构图工艺的前提下，减小18.5英寸的HADS显示产品的钝化层过孔的深度。具体地，本实施例的阵列基板母板的制作方法具体包括以下步骤：
步骤1、提供一衬底基板1，在衬底基板1上沉积第一透明导电层2，通过构图工艺形成第一透明导电层2的图形，参见图2；
其中，衬底基板1可为玻璃基板或石英基板。具体地，可以在衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2017070833-appb-000001
的第一透明导电层2，第一透明导电层2可以选用ITO。在第一透明导电层2上涂覆光刻胶，进行曝光、显影，刻蚀第一透明导电层2，并剥离光刻胶，形成第一透明导电层2的图形，第一透明导电层2的图形包括43英寸的ADS显示产品的公共电极和18.5英寸的HADS显示产品的像素电极。
步骤2、在经过步骤1的衬底基板1上形成栅金属层14的图形；
具体地，可以在经过步骤1的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2017070833-appb-000002
的栅金属层14，栅金属层14可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。栅金属层14可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。在栅金属层14上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于栅金属层14的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属层，剥离剩余的光刻胶，形成栅金属层14的图形，栅金属层14的图形包括43英寸的ADS显示产品的栅线、薄膜晶体管的栅极和18.5英寸的HADS显示产品的栅线、薄膜晶体管的栅极。
步骤3、在经过步骤2的衬底基板1上形成栅绝缘层3和有源层4的图形；
具体地，可以采用等离子体增强化学气相沉积(PECVD)方法，在经过步骤2的衬底基板1上沉积厚度约为
Figure PCTCN2017070833-appb-000003
的栅绝缘层3，其中，栅绝缘层3的材料可以选用氧化物、氮化物或者氮氧化物，栅绝缘层3可以为单 层、双层或多层结构。具体地，栅绝缘层3可以采用SiNx，SiOx或Si(ON)x。
在栅绝缘层3上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2017070833-appb-000004
的半导体层，在半导体层上涂覆光刻胶，进行曝光、显影，刻蚀半导体层，并剥离光刻胶，形成由半导体层组成的有源层4的图形，有源层4的图形包括43英寸的ADS显示产品的有源层和18.5英寸的HADS显示产品的有源层。
步骤4、在经过步骤3的衬底基板1上形成源漏金属层5的图形；
具体地，可以在经过步骤3的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2017070833-appb-000005
的源漏金属层5，源漏金属层5可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层5可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。在源漏金属层5上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于源漏金属层5的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属薄膜，剥离剩余的光刻胶，形成源漏金属层5的图形，源漏金属层5的图形包括43英寸的ADS显示产品的数据线、薄膜晶体管的源极、漏极和18.5英寸的HADS显示产品的数据线、薄膜晶体管的源极、漏极。
步骤5、在经过步骤4的衬底基板1上形成包括有过孔结构的钝化层6的图形，过孔结构包括有对应18.5英寸的HADS显示产品的漏极的第一过孔和对应18.5英寸的HADS显示产品的像素电极的第二过孔，第二过孔还贯穿栅绝缘层3；
具体地，如图2所示，在经过步骤4的衬底基板1上沉积钝化层6，在钝化层6上涂覆光刻胶7，利用灰色调掩膜板8对光刻胶7进行曝光，灰色调掩膜板8包括部分透光图形10、完全透光图形9和完全不透光图形，完全透光图形9对应用以形成过孔结构的区域，部分透光图形10对应第一区域除过孔结构之外的区域，完全不透光图形对应第二区域除过孔结构之外的区域， 其中，第一区域为18.5英寸的HADS显示产品所在区域，第二区域为43英寸的ADS显示产品所在区域。
如图3所示，对光刻胶7进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域(未图示)。
如图4所示，对光刻胶完全去除区域的钝化层6进行刻蚀，形成贯穿钝化层6的过孔结构，在图4所示的第一区域中，过孔结构包括对应18.5英寸的HADS显示产品的漏极的第一过孔12和对应18.5英寸的HADS显示产品的像素电极的第二过孔13，第一过孔12贯穿钝化层6，第二过孔13贯穿钝化层6和栅绝缘层3；
如图5所示，通过灰化工艺去除光刻胶部分保留区域和光刻胶完全保留区域的光刻胶7，使得光刻胶部分保留区域的光刻胶7完全去除，光刻胶完全保留区域的光刻胶7的厚度也得以减薄。
如图6所示，对光刻胶部分保留区域的钝化层6进行刻蚀，通过精确控制刻蚀时间，减小光刻胶部分保留区域的钝化层6的厚度，进而减小第一过孔12和第二过孔13的深度，减少第一过孔12和第二过孔13处段差，避免Mura不良。此时，由于光刻胶完全保留区域仍然保留有光刻胶7，因此，光刻胶完全保留区域的钝化层6的厚度不会减小，即最终使得第一区域的钝化层6的厚度小于第二区域的钝化层6的厚度。
步骤6、在经过步骤5的衬底基板1上形成第二透明导电层11，对第二透明导电层11进行构图形成第二透明导电层11的图形。
具体地，如图7所示，可以在经过步骤5的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2017070833-appb-000006
的第二透明导电层11，第二透明导电层11可以选用ITO。在第二透明导电层11上涂覆光刻胶，进行曝光、显影，刻蚀第二透明导电层11，并剥离光刻胶，形成第二透明导电层11的图形，第二透明导电层11的图形包括导电连接线、43英寸的ADS显示产品的像素电极和18.5英寸的HADS显示产品的公共电极，对于18.5英寸的HADS显示产品而言，导电连接线通过第一过孔12与薄膜晶体管的漏极连接，通过第二过孔13与像素电极连接，这样通过导电连接线即可实现薄膜晶体管的漏极与像素电极之间的电连接。
经过上述步骤1-6即可制作得到如图7所示的阵列基板，本实施例在保持原有阵列基板的制作工艺流程不变的情况下，利用半色调掩膜板或灰色调掩膜板对钝化层进行曝光，使得18.5英寸的HADS显示产品的钝化层厚度小于43英寸的ADS显示产品的钝化层厚度，从而在不增加构图工艺的前提下，减小18.5英寸的HADS显示产品的钝化层过孔的深度，这样之后在阵列基板上涂覆配向膜时，能够提高配向膜在过孔处的扩散效果，从而避免出现Mura不良。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种阵列基板母板的制作方法，包括：在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形，所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度，深孔为贯穿至少两层绝缘层的过孔；
    其中，所述在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形包括：
    在绝缘层上形成第二导电图形之前，减小第一区域所述绝缘层的厚度；
    在所述绝缘层上形成所述第二导电图形，并使得所述第二导电图形通过贯穿所述绝缘层的过孔结构与位于所述绝缘层下的第一导电图形连接。
  2. 根据权利要求1所述的阵列基板母板的制作方法，其中，所述在衬底基板的第一区域形成第一显示产品的膜层图形和在衬底基板的第二区域形成第二显示产品的膜层图形具体包括：
    形成所述第一导电图形；
    形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构；
    减小第一区域所述绝缘层的厚度；
    在所述绝缘层上形成所述第二导电图形。
  3. 根据权利要求2所述的阵列基板母板的制作方法，其中，所述形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构，减小第一区域所述绝缘层的厚度，在所述绝缘层上形成所述第二导电图形包括：
    在形成有第一导电图形的衬底基板上形成所述绝缘层；
    在所述绝缘层上涂覆正性光刻胶，利用灰色调掩膜板对所述正性光刻胶进行曝光，所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形，所述完全透光图形对应用以形成所述过孔结构的区域，所述部分透光图形对应所述第一区域除所述过孔结构之外的区域，所述完全不透光图形对应所述第二区域除所述过孔结构之外的区域；
    对正性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区 域和光刻胶完全保留区域；
    对光刻胶完全去除区域的绝缘层进行刻蚀，形成贯穿所述绝缘层的所述过孔结构；
    去除光刻胶部分保留区域的正性光刻胶，对光刻胶部分保留区域的绝缘层进行刻蚀，减小光刻胶部分保留区域的绝缘层的厚度。
  4. 根据权利要求2所述的阵列基板母板的制作方法，其中，所述形成覆盖所述第一导电图形的绝缘层，并形成贯穿所述绝缘层的过孔结构，减小第一区域所述绝缘层的厚度，在所述绝缘层上形成所述第二导电图形包括：
    在形成有第一导电图形的衬底基板上形成所述绝缘层；
    在所述绝缘层上涂覆负性光刻胶，利用灰色调掩膜板对所述负性光刻胶进行曝光，所述灰色调掩膜板包括部分透光图形、完全透光图形和完全不透光图形，所述完全不透光图形对应用以形成所述过孔结构的区域，所述部分透光图形对应所述第一区域除所述过孔结构之外的区域，所述完全透光图形对应所述第二区域除所述过孔结构之外的区域；
    对负性光刻胶进行显影后形成光刻胶部分保留区域、光刻胶完全去除区域和光刻胶完全保留区域；
    对光刻胶完全去除区域的绝缘层进行刻蚀，形成贯穿所述绝缘层的所述过孔结构；
    去除光刻胶部分保留区域的负性光刻胶，对光刻胶部分保留区域的绝缘层进行刻蚀，减小光刻胶部分保留区域的绝缘层的厚度。
  5. 根据权利要求3或4所述的阵列基板母板的制作方法，其中，位于所述第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极，位于所述第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连接线，位于所述第一区域的所述绝缘层为钝化层。
  6. 根据权利要求5所述的阵列基板母板的制作方法，其中，所述导电连接线为采用透明导电层制成。
  7. 根据权利要求1所述的阵列基板母板的制作方法，其中，位于所述第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极，位于所述第一区域的所述第二导电图形为与所述漏极和所述像素电极分别连接的导电连 接线，位于所述第一区域的所述绝缘层为钝化层；
    所述在衬底基板的第一区域形成第一显示产品的膜层图形还包括：
    在所述衬底基板的第一区域形成像素电极；
    在形成有所述像素电极的衬底基板的第一区域形成薄膜晶体管的栅极；
    在形成有所述栅极的衬底基板的第一区域形成栅绝缘层；
    在第一区域的所述栅绝缘层上形成有源层；
    在形成有所述有源层的衬底基板的第一区域形成薄膜晶体管的源极和漏极；
    在形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域形成包括有所述过孔结构的钝化层的图形，所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔，其中，所述第二过孔还贯穿所述栅绝缘层；
    在第一区域的所述钝化层上形成导电连接线，所述导电连接线通过所述第一过孔与所述漏极连接，通过所述第二过孔与所述像素电极连接。
  8. 根据权利要求7所述的阵列基板母板的制作方法，其中，所述导电连接线为采用透明导电层制成。
  9. 根据权利要求8所述的阵列基板母板的制作方法，其中，所述导电连接线与位于所述第一区域的公共电极为通过一次构图工艺同时形成。
  10. 一种阵列基板母板，包括：形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形，所述第一显示产品的深孔密度大于所述第二显示产品的深孔密度，深孔为贯穿至少两层绝缘层的过孔；
    其中，所述形成在衬底基板第一区域的第一显示产品的膜层图形和形成在衬底基板第二区域的第二显示产品的膜层图形包括：位于绝缘层下的第一导电图形和位于所述绝缘层上的第二导电图形，所述第二导电图形通过贯穿所述绝缘层的过孔结构与所述第一导电图形连接，其中，所述第一区域的所述绝缘层的厚度小于所述第二区域所述绝缘层的厚度。
  11. 根据权利要求10所述的阵列基板母板，其中，所述第一区域的所述第一导电图形包括薄膜晶体管的漏极和像素电极，所述第一区域的所述第二 导电图形为与所述漏极和所述像素电极分别连接的导电连接线，所述第一区域的所述绝缘层为钝化层。
  12. 根据权利要求11所述的阵列基板母板，其中，所述第一显示产品的膜层图形具体包括：
    位于所述衬底基板的第一区域的像素电极；
    位于形成有所述像素电极的衬底基板的第一区域的薄膜晶体管的栅极；
    位于形成有所述栅极的衬底基板的第一区域的栅绝缘层；
    位于第一区域的所述栅绝缘层上的有源层；
    位于形成有所述有源层的衬底基板的第一区域的薄膜晶体管的源极和漏极；
    位于形成有所述薄膜晶体管的源极和漏极的衬底基板的第一区域的包括有所述过孔结构的钝化层的图形，所述过孔结构包括有对应所述漏极的第一过孔和对应所述像素电极的第二过孔，其中，所述第二过孔还贯穿所述栅绝缘层；
    位于第一区域的所述钝化层上的导电连接线，所述导电连接线通过所述第一过孔与所述漏极连接，通过所述第二过孔与所述像素电极连接。
  13. 根据权利要求12所述的阵列基板母板，其中，所述导电连接线与位于所述第一区域的公共电极为同层同材料设置。
  14. 一种阵列基板母板的制作方法，包括：
    在衬底基板的第一区域形成第一显示产品的膜层图形，且所述第一显示产品的深孔的密度为第一密度；和
    在所述衬底基板的第二区域形成第二显示产品的膜层图形，所述第二显示产品的深孔的密度为第二密度，所述第二密度小于所述第一密度；
    其中，每个所述深孔为贯穿至少两层绝缘层的过孔；
    其中，在所述衬底基板的第一区域形成第一显示产品的膜层图形和在所述衬底基板的第二区域形成第二显示产品的膜层图形包括：
    在所述衬底基板上形成第一导电图形；
    形成覆盖所述第一导电图形的绝缘层，并按照所述第一密度在所述绝缘层位于所述第一区域中的部分上形成过孔，并按照所述第二密度在所述绝缘 层位于所述第二区域中的部分上形成过孔；
    减小所述绝缘层位于所述第一区域中的部分的厚度使得位于所述第一区域中的所述过孔的深度小于位于所述第二区域中的所述过孔的深度；
    在所述绝缘层上形成所述第二导电图形，使得所述第二导电图形位于所述第一区域中的部分通过位于所述第一区域中的所述过孔与所述第一导电图形位于所述第一区域中的部分连接，并使得所述第二导电图形位于所述第二区域中的部分通过位于所述第二区域中的所述过孔与所述第一导电图形位于所述第二区域中的部分连接。
  15. 根据权利要求14所述的阵列基板母板的制作方法，其中，所述第一导电图形位于所述第一区域中的部分包括：薄膜晶体管的漏极和像素电极；
    所述第二导电图形位于所述第一区域中的部分包括：与所述漏极和所述像素电极分别连接的导电连接线。
  16. 根据权利要求14所述的阵列基板母板的制作方法，其中，所述第二导电图形位于所述第一区域中的部分还包括：所述第一显示产品的公共电极。
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