WO2019051864A1 - 主动阵列开关的制造方法 - Google Patents

主动阵列开关的制造方法 Download PDF

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Publication number
WO2019051864A1
WO2019051864A1 PCT/CN2017/102869 CN2017102869W WO2019051864A1 WO 2019051864 A1 WO2019051864 A1 WO 2019051864A1 CN 2017102869 W CN2017102869 W CN 2017102869W WO 2019051864 A1 WO2019051864 A1 WO 2019051864A1
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layer
active array
array switch
pattern
semiconductor
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PCT/CN2017/102869
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English (en)
French (fr)
Inventor
何怀亮
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惠科股份有限公司
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Priority to US15/739,345 priority Critical patent/US10622387B2/en
Publication of WO2019051864A1 publication Critical patent/WO2019051864A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • the present application relates to a method of fabricating an active array switch, and more particularly to a method of fabricating an active array switch that utilizes a semiconductor layer to be electrically conductive to maintain an on-state current.
  • the active array switch semiconductor layer that drives the display panel is mainly composed of amorphous silicon (a-Si), oxide (Oxide), and polysilicon (Poly-Si).
  • a-Si amorphous silicon
  • Oxide oxide
  • Poly-Si polysilicon
  • ESL etch stop
  • BCE back channel etch
  • Co-planner Self-Align Top Gate active array switch process is difficult, and Dual Gate active array switch has large parasitic capacitance, so in active array switch flat panel display applications, ESL (etch barrier) and BCE (back channel) Etching is more common, but the BCE (back channel etching) structure has the advantage of saving a mask and is the focus of future development.
  • Gate and Source / Drain (source drain) electrodes tend to overlap areas, Gate and Source / Drain (the source)
  • the source and drain electrodes form parasitic capacitance, which is not conducive to large size and high dynamic display; however, if the parasitic capacitance is reduced, there is no overlapping area between the Gate and Source/Drain electrodes (even gaps are generated). Offset) will cause the TFT on-state current to decrease and the mobility to decrease.
  • an object of the present application is to provide a method for fabricating an active array switch, and more particularly to a method for fabricating an active array switch that utilizes a semiconductor layer to be electrically conductive to maintain an on-state current.
  • Active array switches are widely used in electronic products such as computer chips, mobile phone chips, or thin film transistors liquid crystal display (TFT LCD).
  • TFT LCD thin film transistors liquid crystal display
  • the active array switch acts as a switch for charging or discharging a storage capacitor.
  • the active array switch can be classified into an amorphous silicon active array switch (Amorphous Silicon Transistor) and a polycrystalline silicon active array switch (Low Temperature Polycrystalline Transistor) according to the material of the semiconductor layer.
  • amorphous silicon active array switch Amorphous Silicon Transistor
  • a polycrystalline silicon active array switch Low Temperature Polycrystalline Transistor
  • the Gate and Source/Drain electrodes tend to have overlapping regions.
  • the Gate and Source/Drain electrodes of the region form parasitic capacitance, which is not conducive to large size and high dynamic display; however, if the parasitic capacitance is reduced, Gate and Source/Drain are used.
  • the drain electrode has no overlap region (even the gap Offset), which causes the TFT on-state current to decrease and the mobility to decrease.
  • the present application provides a method for fabricating an active array switch, comprising the steps of: forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern; forming a pattern on the substrate a gate insulating layer covering the gate pattern; forming a semiconductor layer on the gate insulating layer; forming a photoresist layer having a plurality of thicknesses on the semiconductor layer, wherein the gate pattern is The thickness of the upper photoresist layer is greater than the thickness of the photoresist layer above the two sides of the gate pattern; and the photoresist layer is used as a mask to remove a portion of the semiconductor layer to form a semiconductor a pattern; performing a dry etching process on the photoresist layer, removing a thickness of the photoresist layer above both sides of the gate pattern, and drying the photoresist layer above the gate pattern The remaining thickness remaining after the etching still covers part of the semiconductor pattern; the portion of the semiconductor pattern exposed from the photoresist layer is conductor
  • the step of forming the photoresist layer having a plurality of thicknesses comprises: forming a layer of photosensitive material on the semiconductor layer, and performing a layer on the photosensitive material layer using a halftone mask Exposure process, and a development process.
  • the step of forming the photoresist layer having a plurality of thicknesses includes: forming a photosensitive material layer on the semiconductor layer, and performing an exposure on the photosensitive material layer using a gray tone mask The process, as well as a development process.
  • the semiconductor layer is a metal oxide semiconductor layer
  • the metal of the metal oxide semiconductor layer includes a group consisting of a group II-VI element and a compound thereof.
  • the metal semiconductor layer is further doped with one or more elements selected from the group consisting of alkaline earth metals, Group IIIA, Group VA, Group VIA, or transition metals.
  • a passivation layer is formed on the source, the drain, the semiconductor pattern, and the gate insulating layer.
  • an insulating material layer is formed between the semiconductor layer and the photoresist layer.
  • the insulating material layer is an inorganic insulating material layer (such as silicon oxide or silicon nitride) or an organic insulating material layer (such as polymethyl methacrylate or polyvinyl phenol).
  • the present application provides a method for fabricating an active array switch, comprising the steps of: forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern; forming on the substrate a gate insulating layer covering the gate pattern; forming a semiconductor layer on the gate insulating layer; forming an insulating material layer on the semiconductor layer; and forming a photosensitive material on the insulating material layer Layer Performing an exposure process on the photosensitive material layer by using a photomask; performing a developing process to form the photosensitive material layer to form a photoresist layer having a plurality of thicknesses, wherein the photoresist layer is located above the gate pattern a thickness greater than a thickness of the photoresist layer above the two sides of the gate pattern; removing a portion of the semiconductor layer to form a semiconductor pattern; performing a dry etching process on the photoresist layer, removing the a thickness of
  • the Gate (gate) and the Source/Drain (source drain) electrode are not overlapped, and the semiconductor layer is processed by the conductor process in the process.
  • the conductorization further reduces the impedance of the source/Drain (source drain) and the TFT channel, and ensures the on-state current while greatly reducing the parasitic capacitance of the active array switch.
  • FIG. 1A is a schematic view showing a structure in which an overlap region is formed between a gate and a source and drain.
  • FIG. 1B is a schematic diagram showing the structure of a gate and source and drain without overlapping regions.
  • FIG. 2A is a schematic view showing film formation of a semiconductor according to an embodiment of the present application.
  • 2B is a schematic view showing the formation of a photoresist layer according to an embodiment of the present application.
  • 2C is a schematic diagram of forming a semiconductor pattern according to an embodiment of the present application.
  • FIG. 2D is a schematic diagram of a dry etching process according to an embodiment of the present application.
  • FIG. 2E is a schematic diagram of a conductor process according to an embodiment of the present application.
  • FIG. 2F is a schematic diagram of removing all photoresist layers according to an embodiment of the present application.
  • 2G is a flow chart of a method for manufacturing an active array switch according to an embodiment of the present application.
  • FIG 3 is a schematic view showing the structure of forming a passivation layer according to another embodiment of the present application.
  • FIG. 4 is a schematic view showing the structure of forming an insulating material layer according to another embodiment of the present application.
  • FIG. 5 is a flowchart of a method for manufacturing an active array switch according to another embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • the present application provides a method for fabricating an active array switch in which a semiconductor layer is made conductive so that a source-drain impedance of an overlap region is not reduced, and an on-state current is ensured while reducing an active array switch parasitic capacitance.
  • the present application proposes a method of fabricating an active array switch that includes the following steps.
  • FIG. 1A is a schematic structural view of an overlapping region of a gate and a source and a drain
  • FIG. 1B is a schematic structural view of a gate and a source/drain without overlapping regions.
  • a plurality of gate patterns 11 are formed on the substrate 10.
  • a gate insulating layer 12 is formed on the substrate 10 to cover the gate pattern 11.
  • a semiconductor layer 13 is formed on the gate insulating layer 12 and a portion of the semiconductor layer 13 is removed to form a semiconductor pattern 13'.
  • the source 15 and the drain 16 are formed on the semiconductor pattern 13'.
  • the gate pattern 11 of FIG. 1A and the source 15 and the drain 16 have an overlap region (Overlap, OL), and a parasitic capacitance is formed between the overlap regions OL, which is disadvantageous for large size and high dynamic display, but shifting In addition to the overlap region OL, even if there is a gap OS as shown in FIG. 1B, although the parasitic capacitance can be reduced, the impedance between the source and the drain becomes large, and the on-state current of the active array switch is reduced. , reducing its mobility.
  • the semiconductor pattern 13' is electrically conductive under the premise of removing the overlapping region OL to reduce the parasitic capacitance, thereby reducing the impedance between the source and the drain, and reducing the parasitic capacitance of the active array switch. It can still maintain a certain on-state current and mobility.
  • a method for manufacturing the active array switch 1 provided by the present application firstly forms a first metal layer on a substrate 10 and patterns the first metal layer as shown in FIG. 2A .
  • a gate pattern 11 is formed, and a gate insulating layer 12 is formed on the substrate 10 to cover the gate pattern 11.
  • a semiconductor layer 13 is formed on the gate insulating layer 12.
  • the semiconductor layer 13 is a metal oxide semiconductor layer, and the metal of the metal oxide semiconductor layer includes a group of II-VI elements and compounds thereof.
  • the metal semiconductor layer is further doped with one or more elements selected from the group consisting of alkaline earth metals, Group IIIA, Group VA, Group VIA, or transition metals.
  • a photoresist layer 14 having a plurality of thicknesses is formed on the semiconductor layer 13, wherein the thickness of the photoresist layer 14 above the gate pattern 11 is greater than the gate.
  • the step of forming the photoresist layer 14 having a plurality of thicknesses comprises: forming a photosensitive material layer on the semiconductor layer 13, and exposing the photosensitive material layer using a halftone mask The process, as well as a development process.
  • the step of forming the photoresist layer 14 having a plurality of thicknesses comprises: forming a photosensitive material layer on the semiconductor layer 13, and performing an exposure process on the photosensitive material layer using a gray tone mask And performing a development process.
  • a portion of the semiconductor layer 13 is removed with the photoresist layer 14 as a mask to form a semiconductor pattern 13'.
  • the photoresist layer 14 is subjected to a dry etching process (such as plasma etching) to remove the thickness of the photoresist layer 14 located above both sides of the gate pattern 11.
  • a dry etching process such as plasma etching
  • a portion of the semiconductor pattern 13' exposed from the photoresist layer 14' is electrically conductive by a conductor forming process, at which time the semiconductor pattern 13' of the photoresist layer 14' is exposed.
  • the conductor layer 13A is formed by a conductor process.
  • the surface of the semiconductor layer 13 is treated with a gas such as H 2 , NH 3 , CF 4 , SF 6 , He, Ar, N 2 or the like, or deposited on the surface of the semiconductor layer 13 and the surface of the substrate 10 by chemical vapor deposition.
  • the interlayer dielectric achieves the effect of conductorization.
  • the manufacturing method S1 of the active array switch includes the following steps:
  • Step S101 forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern;
  • Step S102 forming a gate insulating layer on the substrate to cover the gate pattern
  • Step S103 forming a semiconductor layer on the gate insulating layer
  • Step S104 forming a photoresist layer having a plurality of thicknesses on the semiconductor layer, wherein a thickness of the photoresist layer above the gate pattern is greater than a light above the two sides of the gate pattern The thickness of the resist layer;
  • Step S105 removing a portion of the semiconductor layer by using the photoresist layer as a mask to form a semiconductor pattern
  • Step S106 performing a dry etching process on the photoresist layer to remove the photoresist layer located on both sides of the gate pattern a thickness, and leaving a remaining thickness of the photoresist layer over the gate pattern after dry etching still covering a portion of the semiconductor pattern;
  • Step S107 Conducting a portion of the semiconductor pattern exposed from the photoresist layer to be a conductor layer by a conducting process
  • Step S108 removing all the photoresist layers above the gate pattern
  • Step S109 forming a second metal layer on the semiconductor pattern, the conductor layer and the gate insulating layer, and patterning the second metal layer into a source and a drain.
  • Another embodiment of the present application may also be formed on the source 15, the drain 16, the semiconductor pattern 13', and the conductor layer 13A and the gate insulating layer 12 as shown in FIG. A passivation layer 17.
  • the semiconductor layer 13' and the conductor layer 13A are covered with an insulating material layer 18, and the insulating material layer 18 may be an inorganic insulating material (such as silicon oxide or Silicon nitride) is an organic insulating material such as polymethyl methacrylate or polyvinyl phenol to protect the semiconductor pattern 13' and the conductor layer 13A.
  • an inorganic insulating material such as silicon oxide or Silicon nitride
  • organic insulating material such as polymethyl methacrylate or polyvinyl phenol to protect the semiconductor pattern 13' and the conductor layer 13A.
  • the present application provides a method S2 for manufacturing an active array switch as shown in FIG. 5, including the following steps:
  • Step S201 forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern
  • Step S202 forming a gate insulating layer on the substrate to cover the gate pattern
  • Step S203 forming a semiconductor layer on the gate insulating layer
  • Step S204 forming an insulating material layer on the semiconductor layer
  • Step S205 forming a photosensitive material layer on the insulating material layer
  • Step S206 performing an exposure process on the photosensitive material layer using a photomask
  • Step S207 performing a developing process to form the photosensitive material layer to form a photoresist layer having a plurality of thicknesses, wherein a thickness of the photoresist layer above the gate pattern is greater than a side of the gate pattern The thickness of the photoresist layer;
  • Step S208 removing a portion of the semiconductor layer to form a semiconductor pattern
  • Step S209 performing a dry etching process on the photoresist layer, removing a thickness of the photoresist layer above both sides of the gate pattern, leaving the first photoresist above the gate pattern The layer covers a portion of the semiconductor pattern;
  • Step S210 Conducting a portion of the semiconductor pattern exposed from the photoresist layer to be a conductor layer by a conducting process
  • Step S211 removing all the photoresist layers above the gate pattern
  • Step S212 forming a second metal layer on the semiconductor pattern, the conductor layer and the gate insulating layer, and patterning the second metal layer to form a source and a drain;
  • Step S213 forming a passivation layer on the source, the drain, the semiconductor pattern and the gate insulating layer.
  • the Gate (gate) and the Source/Drain (source and drain) electrodes are not overlapped, and the process is processed by the conductor. Conducting the semiconductor pattern 13' to thereby reduce the impedance of the source/Drain (source drain) and the TFT channel, and ensuring the on-state current while greatly reducing the parasitic capacitance of the active array switch.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Thin Film Transistor (AREA)

Abstract

主动阵列开关的制造方法，包括：于基板(10)上形成栅极图形(11)、栅极绝缘层(12)以及半导体层(13)；于半导体层(13)上形成一光阻层(14)，移除部分半导体层(13)，以形成半导体图形(13')；对光阻层(14)进行干式蚀刻制程，使只有栅极图形(11)中间上方留下来的光阻层(14')仍覆盖部分半导体图形(13')；利用导体化制程对半导体图形(13')自光阻层(14')所露出的部分进行导体化；移除栅极图形(11)中间上方的全部光阻层(14')并形成一源极(15)和一漏极(16)。

Description

主动阵列开关的制造方法 技术领域
本申请涉及一种主动阵列开关的制造方法，特别是涉及一种利用半导体层导体化以保持开态电流的主动阵列开关的制造方法。
背景技术
驱动显示面板的主动阵列开关半导体层目前主要有非晶硅(a-Si)，氧化物(Oxide)和多晶硅(Poly-Si)等。相对于非晶硅，氧化物半导体具有较高的迁移率，较低的漏电；虽多晶硅主动阵列开关迁移率更高，但其成本较高且不合适于目前主流产品的生产线。
氧化物半导体主动阵列开关常用的结构有ESL(蚀刻阻挡)，BCE(背沟道蚀刻)，Co-planner Self-Align Top Gate(共平面顶栅自对准型)以及Dual Gate(双栅机)等结构。其中Co-planner Self-Align Top Gate主动阵列开关制程难度较大，而Dual Gate主动阵列开关寄生电容较大，因此在主动阵列开关平板显示应用中，以ESL(蚀刻阻挡)和BCE(背沟道蚀刻)较为常见，但BCE(背沟道蚀刻)结构又具有省一道光罩的优点，是未来发展的重点。
然而对于BCE结构，为了保证一定的迁移率，Gate(栅极)与Source/Drain(源漏极)电极往往会有重迭(Overlap)区域，这些区域的Gate(栅极)与Source/Drain(源漏极)电极会形成寄生电容，不利于大尺寸和高动态显示；但若减小寄生电容，使Gate(栅极)与Source/Drain(源漏极)电极无重迭区域(甚至产生间隙Offset)，则会造成TFT开态电流减小，迁移率降低。
发明内容
为了解决上述技术问题，本申请的目的在于提供一种主动阵列开关的制造方法，特别是涉及一种利用半导体层导体化以保持开态电流的主动阵列开关的制造方法。
近年来，由于半导体制程技术的进步，主动阵列开关的制造越趋容易、快速。主动阵列开关广泛应用于诸如计算机芯片、手机芯片或是主动阵列开关液晶显示器(thin film transistor liquid crystal displayer，TFT LCD)等电子产品中。以主动阵列开关液晶显示器为例，主动阵列开关作为储存电容(storage capacitor)充电或放电的开关。
一般而言，主动阵列开关依照半导体层的材料可分为非晶硅主动阵列开关(Amorphous Silicon Transistor)以及多晶硅主动阵列开关(Low Temperature Polycrystalline Transistor)。然而，为了因应市场对于液晶显示器的需求增加，新的主动阵列开关技术研发也有更多的投入。以BCE结构为例，为了保证一定的迁移率，Gate(栅极)与Source/Drain(源漏极)电极往往会有重迭(Overlap)区域，这些 区域的Gate(栅极)与Source/Drain(源漏极)电极会形成寄生电容，不利于大尺寸和高动态显示；但若减小寄生电容，使Gate(栅极)与Source/Drain(源漏极)电极无重迭区域(甚至产生间隙Offset)，则会造成TFT开态电流减小，迁移率降低。
因此本申请提供了一种主动阵列开关的制造方法，包括下列步骤：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；于所述栅极绝缘层上形成一半导体层；于所述半导体层上形成一具有多个厚度的光阻层，其中位于所述栅极图形上方的所述光阻层的厚度大于位于所述栅极图形两侧上方的所述光阻层的厚度；以所述光阻层为罩幕，移除部分所述半导体层，以形成一半导体图形；对所述光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述光阻层的厚度，并使位于所述栅极图形上方的所述光阻层干式蚀刻后留下来的剩余厚度仍覆盖部分所述半导体图形；利用导体化制程对所述半导体图形自所述光阻层所露出的部分进行导体化成为一导体层；移除所述栅极图形上方的全部所述光阻层；以及于所述半导体图形、所述导体层和所述栅极绝缘层上形成一第二金属层，并图案化所述第二金属层成一源极和一漏极。
在本申请的一实施例中，形成所述具有多个厚度的光阻层的步骤包括：于所述半导体层上形成一感光材料层，使用一半色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
在本申请的一实施例中，形成所述具有多个厚度的光阻层的步骤包括：于所述半导体层上形成一感光材料层，使用灰色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
在本申请的一实施例中，所述半导体层为金属氧化物半导体层，所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
在本申请的一实施例中，所述金属半导体层更掺杂选自碱土金属、IIIA族、VA族、VIA族或过渡金属所组成的族群的一或多个元素。
在本申请的一实施例中，于所述源极、所述漏极、所述半导体图形和所述栅极绝缘层上形成一钝化层。
在本申请的一实施例中，于所述半导体层与所述光阻层之间形成一绝缘材料层。
在本申请的上述实施例中，所述绝缘材料层为无机绝缘材料层(如氧化硅或氮化硅)或有机绝缘材料层(如聚甲基丙烯酸甲酯或聚乙烯酚)。
本申请的目的及解决其技术问题还可采用以下技术措施进一步实现。本申请提供了一种主动阵列开关的制造方法，其中，包括下列步骤：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；于所述栅极绝缘层上形成一半导体层；于所述半导体层上形成一绝缘材料层；于所述绝缘材料层上形成一感光材料层；使 用一光罩对所述感光材料层进行一曝光制程；进行一显影制程使所述感光材料层形成一具有多个厚度的光阻层，其中位于所述栅极图形上方的所述光阻层的厚度大于位于所述栅极图形两侧上方的所述光阻层的厚度；移除部分所述半导体层，以形成一半导体图形；对所述光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；利用导体化制程对所述半导体图形自所述光阻层所露出的部分进行导体化成为一导体层；移除所述栅极图形上方的全部所述光阻层；于所述半导体图形、所述导体层和所述栅极绝缘层上形成一第二金属层，并图案化所述第二金属层，以形成一源极和一漏极；以及于所述源极、所述漏极、所述半导体图形和所述栅极绝缘层上形成一钝化层。
经过本申请的改进之后，在半导体的BCE结构主动阵列开关中，使Gate(栅极)与Source/Drain(源漏极)电极无重迭(Overlap)区域，制程中通过导体化处理使半导体层导体化进而使Source/Drain(源漏极)与TFT沟道的阻抗变小，在大大减小主动阵列开关寄生电容的同时保证开态电流。
附图说明
图1A是栅极与源漏极有重迭区域结构示意图。
图1B是栅极与源漏极无重迭区域结构示意图。
图2A是本申请实施例所述半导体的成膜示意图。
图2B是本申请实施例所述形成光阻层示意图。
图2C是本申请实施例所述形成半导体图形示意图。
图2D是本申请实施例所述进行干式蚀刻制程示意图。
图2E是本申请实施例所述导体化制程示意图。
图2F是本申请实施例所述移除全部光阻层示意图。
图2G是本申请一实施例所述主动阵列开关的制造方法流程图。
图3是本申请另一实施例形成钝化层结构示意图。
图4是本申请另一实施例形成绝缘材料层结构示意图。
图5是本申请另一实施例所述主动阵列开关的制造方法流程图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同 标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在……上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定申请目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种主动阵列开关的制造方法，其具体实施方式、结构、特征及其功效，详细说明如后。
本申请是提供一种主动阵列开关的制造方法，使半导体层导体化以使不形成重迭区域的源漏极间阻抗变小，在减小主动阵列开关寄生电容的同时保证开态电流。本申请提出一种主动阵列开关的制造方法，其包括下列步骤。
敬请参阅图1A至图1B，图1A为栅极与源漏极有重迭区域结构示意图，图1B为栅极与源漏极无重迭区域结构示意图。如图1A及图1B所示，首先，于基板10上形成多个栅极图形11。然后，于基板10上形成栅绝缘层12，以覆盖栅极图形11。接着，于栅绝缘层12上形成半导体层13并移除部分半导体层13，以形成半导体图形13′。而后，于半导体图形13′上形成源极15与漏极16。
其中，图1A的栅极图形11与源极15和漏极16具有一重迭区域(Overlap，OL)，在此一重迭区域OL间会形成寄生电容，不利于大尺寸和高动态显示，但移除重迭区域OL如图1B所示甚至存在一间隙OS时，虽可减小寄生电容，但这种方式会形成源漏极间的阻抗变大，进而使得主动阵列开关的开态电流减小，降低其迁移率。
因此，本申请即是在移除重迭区域OL减小寄生电容的前提下，将半导体图形13′导体化，进而使得源漏极间的阻抗降低，让主动阵列开关在寄生电容减小的情形下仍可保持一定的开态电流以及迁移率。
敬请参阅图2A至图2G，本申请提供的一种主动阵列开关1的制造方法首先如图2A所示，于一基板10上形成一第一金属层，并图案化所述第一金属层成一栅极图形11，再于所述基板10上形成一栅极绝缘层12，以覆盖所述栅极图形11，然后于所述栅极绝缘层12上形成一半导体层13。
在一实施例中，所述半导体层13为金属氧化物半导体层，所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
在上述实施例中，所述金属半导体层更掺杂选自碱土金属、IIIA族、VA族、VIA族或过渡金属所组成的族群的一或多个元素。
接下来如图2B所示，于所述半导体层13上形成一具有多个厚度的光阻层14，其中所述栅极图形11中间上方的所述光阻层14的厚度大于所述栅极图形11两侧上方的所述光阻层14的厚度。
在一实施例中，形成所述具有多个厚度的光阻层14的步骤包括：于所述半导体层13上形成一感光材料层，使用一半色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
在一实施例中，形成所述具有多个厚度的光阻层14的步骤包括：于所述半导体层13上形成一感光材料层，使用灰色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
接下来如图2C所示，以所述光阻层14为罩幕，移除部分所述半导体层13，以形成一半导体图形13′。
接下来如图2D所示，对所述光阻层14进行干式蚀刻制程(如电浆蚀刻)，移除位于所述栅极图形11两侧上方的所述光阻层14的厚度，并使位于所述栅极图形11中间上方的所述光阻层14干式蚀刻后留下来的剩余厚度(光阻层14′)仍覆盖部分所述半导体图形13′。
接下来如图2E所示，利用导体化制程对所述半导体图形13′自所述光阻层14′所露出的部分进行导体化，此时露出所述光阻层14′的半导体图形13′经导体化制程形成导体化的导体层13A。如运用H2，NH3，CF4，SF6，He，Ar，N2等气体对半导体层13的表面进行处理，或者于所述半导体层13表面及基板10表面采用化学气相沉积的方法沉积层间介质达到导体化的效果。
最后则是如图2F所示，移除所述栅极图形11中间上方的全部所述光阻层14′；以及于所述半导体图形13′、所述导体层13A和所述栅极绝缘层12上形成一第二金属层，并图案化所述第二金属层成一源极15和一漏极16。此时，于所述源极15和所述漏极16间存在有半导体图形13′以及导体层13A，因此藉由所述导体层13A的导体性质，可使所述源极15和所述漏极16间的阻抗变小，进而保持一定的开态电流与迁移率。综合上述各个步骤，则如图2G的流程图所示，所述主动阵列开关的制造方法S1包括下列步骤：
步骤S101：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
步骤S102：于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
步骤S103：于所述栅极绝缘层上形成一半导体层；
步骤S104：于所述半导体层上形成一具有多个厚度的光阻层，其中位于所述栅极图形上方的所述光阻层的厚度大于位于所述栅极图形两侧上方的所述光阻层的厚度；
步骤S105：以所述光阻层为罩幕，移除部分所述半导体层，以形成一半导体图形；
步骤S106：对所述光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述光阻层 的厚度，并使位于所述栅极图形上方的所述光阻层干式蚀刻后留下来的剩余厚度仍覆盖部分所述半导体图形；
步骤S107：利用导体化制程对所述半导体图形自所述光阻层所露出的部分进行导体化成为一导体层；
步骤S108：移除所述栅极图形上方的全部所述光阻层；以及
步骤S109：于所述半导体图形、所述导体层和所述栅极绝缘层上形成一第二金属层，并图案化所述第二金属层成一源极和一漏极。
本申请的另一实施例亦可如图3所示，于所述源极15、所述漏极16、所述半导体图形13′以及所述导体层13A和所述栅极绝缘层12上形成一钝化层17。
本申请的另一实施例亦可如图4所示，使半导体层13′以及所述导体层13A上覆盖有绝缘材料层18，所述绝缘材料层18可为无机绝缘材质(如氧化硅或氮化硅)或是有机绝缘材质(如聚甲基丙烯酸甲酯或聚乙烯酚)以保护半导体图形13′以及所述导体层13A。
同时，本申请的目的及解决其技术问题还可采用以下技术措施进一步实现。本申请提供了一种如图5所示的主动阵列开关的制造方法S2，包括下列步骤：
步骤S201：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
步骤S202：于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
步骤S203：于所述栅极绝缘层上形成一半导体层；
步骤S204：于所述半导体层上形成一绝缘材料层；
步骤S205：于所述绝缘材料层上形成一感光材料层；
步骤S206：使用一光罩对所述感光材料层进行一曝光制程；
步骤S207：进行一显影制程使所述感光材料层形成一具有多个厚度的光阻层，其中位于所述栅极图形上方的所述光阻层的厚度大于位于所述栅极图形两侧上方的所述光阻层的厚度；
步骤S208：移除部分所述半导体层，以形成一半导体图形；
步骤S209：对所述光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；
步骤S210：利用导体化制程对所述半导体图形自所述光阻层所露出的部分进行导体化成为一导体层；
步骤S211：移除所述栅极图形上方的全部所述光阻层；
步骤S212：于所述半导体图形、所述导体层和所述栅极绝缘层上形成一第二金属层，并图案化所述第二金属层，以形成一源极和一漏极；以及
步骤S213：于所述源极、所述漏极、所述半导体图形和所述栅极绝缘层上形成一钝化层。
经过本申请的改进之后，在半导体的BCE结构主动阵列开关1中，使Gate(栅极)与Source/Drain(源极与漏极)电极无重迭(Overlap)区域，制程中通过导体化处理使半导体图形13′导体化进而使Source/Drain(源漏极)与TFT沟道的阻抗变小，在大大减小主动阵列开关寄生电容的同时保证开态电流。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。该用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种主动阵列开关的制造方法，包括下列步骤：
    于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
    于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
    于所述栅极绝缘层上形成一半导体层；
    于所述半导体层上形成一具有多个厚度的光阻层，其中位于所述栅极图形上方的所述光阻层的厚度大于位于所述栅极图形两侧上方的所述光阻层的厚度；
    移除部分所述半导体层，以形成一半导体图形；
    对所述光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；
    利用导体化制程对所述半导体图形自所述光阻层所露出的部分进行导体化成为一导体层；
    移除所述栅极图形上方的全部所述光阻层；以及
    于所述半导体图形、所述导体层和所述栅极绝缘层上形成一第二金属层，并图案化所述第二金属层，以形成一源极和一漏极。
  2. 如权利要求1所述的主动阵列开关的制造方法，其中，形成所述具有多个厚度的光阻层的步骤包括：于所述半导体层上形成一感光材料层。
  3. 如权利要求2所述的主动阵列开关的制造方法，其中，使用一半色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
  4. 如权利要求2所述的主动阵列开关的制造方法，其中，使用灰色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
  5. 如权利要求1所述的主动阵列开关的制造方法，其中，所述半导体层为金属氧化物半导体层。
  6. 如权利要求5所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
  7. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂碱土金属元素。
  8. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂IIIA族元素。
  9. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂VA族元素。
  10. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂VIA族 元素。
  11. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂选自过渡金属所组成的族群的一个元素。
  12. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂选自过渡金属所组成的族群的多个元素。
  13. 如权利要求1所述的主动阵列开关的制造方法，其中，于所述源极、所述漏极、所述半导体图形和所述栅极绝缘层上形成一钝化层。
  14. 如权利要求1所述的主动阵列开关的制造方法，其中，于所述半导体层与所述光阻层之间形成一绝缘材料层。
  15. 如权利要求14所述的主动阵列开关的制造方法，其中，所述绝缘材料层为无机绝缘材料层。
  16. 如权利要求15所述的主动阵列开关的制造方法，其中，所述无机绝缘材料层为氧化硅或氮化硅。
  17. 如权利要求14所述的主动阵列开关的制造方法，其中，所述绝缘材料层为有机绝缘材料层。
  18. 如权利要求17所述的主动阵列开关的制造方法，其中，所述有机绝缘材料层为聚甲基丙烯酸甲酯。
  19. 如权利要求17所述的主动阵列开关的制造方法，其中，所述有机绝缘材料层为聚乙烯酚。
  20. 一种主动阵列开关的制造方法，包括下列步骤：
    于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
    于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
    于所述栅极绝缘层上形成一半导体层；
    于所述半导体层上形成一绝缘材料层；
    于所述绝缘材料层上形成一感光材料层；
    使用一光罩对所述感光材料层进行一曝光制程；
    进行一显影制程使所述感光材料层形成一具有多个厚度的光阻层，其中位于所述栅极图形上方的所述光阻层的厚度大于位于所述栅极图形两侧上方的所述光阻层的厚度；
    移除部分所述半导体层，以形成一半导体图形；
    对所述光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；
    利用导体化制程对所述半导体图形自所述光阻层所露出的部分进行导体化成为一导体层；
    移除所述栅极图形上方的全部所述光阻层；
    于所述半导体图形、所述导体层和所述栅极绝缘层上形成一第二金属层，并图案化所述第二金 属层，以形成一源极和一漏极；以及
    于所述源极、所述漏极、所述半导体图形和所述栅极绝缘层上形成一钝化层。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020087662A1 (zh) * 2018-10-29 2020-05-07 惠科股份有限公司 显示装置
CN109671723A (zh) * 2018-12-20 2019-04-23 深圳市华星光电半导体显示技术有限公司 一种tft阵列基板
CN111477687A (zh) * 2020-04-26 2020-07-31 昆山龙腾光电股份有限公司 氧化物薄膜晶体管及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1677626A (zh) * 2004-03-29 2005-10-05 广辉电子股份有限公司 自对准式薄膜晶体管的制造方法
CN103383989A (zh) * 2013-03-25 2013-11-06 友达光电股份有限公司 像素结构的制造方法及其结构
CN105990449A (zh) * 2014-12-10 2016-10-05 中华映管股份有限公司 薄膜晶体管以及其制作方法
US9543330B1 (en) * 2015-07-24 2017-01-10 Chunghwa Picture Tubes, Ltd. Method of manufacturing a thin film transistor and a pixel structure

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100225098B1 (ko) * 1996-07-02 1999-10-15 구자홍 박막트랜지스터의 제조방법
TW508830B (en) * 2001-08-28 2002-11-01 Hannstar Display Corp Thin film transistor structure having four procedures of mask processing and the manufacturing method
TWI355553B (en) * 2007-10-30 2012-01-01 Au Optronics Corp Pixel structure and method for manufacturing the s
JP5291928B2 (ja) * 2007-12-26 2013-09-18 株式会社日立製作所 酸化物半導体装置およびその製造方法
CN101625977B (zh) * 2008-07-11 2011-08-31 台湾薄膜电晶体液晶显示器产业协会 薄膜晶体管的制造方法
KR101476817B1 (ko) * 2009-07-03 2014-12-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 트랜지스터를 갖는 표시 장치 및 그 제작 방법
JP2012169344A (ja) * 2011-02-10 2012-09-06 Sony Corp 薄膜トランジスタならびに表示装置および電子機器
CN102351528B (zh) * 2011-09-28 2013-07-10 华南理工大学 硼化镧掺杂的氧化物半导体材料及其应用
KR101960371B1 (ko) * 2012-02-29 2019-03-20 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
CN102790012A (zh) * 2012-07-20 2012-11-21 京东方科技集团股份有限公司 阵列基板的制造方法及阵列基板、显示装置
CN103021939B (zh) * 2012-11-30 2015-01-07 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
JP6264090B2 (ja) * 2013-07-31 2018-01-24 株式会社リコー 電界効果型トランジスタ、及び電界効果型トランジスタの製造方法
CN103715267A (zh) * 2013-12-30 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管、tft阵列基板及其制造方法和显示装置
KR102322015B1 (ko) * 2015-04-07 2021-11-05 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판의 제조 방법 및 그에 따라 제조된 박막 트랜지스터 어레이 기판
CN105226015B (zh) * 2015-09-28 2018-03-13 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1677626A (zh) * 2004-03-29 2005-10-05 广辉电子股份有限公司 自对准式薄膜晶体管的制造方法
CN103383989A (zh) * 2013-03-25 2013-11-06 友达光电股份有限公司 像素结构的制造方法及其结构
CN105990449A (zh) * 2014-12-10 2016-10-05 中华映管股份有限公司 薄膜晶体管以及其制作方法
US9543330B1 (en) * 2015-07-24 2017-01-10 Chunghwa Picture Tubes, Ltd. Method of manufacturing a thin film transistor and a pixel structure

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