US11043515B2 - Display substrate, manufacturing method thereof, and display device - Google Patents

Display substrate, manufacturing method thereof, and display device Download PDF

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US11043515B2
US11043515B2 US15/779,694 US201715779694A US11043515B2 US 11043515 B2 US11043515 B2 US 11043515B2 US 201715779694 A US201715779694 A US 201715779694A US 11043515 B2 US11043515 B2 US 11043515B2
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active layer
pattern
doped region
forming
thin film
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US20200312892A1 (en
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Shuang Sun
Kuanjun PENG
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks

Definitions

  • the present disclosure relates to the field of display technologies, and particularly to a display substrate, a manufacturing method thereof, and a display device.
  • Oxide technology and low-temperature polysilicon technology are widely used due to their own advantages. More specifically, an advantage of a low-temperature polysilicon transistor is having high electron mobility. However, at the same time, the low-temperature polysilicon transistor also has a disadvantage of large leakage current. An advantage of an oxide transistor is having relatively small leakage current. However, the oxide transistor has low electron mobility.
  • the oxide transistor and the low-temperature polysilicon transistor are both limited in practical applications due to their respective disadvantages. More specifically, the low-temperature polysilicon transistor has too large leakage current and is unapplicable to the display area.
  • a manufacturing method of a display substrate comprising: providing a substrate; and forming, on the substrate, a first thin film transistor including a first active layer and a second thin film transistor including a second active layer.
  • the second active layer includes a central area and doped regions located at two sides of the central area, respectively, and forming, on the substrate, a first thin film transistor including a first active layer and a second thin film transistor including a second active layer comprises: forming the first active layer and the doped regions by using a single mask.
  • the manufacturing method of a display substrate further comprises forming a first semiconductor pattern prior to forming the first active layer and the doped regions of the second active layer by using a single mask, the doped regions of the second active layer being formed by doping the first semiconductor pattern.
  • the doped region includes a first doped region and a second doped region, and the first doped region is located between the second doped region and the central area, and forming the first active layer and the doped regions by using a single mask comprises: performing a first doping process to the first semiconductor pattern to form the second doped region; and performing a second doping process to the first semiconductor pattern including the second doped region to form the first doped region.
  • performing a first doping process to the first semiconductor pattern to form the second doped region comprises: forming a second semiconductor thin film, the second semiconductor thin film covering the first semiconductor pattern; forming a photoresist layer on the second semiconductor thin film; exposing and developing the photoresist layer to form a first photoresist pattern and a second photoresist pattern, the first photoresist pattern corresponding to a position where the first active layer is located, the second photoresist pattern corresponding to positions where the central area and the first doped region are located; etching the second semiconductor thin film to form a first active layer and a second semiconductor pattern and expose a portion of the first semiconductor pattern, the second semiconductor pattern corresponding to positions where the central area and the first doped region are located; and doping the portion of the first semiconductor pattern exposed to form the second doped region.
  • performing a second doping process to the first semiconductor pattern including the second doped region to form the first doped region comprises: performing an ashing treatment on the second photoresist pattern to form a third photoresist pattern, the third photoresist pattern corresponding to a position where the central area is located, and doping the first semiconductor pattern a second time to form the first doped region.
  • the manufacturing method of a display substrate further comprises: after forming the first doped region, removing the third photoresist pattern.
  • forming the first active layer and the doped regions of the second active layer by using a single mask comprises: forming a second semiconductor thin film, the second semiconductor thin film covering the first semiconductor pattern; forming a photoresist layer on the second semiconductor thin film; exposing and developing the photoresist layer to form a first photoresist pattern and a second photoresist pattern, the first photoresist pattern corresponding to a position where the first active layer is located, the second photoresist pattern corresponding to a position where the central area is located; etching the second semiconductor thin film to form a first active layer and a second semiconductor pattern and expose a portion of the first semiconductor pattern, the second semiconductor pattern corresponding to a position where the central area is located; doping the portion of the first semiconductor pattern exposed to form the doped region; and removing the first photoresist pattern and the second photoresist pattern.
  • the manufacturing method of a display substrate further comprises: after forming the first active layer and the doped regions by using a single mask, forming a first source/drain pattern over the first active layer, and forming a second source/drain pattern over the second doped region; depositing a first insulating layer and a resin layer on the first source/drain pattern and the second source/drain pattern; and performing using a single mask to the first insulating layer and the resin layer to form a first through hole at a position corresponding to the first source/drain pattern in the first insulating layer and the resin layer, and form a second through hole at a position corresponding to the second semiconductor pattern in the first insulating layer and the resin layer to expose the second semiconductor pattern.
  • the manufacturing method of a display substrate further comprises: after forming the first through hole and the second through hole, forming a common electrode and removing the second semiconductor pattern by using a single mask.
  • forming a common electrode and removing the second semiconductor pattern by using a single mask comprises: depositing a common electrode material on the resin layer, and performing a patterning process to the common electrode material and the second semiconductor pattern on the central area and the first doped region to form the common electrode and remove the second semiconductor pattern.
  • the manufacturing method of a display substrate further comprises: after forming the first active layer and the doped regions of the second active layer by using a single mask, forming a first source/drain pattern on the first active layer, and forming a second source/drain pattern on the doped regions; depositing a first insulating layer and a resin layer on the first source/drain pattern and the second source/drain pattern; and performing using a single mask to the first insulating layer and the resin layer to form a first through hole at a position corresponding to the first source/drain pattern in the first insulating layer and the resin layer, and form a second through hole at a position corresponding to the second semiconductor pattern in the first insulating layer and the resin layer to expose the second semiconductor pattern.
  • the manufacturing method of a display substrate further comprises: after forming the first through hole and the second through hole, forming a common electrode and removing the second semiconductor pattern by using a single mask.
  • forming a common electrode and removing the second semiconductor pattern by using a single mask comprises: depositing a common electrode material on the resin layer, and performing a patterning process to the common electrode material and the second semiconductor pattern on the central area to form the common electrode and remove the second semiconductor pattern.
  • the manufacturing method of a display substrate further comprises: prior to forming the first semiconductor pattern, forming a first gate of the first thin film transistor and a second gate of the second thin film transistor on the substrate by using a single mask; and forming a gate insulating layer on the first gate and the second gate, the first semiconductor pattern being formed on the gate insulating layer.
  • a material of the first active layer includes a metal oxide
  • a material of the second active layer includes polysilicon
  • a display substrate comprising: a substrate; and a first thin film transistor and a second thin film transistor on the substrate, the first thin film transistor including a first active layer, and the second thin film transistor including a second active layer.
  • the second active layer includes a central area and doped regions located at two sides of the central area, respectively.
  • the first active layer and the doped regions are formed by using a single mask.
  • the first active layer is a metal oxide active layer and the second active layer is a polysilicon active layer.
  • the doped region includes a first doped region and a second doped region, the first doped region being located between the second doped region and the central area.
  • the second thin film transistor further includes a second source/drain pattern, the second source/drain pattern covering the second doped region.
  • the second thin film transistor further includes a second source/drain pattern, the second source/drain pattern covering the doped region.
  • the display substrate includes a display area and a peripheral area located around the display area, the first thin film transistor being located in the display area, and the second thin film transistor being located in the peripheral area.
  • a further embodiment of the present disclosure further provides a display device which may comprise the display substrate according to any of the preceding embodiments.
  • FIG. 1 is a schematic flow chart illustrating a manufacturing method of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram illustrating step S 1 in a manufacturing method according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram illustrating step S 2 in a manufacturing method according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram illustrating step S 3 in a manufacturing method according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram illustrating step S 41 in a manufacturing method according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram illustrating step S 43 in a manufacturing method according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram illustrating step S 44 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram illustrating step S 45 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram illustrating step S 46 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram illustrating step S 47 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram illustrating step S 48 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram illustrating step S 5 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram illustrating step S 6 in a manufacturing method according to an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram illustrating step S 7 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram illustrating step S 8 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram illustrating step S 9 in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram illustrating step S 10 in a manufacturing method according to an embodiment of the present disclosure.
  • transistors of top-gate structure are formed, and the gate is used as a mask for a doped region in the low-temperature polysilicon transistor.
  • the gate is used as a mask for a doped region in the low-temperature polysilicon transistor.
  • a method for manufacturing a display substrate comprises providing a substrate; and forming, on the substrate, a first thin film transistor including a first active layer and a second thin film transistor including a second active layer.
  • the second active layer includes a central area and doped regions located at two sides of the central area, respectively.
  • forming a first thin film transistor including a first active layer and a second thin film transistor including a second active layer on the substrate comprises forming the first active layer and the doped regions of the second active layer by using a single mask.
  • FIGS. 1 to 17 illustrate an example of a method for manufacturing a display substrate according to an embodiment of the disclosure.
  • the display substrate may comprise a substrate 1 , and a first thin film transistor and a second thin film transistor on the substrate 1 .
  • the first thin film transistor includes a first active layer 3
  • the second thin film transistor includes a second active layer 6 .
  • the second active layer 6 includes a central area 61 and doped regions located at two sides of the central area 61 , respectively.
  • the display substrate may be provided with a display area A and a peripheral area B around the display area A.
  • the first thin film transistor is located in the display area A, and the second thin film transistor is located in the peripheral area B.
  • the first active layer 3 may be, for example, a metal oxide active layer.
  • the second active layer 6 may be, for example, a polysilicon active layer.
  • An example of the method for manufacturing a display substrate according to an embodiment of the present disclosure may comprise the following steps.
  • a first gate 2 and a second gate 5 are formed on the substrate 1 by using a single mask.
  • the first gate 2 is located in the display area A
  • the second gate 5 is located in the peripheral area B.
  • “using a single mask” referred to in the embodiment of the disclosure means that only one mask plate is used to expose and develop the photoresist, and a corresponding pattern is formed by etching.
  • a gate insulating layer 8 is formed on the first gate 2 and the second gate 5 .
  • step S 3 a first semiconductor pattern 9 is formed.
  • step S 3 may comprise, for example, the steps of: depositing an amorphous silicon material layer on the gate insulating layer 8 ; performing a dehydrogenation process and an excimer laser annealing process to the amorphous silicon material layer to form a low-temperature polysilicon material layer; depositing a photoresist layer on the low-temperature polysilicon material layer; performing exposure and development processes to the photoresist layer; performing an etching process to an exposed low-temperature polysilicon material layer; and removing the photoresist layer that remains at the position corresponding to the second gate 5 to form the first semiconductor pattern 9 .
  • the first active layer of the first thin film transistor and the doped regions of the second active layer of the second thin film transistor are formed by using a single mask.
  • the doped regions of the second active layer may include a first doped region and a second doped region.
  • the first doped region is located between the second doped region and the central area.
  • step S 4 may specifically include the following steps.
  • a second semiconductor thin film 10 is formed.
  • the second semiconductor thin film 10 covers the first semiconductor pattern 9 .
  • the second semiconductor thin film 10 covers the gate insulating layer 8 and the first semiconductor pattern 9 on the gate insulating layer 8 , and the second active layer 6 may be formed based on the first semiconductor pattern.
  • step S 42 a photoresist layer is formed on the second semiconductor thin film 10 .
  • step S 43 referring to FIG. 6 , the photoresist layer is exposed and developed to form a first photoresist pattern 11 and a second photoresist pattern 12 .
  • the first photoresist pattern 11 corresponds to a position where the first active layer is located
  • the second photoresist pattern 12 corresponds to positions where the central area and the first doped region are located.
  • a portion of the second semiconductor thin film 10 is exposed after the photoresist layer is developed.
  • the first photoresist pattern 11 is located in the display area A
  • the second photoresist pattern 12 is located in the peripheral area B.
  • An orthographic projection of the second photoresist pattern 12 on the substrate 1 lies within an orthographic projection of the first semiconductor pattern 9 on the substrate 1 .
  • step S 44 referring to FIG. 7 , the second semiconductor thin film 10 is etched to form a first active layer pattern 31 and a second semiconductor pattern 101 , and expose a portion of the first semiconductor pattern 9 .
  • the second semiconductor pattern 101 corresponds to positions where the central area and the first doped region are located.
  • the exposed second semiconductor thin film 10 is etched. Since the projection of the second photoresist pattern 12 on the substrate 1 lies within the projection of the first semiconductor pattern 9 on the substrate 1 , the edge portion of the first semiconductor pattern 9 is exposed.
  • the edge portion of the first semiconductor pattern 9 can be regarded as a first to-be-doped region 13 .
  • step S 45 referring to FIG. 8 , the exposed portion of the first semiconductor pattern 9 is doped to form a second doped region 622 .
  • the exposed portion of the first semiconductor pattern 9 i.e., the first to-be-doped region 13
  • the exposed portion of the first semiconductor pattern 9 may be heavily doped to form the second doped region 622 .
  • step S 46 the second photoresist pattern 12 is subjected to an ashing treatment to form a third photoresist pattern 121 .
  • the third photoresist pattern 121 corresponds to a position where the central area is located.
  • the second photoresist pattern 12 is subjected to an ashing treatment so as to reduce the coverage area of the second photoresist pattern 12 , thereby forming a third photoresist pattern 121 .
  • An orthographic projection of the third photoresist pattern 121 on the substrate 1 lies within an orthographic projection of the doped region on the substrate 1 .
  • the orthographic projection of the doped region on the substrate 1 includes an orthographic projection of the second doped region 622 on the substrate 1 and an orthographic projection of a second to-be-doped region 14 of the first semiconductor pattern 9 on the substrate 1 .
  • step S 47 referring to FIG. 10 , the first semiconductor pattern 9 is doped a second time to form a first doped region 621 .
  • the second to-be-doped region 14 may be lightly doped to form the first doped region 621 . It can be understood that the doped region of the second active layer includes the first doped region 621 and the second doped region 622 .
  • step S 48 referring to FIG. 11 , the first photoresist pattern 11 and the third photoresist pattern 121 are removed. As shown in FIG. 11 , the first photoresist pattern 11 and the third photoresist pattern 121 are removed to form the first active layer 3 and expose the second semiconductor pattern 101 on the first semiconductor pattern 9 . It can be understood that the first photoresist pattern 11 and the third photoresist pattern 121 may not be removed simultaneously, for example, the first photoresist pattern 11 may be removed before step S 48 .
  • the first active layer 3 is made of, for example, indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the material of the first active layer 3 is not limited thereto. Other types of materials may also be used to form the first active layer 3 , which will not be described here.
  • step S 5 referring to FIG. 12 , a first source/drain pattern 4 is formed on the first active layer 3 , and a second source/drain pattern 7 is formed on the second doped region 622 .
  • the first source/drain pattern 4 includes a first source 41 and a first drain 42 .
  • Part of the first source 41 is located on the first active layer 3
  • part of the first drain 42 is located on the first active layer 3 .
  • the second source/drain pattern 7 includes a second source 71 and a second drain 72 .
  • Part of the second source 71 is located on the second doped region 622
  • part of the second drain 72 is located on the second doped region 622 .
  • the second semiconductor pattern 101 can prevent the first semiconductor pattern 9 from contacting the etching material for forming the first source/drain pattern 4 and the second source/drain pattern 7 , so that the first semiconductor pattern 9 can be protected when the source and the drain are being formed by etching.
  • a first insulating layer 15 and a resin layer 16 are deposited on the first source/drain pattern 4 and the second source/drain pattern 7 .
  • the first insulating layer 15 may be, for example, an interlayer dielectric layer.
  • step S 7 referring to FIG. 14 , using a single mask is performed to the first insulating layer 15 and the resin layer 16 , to form a first through hole at a position corresponding to the first source/drain pattern 4 in the first insulating layer 15 and the resin layer 16 , and form a second through hole 18 at a position corresponding to the second semiconductor pattern 101 in the first insulating layer 15 and the resin layer 16 , thereby exposing the second semiconductor pattern 101 .
  • performing using a single mask to the first insulating layer 15 and the resin layer 16 may comprise: depositing a photoresist layer on the resin layer 16 ; exposing and developing the photoresist layer using a mask plate; then etching the first insulating layer 15 and the resin layer 16 to form the first through hole 17 and the second through hole 18 in the first insulating layer 15 and the resin layer 16 .
  • the first through hole 17 exposes part of the first drain 42
  • the second through hole 18 exposes the second semiconductor pattern 101 on the first semiconductor pattern 9 .
  • step S 8 referring to FIG. 15 , a common electrode 19 is formed and the second semiconductor pattern 101 is removed by using a single mask.
  • step S 8 may comprise: depositing a common electrode material (e.g., ITO) on the resin layer 16 , and performing a patterning process to the common electrode material and the second semiconductor pattern 101 on the central area 61 and the first doped region 621 , to form the common electrode 19 and remove the second semiconductor pattern 101 .
  • a common electrode material e.g., ITO
  • the second semiconductor pattern 101 on the central area 61 and the first doped region 621 of the second active layer may also be etched away to form the common electrode 19 and expose the central area 61 and the first doped region 621 of the second active layer 6 .
  • the common electrode and the second semiconductor pattern 101 may be made of the same type of material (e.g., metal oxide), or may be made of different materials.
  • the common electrode material and the second semiconductor pattern can be etched away simultaneously by selection of the etching material.
  • step S 9 referring to FIG. 16 , a passivation layer material is deposited on the common electrode 19 and the resin layer 16 , and the passivation layer material is subjected to a patterning process to form a passivation layer 20 .
  • the first through hole is disposed in the passivation layer 20 .
  • step S 10 referring to FIG. 17 , a pixel electrode material is deposited on the passivation layer 20 and in the first through hole 17 , and the pixel electrode material is subjected to a patterning process to form a pixel electrode 21 .
  • the pixel electrode 21 is located on the passivation layer 20 and in the first through hole 17 to be connected to the first drain 42 via the first through hole 17 .
  • the first active layer 3 and the doped regions of the second active layer 6 are formed by using a single mask.
  • the second semiconductor pattern 101 on the second active layer 6 on the one hand, can serve as a mask plate for forming the doped regions of the second active layer 6 , and on the other hand, can prevent the etching material from contacting the second active layer 6 when the second source/drain pattern 7 is being formed.
  • the second semiconductor pattern 101 on the second active layer 6 may be removed at the time of forming the common electrode 19 , thereby reducing the process complexity and the manufacturing cost.
  • the display substrate comprises a substrate 1 , and a first thin film transistor and a second thin film transistor on the substrate 1 .
  • the first thin film transistor includes a first active layer 3
  • the second thin film transistor includes a second active layer 6 .
  • the second active layer 6 includes a central area 61 and doped regions located at two sides of the central area 61 , respectively.
  • the first thin film transistor and the second thin film transistor may both be bottom-gate thin film transistors.
  • both the first thin film transistor and the second thin film transistor may also be top-gate thin film transistors.
  • one of the first thin film transistor and the second thin film transistor is a top-gate thin film transistor, and the other is a bottom-gate thin film transistor.
  • the first active layer 3 and the doped regions of the second active layer 6 may be formed by using a single mask.
  • the first active layer 3 may be a metal oxide active layer
  • the second active layer 6 may be a polysilicon active layer.
  • the doped regions may include a first doped region 621 and a second doped region 622 .
  • the first doped region 621 is located between the second doped region 622 and the central area 61 .
  • the second thin film transistor further includes a second source/drain pattern 7 , and the second source/drain pattern 7 covers the second doped region 622 .
  • the display substrate may be provided with a display area A and a peripheral area B around the display area A.
  • the first thin film transistor is located in the display area A, and the second thin film transistor is located in the peripheral area B.
  • the display substrate according to this embodiment may be manufactured using the method for manufacturing a display substrate described above, which will not be described here.
  • the doped region of the second thin film transistor does not include a first doped region and a second doped region, but only includes one type of doped region. Accordingly, steps S 4 and S 5 for this further method for manufacturing a display substrate are different.
  • step S 4 may comprise the following steps.
  • step S 41 a second semiconductor thin film is formed, and the second semiconductor thin film covers the first semiconductor pattern.
  • step S 42 a photoresist layer is formed on the second semiconductor thin film.
  • step S 43 the photoresist layer is exposed and developed to form a first photoresist pattern and a second photoresist pattern.
  • the first photoresist pattern corresponds to a position where the first active layer is located
  • the second photoresist pattern corresponds to a position where the central area is located.
  • step S 44 the second semiconductor thin film is etched to form a first active layer pattern and a second semiconductor pattern, and expose a portion of the first semiconductor pattern.
  • the second semiconductor pattern corresponds to a position where the central area is located.
  • step S 45 the exposed portion of the first semiconductor pattern is doped to form a doped region.
  • step S 46 the first photoresist pattern and the second photoresist pattern are removed.
  • step S 4 of this method for manufacturing a display substrate since it is not necessary to form two types of doped regions (the first doped region and the second doped region), there is no need to perform ashing to the second photoresist pattern, and there is no need to dope the first semiconductor pattern a second time. That is, the doped region is formed only by performing doping once.
  • step S 5 it may specifically comprise forming a first source/drain pattern on the first active layer, and forming a second source/drain pattern on the doped region. That is, in comparison with step S 5 in the method for manufacturing a display substrate described previously, the second source/drain pattern is formed on the doped region instead of being formed on the second doped region.
  • the first active layer and the doped region of the second active layer are formed by using a single mask.
  • the second semiconductor pattern on the second active layer on the one hand, can serve as a mask plate for forming the doped region of the second active layer, and on the other hand, can prevent the etching material from contacting the second active layer when the second source/drain pattern is being formed.
  • the second semiconductor pattern on the second active layer may be removed at the time of forming the common electrode, thereby reducing the process complexity and the manufacturing cost.
  • a display substrate having a similar structure to the display substrate described previously except that the doped region of the second thin film transistor does not include a first doped region and a second doped region, but only includes one type of doped region. Therefore, the second source/drain pattern included by the second thin film transistor covers the doped region instead of covering the second doped region.
  • the display substrate according to this embodiment may be manufactured using the above-mentioned further method for manufacturing a display substrate, which will not be described here.
  • a display panel may comprise the above display substrate. It can be understood that the display panel according to this embodiment may further comprise a counter substrate opposite to the display substrate.
  • a display device may comprise the above display substrate.
  • the display device may be any product or component having a display function such as a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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CN109863598A (zh) * 2017-09-29 2019-06-07 京东方科技集团股份有限公司 阵列基板、显示装置和制造阵列基板的方法
US10559696B2 (en) 2017-10-11 2020-02-11 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Hybrid CMOS device and manufacturing method thereof
CN107768309B (zh) * 2017-10-11 2019-12-10 深圳市华星光电半导体显示技术有限公司 混合型cmos器件及其制作方法
CN110137182A (zh) * 2019-04-04 2019-08-16 惠科股份有限公司 一种阵列基板及其制造方法和显示面板

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