CN107799521A - Cmos反相器及阵列基板 - Google Patents

Cmos反相器及阵列基板 Download PDF

Info

Publication number
CN107799521A
CN107799521A CN201710937121.2A CN201710937121A CN107799521A CN 107799521 A CN107799521 A CN 107799521A CN 201710937121 A CN201710937121 A CN 201710937121A CN 107799521 A CN107799521 A CN 107799521A
Authority
CN
China
Prior art keywords
film transistor
layer
type
gate insulation
cmos inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710937121.2A
Other languages
English (en)
Inventor
周星宇
徐源竣
任章淳
吴元均
吕伯彦
杨伯儒
陈昌东
刘川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN201710937121.2A priority Critical patent/CN107799521A/zh
Priority to PCT/CN2017/110989 priority patent/WO2019071702A1/zh
Priority to US15/743,990 priority patent/US20200152800A1/en
Publication of CN107799521A publication Critical patent/CN107799521A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种CMOS反相器及阵列基板。该CMOS反相器包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：μP；其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，和分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。

Description

CMOS反相器及阵列基板
技术领域
本发明涉及显示技术领域，尤其涉及一种CMOS反相器及阵列基板。
背景技术
随着显示技术的发展，包括液晶显示装置(Liquid Crystal Display，LCD)及有机发光二极管显示装置(Organic Light Emitting Display，OLED)在内的平面显示装置已经成为最为常见的显示装置，被广泛地应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品之中。
CMOS(Complementary Metal Oxide Semiconductor，互补式金属氧化物半导体)反相器是平面显示装置中经常使用的一器件，主要作用为接收一输入信号，并输出与输入信号逻辑相反的一输出信号。
现有的CMOS反相器通常包括一个N型薄膜晶体管(Thin Film Transistor，TFT)和一个P型薄膜晶体管，理想情况希望该N型薄膜晶体管和P型薄膜晶体管均为金属氧化物薄膜晶体管，例如铟镓锌氧化物(IGZO)TFT，然而，IGZOTFT只表现为N型单极性半导体，P型半导体的缺失使得基于IGZO TFT的逻辑电路设计面临难题。
现有技术关于IGZO TFT逻辑电路设计的研究可大体分为两类：第一类是仅使用IGZO TFT组成伪CMOS(Pseduo-CMOS)实现非门(即反相器)，在伪CMOS设计时，两个IGZO TFT要有不同的阈值电压，这就要求在同一块样品上同时制备出耗尽型(Depletion mode)和增强型(Enhancement mode)IGZO TFT。那么在伪CMOS制备时，诸如双栅结构、双层主动层结构和对IGZO TFT额外光照等方法就被发明出来，然而即使在这些工艺改进过的反相器中，伪CMOS的静态功耗大和噪声容限小的问题依旧未能解决。第二类就是采用混合型CMOS设计，也即P型薄膜晶体管由不同于金属氧化物的其他半导体材料来实现。在以往的混合CMOS设计中，P型薄膜晶体管使用的是二维碳纳米管(CNT)材料或有机半导体材料。然而CNT材料的制备中总是会有部分被金属化，而有机半导体TFT的迁移率又很低，且对环境中水氧敏感，使得现有的混合型CMOS中P型薄膜晶体管的稳定性很差。
发明内容
本发明的目的在于提供一种CMOS反相器，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
本发明的目的还在于提供一种阵列基板，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
为实现上述目的，本发明提供了一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；
所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：
其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，和分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率。
所述P型低温多晶硅薄膜晶体管的栅极和N型金属氧化物薄膜晶体管的栅极均接入输入信号；
所述P型低温多晶硅薄膜晶体管的源极和N型金属氧化物薄膜晶体管的源极中的一个接地，所述P型低温多晶硅薄膜晶体管的源极和N型金属氧化物薄膜晶体管的源极中的另一个接入电源电压；
所述P型低温多晶硅薄膜晶体管的漏极和N型金属氧化物薄膜晶体管的漏极均输出输出信号。
所述CMOS反相器包括：基板、形成于所述基板上的第一半导体层、覆盖所述第一半导体层和基板的第一栅绝缘层、设于所述第一栅绝缘层上的第一金属层、覆盖所述第一金属层和第一栅绝缘层的第二栅绝缘层、形成于所述第二栅绝缘层上的第二半导体层、形成于所述第二半导体层和第二栅绝缘层上的第二金属层。
所述第一半导体层为所述P型低温多晶硅薄膜晶体管的半导体层，所述第二半导体层为所述N型金属氧化物薄膜晶体管的半导体层。
所述第一金属层包括：间隔分布的第一栅极和第二栅极，所述第一栅极正对所述第一半导体层设置，所述第二栅极正对所述第二半导体层设置；
所述第一栅极为P型低温多晶硅薄膜晶体管的栅极，所述第二栅极为N型金属氧化物薄膜晶体管的栅极。
所述第二栅绝缘层上形成有贯穿所述第一栅绝缘层和第二栅绝缘层的第一过孔和第二过孔，所述第一过孔和第二过孔分别暴露出所述第一半导体层的两端；
所述第二金属层包括：间隔分布的第一源极和第二源极、以及位于第一源极和第二源极之间的第一漏极和第二漏极；所述第一源极和第一漏极分别通过所述第一过孔和第二过孔与所述第一半导体层的两端接触，所述第二源极和第二漏极分别与所述第二半导体层的两端接触，所述第一漏极和第二漏极接触；
所述第一源极和第一漏极为P型低温多晶硅薄膜晶体管的源极和漏极，所述第二源极和第二漏极为N型金属氧化物薄膜晶体管的源极和漏极。
在所述第一半导体层与基板之间以及第一栅绝缘层与基板之间还设有缓冲层，在所述第二源极和第二漏极之间的第二半导体层上还设有刻蚀阻挡层。
所述第一栅绝缘层和第二栅绝缘层的材料均为氧化硅或氮化硅中的一种或二者的组合，所述第一金属层和第二金属层的材料均为钼、铝、铜、及钛中的一种或多种的组合。
所述N型金属氧化物薄膜晶体管的半导体层的材料为IGZO或IZO。
本发明还提供阵列基板，包括上述的CMOS反相器。
本发明的有益效果：本发明提供一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，和分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率，通过使得P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足上述公式，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。本发明还提供一种阵列基板，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的CMOS反相器的结构图；
图2为本发明的CMOS反相器的等效电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管10和N型金属氧化物薄膜晶体管20；
所述P型低温多晶硅薄膜晶体管10和N型金属氧化物薄膜晶体管20满足以下公式：
其中，Cn和CP分别为N型金属氧化物薄膜晶体管20的栅绝缘层电容和P型低温多晶硅薄膜晶体管10的栅绝缘层电容，和分别为N型金属氧化物薄膜晶体管20的沟道宽长比和P型低温多晶硅薄膜晶体管10的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管20的迁移率和P型低温多晶硅薄膜晶体管10的迁移率。
具体地，如图2所示，本发明的CMOS反相器中，所述P型低温多晶硅薄膜晶体管10的栅极和N型金属氧化物薄膜晶体管20的栅极均接入输入信号Vin；所述P型低温多晶硅薄膜晶体管10的源极接入电源电压Vdd，所述N型金属氧化物薄膜晶体管20的源极接地；所述P型低温多晶硅薄膜晶体管10的漏极和N型金属氧化物薄膜晶体管20的漏极均输出输出信号Vout。
工作时，当所述输入信号Vin为高电位时，所述N型金属氧化物薄膜晶体管20打开，所述输出信号Vout通过所述N型金属氧化物薄膜晶体管20接地，输出信号Vout为低电位，当所述输入信号Vin为低电位时，所述P型低温多晶硅薄膜晶体管10打开，所述输出信号Vout输出电源电压Vdd，输出信号Vout为高电位。
详细地，在本发明的优选实施例中，所述CMOS反相器的详细结构如下，所述CMOS反相器包括：基板30、形成于所述基板30上的第一半导体层11、覆盖所述第一半导体层11和基板30的第一栅绝缘层12、设于所述第一栅绝缘层12上的第一金属层13、覆盖所述第一金属层13和第一栅绝缘层12的第二栅绝缘层18、形成于所述第二栅绝缘层18上的第二半导体层14、形成于所述第二半导体层14和第二栅绝缘层18上的第二金属层15。
进一步地，在上述实施例中，所述第一半导体层11为所述P型低温多晶硅薄膜晶体管10的半导体层，所述第二半导体层14为所述N型金属氧化物薄膜晶体管20的半导体层。
进一步地，所述第一金属层13包括：间隔分布的第一栅极131和第二栅极132，所述第一栅极131正对所述第一半导体层11设置，所述第二栅极132正对所述第二半导体层14设置；其中，所述第一栅极131为P型低温多晶硅薄膜晶体管10的栅极，所述第二栅极132为N型金属氧化物薄膜晶体管20的栅极。
进一步地，所述第二栅绝缘层18上形成有贯穿所述第一栅绝缘层12和第二栅绝缘层18的第一过孔141和第二过孔142，所述第一过孔141和第二过孔142分别暴露出所述第一半导体层11的两端；所述第二金属层14包括：间隔分布的第一源极151和第二源极152、以及位于第一源极151和第二源极152之间的第一漏极153和第二漏极154；所述第一源极151和第一漏极153分别通过所述第一过孔141和第二过孔142与所述第一半导体层11的两端接触，所述第二源极152和第二漏极154分别与所述第二半导体层14的两端接触，所述第一漏极153和第二漏极154接触；其中，所述第一源极151和第一漏极153为P型低温多晶硅薄膜晶体管10的源极和漏极，所述第二源极152和第二漏极154为N型金属氧化物薄膜晶体管20的源极和漏极。
值得一提的是，所述CMOS反相器在所述第一半导体层11与基板30之间以及第一栅绝缘层12与基板30之间还设有缓冲层16，在所述第二源极152和第二漏极154之间的第二半导体层14上还设有刻蚀阻挡层17。
优选地，所述第一栅绝缘层12和第二栅绝缘层14的材料均为氧化硅或氮化硅中的一种或二者的组合，所述第一金属层13和第二金属层15的材料均为钼、铝、铜、及钛中的一种或多种的组合。所述N型金属氧化物薄膜晶体管20的半导体层的材料为IGZO或IZO。
进一步地，本发明针对采用P型低温多晶硅薄膜晶体管10和N型金属氧化物薄膜晶体管20的CMOS反相器，提出了具体的设计准则：
按照此公式设计CMOS反相器，可以使P型薄膜晶体管和N型薄膜晶体管的特性更加匹配，保证P型薄膜晶体管和N型薄膜晶体管均工作于饱和区，达到更好的CMOS反相器效果。
需要说明的是，本发明的CMOS反相器采用低温多晶硅薄膜晶体管作为P型薄膜晶体管，金属氧化物薄膜晶体管作为N型薄膜晶体管，两种薄膜晶体管混合组成CMOS反相器，相比于仅采用刚性的低温多晶硅薄膜晶体管的CMOS反相器，本发明通过采用金属氧化物薄膜晶体管作为N型薄膜晶体管，能够使得CMOS反相器的延展性得到提升，从而使得CMOS反相器更胜任柔性电子产品的要求，且现有的仅采用低温多晶硅薄膜晶体管的CMOS反相器需要至少9次光刻和4次掺杂的复杂制作工艺，而本发明的CMOS反相器只用到6次光刻和1次掺杂即可完成制作，因此本发明相比仅采用低温多晶硅薄膜晶体管的CMOS反相器，还能够减少光刻和掺杂次数，简化制作工艺。而相比于传统的仅采用金属氧化物薄膜晶体管的伪CMOS反相器，本发明又可以减小静态功耗，增大噪声容限，保证CMOS反相器的制作品质。
基于上述的CMOS反相器，本发明还提供一种阵列基板，其包括上述的CMOS反相器，所述CMOS反相器的具体技术特征与上述CMOS反相器相同，在此不再赘述。
需要说明的是，本发明的阵列基板通过在同一基板同时制备了低温多晶硅薄膜晶体管以及金属氧化物薄膜晶体管，两者混合组成了CMOS反相器，其中，低温多晶硅薄膜晶体管作为P型薄膜晶体管，金属氧化物薄膜晶体管作为N型薄膜晶体管，相比于仅采用刚性的低温多晶硅薄膜晶体管的CMOS反相器，本发明通过采用金属氧化物薄膜晶体管作为N型薄膜晶体管，能够使得CMOS反相器的延展性得到提升，从而使得CMOS反相器更胜任柔性电子产品的要求，且现有的仅采用低温多晶硅薄膜晶体管的CMOS反相器需要至少9次光刻和4次掺杂的复杂制作工艺，而本发明的CMOS反相器只用到6次光刻和1次掺杂即可完成制作，在制作阵列基板时CMOS反相器的金属氧化物薄膜晶体管可以与阵列基板中像素阵列内的金属氧化物薄膜晶体管同时制作，因此本发明的阵列基板能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
综上所述，本发明提供一种CMOS反相器，包括：电性连接的P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管；所述P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足以下公式：其中，Cn和CP分别为N型金属氧化物薄膜晶体管的栅绝缘层电容和P型低温多晶硅薄膜晶体管的栅绝缘层电容，和分别为N型金属氧化物薄膜晶体管的沟道宽长比和P型低温多晶硅薄膜晶体管的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管的迁移率和P型低温多晶硅薄膜晶体管的迁移率，通过使得P型低温多晶硅薄膜晶体管和N型金属氧化物薄膜晶体管满足上述公式，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。本发明还提供一种阵列基板，能够提升CMOS反相器的性能，降低CMOS反相器的制作难度和生产成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种CMOS反相器，其特征在于，包括：电性连接的P型低温多晶硅薄膜晶体管(10)和N型金属氧化物薄膜晶体管(20)；
所述P型低温多晶硅薄膜晶体管(10)和N型金属氧化物薄膜晶体管(20)满足以下公式：
<mrow> <msub> <mi>C</mi> <mi>n</mi> </msub> <mfrac> <msub> <mi>W</mi> <mi>n</mi> </msub> <msub> <mi>L</mi> <mi>n</mi> </msub> </mfrac> <msub> <mi>&amp;mu;</mi> <mi>n</mi> </msub> <mo>=</mo> <msub> <mi>C</mi> <mi>P</mi> </msub> <mfrac> <msub> <mi>W</mi> <mi>P</mi> </msub> <msub> <mi>L</mi> <mi>P</mi> </msub> </mfrac> <msub> <mi>&amp;mu;</mi> <mi>P</mi> </msub> </mrow>
其中，Cn和CP分别为N型金属氧化物薄膜晶体管(20)的栅绝缘层电容和P型低温多晶硅薄膜晶体管(10)的栅绝缘层电容，和分别为N型金属氧化物薄膜晶体管(20)的沟道宽长比和P型低温多晶硅薄膜晶体管(10)的沟道宽长比，μn和μP分别为N型金属氧化物薄膜晶体管(20)的迁移率和P型低温多晶硅薄膜晶体管(10)的迁移率。
2.如权利要求1所述的CMOS反相器，其特征在于，所述P型低温多晶硅薄膜晶体管(10)的栅极和N型金属氧化物薄膜晶体管(20)的栅极均接入输入信号(Vin)；
所述P型低温多晶硅薄膜晶体管(10)的源极接入电源电压(Vdd)，N型金属氧化物薄膜晶体管(20)的源极接地，所述P型低温多晶硅薄膜晶体管(10)的漏极和N型金属氧化物薄膜晶体管(20)的漏极均输出输出信号(Vout)。
3.如权利要求1所述的CMOS反相器，其特征在于，包括：基板(30)、形成于所述基板(30)上的第一半导体层(11)、覆盖所述第一半导体层(11)和基板(30)的第一栅绝缘层(12)、设于所述第一栅绝缘层(12)上的第一金属层(13)、覆盖所述第一金属层(13)和第一栅绝缘层(12)的第二栅绝缘层(18)、形成于所述第二栅绝缘层(18)上的第二半导体层(14)、形成于所述第二半导体层(14)和第二栅绝缘层(18)上的第二金属层(15)。
4.如权利要求3所述的CMOS反相器，其特征在于，所述第一半导体层(11)为所述P型低温多晶硅薄膜晶体管(10)的半导体层，所述第二半导体层(14)为所述N型金属氧化物薄膜晶体管(20)的半导体层。
5.如权利要求4所述的CMOS反相器，其特征在于，所述第一金属层(13)包括：间隔分布的第一栅极(131)和第二栅极(132)，所述第一栅极(131)正对所述第一半导体层(11)设置，所述第二栅极(132)正对所述第二半导体层(14)设置；
所述第一栅极(131)为P型低温多晶硅薄膜晶体管(10)的栅极，所述第二栅极(132)为N型金属氧化物薄膜晶体管(20)的栅极。
6.如权利要求5所述的CMOS反相器，其特征在于，所述第二栅绝缘层(18)上形成有贯穿所述第一栅绝缘层(12)和第二栅绝缘层(18)的第一过孔(141)和第二过孔(142)，所述第一过孔(141)和第二过孔(142)分别暴露出所述第一半导体层(11)的两端；
所述第二金属层(14)包括：间隔分布的第一源极(151)和第二源极(152)、以及位于第一源极(151)和第二源极(152)之间的第一漏极(153)和第二漏极(154)；所述第一源极(151)和第一漏极(153)分别通过所述第一过孔(141)和第二过孔(142)与所述第一半导体层(11)的两端接触，所述第二源极(152)和第二漏极(154)分别与所述第二半导体层(14)的两端接触，所述第一漏极(153)和第二漏极(154)接触；
所述第一源极(151)和第一漏极(153)为P型低温多晶硅薄膜晶体管(10)的源极和漏极，所述第二源极(152)和第二漏极(154)为N型金属氧化物薄膜晶体管(20)的源极和漏极。
7.如权利要求3所述的CMOS反相器，其特征在于，在所述第一半导体层(11)与基板(30)之间以及第一栅绝缘层(12)与基板(30)之间还设有缓冲层(16)，在所述第二源极(152)和第二漏极(154)之间的第二半导体层(14)上还设有刻蚀阻挡层(17)。
8.如权利要求3所述的CMOS反相器，其特征在于，所述第一栅绝缘层(12)和第二栅绝缘层(14)的材料均为氧化硅或氮化硅中的一种或二者的组合，所述第一金属层(13)和第二金属层(15)的材料均为钼、铝、铜、及钛中的一种或多种的组合。
9.如权利要求1所述的CMOS反相器，其特征在于，所述N型金属氧化物薄膜晶体管(20)的半导体层的材料为IGZO或IZO。
10.一种阵列基板，其特征在于，包括如权利要求1至9任一项所述的CMOS反相器。
CN201710937121.2A 2017-10-10 2017-10-10 Cmos反相器及阵列基板 Pending CN107799521A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201710937121.2A CN107799521A (zh) 2017-10-10 2017-10-10 Cmos反相器及阵列基板
PCT/CN2017/110989 WO2019071702A1 (zh) 2017-10-10 2017-11-15 Cmos反相器及阵列基板
US15/743,990 US20200152800A1 (en) 2017-10-10 2017-11-15 Cmos inverter and array substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710937121.2A CN107799521A (zh) 2017-10-10 2017-10-10 Cmos反相器及阵列基板

Publications (1)

Publication Number Publication Date
CN107799521A true CN107799521A (zh) 2018-03-13

Family

ID=61533211

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710937121.2A Pending CN107799521A (zh) 2017-10-10 2017-10-10 Cmos反相器及阵列基板

Country Status (3)

Country Link
US (1) US20200152800A1 (zh)
CN (1) CN107799521A (zh)
WO (1) WO2019071702A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950257A (zh) * 2019-04-17 2019-06-28 合肥鑫晟光电科技有限公司 复合薄膜晶体管和制造方法、阵列基板、显示面板和装置
CN110060998A (zh) * 2019-04-29 2019-07-26 厦门天马微电子有限公司 一种反相电路结构、栅极驱动电路及显示面板
CN111081639A (zh) * 2019-12-05 2020-04-28 深圳市华星光电半导体显示技术有限公司 Cmos薄膜晶体管及其制备方法、显示面板
CN111081719A (zh) * 2019-12-12 2020-04-28 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制造方法
CN111128680A (zh) * 2019-12-24 2020-05-08 Tcl华星光电技术有限公司 一种cmos反相器的制备方法
CN113809097A (zh) * 2020-06-11 2021-12-17 香港科技大学 混合型薄膜晶体管集成的电子器件及相应的制造方法
CN114038868A (zh) * 2021-12-09 2022-02-11 南京迪钛飞光电科技有限公司 一种平板探测器及其制造方法
US20230326934A1 (en) * 2020-08-27 2023-10-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112599571B (zh) * 2020-12-08 2022-11-25 武汉华星光电半导体显示技术有限公司 显示面板
GB202217962D0 (en) * 2022-11-29 2023-01-11 Pragmatic Semiconductor Ltd Electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000632A (zh) * 2012-12-12 2013-03-27 京东方科技集团股份有限公司 一种cmos电路结构、其制备方法及显示装置
US20150243220A1 (en) * 2014-02-25 2015-08-27 Lg Display Co., Ltd. Display Backplane and Method of Fabricating the Same
CN105408813A (zh) * 2013-08-26 2016-03-16 苹果公司 具有硅薄膜晶体管和半导体氧化物薄膜晶体管的显示器
CN106252364A (zh) * 2016-10-09 2016-12-21 深圳市华星光电技术有限公司 一种goa阵列基板的制作方法及goa阵列基板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715196B (zh) * 2013-12-27 2015-03-25 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN105390508B (zh) * 2015-12-07 2018-03-13 深圳市华星光电技术有限公司 阵列基板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000632A (zh) * 2012-12-12 2013-03-27 京东方科技集团股份有限公司 一种cmos电路结构、其制备方法及显示装置
CN105408813A (zh) * 2013-08-26 2016-03-16 苹果公司 具有硅薄膜晶体管和半导体氧化物薄膜晶体管的显示器
US20150243220A1 (en) * 2014-02-25 2015-08-27 Lg Display Co., Ltd. Display Backplane and Method of Fabricating the Same
CN106252364A (zh) * 2016-10-09 2016-12-21 深圳市华星光电技术有限公司 一种goa阵列基板的制作方法及goa阵列基板

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
刘培植: "《数字电路设计与数字系统》", 28 February 2005, 北京邮电大学出版社 *
李本俊: "《CMOS集成电路原理与设计》", 30 April 1997, 北京邮电大学出版社 *
贾建章，武岳: "《最新集成电路设计手册》", 31 March 2004, 银声音像出版社 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950257A (zh) * 2019-04-17 2019-06-28 合肥鑫晟光电科技有限公司 复合薄膜晶体管和制造方法、阵列基板、显示面板和装置
CN110060998A (zh) * 2019-04-29 2019-07-26 厦门天马微电子有限公司 一种反相电路结构、栅极驱动电路及显示面板
CN111081639A (zh) * 2019-12-05 2020-04-28 深圳市华星光电半导体显示技术有限公司 Cmos薄膜晶体管及其制备方法、显示面板
CN111081639B (zh) * 2019-12-05 2022-05-31 深圳市华星光电半导体显示技术有限公司 Cmos薄膜晶体管及其制备方法、显示面板
CN111081719A (zh) * 2019-12-12 2020-04-28 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制造方法
CN111128680A (zh) * 2019-12-24 2020-05-08 Tcl华星光电技术有限公司 一种cmos反相器的制备方法
WO2021128467A1 (zh) * 2019-12-24 2021-07-01 Tcl华星光电技术有限公司 一种cmos反相器的制备方法
US11217489B1 (en) 2019-12-24 2022-01-04 Tcl China Star Optoelectronics Technology Co., Ltd. Manufacturing method of CMOS inverter
CN113809097A (zh) * 2020-06-11 2021-12-17 香港科技大学 混合型薄膜晶体管集成的电子器件及相应的制造方法
US20230326934A1 (en) * 2020-08-27 2023-10-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic device
CN114038868A (zh) * 2021-12-09 2022-02-11 南京迪钛飞光电科技有限公司 一种平板探测器及其制造方法

Also Published As

Publication number Publication date
US20200152800A1 (en) 2020-05-14
WO2019071702A1 (zh) 2019-04-18

Similar Documents

Publication Publication Date Title
CN107799521A (zh) Cmos反相器及阵列基板
US10403757B2 (en) Top-gate self-aligned metal oxide semiconductor TFT and method of making the same
US11876099B2 (en) Displays with silicon and semiconducting oxide thin-film transistors
CN107507841B (zh) 阵列基板及其制作方法、显示装置
Bong et al. High-mobility low-temperature ZnO transistors with low-voltage operation
Li et al. High-speed dual-gate a-IGZO TFT-based circuits with top-gate offset structure
Sporea et al. Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits
TWI570919B (zh) 場效應電晶體及半導體裝置
WO2017166431A1 (zh) Tft阵列基板及其制造方法、显示装置
WO2017128557A1 (zh) 阵列基板及液晶显示装置
TWI476931B (zh) 薄膜電晶體與具有此薄膜電晶體的畫素結構
JP2004501501A (ja) 薄いゲート酸化膜用デカップリング・キャパシタ
KR101694270B1 (ko) 고속전자센서용 기판 및 그 제조방법
TWI726939B (zh) 電子裝置、計算裝置及用於形成氧化物半導體之方法
CN106356306A (zh) 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
WO2017147970A1 (zh) 互补型薄膜晶体管及其制造方法
CN207458949U (zh) 薄膜晶体管、阵列基板和显示装置
CN107644878B (zh) 反相器及其制作方法
Zhuang et al. High-performance and low-power source-gated transistors enabled by a solution-processed metal oxide homojunction
Guo et al. Low voltage organic/inorganic hybrid complementary inverter with low temperature all solution processed semiconductor and dielectric layers
JP5701015B2 (ja) 半導体デバイスの駆動方法
US11538395B2 (en) Shift register unit and driving method thereof, gate drive circuit, and display device
CN105140298B (zh) 薄膜晶体管和阵列基板
CN109616444B (zh) Tft基板的制作方法及tft基板
JP4855668B2 (ja) 電界効果トランジスタの高電圧動作方法とそのバイアス回路およびその高電圧動作回路要素

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20180313

RJ01 Rejection of invention patent application after publication