WO2017147970A1 - 互补型薄膜晶体管及其制造方法 - Google Patents

互补型薄膜晶体管及其制造方法 Download PDF

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WO2017147970A1
WO2017147970A1 PCT/CN2016/078753 CN2016078753W WO2017147970A1 WO 2017147970 A1 WO2017147970 A1 WO 2017147970A1 CN 2016078753 W CN2016078753 W CN 2016078753W WO 2017147970 A1 WO2017147970 A1 WO 2017147970A1
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layer
type
transistor region
thin film
type transistor
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PCT/CN2016/078753
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English (en)
French (fr)
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曾勉
萧祥志
张盛东
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深圳市华星光电技术有限公司
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Priority to US15/121,986 priority Critical patent/US10192931B2/en
Publication of WO2017147970A1 publication Critical patent/WO2017147970A1/zh

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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
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    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/20—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising components having an active region that includes an inorganic semiconductor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
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    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors

Definitions

  • the present invention relates to a thin film transistor and a method of fabricating the same, and more particularly to a complementary thin film transistor and a method of fabricating the same.
  • Complementary Metal-Oxide-Semiconductor is an integrated circuit design process for fabricating N-type MOSFETs (NMOS) and P-channel MOS semiconductors on silicon wafer templates.
  • CMOS complementary Metal-Oxide-Semiconductor
  • CMOS complementary Metal-Oxide-Semiconductor
  • CMOS can be used to make static random access memories, microcontrollers, microprocessors, and complementary complementary metal oxide semiconductor image sensing devices and other digital logic circuits in a typical process. That is, the CMOS is composed of a P-channel metal oxide semiconductor and an N-channel metal oxide semiconductor, and the CMOS circuit is a basic circuit configuration in an integrated circuit.
  • FIG. 1 is a complementary thin film transistor (Continuous Time Fourier).
  • CTFT complementary thin film transistor
  • the circuit diagram of the inverter, CTFT), the complementary thin film transistor is electrically connected to a power supply voltage VDD and a common voltage VSS, and the complementary thin film transistor has a P-type thin film transistor 11 and an N-type thin film transistor 12, wherein the N-type thin film transistor 12 is an active component and is formed on the substrate (not shown) and has an input terminal Vin and an output terminal Vout.
  • the driver chip (IC) of the display does not have an integrated separate design with the glass substrate.
  • Low temperature polysilicon (LTPS, Low Temperature) In the technique of Poly-silicon, a semiconductor layer of a region of the P-type thin film transistor 11 and a region of the N-type thin film transistor 12 in a CTFT circuit is separately prepared by using different types of doping, and the CTFT circuit is prepared.
  • the process includes complex processes such as laser annealing and ion implantation, and the manufacturing cost is high.
  • an object of the present invention is to provide a complementary thin film transistor in which an N-type thin film crystal is formed in the N-type transistor region, and a P-type thin film crystal is formed in the P-type transistor region while being blocked by etching.
  • the layer is covered with an entire layer of electrode metal to ensure the planarity of the surface of the channel of the P-type semiconductor layer.
  • Another object of the present invention is to provide a method of fabricating a complementary thin film transistor in which an N-type thin film crystal is formed in an N-type transistor region by an N-type semiconductor layer forming step, and a P-type semiconductor layer forming step is formed in a P-type transistor region. Thin film transistors improve device characteristics.
  • an embodiment of the present invention provides a complementary thin film transistor including a substrate, an N-type semiconductor layer, a P-type semiconductor layer, and an etch stop layer; An N-type transistor region and a P-type transistor region; the N-type semiconductor layer is disposed above the substrate and located in the N-type transistor region, wherein the N-type semiconductor layer comprises a metal oxide material; a P-type semiconductor layer disposed over the substrate and located in the P-type transistor region, wherein the P-type semiconductor layer comprises an organic semiconductor material; the etch stop layer is formed on the N-type semiconductor layer Located in the N-type transistor region and the P-type transistor region, and the P-type semiconductor layer is formed on the etch barrier layer.
  • the complementary thin film transistor further includes a first gate layer and an insulating layer, wherein the first gate layer is formed on the substrate and located in the N-type transistor region
  • the insulating layer is formed on the first gate layer and the substrate and located in the N-type transistor region and the P-type transistor region, wherein the N-type semiconductor layer and the etch stop layer Formed on the insulating layer.
  • the complementary thin film transistor further includes a buffer layer formed on the entire etch barrier layer and located in the N-type transistor region and the P-type transistor region.
  • the complementary thin film transistor further includes an electrode metal layer formed in the N-type transistor region and the P-type transistor region, wherein the electrode metal layer is formed in the On the N-type semiconductor layer, the P-type semiconductor layer is formed on the electrode metal layer.
  • the complementary thin film transistor further includes: a passivation layer formed on the electrode metal layer and located in the N-type transistor region and the P-type transistor region; A second gate layer is formed on the passivation layer and in the P-type transistor region.
  • the metal oxide material of the N-type semiconductor layer is selected from the group consisting of indium gallium zinc oxide, indium zinc oxide, or zinc tin oxide.
  • the organic semiconductor material of the P-type semiconductor layer is selected from the group consisting of pentacene, triphenylamine, fullerene, phthalocyanine, anthracene derivative or cyanine.
  • an embodiment of the present invention provides a method of fabricating a complementary thin film transistor, including a first gate layer forming step, an insulating layer forming step, an N-type semiconductor layer forming step, and a moment.
  • the first gate layer forming step is to define an adjacent N-type transistor region and a P-type transistor region on a substrate And forming a first gate layer on the substrate and located in the N-type transistor region;
  • the insulating layer forming step is to form an insulating layer on the first gate layer and the substrate And in the N-type transistor region and the P-type transistor region;
  • the N-type semiconductor layer forming step is to form an N-type semiconductor layer on the insulating layer and located in the N-type transistor region, wherein
  • the N-type semiconductor layer comprises a metal oxide material;
  • the etch barrier layer forming step is to form an etch barrier layer on the N-type semiconductor layer and the insulating layer and located in the N-type transistor region and P-type crystal
  • the electrode metal layer forming step is to form an electrode metal layer on the N-type semiconductor layer and in the N-type transistor region and the P-type transistor region;
  • the manufacturing method further includes a buffer layer forming step after the etch barrier layer forming step, forming a buffer layer over the entire etch barrier layer and located at the N The transistor region and the P-type transistor region.
  • the manufacturing method further includes a second gate layer forming step after the P-type semiconductor layer forming step, forming a passivation layer on the electrode metal layer and located In the N-type transistor region and the P-type transistor region, a second gate layer is then formed on the passivation layer and in the P-type transistor region.
  • the complementary thin film transistor of the present invention forms an N-type thin film transistor in the N-type transistor region, and forms a P-type thin film transistor in the P-type transistor region, while covering the entire etch stop layer
  • the electrode metal layer of the layer ensures the planarity of the surface at the channel of the P-type semiconductor layer, thereby improving device characteristics.
  • FIG. 1 is a circuit diagram of a conventional complementary thin film transistor inverter.
  • FIG. 2 is a cross-sectional view of a complementary thin film transistor in accordance with a first preferred embodiment of the present invention.
  • Figure 3 is a cross-sectional view of a complementary thin film transistor in accordance with a second preferred embodiment of the present invention.
  • FIG. 4 is a flow chart showing a method of fabricating a complementary thin film transistor according to a first preferred embodiment of the present invention.
  • Figure 5 is a flow chart showing a method of fabricating a complementary thin film transistor according to a second preferred embodiment of the present invention.
  • a complementary thin film transistor 100 according to a first preferred embodiment of the present invention, wherein the complementary thin film transistor 100 comprises a substrate 2, an N-type semiconductor layer 31, and a P-type semiconductor layer 32. a first gate layer 41, an insulating layer 5, an electrode metal layer 6, a passivation layer 7, a second gate layer 42, and an etch stop layer 8.
  • the substrate 2 defines an adjacent N-type transistor region 101 and a P-type transistor region 102.
  • the substrate 2 is a glass substrate, but in other embodiments, it may be a plastic substrate (PEN).
  • the N-type semiconductor layer 31 is disposed above the substrate 2 and located in the N-type transistor region 101, wherein the N-type semiconductor layer 31 comprises a metal oxide material.
  • the metal oxide material of the N-type semiconductor layer 31 is selected from the group consisting of indium gallium zinc oxide, indium zinc oxide, or zinc tin oxide.
  • the P-type semiconductor layer 32 is disposed above the substrate 2 and located in the P-type transistor region 102, wherein the P-type semiconductor layer 32 comprises an organic semiconductor material.
  • the organic semiconductor material of the P-type semiconductor layer 32 is selected from the group consisting of pentacene, triphenylamine, fullerene, phthalocyanine, anthracene derivative or cyanine.
  • the first gate layer 41 is formed on the substrate 2, and the first gate layer 41 is formed in the N-type transistor region 101.
  • the first gate layer 41 is a metal material such as aluminum, manganese, copper or titanium and alloys thereof.
  • the insulating layer 5 is formed on the first gate layer 41 and the substrate 2 and is located in the N-type transistor region 101 and the P-type transistor region 102, wherein the An N-type semiconductor layer 31 is formed on the insulating layer 5 and opposed to the first gate layer 41, and the etch barrier layer 8 is formed over the entire insulating layer 5.
  • the insulating layer 5 is an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx) or the like for insulating the first gate layer 41.
  • the electrode metal layer 6 is formed on the etch stop layer 8 and is located in the N-type transistor region 101 and the P-type transistor region 102, and the electrode metal layer 6 is Is by spraying a whole layer of electrode metal material, such as molybdenum/aluminum/molybdenum (Mo/Al/Mo), copper/titanium (Cu/Ti), gold (Au), etc., on the etch barrier layer 8
  • the electrode metal layer 6 is formed through processes such as exposure, development, etching, and lift-off.
  • the electrode metal layer 6 is further in contact with the N-type semiconductor layer 31 through at least one via hole of the etch stop layer 8, and the P-type semiconductor layer 32 is formed on the electrode metal layer 6.
  • the passivation layer 7 is formed on the electrode metal layer 6 and the etch barrier layer 8 and is located in the N-type transistor region 101 and the P-type transistor region 102. In the embodiment, the passivation layer 7 is used to insulate the second gate layer 42.
  • the second gate layer 42 is formed on the passivation layer 7, and the second gate layer 42 is formed in the P-type transistor region 102.
  • the N-type semiconductor layer 31 and the P-type semiconductor layer 32 are provided on the substrate 2, so that the complementary thin film transistor 100 forms an N-type thin film transistor in the N-type transistor region 101, respectively.
  • N Type TFT and forming a P-type thin film transistor (Ptype TFT) in the P-type transistor region 102, and further capable of using an organic thin film transistor (Organic) TFT) as a region structure of a P-type thin film transistor, that is, a P-type semiconductor layer 32 is prepared using a P-type organic semiconductor material, and a metal oxide thin film transistor (Oxide) TFT) is used as a region structure of an N-type thin film transistor, that is, an N-type semiconductor layer 31 is prepared using an oxide material. Therefore, the flatness of the surface at the channel of the P-type semiconductor layer 32 can be ensured, thereby improving device characteristics such as increasing on-state current (Ion), decreasing off-state current (Ioff), and improving Vth shift and the like.
  • Ion organic thin film transistor
  • the complementary thin film transistor 100 of the present invention forms an N-type thin film transistor in the N-type transistor region 101, and a P-type thin film transistor in the P-type transistor region 102, while passing through the etching barrier layer.
  • An entire layer of the electrode metal layer 6 is overlaid on the layer 8 to ensure the planarity of the surface of the channel of the P-type semiconductor layer 32, thereby improving device characteristics.
  • a complementary thin film transistor 100' is similar to the first embodiment of the present invention and substantially uses the same component name and figure number, wherein the complementary thin film transistor 100' includes a substrate 2, an N-type semiconductor layer 31, a P-type semiconductor layer 32, a first gate layer 41, an insulating layer 5, an electrode metal layer 6, a passivation layer 7, and a second gate.
  • the second embodiment of the present invention is characterized in that the complementary thin film transistor 100' further includes a buffer layer 9, wherein the buffer layer 9 is formed on the entire etch stop layer 8 and is located at the N-type.
  • the buffer layer 9 is an organic material.
  • the complementary thin film transistor 100' of the present invention can ensure the flatness of the surface of the channel of the P-type semiconductor layer 32, thereby improving device characteristics.
  • the entire etch stop is formed by using the buffer layer 9 of an organic material. On the layer 8, the problem of instability of the organic material and environmental influence can be overcome to optimize the structure of the original complementary thin film transistor.
  • FIG. 4 and FIG. 2 it is a flowchart of a method for fabricating a complementary thin film transistor according to a first preferred embodiment of the present invention, wherein the method for fabricating the complementary thin film transistor includes a first gate a layer forming step S201, an insulating layer forming step S202, an N-type semiconductor layer forming step S203, an etch stop layer forming step S204, an electrode metal layer forming step S205, a P-type semiconductor layer forming step S206, and a second gate.
  • the pole layer formation step S207 The pole layer formation step S207.
  • the first gate layer forming step S201 defines an adjacent N-type transistor region 101 and a P-type transistor region 102 on a substrate 2, and a first A gate layer 41 is formed on the substrate 2 and is located in the N-type transistor region 101.
  • the insulating layer forming step S202 is formed on the first gate layer 41 and the substrate 2, and is located in the N-type transistor region 101. in.
  • the N-type semiconductor layer forming step S203 is formed by forming an N-type semiconductor layer 31 on the insulating layer 5 and located in the N-type transistor region 101, wherein the N-type The semiconductor layer 31 comprises a metal oxide material.
  • the etch barrier layer forming step S204 is to form an etch stop layer 8 on the N-type semiconductor layer 31 and the insulating layer 5 and located in the N-type transistor.
  • the region 101 and the P-type transistor region 102 are included.
  • the electrode metal layer forming step S205 is to form an electrode metal layer 6 on the N-type semiconductor layer 31 and the etch stop layer 8, and is located at the N
  • the transistor region 101 and the P-type transistor region 102 are included.
  • the P-type semiconductor layer forming step S206 is formed on the electrode metal layer 6 and in the P-type transistor region 102, wherein the P-type semiconductor layer forming step S206 is performed.
  • the P-type semiconductor layer 32 comprises an organic semiconductor material.
  • the second gate layer forming step S207 is to form a passivation layer 7 on the electrode metal layer 6 and in the N-type transistor region 101 and the P.
  • a second gate layer 42 is then formed on the passivation layer 7 and in the P-type transistor region 102.
  • the complementary thin film transistor 100 of the present invention forms an N-type thin film transistor in the N-type transistor region 101, and a P-type thin film transistor in the P-type transistor region 102, while passing through the etching barrier layer.
  • An entire layer of the electrode metal layer 6 is overlaid on the layer 8 to ensure the planarity of the surface of the channel of the P-type semiconductor layer 32, thereby improving device characteristics.
  • the method for fabricating the complementary thin film transistor includes a first gate layer Forming step S201, an insulating layer forming step S202, an N-type semiconductor layer forming step S203, an etch stop layer forming step S204, a buffer layer forming step S208, an electrode metal layer forming step S205, and a P-type semiconductor layer forming step S206 and a second gate layer forming step S207.
  • the first gate layer forming step S201 defines an adjacent N-type transistor region 101 and a P-type transistor region 102 on a substrate 2, and a first A gate layer 41 is formed on the substrate 2 and is located in the N-type transistor region 101.
  • the insulating layer forming step S202 is formed on the first gate layer 41 and the substrate 2, and is located in the N-type transistor region 101. in.
  • the N-type semiconductor layer forming step S203 is formed by forming an N-type semiconductor layer 31 on the insulating layer 5 and located in the N-type transistor region 101, wherein the N-type The semiconductor layer 31 comprises a metal oxide material.
  • the etch barrier layer forming step S204 is to form an etch stop layer 8 on the N-type semiconductor layer 31 and the insulating layer 5 and located in the N-type transistor.
  • the region 101 and the P-type transistor region 102 are included.
  • the buffer layer forming step S208 is to form a buffer layer 9 on the entire etch stop layer 8 and in the N-type transistor region 101 and the P-type transistor. In area 102.
  • the electrode metal layer forming step S205 is to form an electrode metal layer 6 on the N-type semiconductor layer 31 and the etch stop layer 8, and is located at the N
  • the transistor region 101 and the P-type transistor region 102 are included.
  • the P-type semiconductor layer forming step S206 is formed on the electrode metal layer 6 and in the P-type transistor region 102, wherein the P-type semiconductor layer forming step S206 is performed.
  • the P-type semiconductor layer 32 comprises an organic semiconductor material.
  • the second gate layer forming step S207 is to form a passivation layer 7 on the electrode metal layer 6 and located in the N-type transistor region 101 and the P.
  • a second gate layer 42 is then formed on the passivation layer 7 and in the P-type transistor region 102.
  • the complementary thin film transistor 100' of the present invention can ensure the flatness of the surface of the channel of the P-type semiconductor layer 32, thereby improving device characteristics.
  • the entire etch stop is formed by using the buffer layer 9 of an organic material. On the layer 8, the problem of instability of the organic material and environmental influence can be overcome to optimize the structure of the original complementary thin film transistor.

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Abstract

一种互补型薄膜晶体管（100）及其制造方法，所述互补型薄膜晶体管（100）包含一基板（2）、一N型半导体层（31）、一P型半导体层（32）及一刻蚀阻挡层（8）；所述基板（2）定义有相邻的一N型晶体管区（101）及一P型晶体管区（102），所述N型半导体层（31）设置在所述基板（2）上方且位于所述N型晶体管区（101）中，所述N型半导体层（31）包含一金属氧化物材料，所述P型半导体层（32）设置在所述基板（2）上方且位于所述P型晶体管区（102）中，所述P型半导体层（32）包含一有机半导体材料，所述刻蚀阻挡层（8）形成在所述N型半导体层（31）上并位于所述N型晶体管区（101）及所述P型晶体管区（102）中，且所述P型半导体层（32）形成在所述刻蚀阻挡层（8）上。

Description

互补型薄膜晶体管及其制造方法 技术领域
本发明是有关于一种薄膜晶体管及其制造方法，特别是有关于一种互补型薄膜晶体管及其制造方法。
 背景技术
互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor, CMOS)是一种集成电路的设计制程，可以在硅质晶圆模板上制出N 型沟道金属氧化物半导体(n-type MOSFET, NMOS)和P型沟道金属氧化物半导体 (p-type MOSFET, PMOS)的基本组件，由于NMOS与PMOS在物理特性上为互补性，因此被称为CMOS。CMOS在一般的制程上，可用来制作静态随机存储器、微控制器、微处理器、以及互补式互补式金属氧化物半导体图像传感装置与其他数位逻辑电路系统。也就是说，CMOS由P型沟道金属氧化物半导体和N型沟道金属氧化物半导体共同构成，而CMOS电路是作为集成电路中的基本电路构造。
目前显示面板中的基板大部分为玻璃基板或塑料基板(PEN)等，如图1所示，为一种互补型薄膜晶体管(Continuous Time Fourier Transform,CTFT)反相器的电路图，所述互补型薄膜晶体管电性连接一电源电压VDD及一公共电压VSS，且所述互补型薄膜晶体管具有一P型薄膜晶体管11，及一N型薄膜晶体管12，其中所述N型薄膜晶体管12为主动组件且形成在所述基板(未绘示)上，并具有一输入端Vin及一输出端Vout。
然而，传统的LCD(Liquid Crystal Display)显示器的驱动芯片(IC)与玻璃基板不具有集成的分离式设计，在低温多晶硅(LTPS，Low Temperature Poly-silicon)的技术中，通过采用不同类型的掺杂来分别制备CTFT电路中所述P型薄膜晶体管11的区域及所述N型薄膜晶体管12的区域的半导体层，所述CTFT电路的制备工艺包括激光退火、离子注入等复杂工艺，制造成本较高。
 技术问题
有鉴于此，本发明的目的在于提供一种互补型薄膜晶体管，利用在所述N型晶体管区形成N型薄膜晶体，在所述P型晶体管区形成P型薄膜晶体，同时通过在刻蚀阻挡层上覆盖一整层的电极金属层，以确保P型半导体层的沟道处表面的平整性。
本发明的另一目的在于提供一种互补型薄膜晶体管的制造方法，利用N型半导体层形成步骤在N型晶体管区形成N型薄膜晶体，及P型半导体层形成步骤在P型晶体管区形成P型薄膜晶体管，可改善器件特性。
 技术解决方案
为达成本发明的前述目的，本发明一实施例提供一种互补型薄膜晶体管，其包含一基板、一N型半导体层、一P型半导体层及一刻蚀阻挡层；所述基板定义有相邻的一N型晶体管区及一P型晶体管区；所述N型半导体层设置在所述基板上方且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；所述P型半导体层设置在所述基板上方且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料；所述刻蚀阻挡层形成在所述N型半导体层上并位于所述N型晶体管区及所述P型晶体管区中，且所述P型半导体层形成在所述刻蚀阻挡层上。
在本发明的一实施例中，所述互补型薄膜晶体管还包含一第一栅极层及一绝缘层，其中所述第一栅极层形成在所述基板上且位于所述N型晶体管区，所述绝缘层形成在所述第一栅极层及所述基板上且位于所述N型晶体管区及所述P型晶体管区中，其中所述N型半导体层及所述刻蚀阻挡层形成在所述绝缘层上。
在本发明的一实施例中，所述互补型薄膜晶体管还包含一缓冲层，形成在整个所述刻蚀阻挡层上并位于所述N型晶体管区及所述P型晶体管区中。
在本发明的一实施例中，所述互补型薄膜晶体管还包含一电极金属层，形成在位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
在本发明的一实施例中，所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述P型晶体管区中。
在本发明的一实施例中，所述N型半导体层的金属氧化物材料选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物。
在本发明的一实施例中，所述P型半导体层的有机半导体材料选自于并五苯、三苯基胺、富勒烯、酞菁、茈衍生物或花菁。
为达成本发明的前述目的，本发明一实施例提供一种互补型薄膜晶体管的制造方法，其包含一第一栅极层形成步骤、一绝缘层形成步骤、一N型半导体层形成步骤、一刻蚀阻挡层形成步骤、一电极金属层形成步骤及一P型半导体层形成步骤；所述第一栅极层形成步骤是在一基板上定义相邻的一N型晶体管区及一P型晶体管区，并将一第一栅极层形成在所述基板上并位于所述N型晶体管区中；所述绝缘层形成步骤是将一绝缘层形成在所述第一栅极层及所述基板上且位于所述N型晶体管区及所述P型晶体管区中；所述N型半导体层形成步骤是将一N型半导体层形成在绝缘层上且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；所述刻蚀阻挡层形成步骤是将一刻蚀阻挡层形成在所述N型半导体层及所述绝缘层上并位于所述N型晶体管区及所述P型晶体管区中；所述电极金属层形成步骤是将一电极金属层形成在所述N型半导体层上且位于所述N型晶体管区及所述P型晶体管区中；所述P型半导体层形成步骤是将一P型半导体层形成在所述电极金属层上且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料。
在本发明的一实施例中，所述制造方法在所述刻蚀阻挡层形成步骤之后还包含一缓冲层形成步骤，将一缓冲层形成在整个所述刻蚀阻挡层上并位于所述N型晶体管区及所述P型晶体管区中。
在本发明的一实施例中，所述制造方法还包含在所述P型半导体层形成步骤之后的一第二栅极层形成步骤，将一钝化层形成在所述电极金属层上且位于所述N型晶体管区及所述P型晶体管区中，接着将一第二栅极层形成在所述钝化层上且位于所述P型晶体管区中。
 有益效果
如上所述，本发明互补型薄膜晶体管分别在所述N型晶体管区形成N型薄膜晶体管，在所述P型晶体管区形成P型薄膜晶体管，同时通过在所述刻蚀阻挡层上覆盖一整层的所述电极金属层，以确保所述P型半导体层的沟道处表面的平整性，进而改善器件特性。
 附图说明
图1是一现有的互补型薄膜晶体管反相器的电路图。
图2是根据本发明一第一优选实施例的互补型薄膜晶体管的一剖视图。
图3是根据本发明一第二优选实施例的互补型薄膜晶体管的一剖视图。
图4是本发明所述第一优选实施例的互补型薄膜晶体管的制造方法的一流程图。
图5是本发明所述第二优选实施例的互补型薄膜晶体管的制造方法的一流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图2所示，是根据本发明一第一优选实施例的互补型薄膜晶体管100，其中所述互补型薄膜晶体管100包含一基板2、一N型半导体层31、一P型半导体层32、一第一栅极层41、一绝缘层5、一电极金属层6、一钝化层7、一第二栅极层42及一刻蚀阻挡层8。本发明将于下文详细说明各实施例上述各组件的细部构造、组装关系及其运作原理。
续参照图2所示，所述基板2定义有相邻的一N型晶体管区101及一P型晶体管区102。在本实施例中，所述基板2为玻璃基板，但在其他实施例中，也可为塑料基板(PEN)。
续参照图2所示，所述N型半导体层31设置在所述基板2上方且位于所述N型晶体管区101中，其中所述N型半导体层31包含一金属氧化物材料。在本实施例中，所述N型半导体层31的金属氧化物材料是选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物。
续参照图2所示，所述P型半导体层32设置在所述基板2上方且位于所述P型晶体管区102中，其中所述P型半导体层32包含一有机半导体材料。在本实施例中，所述P型半导体层32的有机半导体材料是选自于并五苯、三苯基胺、富勒烯、酞菁、茈衍生物或花菁。
续参照图2所示，所述第一栅极层41形成在所述基板2上，且所述第一栅极层41形成在所述N型晶体管区101中。在本实施例中，所述第一栅极层41为金属材料，例如铝、锰、铜或钛以及其合金。
续参照图2所示，所述绝缘层5形成在所述第一栅极层41及所述基板2上且位于所述N型晶体管区101及所述P型晶体管区102中，其中所述N型半导体层31是形成在所述绝缘层5上且对位于所述第一栅极层41，而所述刻蚀阻挡层8是形成在整个所述绝缘层5上。在本实施例中，所述绝缘层5为无机绝缘材料，如氮化硅(SiNx)、氧化硅(SiOx)等，用以绝缘所述第一栅极层41。
续参照图2所示，所述电极金属层6形成在所述刻蚀阻挡层8上且位于所述N型晶体管区101及所述P型晶体管区102中，而且所述电极金属层6是是通过在所述刻蚀阻挡层8溅射一整层的电极金属材料，如钼/铝/钼(Mo/Al/Mo)、铜/钛(Cu/Ti)、金(Au)等，再经由曝光、显影、刻蚀、剥离等工序而形成所述电极金属层6。其中，所述电极金属层6还通过所述刻蚀阻挡层8的至少一通孔而与所述N型半导体层31接触，所述P型半导体层32形成在所述电极金属层6上。
续参照图2所示，所述钝化层7形成在所述电极金属层6及所述刻蚀阻挡层8上且位于所述N型晶体管区101及所述P型晶体管区102中。在本实施例中，所述钝化层7用以绝缘所述第二栅极层42。
续参照图2所示，所述第二栅极层42形成在所述钝化层7上，且所述第二栅极层42形成在所述P型晶体管区102中。
依据上述的结构，通过在所述基板2设置所述N型半导体层31及所述P型半导体层32，使所述互补型薄膜晶体管100分别在所述N型晶体管区101形成N型薄膜晶体管(N type TFT)，及在所述P型晶体管区102形成P型薄膜晶体管(Ptype TFT)，进而能够以有机薄膜晶体管(Organic TFT)作为P型薄膜晶体管的区域结构，也就是使用P型有机半导体材料制备所述P型半导体层32，又以金属氧化物薄膜晶体管(Oxide TFT)作为N型薄膜晶体管的区域结构，也就是使用氧化物材料制备所述N型半导体层31。因此，能够确保所述P型半导体层32的沟道处表面的平整性，进而改善器件特性，例如增大开态电流(Ion)，减小关态电流(Ioff)及改善Vth偏移等。
利用上述的设计，本发明互补型薄膜晶体管100分别在所述N型晶体管区101形成N型薄膜晶体管，在所述P型晶体管区102形成P型薄膜晶体管，同时通过在所述刻蚀阻挡层8上覆盖一整层的所述电极金属层6，以确保所述P型半导体层32的沟道处表面的平整性，进而改善器件特性。
请参照图3所示，是根据本发明一第二优选实施例的互补型薄膜晶体管100’，相似于本发明第一实施例并大致沿用相同组件名称及图号，其中所述互补型薄膜晶体管100’包含一基板2、一N型半导体层31、一P型半导体层32、一第一栅极层41、一绝缘层5、一电极金属层6、一钝化层7、一第二栅极层42及一刻蚀阻挡层8。但本发明第二实施例的差异特征在于：所述互补型薄膜晶体管100’还包含一缓冲层9，其中所述缓冲层9形成在整个所述刻蚀阻挡层8上并位于所述N型晶体管区101及所述P型晶体管区102中，其中所述缓冲层9为有机材料。
利用上述的设计，本发明互补型薄膜晶体管100’能够确保所述P型半导体层32的沟道处表面的平整性，进而改善器件特性。另外，当无机绝缘材料的所述刻蚀阻挡层8及有机半导体材料的所述P型半导体层32两者不能匹配时，通过采用有机材料的所述缓冲层9形成在整个所述刻蚀阻挡层8上，能够克服有机材料的不稳定及容易受到环境影响的问题，以优化原有的所述互补型薄膜晶体管的结构。
请参照图4并配合图2所示，是依照本发明所述第一优选实施例的互补型薄膜晶体管的制造方法的流程图，其中所述互补型薄膜晶体管的制造方法包含一第一栅极层形成步骤S201、一绝缘层形成步骤S202、一N型半导体层形成步骤S203、一刻蚀阻挡层形成步骤S204、一电极金属层形成步骤S205、一P型半导体层形成步骤S206及一第二栅极层形成步骤S207。
续参照图4并配合图2所示，所述第一栅极层形成步骤S201是在一基板2上定义相邻的一N型晶体管区101及一P型晶体管区102，并将一第一栅极层41形成在所述基板2上，并位于所述N型晶体管区101中。
续参照图4并配合图2所示，所述绝缘层形成步骤S202是将一绝缘层5形成在所述第一栅极层41及所述基板2上，且位于所述N型晶体管区101中。
续参照图4并配合图2所示，所述N型半导体层形成步骤S203是将一N型半导体层31形成在绝缘层5上且位于所述N型晶体管区101中，其中所述N型半导体层31包含一金属氧化物材料。
续参照图4并配合图2所示，所述刻蚀阻挡层形成步骤S204是将一刻蚀阻挡层8形成在所述N型半导体层31及所述绝缘层5上并位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图4并配合图2所示，所述电极金属层形成步骤S205是将一电极金属层6形成在所述N型半导体层31及所述刻蚀阻挡层8上，且位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图4并配合图2所示，所述P型半导体层形成步骤S206是将一P型半导体层32形成在所述电极金属层6上且位于所述P型晶体管区102中，其中所述P型半导体层32包含一有机半导体材料。
续参照图4并配合图2所示，所述第二栅极层形成步骤S207是将一钝化层7形成在所述电极金属层6上且位于所述N型晶体管区101及所述P型晶体管区102中，接着将一第二栅极层42形成在所述钝化层7上且位于所述P型晶体管区102中。
利用上述的设计，本发明互补型薄膜晶体管100分别在所述N型晶体管区101形成N型薄膜晶体管，在所述P型晶体管区102形成P型薄膜晶体管，同时通过在所述刻蚀阻挡层8上覆盖一整层的所述电极金属层6，以确保所述P型半导体层32的沟道处表面的平整性，进而改善器件特性。
请参照图5并配合图3所示，是依照本发明所述第二优选实施例的互补型薄膜晶体管的制造方法的流程图，所述互补型薄膜晶体管的制造方法包含一第一栅极层形成步骤S201、一绝缘层形成步骤S202、一N型半导体层形成步骤S203、一刻蚀阻挡层形成步骤S204、一缓冲层形成步骤S208、一电极金属层形成步骤S205、一P型半导体层形成步骤S206及一第二栅极层形成步骤S207。
续参照图5并配合图3所示，所述第一栅极层形成步骤S201是在一基板2上定义相邻的一N型晶体管区101及一P型晶体管区102，并将一第一栅极层41形成在所述基板2上，并位于所述N型晶体管区101中。
续参照图4并配合图2所示，所述绝缘层形成步骤S202是将一绝缘层5形成在所述第一栅极层41及所述基板2上，且位于所述N型晶体管区101中。
续参照图5并配合图3所示，所述N型半导体层形成步骤S203是将一N型半导体层31形成在绝缘层5上且位于所述N型晶体管区101中，其中所述N型半导体层31包含一金属氧化物材料。
续参照图5并配合图3所示，所述刻蚀阻挡层形成步骤S204是将一刻蚀阻挡层8形成在所述N型半导体层31及所述绝缘层5上并位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图5并配合图3所示，所述缓冲层形成步骤S208是将一缓冲层9形成在整个所述刻蚀阻挡层8上并位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图5并配合图3所示，所述电极金属层形成步骤S205是将一电极金属层6形成在所述N型半导体层31及所述刻蚀阻挡层8上，且位于所述N型晶体管区101及所述P型晶体管区102中。
续参照图5并配合图3所示，所述P型半导体层形成步骤S206是将一P型半导体层32形成在所述电极金属层6上且位于所述P型晶体管区102中，其中所述P型半导体层32包含一有机半导体材料。
续参照图5并配合图3所示，所述第二栅极层形成步骤S207是将一钝化层7形成在所述电极金属层6上且位于所述N型晶体管区101及所述P型晶体管区102中，接着将一第二栅极层42形成在所述钝化层7上且位于所述P型晶体管区102中。
利用上述的设计，本发明互补型薄膜晶体管100’能够确保所述P型半导体层32的沟道处表面的平整性，进而改善器件特性。另外，当无机绝缘材料的所述刻蚀阻挡层8及有机半导体材料的所述P型半导体层32两者不能匹配时，通过采用有机材料的所述缓冲层9形成在整个所述刻蚀阻挡层8上，能够克服有机材料的不稳定及容易受到环境影响的问题，以优化原有的所述互补型薄膜晶体管的结构。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (19)

  1. 一种互补型薄膜晶体管，其中：所述互补型薄膜晶体管包含：
    一基板，定义有相邻的一N型晶体管区及一P型晶体管区；
    一N型半导体层，设置在所述基板上方且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料，且所述N型半导体层的金属氧化物材料选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物；
    一P型半导体层，设置在所述基板上方且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料；及
    一刻蚀阻挡层，形成在所述N型半导体层上并位于所述N型晶体管区及所述P型晶体管区中，且所述P型半导体层形成在所述刻蚀阻挡层上，且所述P型半导体层的有机半导体材料选自于并五苯、三苯基胺、富勒烯、酞菁、茈衍生物或花菁。
  2. 如权利要求1所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一第一栅极层及一绝缘层，其中所述第一栅极层形成在所述基板上且位于所述N型晶体管区，所述绝缘层形成在所述第一栅极层及所述基板上且位于所述N型晶体管区及所述P型晶体管区中，其中所述N型半导体层及所述刻蚀阻挡层形成在所述绝缘层上。
  3. 如权利要求2所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  4. 如权利要求2所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述P型晶体管区中。
  5. 如权利要求1所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一缓冲层，形成在整个所述刻蚀阻挡层上并位于所述N型晶体管区及所述P型晶体管区中。
  6. 如权利要求5所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  7. 如权利要求5所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述P型晶体管区中。
  8. 一种互补型薄膜晶体管，其中：所述互补型薄膜晶体管包含：
    一基板，定义有相邻的一N型晶体管区及一P型晶体管区；
    一N型半导体层，设置在所述基板上方且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；
    一P型半导体层，设置在所述基板上方且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料；及
    一刻蚀阻挡层，形成在所述N型半导体层上并位于所述N型晶体管区及所述P型晶体管区中，且所述P型半导体层形成在所述刻蚀阻挡层上。
  9. 如权利要求8所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一第一栅极层及一绝缘层，其中所述第一栅极层形成在所述基板上且位于所述N型晶体管区，所述绝缘层形成在所述第一栅极层及所述基板上且位于所述N型晶体管区及所述P型晶体管区中，其中所述N型半导体层及所述刻蚀阻挡层形成在所述绝缘层上。
  10. 如权利要求9所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  11. 如权利要求9所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述P型晶体管区中。
  12. 如权利要求8所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一缓冲层，形成在整个所述刻蚀阻挡层上并位于所述N型晶体管区及所述P型晶体管区中。
  13. 如权利要求12所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含一电极金属层，形成在位于所述N型晶体管区及所述P型晶体管区中，其中所述电极金属层形成在所述N型半导体层上，所述P型半导体层形成在所述电极金属层上。
  14. 如权利要求12所述的互补型薄膜晶体管，其中：所述互补型薄膜晶体管还包含：一钝化层，形成在所述电极金属层上且位于所述N型晶体管区及所述P型晶体管区中；及一第二栅极层，形成在所述钝化层上且位于所述P型晶体管区中。
  15. 如权利要求8所述的互补型薄膜晶体管，其中：所述N型半导体层的金属氧化物材料选自于铟镓锌氧化物、铟锌氧化物或锌锡氧化物。
  16. 如权利要求8所述的互补型薄膜晶体管，其中：所述P型半导体层的有机半导体材料选自于并五苯、三苯基胺、富勒烯、酞菁、茈衍生物或花菁。
  17. 一种互补型薄膜晶体管的制造方法，其中：所述制造方法包含步骤：
    一第一栅极层形成步骤，在一基板上定义相邻的一N型晶体管区及一P型晶体管区，并将一第一栅极层形成在所述基板上并位于所述N型晶体管区中；
    一绝缘层形成步骤，将一绝缘层形成在所述第一栅极层及所述基板上且位于所述N型晶体管区及所述P型晶体管区中；
    一N型半导体层形成步骤，将一N型半导体层形成在绝缘层上且位于所述N型晶体管区中，其中所述N型半导体层包含一金属氧化物材料；
    一刻蚀阻挡层形成步骤，将一刻蚀阻挡层形成在所述N型半导体层及所述绝缘层上并位于所述N型晶体管区及所述P型晶体管区中；
    一电极金属层形成步骤，将一电极金属层形成在所述N型半导体层上且位于所述N型晶体管区及所述P型晶体管区中；及
    一P型半导体层形成步骤，将一P型半导体层形成在所述电极金属层上且位于所述P型晶体管区中，其中所述P型半导体层包含一有机半导体材料。
  18. 如权利要求17所述的制造方法，其中：所述制造方法在所述刻蚀阻挡层形成步骤之后还包含一缓冲层形成步骤，将一缓冲层形成在整个所述刻蚀阻挡层上并位于所述N型晶体管区及所述P型晶体管区中。
  19. 如权利要求17所述的制造方法，其中：所述制造方法还包含在所述P型半导体层形成步骤之后的一第二栅极层形成步骤，将一钝化层形成在所述电极金属层上且位于所述N型晶体管区及所述P型晶体管区中，接着将一第二栅极层形成在所述钝化层上且位于所述P型晶体管区中。
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