CN207458949U - 薄膜晶体管、阵列基板和显示装置 - Google Patents
薄膜晶体管、阵列基板和显示装置 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 239000012212 insulator Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000007769 metal material Substances 0.000 claims abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
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- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 24
- 239000002184 metal Substances 0.000 abstract description 24
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- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
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- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
本申请公开了一种薄膜晶体管、阵列基板和显示装置,属于显示器领域。所述薄膜晶体管包括衬底基板、栅极层、栅极绝缘层、有源层和源漏极层,其特征在于,栅极层包括采用金属材料制成的第一栅极层、以及设置在第一栅极层和栅极绝缘层之间的第二栅极层,第二栅极层为掺杂的半导体材料层。本申请提供的薄膜晶体管的栅极由两个部分组成:采用金属制作的第一栅极层,以及采用掺杂的半导体材料制作第二栅极层,第二栅极层位于第一栅极层和栅极绝缘层之间,将相关设计中栅极与栅极绝缘层界面从金属/SiO变更为半导体/SiO,从而降低了栅极和栅极绝缘层之间的缺陷密度,降低了界面态。另外,通过调整第二栅极层的半导体的掺杂量,可以调整制作出的TFT的阈值电压。
Description
技术领域
本申请涉及显示器领域,特别涉及一种薄膜晶体管、阵列基板和显示装置。
背景技术
薄膜晶体管(英文Thin Film Transistor,简称TFT)是液晶显示器(英文 LiquidCrystal Display,简称LCD)的重要组成部件。通常,TFT按照其层级结构顺序不同可分为顶栅型TFT和底栅型TFT,以底栅型TFT为例,底栅型TFT 的基本结构包括衬底以及依次层叠设置在所述衬底上的栅极层、栅极绝缘层、有源层、源漏(英文Source/Drain,简称S/D)极以及绝缘保护层。
在TFT中,栅极的材料通常选择金属,如铜(Cu)、铝(Al)等,而栅极绝缘层则多采用二氧化硅、氮化硅等材料制成,采用上述材料制成的TFT,由于栅极与栅极绝缘层之间的材料晶格不匹配,造成栅极与栅极绝缘层之间晶格失配,存在大量界面态,影响TFT的性能;另外,TFT的阈值电压大小与栅极材料的功函数相关,当栅极采用某一种金属材料制作栅极时,由于金属材料功函数固定,所以TFT的阈值电压大小固定,造成采用某一种金属材料制作栅极时制作出的TFT的阈值电压单一,难以满足对阈值电压的多样化需求。
实用新型内容
本申请提供了一种薄膜晶体管、阵列基板和显示装置,可以解决相关技术中栅极与栅极绝缘层之间存在大量界面态,且TFT的阈值电压单一的问题。所述技术方案如下:
第一方面,本实用新型实施例提供了一种薄膜晶体管,所述薄膜晶体管包括衬底基板、栅极层、栅极绝缘层、有源层和源漏极层,所述栅极层包括采用金属材料制成的第一栅极层、以及设置在所述第一栅极层和所述栅极绝缘层之间的第二栅极层,所述第二栅极层为掺杂的半导体材料层。
在本实用新型实施例的一种实现方式中,所述有源层在所述衬底基板上的正投影位于所述第二栅极层在所述衬底基板上的正投影内,或者所述有源层在所述衬底基板上的正投影与所述第二栅极层在所述衬底基板上的正投重合。
在本实用新型实施例的另一种实现方式中,所述第二栅极层为N型重掺杂非晶硅层、P型重掺杂非晶硅层、铟镓锌氧化物层、N型低温多晶硅层或者P 型低温多晶硅层。
在本实用新型实施例的另一种实现方式中,所述第二栅极层的厚度为 300-500埃。
在本实用新型实施例的另一种实现方式中,所述第一栅极层为铜层或铝层,所述第一栅极层的厚度为3000-5000埃。
在本实用新型实施例的另一种实现方式中,所述栅极绝缘层为二氧化硅层、氮化硅层或氮氧化硅层。
在本实用新型实施例的另一种实现方式中,所述栅极层、所述栅极绝缘层、所述有源层和所述源漏极层依次层叠设置在所述衬底基板上。
在本实用新型实施例的另一种实现方式中,所述源漏极层、所述有源层、所述栅极绝缘层和所述栅极依次层叠设置在所述衬底基板上。
第二方面,本实用新型实施例还提供了一种阵列基板,所述阵列基板包括如第一方面任一项所述的薄膜晶体管。
第三方面,本实用新型实施例还提供了一种显示装置,所述显示装置包括如第二方面所述的阵列基板。
本实用新型实施例提供的技术方案带来的有益效果是:
在本申请提供的TFT中,TFT的栅极由两个部分组成:采用金属制作的第一栅极层,以及采用掺杂的半导体材料制作第二栅极层,第二栅极层位于第一栅极层和栅极绝缘层之间,将相关设计中栅极与栅极绝缘层界面从金属/SiO(或 SiN)变更为半导体/SiO(或SiN),半导体/SiO相比金属/SiO降低了栅极和栅极绝缘层之间的缺陷密度,降低了界面态,从而有效改善TFT的亚阈值摆幅(使 TFT开关速度更快)和迟滞性能、同时能够保证TFT阈值电压均一性,从而提升了TFT的性能。另外,通过调整第二栅极层的半导体的掺杂量,可以改变TFT 的栅极材料功函数,进而能够调整制作出的TFT的阈值电压。
附图说明
为了更清楚地说明本实用新型实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本实用新型实施例提供的一种薄膜晶体管的结构示意图;
图2是本实用新型实施例提供的另一种薄膜晶体管的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚,下面将结合附图对本申请实施方式作进一步地详细描述。
图1是本实用新型实施例提供的一种薄膜晶体管的结构示意图,参见图1,该薄膜晶体管包括衬底基板100、栅极层101、栅极绝缘层102、有源层103和源漏极层104。其中,所述栅极层101包括采用金属材料制成的第一栅极层1011、以及设置在所述第一栅极层1011和所述栅极绝缘层102之间的第二栅极层 1012,所述第二栅极层1012为掺杂的半导体材料层。
在该TFT中,TFT的栅极由两个部分组成:采用金属制作的第一栅极层,以及采用掺杂的半导体材料制作第二栅极层,第二栅极层位于第一栅极层和栅极绝缘层之间,将相关设计中栅极与栅极绝缘层界面从金属/SiO(或SiN)变更为半导体/SiO(或SiN),半导体/SiO相比金属/SiO降低了栅极和栅极绝缘层之间的缺陷密度,降低了界面态,从而有效改善TFT的亚阈值摆幅(使TFT开关速度更快)和迟滞性能、同时能够保证TFT阈值电压均一性,从而提升了TFT 的性能。另外,通过调整第二栅极层的半导体的掺杂量,可以改变TFT的栅极材料功函数,进而能够调整制作出的TFT的阈值电压。
下面结合公式对第二栅极层上述两方面的作用进行详细说明:
1、提升TFT的性能:
TFT的亚阈值摆幅S公式如下:
其中,K为波尔兹曼常数,T为温度,q为电子电荷,ε0为真空介电常数,εs为半导体(有源层)介电常数,Ci为栅极绝缘层电容,Ns为半导体(有源层) 中固定电荷数,Nit为界面缺陷态密度。
第一,第二栅极层与栅极绝缘层形成Si/SiO界面,对比传统金属/SiO界面,可降低界面缺陷,即上述公式中的Nit,可以有效改善TFT器件的亚阈值摆幅。第二,界面缺陷的多少也将影响半导体能带弯曲情况从而影响平带电压,造成阈值电压的不稳定性,本实用新型实施例大幅降低界面缺陷,对阈值电压均一性也起到改善作用。第三,TFT迟滞性能也与界面缺陷强相关,界面缺陷降低,也将对TFT的迟滞性能带来改善。
2、TFT的阈值电压
平带定压Vfb=(Ws-Wm)/q,平带定压是指使半导体能带拉平所需要施加的栅极电压;其中,Wm为栅极功函数,Ws为有源层功函数。通过调整第二栅极层的掺杂量,可以调整第二栅极的功函数Wm,从而调整Vfb的大小,而阈值电压Vth正是由平带电压Vfb以及沟道反型层形成电压Vt共同组成, Vth=Vfb+Vt,所以通过调节第二栅极层的掺杂量能够实现对阈值电压Vth的调整。
在本实用新型实施例中,所述第二栅极层1012可以为N型重掺杂非晶硅 (N+a-Si)层、P型重掺杂非晶硅(P+a-Si)层、铟镓锌氧化物(IGZO)层、N 型低温多晶硅(LTPS)层或者P型低温多晶硅层。采用这些材料制成的第二栅极层1012,一方面可以降低金属栅极与栅极绝缘层之间的界面态密度,另一方面可以通过调整掺杂量,实现对TFT阈值电压的调整。其中,IGZO层可以调整其中O的掺杂量,实现对TFT阈值电压的调整;在a-Si或LTPS中,N型掺杂可以为掺杂磷,P型掺杂可以为掺杂硼。当然,上述材料仅为示例,本实用新型实施例并不限制采用其他掺杂的半导体材料制作第二栅极层。
在本实用新型实施例中,所述第二栅极层1012的厚度可以为300-500埃。将第二栅极层1012制作为300-500埃,一方面能够保证第二栅极层1012成膜,另一方面该厚度的第二栅极层1012能够起到改善TFT性能、实现TFT阈值调节的效果。示例性地,第二栅极层1012的厚度可以为400或450埃。
在本实用新型实施例中,所述有源层103在所述衬底基板100上的正投影位于所述第二栅极层1012在所述衬底基板100上的正投影内,或者所述有源层 103在所述衬底基板100上的正投影与所述第二栅极层1012在所述衬底基板100 上的正投重合。也就是说,第二栅极层1012的尺寸需要保证能够将第一栅极层1011和有源层103之间重叠的区域完全覆盖,即保证第一栅极层1011与有源层103之间的部分(沟道区域)设置有第二栅极层1012。由于TFT的阈值电压大小和有源层在栅极上的投影区域相关联(也和栅极绝缘层相关联,但是本申请不讨论栅极绝缘层,假设该栅极绝缘层的影响是定值),所以在第二栅极层1012 将第一栅极层1011和有源层103之间重叠的区域完全覆盖时,有源层在栅极上的投影区域全部位于第二栅极层上,因此TFT的阈值电压大小只和第二栅极层相关,而与第一栅极层无关,这样就保证阈值电压只受第二栅极层的影响,从而实现阈值电压单一性,以及通过调节第二栅极层的掺杂浓度对阈值电压进行调控的目的。
示例性地,所述有源层103在所述衬底基板100上的正投影位于所述第二栅极层1012在所述衬底基板100上的正投影内,这种设计中,第二栅极层1012 的面积设计较大,而不是与有源层103完全对应,精度要求低,使得制作较为简单。
在本实用新型实施例中,所述第一栅极层1011可以为铜(Cu)层或铝(Al) 层。采用Cu或Al作为栅极金属材料,电阻小、导电性强,能够保证栅极的导电性能。
在本实用新型实施例中,所述第一栅极层1011的厚度可以为3000-5000埃。采用这种厚度的第一栅极层1011,保证整个栅极厚度不至于过大造成TFT整体厚度太大,同时,该厚度也不会造成由于第一栅极层1011厚度过小导致栅极导电性能差。
在本实用新型实施例中,所述栅极绝缘层102可以为二氧化硅层、氮化硅层或氮氧化硅层。采用上述材料制成的栅极绝缘层102绝缘性能好,且在使用上述双层结构的栅极后,能够减少栅极和栅极绝缘层102之间的界面态,提高 TFT整体性能。
本实用新型实施例提供的TFT既可以为底栅型TFT,也可以为顶栅型TFT。其中底栅型TFT结构如图1所示,栅极层101、所述栅极绝缘层102、所述有源层103和所述源漏极层104依次层叠设置在所述衬底基板100上。
在本实用新型实施例中,衬底100可以为透明衬底,例如玻璃衬底、硅衬底和塑料衬底等。
在本实用新型实施例中,有源层103可以使用非晶硅、微晶硅或者多晶硅制成。例如,有源层103可以包括设置在栅极绝缘层102上的非晶硅层1031和设置在非晶硅层1031上的N型掺杂非晶硅层1032。通过在非晶硅层上设置N 型掺杂非晶硅层,可以避免非晶硅层与源漏极直接接触,降低非晶硅层与源漏极之间的晶格失配。
在本实用新型实施例中,源漏极层104可以采用与第一栅极层1011相同的材料制成,如Cu、Al等。源漏极层104包括相对设置的源极1041和漏极1042。
进一步地,该薄膜晶体管还可以包括设置在源漏极层104上的钝化层105,通过设置钝化层105,可以对TFT起保护作用。其中,钝化层105可以为氮化硅或氮氧化硅层。该钝化层105上开设有过孔(图未示出),从而连通源漏极层104与设置在钝化层105上的像素电极层。
图2是本实用新型实施例提供的另一种薄膜晶体管的结构示意图,参见图2,该TFT为顶栅型TFT,在顶栅型TFT中,源漏极层104、所述有源层103、所述栅极绝缘层102和所述栅极层101依次层叠设置在所述衬底基板100上。
在顶栅型TFT中,第二栅极层1012设置在栅极绝缘层102上,第一栅极层 1011设置在第二栅极层1012上。
在顶栅型TFT中,N型掺杂非晶硅层1032设置在源漏极层104上,非晶硅层1031设置在N型掺杂非晶硅层1032上。
在顶栅型TFT中,钝化层105设置在栅极层101上。
下面分别简单介绍图1和图2中的栅极层101的制作过程。
图1中的栅极可以采用如下两种方式制作:
第一种,在衬底基板上制作一层金属层(例如采用蒸镀、溅射等方式);对所述金属层进行图形化处理,得到所述第一栅极层;在所述第一栅极层上,制作一层掺杂的半导体材料层(例如采用沉积等方式);对所述掺杂的半导体材料层进行图形化处理,得到所述第二栅极层。通过这种方式制作栅极,解决底栅型TFT栅极与栅极绝缘层之间存在大量界面态,且TFT的阈值电压难以调整的问题。在这种制作方式中,两个栅极层分别采用两次图形化工艺实现。
在第一种方式中,两个栅极层的图形化既可以采用干刻法实现,也可以采用湿刻法实现。
第二种,在衬底基板上制作一层金属层(例如采用蒸镀、溅射等方式);在所述金属层上,制作一层掺杂的半导体材料层(例如采用沉积等方式);对所述金属层和所述掺杂的半导体材料层进行图形化处理,得到所述第一栅极层和所述第二栅极层。通过这种方式制作栅极,解决底栅型TFT栅极与栅极绝缘层之间存在大量界面态,且TFT的阈值电压难以调整的问题。在这种制作方式中,两个栅极层通过一次图形化工艺实现。
在第二种方式中,两个栅极层采用一次图形化工艺处理时,既可以采用干刻法一步完成,也可以采用湿刻法通过先后使用两种刻蚀液两步完成。
图2中的栅极可以采用如下两种方式制作:
第一种,在所述薄膜晶体管的栅极绝缘层上,制作一层掺杂的半导体材料层(例如采用沉积等方式);对所述掺杂的半导体材料层进行图形化处理,得到所述第二栅极层;在所述第二栅极层上,制作一层金属层(例如采用蒸镀、溅射等方式);对所述金属层进行图形化处理,得到所述第一栅极层。通过这种方式制作栅极,解决顶栅型TFT栅极与栅极绝缘层之间存在大量界面态,且 TFT的阈值电压难以调整的问题。在这种制作方式中,两个栅极层分别采用两次图形化工艺实现。
第二种,在所述薄膜晶体管的栅极绝缘层上,制作一层掺杂的半导体材料层(例如采用沉积等方式);在所述掺杂的半导体材料层上,制作一层金属层 (例如采用蒸镀、溅射等方式);对所述掺杂的半导体材料层和所述金属层进行图形化处理,得到所述第一栅极层和所述第二栅极层。通过这种方式制作栅极,解决顶栅型TFT栅极与栅极绝缘层之间存在大量界面态,且TFT的阈值电压难以调整的问题。在这种制作方式中,两个栅极层通过一次图形化工艺实现。
本实用新型实施例还提供了一种阵列基板,阵列基板包括图1所示的薄膜晶体管。
本实用新型实施例提供的阵列基板的TFT中,TFT的栅极由两个部分组成:采用金属制作的第一栅极层,以及采用掺杂的半导体材料制作第二栅极层,第二栅极层位于第一栅极层和栅极绝缘层之间,将相关设计中栅极与栅极绝缘层界面从金属/SiO(或SiN)变更为半导体/SiO(或SiN),半导体/SiO相比金属 /SiO降低了栅极和栅极绝缘层之间的缺陷密度,降低了界面态,从而有效改善 TFT的亚阈值摆幅(使TFT开关速度更快)和迟滞性能、同时能够保证TFT阈值电压均一性,从而提升了TFT的性能。另外,通过调整第二栅极层的半导体的掺杂量,可以改变TFT的栅极材料功函数,进而能够调整制作出的TFT的阈值电压。
本实用新型实施例还提供了一种显示装置,该显示装置包括前文所述的阵列基板。
在具体实施时,本实用新型实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实用新型实施例提供的显示装置的TFT中,TFT的栅极由两个部分组成:采用金属制作的第一栅极层,以及采用掺杂的半导体材料制作第二栅极层,第二栅极层位于第一栅极层和栅极绝缘层之间,将相关设计中栅极与栅极绝缘层界面从金属/SiO(或SiN)变更为半导体/SiO(或SiN),半导体/SiO相比金属 /SiO降低了栅极和栅极绝缘层之间的缺陷密度,降低了界面态,从而有效改善 TFT的亚阈值摆幅(使TFT开关速度更快)和迟滞性能、同时能够保证TFT阈值电压均一性,从而提升了TFT的性能。另外,通过调整第二栅极层的半导体的掺杂量,可以改变TFT的栅极材料功函数,进而能够调整制作出的TFT的阈值电压。
以上仅为本申请的较佳实施例,并不用以限制本申请,凡在本申请的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。
Claims (10)
1.一种薄膜晶体管,所述薄膜晶体管包括衬底基板、栅极层、栅极绝缘层、有源层和源漏极层,其特征在于,所述栅极层包括采用金属材料制成的第一栅极层、以及设置在所述第一栅极层和所述栅极绝缘层之间的第二栅极层,所述第二栅极层为掺杂的半导体材料层。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述有源层在所述衬底基板上的正投影位于所述第二栅极层在所述衬底基板上的正投影内,或者所述有源层在所述衬底基板上的正投影与所述第二栅极层在所述衬底基板上的正投重合。
3.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述第二栅极层为N型重掺杂非晶硅层、P型重掺杂非晶硅层、铟镓锌氧化物层、N型低温多晶硅层或者P型低温多晶硅层。
4.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述第二栅极层的厚度为300-500埃。
5.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述第一栅极层为铜层或铝层,所述第一栅极层的厚度为3000-5000埃。
6.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述栅极绝缘层为二氧化硅层、氮化硅层或氮氧化硅层。
7.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述栅极层、所述栅极绝缘层、所述有源层和所述源漏极层依次层叠设置在所述衬底基板上。
8.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述源漏极层、所述有源层、所述栅极绝缘层和所述栅极依次层叠设置在所述衬底基板上。
9.一种阵列基板,其特征在于,所述阵列基板包括如权利要求1-8任一项所述的薄膜晶体管。
10.一种显示装置,其特征在于,所述显示装置包括如权利要求9所述的阵列基板。
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Cited By (4)
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WO2019062738A1 (zh) * | 2017-09-26 | 2019-04-04 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板和显示装置 |
CN109659235A (zh) * | 2018-12-14 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | Tft的制备方法、tft、阵列基板及显示装置 |
WO2022120746A1 (zh) * | 2020-12-10 | 2022-06-16 | 昆山龙腾光电股份有限公司 | 阵列基板及其制作方法和显示面板 |
CN115377208A (zh) * | 2021-05-20 | 2022-11-22 | 合肥京东方显示技术有限公司 | 薄膜晶体管及其制造方法、阵列基板、显示面板和装置 |
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KR20120138074A (ko) * | 2011-06-14 | 2012-12-24 | 삼성디스플레이 주식회사 | 박막 트랜지스터, 및 박막 트랜지스터 표시판과 이들을 제조하는 방법 |
KR101971925B1 (ko) * | 2012-09-19 | 2019-08-19 | 삼성디스플레이 주식회사 | 박막 트랜지스터 어레이 기판 및 유기 발광 표시 장치 |
KR102223971B1 (ko) * | 2014-06-11 | 2021-03-10 | 삼성전자주식회사 | 결정성의 다중-나노시트 스트레인 채널 전계 효과 트랜지스터 및 그 제조 방법 |
CN207458949U (zh) * | 2017-09-26 | 2018-06-05 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板和显示装置 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2019062738A1 (zh) * | 2017-09-26 | 2019-04-04 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板和显示装置 |
CN109659235A (zh) * | 2018-12-14 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | Tft的制备方法、tft、阵列基板及显示装置 |
CN109659235B (zh) * | 2018-12-14 | 2021-12-03 | 武汉华星光电半导体显示技术有限公司 | Tft的制备方法、tft、阵列基板及显示装置 |
WO2022120746A1 (zh) * | 2020-12-10 | 2022-06-16 | 昆山龙腾光电股份有限公司 | 阵列基板及其制作方法和显示面板 |
CN115377208A (zh) * | 2021-05-20 | 2022-11-22 | 合肥京东方显示技术有限公司 | 薄膜晶体管及其制造方法、阵列基板、显示面板和装置 |
WO2022242028A1 (zh) * | 2021-05-20 | 2022-11-24 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制造方法、阵列基板、显示面板和装置 |
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US20190371904A1 (en) | 2019-12-05 |
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