WO2022120746A1 - 阵列基板及其制作方法和显示面板 - Google Patents

阵列基板及其制作方法和显示面板 Download PDF

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Publication number
WO2022120746A1
WO2022120746A1 PCT/CN2020/135371 CN2020135371W WO2022120746A1 WO 2022120746 A1 WO2022120746 A1 WO 2022120746A1 CN 2020135371 W CN2020135371 W CN 2020135371W WO 2022120746 A1 WO2022120746 A1 WO 2022120746A1
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Prior art keywords
layer
semiconductor layer
electrode
metal oxide
oxide semiconductor
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PCT/CN2020/135371
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English (en)
French (fr)
Inventor
钟德镇
蔡志承
郑会龙
王新刚
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昆山龙腾光电股份有限公司
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Application filed by 昆山龙腾光电股份有限公司 filed Critical 昆山龙腾光电股份有限公司
Priority to PCT/CN2020/135371 priority Critical patent/WO2022120746A1/zh
Priority to US18/013,898 priority patent/US20230290788A1/en
Priority to CN202080014831.8A priority patent/CN113454783B/zh
Publication of WO2022120746A1 publication Critical patent/WO2022120746A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display panel having the array substrate.
  • the liquid crystal display panel (Liquid Crystal Display, LCD) is more and more popular because of its advantages of light weight and low radiation.
  • the liquid crystal display panel includes opposing color filter substrates (Color filter, CF) and thin film transistor array substrate (Thin film transistor array substrate, TFT array) and the liquid crystal layer (Liquid crystal layer, LC layer).
  • Amorphous silicon (a-Si) is currently the most widely used semiconductor layer material in the semiconductor industry. Due to the large potential energy difference between a-Si material and metal, it is difficult to form ohmic contact. In practical applications, in order to obtain metal and semiconductor For the ohmic contact between the semiconductors, the surface of the semiconductor is generally heavily doped with P (phosphorus) element, which reduces the contact resistance between the metal and the semiconductor and improves the current efficiency.
  • the off-state leakage current (Ioff) of amorphous silicon TFT (thin film transistor) is larger than 10-11 ⁇ 10-12A, and the Ion/Ioff (ratio of on-state current to off-state current) is only 106, and it is driven at low frequency below 30Hz.
  • FIG. 1 is a schematic cross-sectional view of a conventional array substrate.
  • the array substrate includes a base 1, a gate 2 disposed on the base 1, a gate insulating layer 3 disposed on the base 1 and covering the gate 2, and an amorphous electrode corresponding to the gate 2 and disposed on the gate insulating layer 3.
  • the middle portion of the doped amorphous silicon 5 is recessed downward and forms a channel above the corresponding gate 2 .
  • FIG. 2 is a graph showing the leakage current of the a-Si device with the array substrate in FIG. 1 . It can be seen from FIG. 2 that while the array substrate structure of FIG. 1 increases the operating current (Ion), there is also a certain question.
  • the purpose of the present invention is to provide an array substrate and a manufacturing method thereof, so as to solve the problem that the off-state leakage current of the a-Si device of the array substrate in the prior art is relatively large, resulting in low frequency display. less effective problem.
  • the present invention provides an array substrate, comprising:
  • a gate disposed on the substrate
  • a first semiconductor layer and a second semiconductor layer are provided on the first insulating layer, the second semiconductor layer is stacked on the first semiconductor layer, and the first semiconductor layer is an amorphous silicon layer, so The second semiconductor layer is a metal oxide semiconductor layer, and a channel corresponding to the gate is provided on the first semiconductor layer and the second semiconductor layer;
  • the second semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer arranged in layers, and both the first metal oxide semiconductor layer and the second metal oxide semiconductor layer are located in the groove.
  • the channel is disconnected, and the oxygen vacancy concentration of the second metal oxide semiconductor layer is smaller than the oxygen vacancy concentration of the first metal oxide semiconductor layer;
  • a source electrode and a drain electrode are provided on the second semiconductor layer, and both the source electrode and the drain electrode are in conductive contact with the second semiconductor layer.
  • the first semiconductor layer includes a stacked amorphous silicon layer and a doped amorphous silicon layer, and the doped amorphous silicon layer is disconnected at the channel.
  • the amorphous silicon layer, the doped amorphous silicon layer, the first metal oxide semiconductor layer and the second metal oxide semiconductor layer are directly above the gate from bottom to top
  • the settings are stacked one after the other.
  • both the first metal oxide semiconductor layer and the second metal oxide semiconductor layer are indium gallium zinc oxide.
  • the source electrode and the drain electrode cover the second metal oxide semiconductor layer, and the second metal oxide semiconductor layer is divided into two parts by the channel.
  • the drains are in conductive contact with the two parts, respectively.
  • the second semiconductor layer covers the top and both sides of the first semiconductor layer, and the second semiconductor layer separates the first semiconductor layer from the source electrode and the drain electrode.
  • the array substrate further includes a second insulating layer, a flat layer, a first electrode layer, a third insulating layer and a second electrode layer, and the second insulating layer is disposed on the first insulating layer and covers all the source electrode and the drain electrode, the flat layer is arranged on the second insulating layer, the first electrode layer is arranged on the flat layer, and the third insulating layer is arranged on the flat layer and cover the first electrode layer, the third insulating layer, the flat layer and the second insulating layer are provided with contact holes corresponding to the source electrodes, and the second electrode layer is provided on the The third insulating layer is in conductive contact with the source electrode through the contact hole.
  • the array substrate further includes a second insulating layer, a first electrode layer and a second electrode layer, the second electrode layer is provided on the first insulating layer and is in conductive contact with the source electrode, the A second insulating layer is disposed on the first insulating layer and covers the source electrode, the drain electrode and the second electrode layer, and the first electrode layer is disposed on the second insulating layer.
  • the array substrate further includes a second insulating layer and a second electrode layer, the second insulating layer is disposed on the first insulating layer and covers the source electrode and the drain electrode, the second insulating layer is The insulating layer is provided with a contact hole corresponding to the source electrode, and the second electrode layer is provided on the second insulating layer and is in conductive contact with the source electrode through the contact hole.
  • the present invention also provides a method for fabricating an array substrate, comprising:
  • a first semiconductor layer and a second semiconductor layer are formed on the first insulating layer, the second semiconductor layer is stacked on the first semiconductor layer, the first semiconductor layer is an amorphous silicon layer, and the The second semiconductor layer is a metal oxide semiconductor layer, the second semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer that are stacked and arranged, and the oxygen vacancy concentration of the second metal oxide semiconductor layer is less than the oxygen vacancy concentration of the first metal oxide semiconductor layer;
  • a source electrode and a drain electrode on the second semiconductor layer, the source electrode and the drain electrode are both in conductive contact with the second semiconductor layer;
  • the second semiconductor layer and the first semiconductor layer are etched to form a channel.
  • the first semiconductor layer includes an amorphous silicon layer and a doped amorphous silicon layer, and an amorphous silicon film, a doped amorphous silicon film, and a first metal oxide are successively deposited on the first insulating layer. semiconductor thin film and second metal oxide semiconductor thin film, and then etching the amorphous silicon thin film, the doped amorphous silicon thin film, the first metal oxide semiconductor thin film and the second metal oxide semiconductor thin film , so as to form an island-shaped semiconductor structure directly above the gate.
  • the first semiconductor layer includes an amorphous silicon layer and a doped amorphous silicon layer, and an amorphous silicon film and a doped amorphous silicon film are sequentially deposited on the first insulating layer.
  • the silicon film and the doped amorphous silicon film are etched to form an island-like structure just above the gate, and then a first metal oxide semiconductor film and a second metal film are successively deposited on the first insulating layer.
  • the oxide semiconductor thin film covers the first semiconductor layer, and the first metal oxide semiconductor thin film and the second metal oxide semiconductor thin film are etched to form an island-like structure just above the gate, so
  • the second semiconductor layer covers the top and both sides of the first semiconductor layer, and the second semiconductor layer separates the first semiconductor layer from the source electrode and the drain electrode.
  • a first metal layer is deposited on the substrate, and the first metal layer is etched to form the gate electrode; on the second semiconductor
  • a second metal layer is deposited on the first insulating layer and covers the first semiconductor layer and the second semiconductor layer, and the second metal layer is etched to form
  • a first through hole is formed between the source electrode and the drain electrode, and the first through hole corresponds to a position where the channel will be formed in the future.
  • the source electrode and the drain electrode are used as shields, and the second semiconductor layer is exposed to the second semiconductor layer through the first through hole.
  • the semiconductor layer is etched to form a second through hole, and the first semiconductor layer is exposed from the second through hole, and then the first semiconductor layer is etched through the second through hole, so that the doping
  • the amorphous silicon film is etched and disconnected to form a third through hole, and the channel is formed by the second through hole and the third through hole, wherein the amorphous silicon film is etched to form the amorphous silicon
  • the doped amorphous silicon film forms the doped amorphous silicon layer after etching
  • the first metal oxide semiconductor film forms the first metal oxide semiconductor layer after etching
  • the second metal oxide semiconductor film forms the first metal oxide semiconductor layer after etching.
  • the metal oxide semiconductor thin film forms the second metal oxide semiconductor layer after etching.
  • the first metal oxide semiconductor layer is prepared by annealing indium gallium zinc oxide in a nitrogen atmosphere at a temperature of 300°C to 450°C and a time of 20 to 60 minutes;
  • the second metal oxide semiconductor layer It is prepared by indium gallium zinc oxide under the conditions of sputtering power of 80-110W and oxygen partial pressure of 5%-9%, or the second metal oxide semiconductor layer is processed by indium gallium zinc oxide plasma treatment process It is prepared by N-type doping, or the second metal oxide semiconductor layer is prepared by plasma conduction treatment of indium gallium zinc oxide.
  • a second insulating layer and a planarization layer are sequentially formed on the first insulating layer, and the second insulating layer covers the source electrode, the drain electrode and the channel;
  • a second transparent electrode film covering the contact hole is formed on the third insulating layer, the second transparent electrode film is etched to form a second electrode layer, and the second electrode layer is connected to the contact hole through the contact hole.
  • the source conductive contact is formed on the third insulating layer, the second transparent electrode film is etched to form a second electrode layer, and the second electrode layer is connected to the contact hole through the contact hole.
  • a second transparent electrode film is formed on the first insulating layer, and the second transparent electrode film is etched to form a second electrode layer;
  • a second insulating layer covering the source electrode, the drain electrode, the channel and the second electrode layer is formed, and a first metal layer is formed on the second insulating layer.
  • the metal layer is etched and a first electrode layer is formed.
  • a second insulating layer is formed on the first insulating layer, the second insulating layer covers the source electrode, the drain electrode and the channel, and the second insulating layer is etched to form a The contact hole corresponding to the source;
  • a second transparent electrode film covering the contact hole is formed on the second insulating layer, the second transparent electrode film is etched to form a second electrode layer, and the second electrode layer is connected to the contact hole through the contact hole.
  • the source is conductively contacted.
  • the present invention also provides a display panel, comprising a color filter substrate, a liquid crystal layer, and the above-mentioned array substrate, wherein the color filter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is disposed between the color filter substrate and the array substrate. between the array substrates.
  • a first semiconductor layer and a second semiconductor layer are stacked on the base of the array substrate, wherein the first semiconductor layer is an amorphous silicon layer, the second semiconductor layer is a metal oxide semiconductor layer, and the second semiconductor layer includes a stacked first semiconductor layer.
  • the oxygen vacancy concentration of the second metal oxide semiconductor layer is lower than the oxygen vacancy concentration of the first metal oxide semiconductor layer; the source electrode and the second metal oxide semiconductor layer are arranged on the second semiconductor layer A drain electrode, and both the source electrode and the drain electrode are in conductive contact with the second metal oxide semiconductor layer.
  • Ordinary a-Si can be improved by depositing two metal oxide semiconductor layers with different oxygen vacancy concentrations over the first semiconductor layer TFT has the problem of high off-state leakage current, which can realize low-frequency driving.
  • the display panel can be switched to low-frequency refresh mode when displaying still pictures or in standby, so as to reduce power consumption and reduce power consumption.
  • the extremely high contact resistance can effectively increase the on-state current and improve the response speed.
  • FIG. 1 is a schematic structural diagram of an array substrate in the prior art
  • FIG. 2 is a-Si of the array substrate in FIG. 1 Graph of leakage current of TFT devices
  • Figure 3 is a-Si TFT devices and a-IGZO Graph of leakage current of TFT devices
  • FIG. 4 is a schematic structural diagram of a TFT device of an array substrate in the present invention.
  • FIG. 6 is a graph showing the leakage current of the TFT device of the array substrate in the first embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a display panel in Embodiment 1 of the present invention.
  • Embodiment 8 is a schematic structural diagram of an array substrate in Embodiment 2 of the present invention.
  • Embodiment 9 is a schematic structural diagram of an array substrate in Embodiment 3 of the present invention.
  • FIG. 10 is a schematic structural diagram of an array substrate in Embodiment 4 of the present invention.
  • FIGS. 5a-5j are a flow chart of the fabrication of the array substrate in Embodiment 1 of the present invention.
  • an array substrate provided by Embodiment 1 of the present invention includes:
  • the substrate 10 may be made of glass, quartz, acrylic, or polycarbonate.
  • the gate 11 is disposed on the substrate 10, and the gate 11 and the scan line (not shown) are located in the same layer and are electrically connected.
  • the material is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.
  • the first semiconductor layer 12 and the second semiconductor layer 13 are provided on the first insulating layer 101 , and the second semiconductor layer 13 is stacked on the first semiconductor layer 12 .
  • the first semiconductor layer 12 is specifically an amorphous silicon layer, including a stacked amorphous silicon layer (a-Si) 121 and a doped amorphous silicon layer (n+a-Si) 122.
  • the doped amorphous silicon layer 122 is used for In order to reduce the contact resistance between the amorphous silicon layer 121 and the second semiconductor layer 13 .
  • the first semiconductor layer 12 has an island structure and is disposed directly above the gate electrode 11 .
  • the projected area of the first semiconductor layer 12 on the substrate 10 is smaller than the projected area of the gate electrode 11 on the substrate 10 .
  • the second semiconductor layer 13 is specifically a metal oxide semiconductor layer, and includes a first metal oxide semiconductor layer 131 and a second metal oxide semiconductor layer 132 that are stacked in layers, and the oxygen vacancy concentration of the second metal oxide semiconductor layer 132 is lower than that of the first metal oxide semiconductor layer 132
  • the oxygen vacancy concentration of the metal oxide semiconductor layer 131, the second metal oxide semiconductor layer 132 is used to reduce the contact resistance between the first metal oxide semiconductor layer 131 and the source electrode 141 and the drain electrode 142, the amorphous silicon layer 121, The doped amorphous silicon layer 122 , the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132 are sequentially stacked from bottom to top.
  • the second semiconductor layer 13 has an island structure and is disposed directly above the gate 11 .
  • the projected area of the second semiconductor layer 13 on the substrate 10 is smaller than the projected area of the first semiconductor layer 12 on the substrate 10 .
  • the amorphous silicon layer 121 , the doped amorphous silicon layer 122 , the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132 are stacked in order from bottom to top right above the gate 11 .
  • the first semiconductor layer 12 and the second semiconductor layer 13 are provided with a channel 110 corresponding to the gate electrode 11 , and the doped amorphous silicon layer 122 , the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132 are all formed thereon.
  • the channel 110 is open.
  • the holes on the back channel at the interface of the first semiconductor layer 12 and the second insulating layer 102 participate in conduction to form a back channel current.
  • thermions are generated between the gate electrode 141 and the drain electrode 142 to emit holes to form hole carriers, at the interface between the first semiconductor layer 12 and the second insulating layer 102 A hole accumulation is formed, resulting in a hole current.
  • the front channel (the part of the channel close to the surface of the amorphous silicon layer 121 ) is the main conduction channel of the TFT device, and the corresponding back channel (the part of the channel far from the surface of the amorphous silicon layer 121 ) is hole-carrying Substance is the main conductive medium.
  • the source electrode 141 and the drain electrode 142 disposed on the second semiconductor layer 13, the source electrode 141, the drain electrode 142 and the data line (not shown) are located in the same layer and made of the same layer of metal, and the source electrode 141 and the drain electrode 142
  • the electrodes 142 are all in conductive contact with the second semiconductor layer 13 , and the source electrodes 141 and the drain electrodes 142 are spaced apart at the channel 110 .
  • the source electrode 141 and the drain electrode 142 are disposed on and cover the second metal oxide semiconductor layer 132, and the second metal oxide semiconductor layer 132 is divided into two parts by the channel 110,
  • the source electrode 141 and the drain electrode 142 are respectively in conductive contact with the two parts.
  • the array substrate further includes a second insulating layer 102 , a flat layer 103 , a first electrode layer 15 , a third insulating layer 104 and a second electrode layer 16 .
  • the second insulating layer 102 is provided on the first insulating layer 101 and covers the source electrode 141 and the drain electrode 142
  • the flat layer 103 is provided on the second insulating layer 102
  • the first electrode layer 15 is provided on the flat layer 103
  • the layer 104 is provided on the flat layer 103 and covers the first electrode layer 15, the third insulating layer 104, the flat layer 103 and the second insulating layer 102 are provided with contact holes 105 corresponding to the source electrode 141
  • the second electrode layer 16 is provided with a contact hole 105 corresponding to the source electrode 141.
  • the first electrode layer 15 serves as a common electrode
  • the second electrode layer 16 serves as a pixel electrode.
  • the common electrode 15 and the pixel electrode 16 are located in different layers and are insulated and isolated by the third insulating layer 104 .
  • the common electrode 15 may be located above or below the pixel electrode 16 (in FIG. 5j, the common electrode 15 is shown below the pixel electrode 16).
  • the common electrode 15 is a planar electrode provided on the entire surface
  • the pixel electrode 16 is a block electrode provided integrally in each pixel unit or a slit electrode with a plurality of electrode strips, so as to form a fringe field switching mode ( Fringe Field Switching, FFS).
  • FFS Fringe Field Switching
  • the pixel electrode 16 and the common electrode 15 may be located in the same layer, but they are insulated and isolated from each other.
  • Each of the pixel electrode 16 and the common electrode 15 may include a plurality of electrode strips. and the electrode strips of the common electrode 15 are alternately arranged to form an in-plane switching mode (In-Plane Switching, IPS).
  • the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132 are both made of indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO).
  • the oxygen vacancy concentration of the second metal oxide semiconductor layer 132 is smaller than that of the first metal oxide semiconductor layer 131, and the indium gallium zinc oxide can be deposited by methods such as magnetron sputtering or thermal evaporation, wherein oxygen The vacancy concentration represents the oxygen content in the metal oxide semiconductor layer, and a higher oxygen vacancy concentration represents a lower oxygen content, and a lower oxygen vacancy concentration represents a higher oxygen content.
  • a first metal oxide semiconductor layer 131 with a high oxygen vacancy concentration is deposited over the first semiconductor layer 12, and the first metal oxide semiconductor layer 131 with a high oxygen vacancy concentration can effectively inhibit a-Si The hole carriers generated in the off state of the TFT are turned on, thereby effectively reducing a-Si The off-state leakage current of the TFT cut-off region.
  • a second metal oxide semiconductor layer 132 with a low oxygen vacancy concentration is deposited over the first metal oxide semiconductor layer 131 with a high oxygen vacancy concentration to form an n+IGZO layer, so that the second metal oxide semiconductor layer 132 is connected to the source electrode 141 , the drain 142 forms an Ohmic contact, which reduces the contact resistance of the source 141, the drain 142 and the second metal oxide semiconductor layer 132, effectively increases the on-state current, and improves the response speed.
  • a-IGZO fabricated with indium gallium zinc oxide TFT devices although the leakage current is relative to a-Si TFT devices are much smaller, a-IGZO TFT off-state leakage current ratio a-Si TFT is two orders of magnitude lower, about 10-13 ⁇ 10-14A left and right, but a-IGZO TFT has the problem of complex process and high sensitivity to the process environment.
  • the threshold voltage (Vth) shift in high temperature or low temperature environment is serious, and it is more sensitive to environmental water vapor, O (oxygen) atoms or H (hydrogen) atoms, which will make IGZO thin film transistors fail due to the infiltration of water vapor, O atoms or H atoms. .
  • the present application improves the ordinary a-Si by depositing two metal oxide semiconductor layers with different oxygen vacancy concentrations above the first semiconductor layer 12.
  • TFT has the problem of high off-state leakage current, which can realize low-frequency driving.
  • the display panel can switch to low-frequency refresh mode when displaying still pictures or in standby, so as to reduce power consumption and avoid indium-gallium-zinc oxide being affected.
  • Environmental influences lead to serious problems with threshold voltage (Vth) shifts, as shown in Figure 6.
  • the present application further provides a display panel, which includes a color filter substrate 20 , a liquid crystal layer 30 and the above-mentioned array substrate.
  • the color filter substrate 20 is disposed opposite to the array substrate, and the liquid crystal layer 30 is disposed on the color filter substrate. 20 and the array substrate.
  • positive liquid crystal molecules that is, liquid crystal molecules with positive dielectric anisotropy
  • the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color filter substrate 20 and the array substrate, and the positive liquid crystal molecules on the side of the color filter substrate 20 are aligned with the array substrate.
  • the alignment directions of the positive liquid crystal molecules on the side are parallel or anti-parallel.
  • the color filter substrate 20 is provided with color resist layers 22 arranged in an array and a black matrix 21 separating the color resist layers 22.
  • the color resist layers 22 include three colors of red (R), green (G) and blue (B). color resist material, and correspondingly form sub-pixels of red (R), green (G), and blue (B) colors.
  • the present application also provides a method for fabricating an array substrate, the fabrication method comprising:
  • a substrate 10 is provided, which may be made of glass, quartz, acrylic, or polycarbonate, among other materials.
  • a patterned gate 11 is formed on the substrate 10. Specifically, as shown in FIG. 5a, a first metal layer is deposited on the substrate 10, and an etching process is used to pattern the first metal layer to form the gate 11 and scan lines (Fig. not shown).
  • a first insulating layer 101 covering the gate electrode 11 is formed on the substrate 10. Specifically, as shown in FIG. 5b, a first insulating layer 101 covering the gate electrode 11 and the scan lines is deposited on the substrate 10, and the first insulating layer 101 is the gate electrode.
  • the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
  • the first semiconductor layer 12 and the second semiconductor layer 13 are formed on the first insulating layer 101 , and the second semiconductor layer 13 is stacked on the first semiconductor layer 12 .
  • the first semiconductor layer 12 is specifically an amorphous silicon layer, including a stacked amorphous silicon layer 121 and a doped amorphous silicon layer 122 .
  • the second semiconductor layer 13 is specifically a metal oxide semiconductor layer, including a first metal oxide semiconductor layer 131 and a second metal oxide semiconductor layer 132 that are stacked and arranged, an amorphous silicon layer 121, a doped amorphous silicon layer 122, a A metal oxide semiconductor layer 131 and a second metal oxide semiconductor layer 132 are sequentially stacked from bottom to top. Specifically, as shown in FIG.
  • an amorphous silicon film 121 a , a doped amorphous silicon film 122 a , a first metal oxide semiconductor film 131 a and a second metal oxide semiconductor film 132 a are successively deposited on the first insulating layer 101 .
  • the amorphous silicon film 121a, the doped amorphous silicon film 122a, the first metal oxide semiconductor film 131a and the The metal oxide semiconductor thin film 132a is etched to form an island-shaped semiconductor layer structure directly above the gate electrode 11, but at this time, the channel 110 is not etched first.
  • the second semiconductor layer 13 may be etched first by using an etchant capable of etching the second semiconductor layer 13 , and then the second semiconductor layer 13 may be shielded by using an etchant capable of etching the first semiconductor layer 12 .
  • the first semiconductor layer 12 is etched.
  • a source electrode 141 and a drain electrode 142 are formed on the second semiconductor layer 13 , and both the source electrode 141 and the drain electrode 142 are in conductive contact with the second semiconductor layer 13 .
  • the second metal layer 14 is deposited on the first insulating layer 101 and covers the first semiconductor layer 12 and the second semiconductor layer 13 .
  • the second metal layer 14 is patterned by an etching process to form a source electrode 141, a drain electrode 142 and a data line (not shown), a first through hole 143 is formed between the source electrode 141 and the drain electrode 142, The first through hole 143 corresponds to the position where the channel 110 will be formed in the future.
  • the second semiconductor layer 13 is protected by the dense second metal layer 14 , and the surface is less affected by subsequent processes. It is difficult for water vapor, O atoms or H atoms to contact the IGZO film in the external environment, and the film characteristics are protected.
  • the second semiconductor layer 13 and the first semiconductor layer 12 are etched to form the channel 110 .
  • the second semiconductor layer 13 is etched through the first through hole 143 to form a second through hole 133 , and the first through hole 133 is exposed.
  • semiconductor layer 12 As shown in FIG. 5g, the first semiconductor layer 12 is etched through the second through hole 133, and the etching time is controlled so that the doped amorphous silicon film 122a is etched and disconnected to form the third through hole 123 and the amorphous silicon layer 121.
  • the channel 110 is formed by the second via 133 and the third via 123 .
  • different etching solutions can be used to etch the second semiconductor layer 13 and the first semiconductor layer 12 .
  • the amorphous silicon film 121a forms the amorphous silicon layer 121 after etching
  • the doped amorphous silicon film 122a forms the doped amorphous silicon layer 122 after etching
  • the first metal oxide semiconductor film 131a forms the first metal oxide after etching
  • the material semiconductor layer 131 and the second metal oxide semiconductor thin film 132a are etched to form a second metal oxide semiconductor layer 132.
  • a second insulating layer 102 and a planarization layer 103 are sequentially formed on the first insulating layer 101 , and the second insulating layer 102 covers the source electrode 141 , the drain electrode 142 and the channel 110 .
  • a first transparent electrode film is formed on the flat layer 103, and the first transparent electrode film is etched to form a first electrode layer 15, and the first electrode layer 15 serves as a common electrode.
  • FIG. 5i a first transparent electrode film is formed on the flat layer 103, and the first transparent electrode film is etched to form a first electrode layer 15, and the first electrode layer 15 serves as a common electrode.
  • a third insulating layer 104 is formed on the first electrode layer 15, and the third insulating layer 104, the flat layer 103 and the second insulating layer 102 are etched to form a contact hole 105 corresponding to the source electrode 141, so that the source electrode 141 is exposed from the contact hole 105, and then a second transparent electrode film covering the contact hole 105 is formed on the third insulating layer 104, and the second transparent electrode film is etched to form a second electrode layer 16.
  • the hole 105 is in conductive contact with the source electrode 141, and the second electrode layer 16 serves as a pixel electrode.
  • the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132 are both made of indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium gallium zinc oxide can be deposited by methods such as magnetron sputtering or thermal evaporation.
  • the oxygen vacancy concentration of the second metal oxide semiconductor layer 132 is smaller than the oxygen vacancy concentration of the first metal oxide semiconductor layer 131, so that the second metal oxide semiconductor layer 132 forms an n+IGZO layer, and the second metal oxide semiconductor layer 132 forms an n+IGZO layer.
  • the layer 132 forms ohmic contact with the source electrode 141 and the drain electrode 142, which effectively reduces the contact resistance between the source electrode 141, the drain electrode 142 and the second metal oxide semiconductor layer 132, effectively increases the on-state current, and improves the response speed.
  • the first metal oxide semiconductor layer 131 is obtained by annealing indium gallium zinc oxide in a nitrogen atmosphere at a temperature of 300° C. to 450° C. and a time of 20 to 60 minutes; the second metal oxide semiconductor layer 132 is made of indium
  • the gallium zinc oxide is prepared under the conditions that the sputtering power is 80-110W and the oxygen partial pressure is 5%-9%, so that the second metal oxide semiconductor layer 132 is smaller than the oxygen vacancies of the first metal oxide semiconductor layer 131
  • the concentration reduces the contact resistance between the second metal oxide semiconductor layer 132 and the source electrode 141 and the drain electrode 142 .
  • the second metal oxide semiconductor layer 132 is prepared by performing N-type doping through an indium gallium zinc oxide plasma treatment process to form an n+IGZO region, so that the oxygen vacancy concentration of the second metal oxide semiconductor layer 132 is reduced.
  • the oxygen vacancy concentration of the first metal oxide semiconductor layer 131 is lower than that of the first metal oxide semiconductor layer 131, which reduces the contact resistance between the second metal oxide semiconductor layer 132 and the source electrode 141 and the drain electrode 142; or the second metal oxide semiconductor layer 132 passes through the indium gallium zinc oxide
  • the plasma conductorization treatment is performed, so that the oxygen vacancy concentration of the second metal oxide semiconductor layer 132 is smaller than that of the first metal oxide semiconductor layer 131, and the second metal oxide semiconductor layer 132 obtains a low contact resistance, reducing Contact resistance between the second metal oxide semiconductor layer 132 and the source electrode 141 and the drain electrode 142 .
  • FIG. 8 is a schematic structural diagram of an array substrate in Embodiment 2 of the present invention. As shown in FIG. 8 , the difference between the array substrate provided in the second embodiment and the array substrate in the first embodiment ( FIGS. 4 to 5j ) is that in this embodiment, the array substrate omits the flat layer 103 and the third The insulating layer 104, and the arrangement order of the first electrode layer 15 and the second electrode layer 16 are changed.
  • the second electrode layer 16 is provided on the first insulating layer 101 and is in conductive contact with the source electrode 141
  • the second insulating layer 102 is provided on the first insulating layer 101 and covers the source electrode 141 , the drain electrode 142 and the second electrode Layer 16
  • the first electrode layer 15 is disposed on the second insulating layer 102 .
  • a second transparent electrode film is first formed on the first insulating layer 101, the second transparent electrode film is etched and the second electrode layer 16 is formed;
  • a second metal layer 14 is formed on the electrode layer 16, and the second metal layer 14 is patterned by an etching process to form a source electrode 141, a drain electrode 142 and a data line (not shown);
  • the electrode 142 , the channel 110 and the second insulating layer 102 of the second electrode layer 16 and a first metal layer is formed on the second insulating layer 102 , the first metal layer is etched and the first electrode layer 15 is formed.
  • the first electrode layer 15 is used as a common electrode, and the second electrode layer 16 is used as a pixel electrode.
  • the present embodiment reduces the processes of fabricating the flat layer 103 and the third insulating layer 104 and fabricating the contact holes 105 .
  • FIG. 9 is a schematic structural diagram of an array substrate in Embodiment 3 of the present invention.
  • the difference between the array substrate provided in Embodiment 3 and the array substrate in Embodiment 1 ( FIGS. 4 to 5j ) is that in this embodiment, the array substrate omits the flat layer 103 , the first The electrode layer 15 and the third insulating layer 104 .
  • the second insulating layer 102 is provided on the first insulating layer 101 and covers the source electrode 141 and the drain electrode 142
  • the second insulating layer 102 is provided with a contact hole 105 corresponding to the source electrode 141
  • the second electrode layer 16 is provided with a contact hole 105 corresponding to the source electrode 141 . on the second insulating layer 102 and in conductive contact with the source electrode 141 through the contact hole 105 .
  • a second insulating layer 102 covering the source electrode 141, the drain electrode 142 and the channel 110 is formed on the first insulating layer 101, and the second insulating layer 102 is etched to form a contact hole 105 corresponding to the source electrode 141, Then, a second transparent electrode film covering the contact hole 105 is formed on the second insulating layer 102 , and the second transparent electrode film is etched to form a second electrode layer 16 , and the second electrode layer 16 is in conductive contact with the source electrode 141 through the contact hole 105 , the second electrode layer 16 serves as a pixel electrode.
  • this embodiment reduces the process of fabricating the flat layer 103 , the first electrode layer 15 and the third insulating layer 104 .
  • the array substrate in this embodiment is not provided with a common electrode, and the common electrode can be optionally provided on the color filter substrate, so as to be suitable for the TN display mode or the VA display mode.
  • FIG. 10 is a schematic structural diagram of an array substrate in Embodiment 4 of the present invention.
  • the difference between the array substrate provided in the fourth embodiment and the array substrate in the first embodiment is that in this embodiment, the second semiconductor layer 13 covers the first semiconductor On the top and both sides of the layer 12 , the second semiconductor layer 13 separates the first semiconductor layer 12 from the source electrode 141 and the drain electrode 142 . Therefore, the amorphous silicon layer 121 and the doped amorphous silicon layer 122 in the first semiconductor layer 12 are prevented from directly contacting the source electrode 141 and the drain electrode 142 , and the off-state leakage current is more effectively reduced, thereby enabling low-frequency driving.
  • the first metal oxide semiconductor layer 131 covers the top and both sides of the first semiconductor layer 12 , the two sides of the first metal oxide semiconductor layer 131 are further provided with steps, and the second metal oxide semiconductor layer 132 Covering the top and the steps of the first metal oxide semiconductor layer 131 increases the contact area between the second metal oxide semiconductor layer 132 and the source electrode 141 and the drain electrode 142 , which is more conducive to reducing contact resistance.
  • the second metal oxide semiconductor layer 132 may also cover the top of the first metal oxide semiconductor layer 131 and both sides of the first metal oxide semiconductor layer 131 and the first semiconductor layer 12 , to further reduce the contact resistance.
  • the first metal oxide semiconductor layer 131 covers the top and both sides of the first semiconductor layer 12
  • the second metal oxide semiconductor layer 132 covers the top and both sides of the first metal oxide semiconductor layer 131
  • the first metal oxide The bottoms of the material semiconductor layer 131 and the second metal oxide semiconductor layer 132 are both in contact with the first insulating layer 101 .
  • the method of fabricating the array substrate of this embodiment is basically the same as that of the first embodiment, except that the first semiconductor layer 12 is first etched to form islands, and then the first metal oxide semiconductor layer 131 is covered and etched, and then the first semiconductor layer 131 is etched.
  • the second metal oxide semiconductor layer 132 is covered and etched, and finally the source electrode 141 and the drain electrode 142 are formed, and then the channel 110 is etched.
  • the amorphous silicon thin film 121a and the doped amorphous silicon thin film 122a are successively deposited on the first insulating layer 101 , and the amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a and the doped amorphous silicon thin film 121a are deposited on the first insulating layer 101 in sequence.
  • the silicon thin film 122a is etched to form an island-shaped semiconductor layer structure directly above the gate electrode 11, but at this time, the channel 110 is not etched first.
  • the first insulating layer 101 covers the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132, the first metal oxide semiconductor layer 131 completely covers the amorphous silicon film 121a and the doped amorphous silicon film 122a,
  • the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132 are simultaneously etched and formed into an island-like structure. At this time, the tops of the amorphous silicon film 121a, the doped amorphous silicon film 122a, the first metal oxide semiconductor layer 131 and the second metal oxide semiconductor layer 132 are not etched to form the channel 110.
  • a second metal layer 14 is deposited on the first insulating layer 101 and covers the first semiconductor layer 12 and the second semiconductor layer 13 .
  • the second metal layer 14 is patterned by an etching process to form a source electrode 141, a drain electrode 142 and a data line (not shown), a first through hole 143 is formed between the source electrode 141 and the drain electrode 142, and the first through hole 143 corresponds to the location where the channel 110 is to be formed in the future.
  • the second semiconductor layer 13 is protected by the dense second metal layer 14 , and the surface is less affected by subsequent processes. It is difficult for water vapor, O atoms or H atoms to contact the IGZO film in the external environment, and the film characteristics are protected.
  • the second semiconductor layer 13 and the first semiconductor layer 12 are etched to form the channel 110 .
  • the second semiconductor layer 13 is etched through the first through hole 143 to form the second through hole 133
  • the first semiconductor layer 12 is exposed from the second through hole 133 .
  • the first semiconductor layer 12 is etched through the second through hole 133, and the etching time is controlled, so that the doped amorphous silicon film 122a is etched and disconnected to form the third through hole 123, and the amorphous silicon layer 121 may have a small amount.
  • the channel 110 is formed by the second through hole 133 and the third through hole 123 .

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Abstract

本发明公开了一种阵列基板、显示面板及制作方法。阵列基板包括：基底；设于基底上的栅极；覆盖栅极的第一绝缘层；设于第一绝缘层上的第一半导体层和第二半导体层，第一半导体层和第二半导体层上设有对应栅极的沟道；第二半导体层包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，第一金属氧化物半导体层和第二金属氧化物半导体层均在沟道处断开，第二金属氧化物半导体层的氧空位浓度小于第一金属氧化物半导体层的氧空位浓度；设于第二半导体层上的源极和漏极，并且源极和漏极均与第二半导体层导电接触。

Description

阵列基板及其制作方法和显示面板 技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板及其制作方法和具有该阵列基板的显示面板。
 背景技术
随着显示技术的发展，液晶显示面板(Liquid Crystal Display，LCD)因其轻便、低辐射等优点越来越受到人们的欢迎。液晶显示面板包括对置的彩色滤光片基板(Color filter，CF)和薄膜晶体管阵列基板(Thin film transistor array substrate，TFT array)以及夹置在两者之间的液晶层(Liquid crystal layer，LC layer)。
非晶硅(a-Si)是目前半导体行业应用最广泛的半导体层材料，a-Si材料与金属接触时因为有较大的势能差，难以形成欧姆接触，实际应用中，为了获得金属和半导体之间的欧姆接触，一般对半导体表面进行重掺杂P(磷)元素，降低金属和半导体的接触阻抗，提高电流效率。目前非晶硅TFT(薄膜晶体管)的关态漏电流(Ioff)较大10-11~10-12A，Ion/Ioff(开态电流与关态电流之比)仅有106，在30Hz以下低频驱动的时候，开态与关态的持续时间会变长，此时较大的关态漏电流会导致像素电极压降过大，进而使显示画面出现失真和闪烁问题，所以无法实现30Hz及以下低频显示。所以常规a-Si TFT产品无法在面板显示静止画面或者待机情况下切换至低频刷新模式，达到降低功耗效果。
图1所示为一种现有阵列基板的剖面示意图。阵列基板包括基底1、设于基底1上的栅极2、设于基底1上覆盖所述栅极2的栅极绝缘层3、对应栅极2上方设于栅极绝缘层3上的非晶硅层4、设于非晶硅层4上的掺杂非晶硅(n+a-Si)5、及设于栅极绝缘层3上的源极6与漏极7。掺杂非晶硅5的中部向下凹陷并形成对应栅极2上方的沟道。
图2为具有图1中阵列基板的a-Si器件的漏电流的曲线图，从图2中可以看出，图1的阵列基板结构在增大工作电流(Ion)的同时，也存在一定的问题。
 技术问题
也就是说，当加负电压到一定程度时，会引出正电荷形成空穴导电通道，关态漏电流(Ioff)也随之增大，曲线翘曲严重，造成在低频显示时，显示画面出现失真和闪烁的问题。
 技术解决方案
为了克服现有技术中存在的缺点和不足，本发明的目的在于提供一种阵列基板及其制作方法，以解决现有技术中阵列基板的a-Si器件关态漏电流较大，导致低频显示效果较差的问题。
本发明提供一种阵列基板，包括：
基底；
设于所述基底上的栅极；
覆盖所述栅极的第一绝缘层；
设于所述第一绝缘层上的第一半导体层和第二半导体层，所述第二半导体层层叠设置在所述第一半导体层上，所述第一半导体层为非晶硅层，所述第二半导体层为金属氧化物半导体层，所述第一半导体层和所述第二半导体层上设有对应所述栅极的沟道；
所述第二半导体层包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，所述第一金属氧化物半导体层和所述第二金属氧化物半导体层均在所述沟道处断开，所述第二金属氧化物半导体层的氧空位浓度小于所述第一金属氧化物半导体层的氧空位浓度；
设于所述第二半导体层上的源极和漏极，所述源极和所述漏极均与所述第二半导体层导电接触。
进一步地，所述第一半导体层包括层叠设置的非晶硅层和掺杂非晶硅层，所述掺杂非晶硅层在所述沟道处断开。
进一步地，所述非晶硅层、所述掺杂非晶硅层、所述第一金属氧化物半导体层和所述第二金属氧化物半导体层在所述栅极的正上方由下往上依次层叠设置。
进一步地，所述第一金属氧化物半导体层和所述第二金属氧化物半导体层均采用铟镓锌氧化物。
进一步地，所述源极和所述漏极覆盖所述第二金属氧化物半导体层，所述第二金属氧化物半导体层被所述沟道分割成两个部分，所述源极和所述漏极分别与该两个部分导电接触。
进一步地，所述第二半导体层覆盖住所述第一半导体层的顶部以及两侧，所述第二半导体层将所述第一半导体层与所述源极、所述漏极间隔开。
进一步地，所述阵列基板还包括第二绝缘层、平坦层、第一电极层、第三绝缘层以及第二电极层，所述第二绝缘层设于所述第一绝缘层上并覆盖所述源极和所述漏极，所述平坦层设于所述第二绝缘层上，所述第一电极层设于所述平坦层上，所述第三绝缘层设于所述平坦层上并覆盖所述第一电极层，所述第三绝缘层、所述平坦层和所述第二绝缘层上设有与所述源极对应的接触孔，所述第二电极层设于所述第三绝缘层上并通过所述接触孔与所述源极导电接触。
进一步地，所述阵列基板还包括第二绝缘层、第一电极层以及第二电极层，所述第二电极层设于所述第一绝缘层上并与所述源极导电接触，所述第二绝缘层设于所述第一绝缘层上并覆盖所述源极、所述漏极以及所述第二电极层，所述第一电极层设于所述第二绝缘层上。
进一步地，所述阵列基板还包括第二绝缘层以及第二电极层，所述第二绝缘层设于所述第一绝缘层上并覆盖所述源极和所述漏极，所述第二绝缘层上设有与所述源极对应的接触孔，所述第二电极层设于所述第二绝缘层上并通过所述接触孔与所述源极导电接触。
本发明还提供一种阵列基板的制作方法，包括：
提供基底；
在所述基底上形成图案化的栅极；
在所述基底上形成覆盖所述栅极的第一绝缘层；
在所述第一绝缘层上形成第一半导体层和第二半导体层，所述第二半导体层层叠设置在所述第一半导体层上，所述第一半导体层为非晶硅层，所述第二半导体层为金属氧化物半导体层，所述第二半导体层包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，所述第二金属氧化物半导体层的氧空位浓度小于所述第一金属氧化物半导体层的氧空位浓度；
在所述第二半导体层上形成源极和漏极，所述源极和所述漏极均与所述第二半导体层导电接触；
在形成所述源极和所述漏极之后，对所述第二半导体层和所述第一半导体层进行蚀刻形成沟道。
进一步地，所述第一半导体层包括非晶硅层和掺杂非晶硅层，在所述第一绝缘层上依次连续沉积非晶硅薄膜、掺杂非晶硅薄膜、第一金属氧化物半导体薄膜和第二金属氧化物半导体薄膜，然后对所述非晶硅薄膜、所述掺杂非晶硅薄膜、所述第一金属氧化物半导体薄膜和所述第二金属氧化物半导体薄膜进行蚀刻，以在所述栅极的正上方形成岛状的半导体结构。
进一步地，所述第一半导体层包括非晶硅层和掺杂非晶硅层，在所述第一绝缘层上依次连续沉积非晶硅薄膜和掺杂非晶硅薄膜，对所述非晶硅薄膜和所述掺杂非晶硅薄膜进行蚀刻并在所述栅极的正上方呈岛状结构，然后在所述第一绝缘层上依次连续沉积第一金属氧化物半导体薄膜和第二金属氧化物半导体薄膜并覆盖住所述第一半导体层，对所述第一金属氧化物半导体薄膜和所述第二金属氧化物半导体薄膜进行蚀刻并在所述栅极的正上方呈岛状结构，所述第二半导体层覆盖住所述第一半导体层的顶部以及两侧，所述第二半导体层将所述第一半导体层与所述源极、所述漏极间隔开。
进一步地，在所述基底上制作图案化的栅极时，在所述基底上沉积第一金属层，并对所述第一金属层进行蚀刻以形成所述栅极；在所述第二半导体层上制作源极和漏极时，在所述第一绝缘层上沉积第二金属层并覆盖所述第一半导体层和所述第二半导体层，对所述第二金属层进行蚀刻以形成所述源极和所述漏极，所述源极和所述漏极之间形成第一通孔，所述第一通孔对应于将来要形成所述沟道的位置。
进一步地，在对所述第二半导体层和所述第一半导体层进行蚀刻形成沟道时，以所述源极和所述漏极为遮挡，透过所述第一通孔对所述第二半导体层进行蚀刻形成第二通孔，并从所述第二通孔露出所述第一半导体层，再透过所述第二通孔对所述第一半导体层进行蚀刻，使所述掺杂非晶硅薄膜刻蚀断开形成第三通孔，由所述第二通孔和所述第三通孔形成所述沟道，其中所述非晶硅薄膜在蚀刻之后形成所述非晶硅层，所述掺杂非晶硅薄膜在蚀刻之后形成所述掺杂非晶硅层，所述第一金属氧化物半导体薄膜在蚀刻之后形成所述第一金属氧化物半导体层，所述第二金属氧化物半导体薄膜在蚀刻之后形成所述第二金属氧化物半导体层。
进一步地，所述第一金属氧化物半导体层通过铟镓锌氧化物在氮气气氛下进行温度为300℃~450℃、时间为20~60min退火处理制得；所述第二金属氧化物半导体层通过铟镓锌氧化物在溅射功率为80～110W、氧分压为5％-9％的条件下制得，或者所述第二金属氧化物半导体层通过铟镓锌氧化物等离子处理工艺进行N型掺杂制得，再或者所述第二金属氧化物半导体层通过铟镓锌氧化物进行等离子体导体化处理制得。
进一步地，还包括：
在所述第一绝缘层上依次形成第二绝缘层和平坦层，所述第二绝缘层覆盖所述源极、所述漏极以及所述沟道；
在所述平坦层上形成第一透明电极薄膜，对所述第一透明电极薄膜进行蚀刻形成第一电极层；
在所述第一电极层上形成第三绝缘层，对所述第三绝缘层、所述平坦层和所述第二绝缘层进行刻蚀形成对应所述源极的接触孔；
在所述第三绝缘层上形成覆盖所述接触孔的第二透明电极薄膜，对所述第二透明电极薄膜进行蚀刻形成第二电极层，所述第二电极层通过所述接触孔与所述源极导电接触。
进一步地，还包括：
在形成所述源极和所述漏极之前，先在所述第一绝缘层上形成第二透明电极薄膜，对所述第二透明电极薄膜进行蚀刻并形成第二电极层；
然后再在所述第二电极层上形成第二金属层，对所述第二金属层进行蚀刻以形成所述源极和所述漏极；
之后再形成覆盖所述源极、所述漏极、所述沟道以及所述第二电极层的第二绝缘层和在所述第二绝缘层上形成第一金属层，对所述第一金属层进行蚀刻并形成第一电极层。
进一步地，还包括：
在所述第一绝缘层上形成第二绝缘层，所述第二绝缘层覆盖所述源极、所述漏极以及所述沟道，并对所述第二绝缘层进行蚀刻形成与所述源极对应的接触孔；
然后在所述第二绝缘层上形成覆盖所述接触孔的第二透明电极薄膜，对所述第二透明电极薄膜进行蚀刻形成第二电极层，所述第二电极层通过所述接触孔与所述源极导电接触。
本发明还提供一种显示面板，包括彩膜基板、液晶层以及如上所述的阵列基板，所述彩膜基板与所述阵列基板相对设置，所述液晶层设于所述彩膜基板与所述阵列基板之间。
 有益效果
在阵列基板的基底上层叠设有第一半导体层和第二半导体层，其中第一半导体层为非晶硅层，第二半导体层为金属氧化物半导体层，第二半导体层包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，第二金属氧化物半导体层的氧空位浓度小于第一金属氧化物半导体层的氧空位浓度；设于第二半导体层上的源极和漏极，并且源极和漏极均与第二金属氧化物半导体层导电接触。通过在第一半导体层上方沉积两层不同氧空位浓度的金属氧化物半导体层，能够改善普通a-Si TFT存在的关态漏电流高问题，进而可以实现低频驱动，显示面板在显示静止画面或者待机情况下可以切换至低频刷新模式，以达到降低功耗效果，同时还能减小与源极和漏极的接触电阻，有效增大开态电流，提高响应速度。
 附图说明
图1是现有技术中阵列基板的结构示意图；
图2是图1中阵列基板的a-Si TFT器件的漏电流的曲线图；
图3是a-Si TFT器件和a-IGZO TFT器件的漏电流的曲线图；
图4是本发明中阵列基板的TFT器件的结构示意图；
图5a-图5j是本发明实施例一中阵列基板的制作流程图；
图6是本发明实施例一中阵列基板的TFT器件的漏电流的曲线图；
图7是本发明实施例一中显示面板的结构示意图；
图8是本发明实施例二中阵列基板的结构示意图；
图9是本发明实施例三中阵列基板的结构示意图；
图10是本发明实施例四中阵列基板的结构示意图。
 本发明的实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的阵列基板、显示面板及制作方法的具体实施方式、结构、特征及其功效，详细说明如下：
实施例一
图4是本发明中阵列基板的TFT器件的结构示意图，图5a-图5j是本发明实施例一中阵列基板的制作流程图。
如图4至图5j所示，本发明实施例一提供的一种阵列基板，包括：
基底10，基底10可以由玻璃、石英、丙烯酸或聚碳酸酯等材料制成。
设于基底10上的栅极11，栅极11与扫描线(图未示)位于同一层并电性连接。
覆盖栅极11的第一绝缘层101，第一绝缘层101为栅极绝缘层，第一绝缘层101整面的设置在基底10上并覆盖栅极11和扫描线，第一绝缘层101的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。
设于第一绝缘层101上的第一半导体层12和第二半导体层13，第二半导体层13层叠设置在第一半导体层12上。第一半导体层12具体为非晶硅层，包括层叠设置的非晶硅层(a-Si)121和掺杂非晶硅层(n+a-Si)122，掺杂非晶硅层122用于降低非晶硅层121与第二半导体层13之间的接触电阻。第一半导体层12为岛状结构并设于栅极11的正上方，第一半导体层12在基底10上的投影面积小于栅极11在基底10上的投影面积。第二半导体层13具体为金属氧化物半导体层，包括层叠设置的第一金属氧化物半导体层131和第二金属氧化物半导体层132，第二金属氧化物半导体层132的氧空位浓度小于第一金属氧化物半导体层131的氧空位浓度，第二金属氧化物半导体层132用于降低第一金属氧化物半导体层131与源极141、漏极142之间的接触电阻，非晶硅层121、掺杂非晶硅层122、第一金属氧化物半导体层131以及第二金属氧化物半导体层132从下至上依次层叠设置。
第二半导体层13为岛状结构并设于栅极11的正上方，第二半导体层13在基底10上的投影面积小于第一半导体层12在基底10上的投影面积。具体而言，非晶硅层121、掺杂非晶硅层122、第一金属氧化物半导体层131和第二金属氧化物半导体层132在栅极11的正上方由下往上依次层叠设置。第一半导体层12和第二半导体层13上设有对应栅极11的沟道110，掺杂非晶硅层122、第一金属氧化物半导体层131和第二金属氧化物半导体层132均在沟道110处断开。第一半导体层12与第二绝缘层102界面的背沟道上空穴参与导电，形成背沟道电流，与此同时在负性Vgs(栅极与源极电压之差)和正性Vds(漏极与源极电压之差)电压共同作用下，在栅极141和漏极142之间产生热离子发射出空穴，形成空穴载流子，在第一半导体层12与第二绝缘层102界面形成空穴积累，产生空穴电流。此时前沟道(沟道靠近非晶硅层121表面处的部分)是TFT器件的主要导通通道，相应的背沟道(沟道远离非晶硅层121表面的部分)空穴载流子是主要导电介质。
设于第二半导体层13上的源极141和漏极142，源极141、漏极142以及数据线(图未示)位于同一层并由同一层金属制作而成，并且源极141和漏极142均与第二半导体层13导电接触，源极141和漏极142在沟道110处间隔开。具体地，源极141和漏极142设置在第二金属氧化物半导体层132上并覆盖第二金属氧化物半导体层132，第二金属氧化物半导体层132被沟道110分割成两个部分，源极141和漏极142分别与该两个部分导电接触。
本实施例中，阵列基板还包括第二绝缘层102、平坦层103、第一电极层15、第三绝缘层104以及第二电极层16。第二绝缘层102设于第一绝缘层101上并覆盖源极141和漏极142，平坦层103设于第二绝缘层102上，第一电极层15设于平坦层103上，第三绝缘层104设于平坦层103上并覆盖第一电极层15，第三绝缘层104、平坦层103和第二绝缘层102上设有与源极141对应的接触孔105，第二电极层16设于第三绝缘层104上并通过接触孔105与源极141导电接触。第一电极层15作为公共电极，第二电极层16作为像素电极，公共电极15与像素电极16位于不同层并通过第三绝缘层104绝缘隔离。公共电极15可位于像素电极16上方或下方(图5j中所示为公共电极15位于像素电极16的下方)。优选地，公共电极15为整面设置的面状电极，像素电极16为在每个像素单元内整块设置的块状电极或者具有多个电极条的狭缝电极，以形成边缘场开关模式(Fringe Field Switching，FFS)。当然，在其他实施例中，像素电极16与公共电极15可位于同一层，但是两者相互绝缘隔离开，像素电极16和公共电极15各自均可包括多个电极条，像素电极16的电极条和公共电极15的电极条相互交替排列，以形成面内切换模式(In-Plane Switching，IPS)。
本实施例中，第一金属氧化物半导体层131和第二金属氧化物半导体层132均采用铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。具体地，第二金属氧化物半导体层132的氧空位浓度小于第一金属氧化物半导体层131的氧空位浓度，铟镓锌氧化物可以通过例如磁控溅射或热蒸发等方法沉积，其中氧空位浓度表示金属氧化物半导体层中的含氧量，氧空位浓度越高代表含氧量越低，氧空位浓度越低代表含氧量越高。在第一半导体层12上方沉积高氧空位浓度的第一金属氧化物半导体层131，高氧空位浓度的第一金属氧化物半导体层131可以有效抑制a-Si TFT在关态产生的空穴载流子导通，进而有效降低a-Si TFT截止区关态漏电流。在高氧空位浓度的第一金属氧化物半导体层131上方沉积低氧空位浓度的第二金属氧化物半导体层132层，形成n+IGZO层，使第二金属氧化物半导体层132与源极141、漏极142形成欧姆(Ohmic)接触，降低源极141、漏极142和第二金属氧化物半导体层132的接触电阻，有效增大开态电流，提高响应速度。
如图3所示，采用铟镓锌氧化物制作的a-IGZO TFT器件，虽然漏电流相对a-Si TFT器件小了很多，a-IGZO TFT关态漏电流比a-Si TFT低两个数量级，大概10-13~10-14A 左右，但是a-IGZO TFT 存在制程复杂，对制程环境敏感度高等问题。如高温或者低温环境阈值电压(Vth)偏移较严重，同时对环境水汽、O(氧)原子或H(氢)原子较为敏感，会因为水汽、O原子或H原子的渗入使得IGZO薄膜晶体管失效。
本申请在第一半导体层12的基础上，通过在第一半导体层12上方沉积两层不同氧空位浓度的金属氧化物半导体层，来改善普通a-Si TFT存在的关态漏电流高问题，进而可以实现低频驱动，显示面板在显示静止画面或者待机情况下可以切换至低频刷新模式，以达到降低功耗效果，同时也避免了铟镓锌氧化物受环境影响导致阈值电压(Vth)偏移较严重的问题，如图6所示。
如图7所示，本申请还提供一种显示面板，包括彩膜基板20、液晶层30以及如上所述的阵列基板，彩膜基板20与阵列基板相对设置，液晶层30设于彩膜基板20与阵列基板之间。
本实施例中，液晶层30中采用正性液晶分子，即介电各向异性为正的液晶分子。如图7所示，在初始状态的时候，液晶层30中的正性液晶分子平行于彩膜基板20与阵列基板进行配向，靠近彩膜基板20一侧的正性液晶分子与靠近阵列基板一侧的正性液晶分子的配向方向平行或反向平行。
彩膜基板20上设有呈阵列排布的色阻层22以及将色阻层22间隔开的黑矩阵21，色阻层22包括红(R)、绿(G)、蓝(B)三色的色阻材料，并对应形成红(R)、绿(G)、蓝(B)三色的子像素。
如图5a-5j所示，本申请还提供一种阵列基板的制作方法，该制作方法包括：
提供基底10，基底10可以由玻璃、石英、丙烯酸或聚碳酸酯等材料制成。
在基底10上形成图案化的栅极11，具体地，如图5a，在基底10上沉积第一金属层，采用蚀刻工艺对第一金属层进行图形化以形成栅极11和扫描线(图未示)。
在基底10上形成覆盖栅极11的第一绝缘层101，具体地，如图5b，在基底10上沉积覆盖栅极11和扫描线的第一绝缘层101，第一绝缘层101为栅极绝缘层，第一绝缘层101的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。
在第一绝缘层101上形成第一半导体层12和第二半导体层13，第二半导体层13层叠设置在第一半导体层12上。第一半导体层12具体为非晶硅层，包括层叠设置的非晶硅层121和掺杂非晶硅层122。第二半导体层13具体为金属氧化物半导体层，包括层叠设置的第一金属氧化物半导体层131和第二金属氧化物半导体层132，非晶硅层121、掺杂非晶硅层122、第一金属氧化物半导体层131以及第二金属氧化物半导体层132从下至上依次层叠设置。具体地，如图5b，在第一绝缘层101上依次连续沉积非晶硅薄膜121a、掺杂非晶硅薄膜122a、第一金属氧化物半导体薄膜131a和第二金属氧化物半导体薄膜132a。如图5c，使用既能蚀刻第一半导体层12又能蚀刻第二半导体层13的刻蚀液对非晶硅薄膜121a、掺杂非晶硅薄膜122a、第一金属氧化物半导体薄膜131a以及第二金属氧化物半导体薄膜132a进行蚀刻，以在栅极11的正上方形成岛状的半导体层结构，但此时先不蚀刻形成沟道110。或者可选地，也可以采用能蚀刻第二半导体层13的刻蚀液先对第二半导体层13进行蚀刻，再采用能蚀刻第一半导体层12的刻蚀液以第二半导体层13为遮挡对第一半导体层12进行蚀刻。
在第二半导体层13上形成源极141和漏极142，并且源极141和漏极142均与第二半导体层13导电接触。具体地，如图5d，在第一绝缘层101上沉积第二金属层14并覆盖第一半导体层12和第二半导体层13。如图5e，采用蚀刻工艺对第二金属层14进行图形化以形成源极141、漏极142和数据线(图未示)，源极141和漏极142之间形成第一通孔143，第一通孔143对应于将来要形成沟道110的位置。通过第一半导体层12和第二半导体层13连续成膜，第二半导体层13受到致密第二金属层14的保护，表面受到后续制程影响较小。外界环境中水汽、O原子或H原子难以接触到IGZO薄膜，薄膜特性得到保护。
在形成源极141和漏极142之后，对第二半导体层13和第一半导体层12进行蚀刻形成沟道110。具体地，如图5f，以源极141和漏极142为遮挡，透过第一通孔143对第二半导体层13进行蚀刻形成第二通孔133，并从第二通孔133露出第一半导体层12。如图5g，再透过第二通孔133对第一半导体层12进行蚀刻，控制蚀刻时间，使掺杂非晶硅薄膜122a刻蚀断开形成第三通孔123，而非晶硅层121可以有少量的刻蚀，由第二通孔133和第三通孔123形成沟道110。具体地，可以采用不同的刻蚀液对第二半导体层13和第一半导体层12进行蚀刻。非晶硅薄膜121a在蚀刻之后形成非晶硅层121，掺杂非晶硅薄膜122a在蚀刻之后形成掺杂非晶硅层122，第一金属氧化物半导体薄膜131a在蚀刻之后形成第一金属氧化物半导体层131，第二金属氧化物半导体薄膜132a在蚀刻之后形成第二金属氧化物半导体层132。
进一步地，如图5h，在第一绝缘层101上依次形成第二绝缘层102和平坦层103，第二绝缘层102覆盖源极141、漏极142以及沟道110。如图5i，在平坦层103上形成第一透明电极薄膜，对第一透明电极薄膜进行蚀刻形成第一电极层15，第一电极层15作为公共电极。如图5j，在第一电极层15上形成第三绝缘层104，对第三绝缘层104、平坦层103和第二绝缘层102进行刻蚀形成对应源极141的接触孔105，使源极141从接触孔105中露出，然后在第三绝缘层104上形成覆盖接触孔105的第二透明电极薄膜，对第二透明电极薄膜进行蚀刻形成第二电极层16，第二电极层16通过接触孔105与源极141导电接触，第二电极层16作为像素电极。
本实施例中，第一金属氧化物半导体层131和第二金属氧化物半导体层132均采用铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)，铟镓锌氧化物可以通过例如磁控溅射或热蒸发等方法沉积。具体地，第二金属氧化物半导体层132的氧空位浓度小于第一金属氧化物半导体层131的氧空位浓度，使第二金属氧化物半导体层132形成n+IGZO层，第二金属氧化物半导体层132与源极141、漏极142形成欧姆(Ohmic)接触，有效降低源极141、漏极142与第二金属氧化物半导体层132的接触电阻，有效增大开态电流，提高响应速度。
具体地，第一金属氧化物半导体层131通过铟镓锌氧化物在氮气气氛下进行温度为300℃~450℃、时间为20~60min退火处理制得；第二金属氧化物半导体层132通过铟镓锌氧化物在溅射功率为80～110W、氧分压为5％-9％的条件下制得，从而使得第二金属氧化物半导体层132小于第一金属氧化物半导体层131的氧空位浓度，降低第二金属氧化物半导体层132与源极141和漏极142的接触电阻。在其他实施例中，第二金属氧化物半导体层132通过铟镓锌氧化物等离子处理工艺进行N型掺杂制得，形成n+IGZO区域，使第二金属氧化物半导体层132的氧空位浓度小于第一金属氧化物半导体层131的氧空位浓度，降低第二金属氧化物半导体层132与源极141和漏极142的接触电阻；或者第二金属氧化物半导体层132通过铟镓锌氧化物进行等离子体导体化处理制得，使第二金属氧化物半导体层132的氧空位浓度小于第一金属氧化物半导体层131的氧空位浓度，第二金属氧化物半导体层132获得低接触电阻，降低第二金属氧化物半导体层132与源极141和漏极142的接触电阻。
实施例二
图8是本发明实施例二中阵列基板的结构示意图。如图8所示，本实施例二提供的阵列基板与实施例一(图4至图5j)中的阵列基板不同之处在于，在本实施例中，阵列基板省略了平坦层103和第三绝缘层104，而且第一电极层15与第二电极层16的设置顺序做了改变。具体地，第二电极层16设于第一绝缘层101上并与源极141导电接触，第二绝缘层102设于第一绝缘层101上并覆盖源极141、漏极142以及第二电极层16，第一电极层15设于第二绝缘层102上。
具体地，在形成源极141和漏极142之前，先在第一绝缘层101上形成第二透明电极薄膜，对第二透明电极薄膜进行蚀刻并形成第二电极层16；然后再在第二电极层16上形成第二金属层14，采用蚀刻工艺对第二金属层14进行图形化以形成源极141、漏极142和数据线(图未示)；之后再形成覆盖源极141、漏极142、沟道110以及第二电极层16的第二绝缘层102和在第二绝缘层102上形成第一金属层，对第一金属层进行蚀刻并形成第一电极层15。其中第一电极层15作为公共电极，第二电极层16作为像素电极。本实施例相对实施例一而言，减少了制作平坦层103和第三绝缘层104以及制作接触孔105的工艺。
本领域的技术人员应当理解的是，本实施例的其余结构以及工作原理均与实施例一相同，这里不再赘述。
实施例三
图9是本发明实施例三中阵列基板的结构示意图。如图9所示，本实施例三提供的阵列基板与实施例一(图4至图5j)中的阵列基板不同之处在于，在本实施例中，阵列基板省略了平坦层103、第一电极层15和第三绝缘层104。具体地，第二绝缘层102设于第一绝缘层101上并覆盖源极141和漏极142，第二绝缘层102上设有与源极141对应的接触孔105，第二电极层16设于第二绝缘层102上并通过接触孔105与源极141导电接触。
具体地，在第一绝缘层101上形成覆盖源极141、漏极142以及沟道110的第二绝缘层102，并对第二绝缘层102进行蚀刻形成与源极141对应的接触孔105，然后在第二绝缘层102上形成覆盖接触孔105的第二透明电极薄膜，对第二透明电极薄膜进行蚀刻形成第二电极层16，第二电极层16通过接触孔105与源极141导电接触，第二电极层16作为像素电极。本实施例相对于实施例一而言，减少了制作平坦层103、第一电极层15和第三绝缘层104的工艺。而且，本实施例中的阵列基板没有设置公共电极，可以选择将公共电极设置于彩膜基板上，以适用于TN显示模式或VA显示模式。
本领域的技术人员应当理解的是，本实施例的其余结构以及工作原理均与实施例一相同，这里不再赘述。
实施例四
图10是本发明实施例四中阵列基板的结构示意图。如图10所示，本实施例四提供的阵列基板与实施例一(图4至图5j)中的阵列基板不同之处在于，在本实施例中，第二半导体层13覆盖住第一半导体层12的顶部以及两侧，第二半导体层13将第一半导体层12与源极141、漏极142间隔开。从而避免第一半导体层12中的非晶硅层121和掺杂非晶硅层122直接与源极141、漏极142接触，更有效地降低关态漏电流，进而可以实现低频驱动。
本实施例中，第一金属氧化物半导体层131覆盖住第一半导体层12的顶部以及两侧，第一金属氧化物半导体层131的两侧还设有台阶，第二金属氧化物半导体层132覆盖住第一金属氧化物半导体层131的顶部以及台阶，以增加第二金属氧化物半导体层132与源极141、漏极142的接触面积，更有利于减小接触电阻。当然，在其他实施例中，也可以是第二金属氧化物半导体层132覆盖住第一金属氧化物半导体层131的顶部以及第一金属氧化物半导体层131和第一半导体层12的两侧，以进一步减小接触电阻。或者第一金属氧化物半导体层131覆盖住第一半导体层12的顶部以及两侧，第二金属氧化物半导体层132覆盖住第一金属氧化物半导体层131的顶部以及两侧，第一金属氧化物半导体层131和第二金属氧化物半导体层132的底部均与第一绝缘层101接触。
制作本实施例的阵列基板的方法与实施例一基本相同，不同之处在于，先第一半导体层12进行蚀刻并形成岛状物，再覆盖第一金属氧化物半导体层131并进行蚀刻，其次覆盖第二金属氧化物半导体层132并进行蚀刻，最后形成源极141、漏极142之后再刻蚀出沟道110。
具体地，在第一绝缘层101上依次连续沉积非晶硅薄膜121a和掺杂非晶硅薄膜122a，使用能蚀刻第一半导体层12的刻蚀液对非晶硅薄膜121a和掺杂非晶硅薄膜122a进行蚀刻，以在栅极11的正上方形成岛状的半导体层结构，但此时先不蚀刻形成沟道110。在第一绝缘层101覆盖第一金属氧化物半导体层131和第二金属氧化物半导体层132，第一金属氧化物半导体层131完全覆盖住非晶硅薄膜121a和掺杂非晶硅薄膜122a，对第一金属氧化物半导体层131和第二金属氧化物半导体层132同时进行蚀刻并呈岛状结构。此时，非晶硅薄膜121a、掺杂非晶硅薄膜122a、第一金属氧化物半导体层131以及第二金属氧化物半导体层132的顶部均没有蚀刻形成沟道110。
在第一绝缘层101上沉积第二金属层14并覆盖第一半导体层12和第二半导体层13。采用蚀刻工艺对第二金属层14进行图形化以形成源极141、漏极142和数据线(图未示)，源极141和漏极142之间形成第一通孔143，第一通孔143对应于将来要形成沟道110的位置。通过第一半导体层12和第二半导体层13连续成膜，第二半导体层13受到致密第二金属层14的保护，表面受到后续制程影响较小。外界环境中水汽、O原子或H原子难以接触到IGZO薄膜，薄膜特性得到保护。
在形成源极141和漏极142之后，对第二半导体层13和第一半导体层12进行蚀刻形成沟道110。具体地，以源极141和漏极142为遮挡，透过第一通孔143对第二半导体层13进行蚀刻形成第二通孔133，并从第二通孔133露出第一半导体层12。再透过第二通孔133对第一半导体层12进行蚀刻，控制蚀刻时间，使掺杂非晶硅薄膜122a刻蚀断开形成第三通孔123，而非晶硅层121可以有少量的刻蚀，由第二通孔133和第三通孔123形成沟道110。
本领域的技术人员应当理解的是，本实施例的其余结构以及工作原理均与实施例一相同，这里不再赘述。
在本文中，所涉及的上、下、左、右、前、后等方位词是以附图中的结构位于图中的位置以及结构相互之间的位置来定义的，只是为了表达技术方案的清楚及方便。应当理解，所述方位词的使用不应限制本申请请求保护的范围。还应当理解，本文中使用的术语“第一”和“第二”等，仅用于名称上的区分，并不用于限制数量和顺序。
以上所述，仅是本发明的较佳实施例而已，并非对本发明做任何形式上的限定，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰，为等同变化的等效实施例，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的保护范围之内。

Claims (19)

  1. 一种阵列基板，其特征在于，包括：
    基底(10)；
    设于所述基底(10)上的栅极(11)；
    覆盖所述栅极(11)的第一绝缘层(101)；
    设于所述第一绝缘层(101)上的第一半导体层(12)和第二半导体层(13)，所述第二半导体层(13)层叠设置在所述第一半导体层(12)上，所述第一半导体层(12)为非晶硅层，所述第二半导体层(13)为金属氧化物半导体层，所述第一半导体层(12)和所述第二半导体层(13)上设有对应所述栅极(11)的沟道(110)；
    所述第二半导体层(13)包括层叠设置的第一金属氧化物半导体层(131)和第二金属氧化物半导体层(132)，所述第一金属氧化物半导体层(131)和所述第二金属氧化物半导体层(132)均在所述沟道(110)处断开，所述第二金属氧化物半导体层(132)的氧空位浓度小于所述第一金属氧化物半导体层(131)的氧空位浓度；
    设于所述第二半导体层(13)上的源极(141)和漏极(142)，所述源极(141)和所述漏极(142)均与所述第二半导体层(13)导电接触。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述第一半导体层(12)包括层叠设置的非晶硅层(121)和掺杂非晶硅层(122)，所述掺杂非晶硅层(122)在所述沟道(110)处断开。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述非晶硅层(121)、所述掺杂非晶硅层(122)、所述第一金属氧化物半导体层(131)和所述第二金属氧化物半导体层(132)在所述栅极(11)的正上方由下往上依次层叠设置。
  4. 根据权利要求1所述的阵列基板，其特征在于，所述第一金属氧化物半导体层(131)和所述第二金属氧化物半导体层(132)均采用铟镓锌氧化物。
  5. 根据权利要求1所述的阵列基板，其特征在于，所述第二半导体层(13)覆盖住所述第一半导体层(12)的顶部以及两侧，所述第二半导体层(13)将所述第一半导体层(12)与所述源极(141)、所述漏极(142)间隔开。
  6. 根据权利要求1所述的阵列基板，其特征在于，所述源极(141)和所述漏极(142)覆盖所述第二金属氧化物半导体层(132)，所述第二金属氧化物半导体层(132)被所述沟道(110)分割成两个部分，所述源极(141)和所述漏极(142)分别与该两个部分导电接触。
  7. 根据权利要求1-6任一项所述的阵列基板，其特征在于，所述阵列基板还包括第二绝缘层(102)、平坦层(103)、第一电极层(15)、第三绝缘层(104)以及第二电极层(16)，所述第二绝缘层(102)设于所述第一绝缘层(101)上并覆盖所述源极(141)和所述漏极(142)，所述平坦层(103)设于所述第二绝缘层(102)上，所述第一电极层(15)设于所述平坦层(103)上，所述第三绝缘层(104)设于所述平坦层(103)上并覆盖所述第一电极层(15)，所述第三绝缘层(104)、所述平坦层(103)和所述第二绝缘层(102)上设有与所述源极(141)对应的接触孔(105)，所述第二电极层(16)设于所述第三绝缘层(104)上并通过所述接触孔(105)与所述源极(141)导电接触。
  8. 根据权利要求1-6任一项所述的阵列基板，其特征在于，所述阵列基板还包括第二绝缘层(102)、第一电极层(15)以及第二电极层(16)，所述第二电极层(16)设于所述第一绝缘层(101)上并与所述源极(141)导电接触，所述第二绝缘层(102)设于所述第一绝缘层(101)上并覆盖所述源极(141)、所述漏极(142)以及所述第二电极层(16)，所述第一电极层(15)设于所述第二绝缘层(102)上。
  9. 根据权利要求1-6任一项所述的阵列基板，其特征在于，所述阵列基板还包括第二绝缘层(102)以及第二电极层(16)，所述第二绝缘层(102)设于所述第一绝缘层(101)上并覆盖所述源极(141)和所述漏极(142)，所述第二绝缘层(102)上设有与所述源极(141)对应的接触孔(105)，所述第二电极层(16)设于所述第二绝缘层(102)上并通过所述接触孔(105)与所述源极(141)导电接触。
  10. 一种阵列基板的制作方法，其特征在于，包括：
    提供基底(10)；
    在所述基底(10)上形成图案化的栅极(11)；
    在所述基底(10)上形成覆盖所述栅极(11)的第一绝缘层(101)；
    在所述第一绝缘层(101)上形成第一半导体层(12)和第二半导体层(13)，所述第二半导体层(13)层叠设置在所述第一半导体层(12)上，所述第一半导体层(12)为非晶硅层，所述第二半导体层(13)为金属氧化物半导体层，所述第二半导体层(13)包括层叠设置的第一金属氧化物半导体层(131)和第二金属氧化物半导体层(132)，所述第二金属氧化物半导体层(132)的氧空位浓度小于所述第一金属氧化物半导体层(131)的氧空位浓度；
    在所述第二半导体层(13)上形成源极(141)和漏极(142)，所述源极(141)和所述漏极(142)均与所述第二半导体层(13)导电接触；
    在形成所述源极(141)和所述漏极(142)之后，对所述第二半导体层(13)和所述第一半导体层(12)进行蚀刻形成沟道(110)。
  11. 根据权利要求10所述的制作方法，其特征在于，所述第一半导体层(12)包括非晶硅层(121)和掺杂非晶硅层(122)，在所述第一绝缘层(101)上依次连续沉积非晶硅薄膜(121a)、掺杂非晶硅薄膜(122a)、第一金属氧化物半导体薄膜(131a)和第二金属氧化物半导体薄膜(132a)，然后对所述非晶硅薄膜(121a)、所述掺杂非晶硅薄膜(122a)、所述第一金属氧化物半导体薄膜(131a)和所述第二金属氧化物半导体薄膜(132a)进行蚀刻，以在所述栅极(11)的正上方形成岛状的半导体结构。
  12. 根据权利要求10所述的制作方法，其特征在于，所述第一半导体层(12)包括非晶硅层(121)和掺杂非晶硅层(122)，在所述第一绝缘层(101)上依次连续沉积非晶硅薄膜(121a)和掺杂非晶硅薄膜(122a)，对所述非晶硅薄膜(121a)和所述掺杂非晶硅薄膜(122a)进行蚀刻并在所述栅极(11)的正上方呈岛状结构，然后在所述第一绝缘层(101)上依次连续沉积第一金属氧化物半导体薄膜(131a)和第二金属氧化物半导体薄膜(132a)并覆盖住所述第一半导体层(12)，对所述第一金属氧化物半导体薄膜(131a)和所述第二金属氧化物半导体薄膜(132a)进行蚀刻并在所述栅极(11)的正上方呈岛状结构，所述第二半导体层(13)覆盖住所述第一半导体层(12)的顶部以及两侧，所述第二半导体层(13)将所述第一半导体层(12)与所述源极(141)、所述漏极(142)间隔开。
  13. 根据权利要求11或12所述的制作方法，其特征在于，在所述基底(10)上制作图案化的栅极(11)时，在所述基底(10)上沉积第一金属层，并对所述第一金属层进行蚀刻以形成所述栅极(11)；在所述第二半导体层(13)上制作源极(141)和漏极(142)时，在所述第一绝缘层(101)上沉积第二金属层(14)并覆盖所述第一半导体层(12)和所述第二半导体层(13)，对所述第二金属层(14)进行蚀刻以形成所述源极(141)和所述漏极(142)，所述源极(141)和所述漏极(142)之间形成第一通孔(143)，所述第一通孔(143)对应于将来要形成所述沟道(110)的位置。
  14. 根据权利要求13所述的制作方法，其特征在于，在对所述第二半导体层(13)和所述第一半导体层(12)进行蚀刻形成沟道(110)时，以所述源极(141)和所述漏极(142)为遮挡，透过所述第一通孔(143)对所述第二半导体层(13)进行蚀刻形成第二通孔(133)，并从所述第二通孔(133)露出所述第一半导体层(12)，再透过所述第二通孔(133)对所述第一半导体层(12)进行蚀刻，使所述掺杂非晶硅薄膜(122a)刻蚀断开形成第三通孔(123)，由所述第二通孔(133)和所述第三通孔(123)形成所述沟道(110)，其中所述非晶硅薄膜(121a)在蚀刻之后形成所述非晶硅层(121)，所述掺杂非晶硅薄膜(122a)在蚀刻之后形成所述掺杂非晶硅层(122)，所述第一金属氧化物半导体薄膜(131a)在蚀刻之后形成所述第一金属氧化物半导体层(131)，所述第二金属氧化物半导体薄膜(132a)在蚀刻之后形成所述第二金属氧化物半导体层(132)。
  15. 根据权利要求10所述的制作方法，其特征在于，所述第一金属氧化物半导体层(131)通过铟镓锌氧化物在氮气气氛下进行温度为300℃~450℃、时间为20~60min退火处理制得；所述第二金属氧化物半导体层(132)通过铟镓锌氧化物在溅射功率为80～110W、氧分压为5％-9％的条件下制得，或者所述第二金属氧化物半导体层(132)通过铟镓锌氧化物等离子处理工艺进行N型掺杂制得，再或者所述第二金属氧化物半导体层(132)通过铟镓锌氧化物进行等离子体导体化处理制得。
  16. 根据权利要求10-15任一项所述的制作方法，其特征在于，还包括：
    在所述第一绝缘层(101)上依次形成第二绝缘层(102)和平坦层(103)，所述第二绝缘层(102)覆盖所述源极(141)、所述漏极(142)以及所述沟道(110)；
    在所述平坦层(103)上形成第一透明电极薄膜，对所述第一透明电极薄膜进行蚀刻形成第一电极层(15)；
    在所述第一电极层(15)上形成第三绝缘层(104)，对所述第三绝缘层(104)、所述平坦层(103)和所述第二绝缘层(102)进行刻蚀形成对应所述源极(141)的接触孔(105)；
    在所述第三绝缘层(104)上形成覆盖所述接触孔(105)的第二透明电极薄膜，对所述第二透明电极薄膜进行蚀刻形成第二电极层(16)，所述第二电极层(16)通过所述接触孔(105)与所述源极(141)导电接触。
  17. 根据权利要求10-15任一项所述的制作方法，其特征在于，还包括：
    在形成所述源极(141)和所述漏极(142)之前，先在所述第一绝缘层(101)上形成第二透明电极薄膜，对所述第二透明电极薄膜进行蚀刻并形成第二电极层(16)；
    然后再在所述第二电极层(16)上形成第二金属层(14)，对所述第二金属层(14)进行蚀刻以形成所述源极(141)和所述漏极(142)；
    之后再形成覆盖所述源极(141)、所述漏极(142)、所述沟道(110)以及所述第二电极层(16)的第二绝缘层(102)和在所述第二绝缘层(102)上形成第一金属层，对所述第一金属层进行蚀刻并形成第一电极层(15)。
  18. 根据权利要求10-15任一项所述的制作方法，其特征在于，还包括：
    在所述第一绝缘层(101)上形成第二绝缘层(102)，所述第二绝缘层(102)覆盖所述源极(141)、所述漏极(142)以及所述沟道(110)，并对所述第二绝缘层(102)进行蚀刻形成与所述源极(141)对应的接触孔(105)；
    然后在所述第二绝缘层(102)上形成覆盖所述接触孔(105)的第二透明电极薄膜，对所述第二透明电极薄膜进行蚀刻形成第二电极层(16)，所述第二电极层(16)通过所述接触孔(105)与所述源极(141)导电接触。
  19. 一种显示面板，其特征在于，包括彩膜基板(20)、液晶层(30)以及如权利要求1-9任一项所述的阵列基板，所述彩膜基板(20)与所述阵列基板相对设置，所述液晶层(30)设于所述彩膜基板(20)与所述阵列基板之间。
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