WO2017166431A1 - Tft阵列基板及其制造方法、显示装置 - Google Patents

Tft阵列基板及其制造方法、显示装置 Download PDF

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WO2017166431A1
WO2017166431A1 PCT/CN2016/084947 CN2016084947W WO2017166431A1 WO 2017166431 A1 WO2017166431 A1 WO 2017166431A1 CN 2016084947 W CN2016084947 W CN 2016084947W WO 2017166431 A1 WO2017166431 A1 WO 2017166431A1
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layer
active layer
gate insulating
active
thin film
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PCT/CN2016/084947
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English (en)
French (fr)
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刘政
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京东方科技集团股份有限公司
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Priority to KR1020177015359A priority Critical patent/KR102055247B1/ko
Priority to US15/531,154 priority patent/US10325938B2/en
Priority to EP16865283.2A priority patent/EP3439035A4/en
Priority to JP2017531238A priority patent/JP6896627B2/ja
Publication of WO2017166431A1 publication Critical patent/WO2017166431A1/zh

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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • Embodiments of the present invention generally relate to the field of display technology, and in particular, to a TFT array substrate capable of improving the resolution of a display panel, a method of fabricating the same, and a display device including the TFT array substrate.
  • TFT Thin Film Transistor
  • the array substrate in the display panel is increasingly used in high-resolution, high-quality organic electroluminescence displays and liquid crystal display panels.
  • a high-resolution display panel a plurality of thin-film transistors of a small size are required, and the process realization, electrical performance, and reliability of the thin film transistor array substrate are more demanded.
  • the driving thin film transistor generally requires a long channel, which occupies a large substrate area, and the high resolution design is A limit.
  • FIG. 1 is a schematic structural view of a conventional low-temperature polysilicon thin film transistor array substrate, including a substrate 1, an active layer 2, a gate insulating layer 3, a gate layer 4, an intermediate insulating layer 5, a penetrating intermediate insulating layer, and a gate.
  • Achieving such an existing array substrate requires at least six masks for forming an active layer, a gate layer, a via, source and drain electrode layers, a planarization layer, and a pixel electrode layer.
  • the channel length is a key factor, especially for the driving thin film transistor in the organic electroluminescent diode display device, the channel length of 2L can reach several tens of micrometers, which will occupy Larger area is not conducive to high resolution implementation.
  • the present invention has been made in order to overcome at least one of the above and other problems and disadvantages of the prior art.
  • a TFT array substrate comprising: a substrate substrate; and two thin film transistors on the substrate substrate, each thin film transistor including an active layer having a source region and a drain region, Two active layers of two thin film transistors are stacked on each other in a direction perpendicular to the substrate, and a drain region of one of the two active layers and a source region of another active layer Electrically connected such that the two thin film transistors are connected in series.
  • the two active layers may include a first active layer formed on the base substrate and a second active layer above the first active layer, and the two thin film transistors may also A first gate insulating layer covering the first active layer and a second gate insulating layer covering the first gate insulating layer, at least between the first active layer and the second active layer, And a gate between the first gate insulating layer and the second gate insulating layer to serve as a common gate of the two thin film transistors, and the second active layer is disposed on the second gate On the insulation layer.
  • the TFT array substrate is provided with a through hole penetrating the first gate insulating layer and the second gate insulating layer to expose a drain region of the first active layer, and the second active layer may be included
  • the through hole is electrically connected to the connection portion of the drain region of the first active layer and the source region of the second active layer.
  • one of the two thin film transistors may include a first gate on the substrate, a first gate insulating layer overlying the first gate, and a first gate.
  • a first active layer on the insulating layer and the other of the two thin film transistors may include a second active layer over the first active layer and a second gate insulating over the second active layer And a second gate on the second gate insulating layer, and the source region of the second active layer may be electrically connected to the drain region of the first active layer.
  • the TFT array substrate may further include an interlayer insulating layer overlying the one thin film transistor, wherein the second active layer is on the interlayer insulating layer.
  • the TFT array substrate is provided with a through hole penetrating through the interlayer insulating layer to expose a drain region of the first active layer, and the second active layer may be disposed in the via hole to electrically connect the first a connection portion of the drain region of the source layer and the source region of the second active layer.
  • the TFT array substrate may further include a source electrode layer electrically connected to a source region of the first active layer and a pixel electrode electrically connected to a drain region of the second active layer.
  • Polar layer electrically connected to a source region of the first active layer and a pixel electrode electrically connected to a drain region of the second active layer.
  • connection portion may include a portion formed and doped by the same material as the second active layer.
  • the active layer may include a low temperature polysilicon layer.
  • a method of fabricating a TFT array substrate comprising the steps of:
  • each thin film transistor includes an active layer having a source region and a drain region such that two active layers of the two thin film transistors are in a direction perpendicular to the substrate
  • the plurality of thin film transistors are connected in series to each other, and the drain regions of one of the two active layers are electrically connected to the source regions of the other.
  • the step of forming a thin film transistor may include:
  • a connection portion is formed inside to electrically connect the drain region of the first active layer and the source region of the second active layer.
  • the steps of forming the first semiconductor material layer and/or the second semiconductor material layer may include: forming an amorphous silicon layer; and employing excimer laser crystallization, metal induced crystallization, or solid phase crystallization
  • the amorphous silicon layer is converted into a polysilicon layer.
  • the method may further include: forming a conductive material layer on the base substrate And patterning the layer of conductive material into a source electrode layer using a fourth mask, wherein a portion of the first active layer overlaps a portion of the source electrode layer.
  • the method may further include:
  • a first ion implantation process is performed with the gate as an occlusion mask to ion doping the source and drain regions of the first active layer;
  • a second ion implantation process is performed with the second mask as another occlusion mask to ion doping the source and drain regions of the second active layer.
  • the method may further include: after forming the second active layer, performing an ion implantation process using the second mask as an occlusion mask to the first active layer and the second active layer
  • the source and drain regions are ion doped.
  • connection portion of the second active layer located in the via hole may also be doped when the second active layer is ion doped.
  • the method may further include:
  • a pixel electrode layer is formed on the planarization layer by a sixth mask, and the pixel electrode layer is electrically connected to a drain region of the second active layer.
  • a display device comprising the TFT array substrate of any of the above embodiments, or a TFT array substrate manufactured according to the method of any of the above embodiments.
  • Embodiments of the present invention provide a TFT array substrate, a method of manufacturing the same, and a display device.
  • the TFT array substrate includes two active layers stacked on each other in a direction perpendicular to the substrate, and the two active layers are electrically connected to each other, such as a drain region and an active layer in one active layer
  • the source regions are electrically connected to form two thin film transistors stacked in a vertical direction and connected in series, so that each thin film transistor can be reduced or saved while maintaining the total effective channel length
  • the area occupied is advantageous for the high resolution design of the display panel, so as to meet the requirement of thin film transistors which are sensitive to channel length in the application of high resolution display panels.
  • FIG. 1 is a cross-sectional view showing the structure of a part of a TFT array substrate in the prior art
  • FIG. 2 is a cross-sectional view showing a structure of a portion of a TFT array substrate in accordance with an exemplary embodiment of the present invention
  • FIG. 3 is a cross-sectional view showing a structure of a portion of a TFT array substrate according to another exemplary embodiment of the present invention.
  • FIGS. 4a-4d are schematic diagrams showing steps of a method of fabricating a TFT array substrate, in accordance with an exemplary embodiment of the present invention.
  • a TFT array substrate comprising two active layers stacked on each other in a direction perpendicular to a substrate, the two active layers being electrically connected to each other, such as The drain region in the active layer is electrically connected to the source region in the other active layer to form two thin film transistors stacked in the vertical direction and connected in series, so that while maintaining the total effective channel length constant Reducing or saving the area occupied by each thin film transistor on the substrate facilitates the high resolution design of the display panel, thereby satisfying the requirement of the thin film transistor to be sensitive to the channel length in the application of the high resolution display panel.
  • the TFT array substrate is a low temperature polysilicon array substrate.
  • FIG. 2 illustrates a structure of a portion of a TFT array substrate in accordance with an exemplary embodiment of the present invention.
  • the TFT array substrate includes a base substrate 100, a first active layer 102 formed on the base substrate 100, and a first gate insulating layer 103 covering the first active layer 102, formed at the first Gate 104 on gate insulating layer 103, to The second gate insulating layer 105 covering the gate 104 and the second active layer 107 at least partially disposed on the second gate insulating layer 105, wherein the first active layer 102 and the first gate insulating layer 103 are And the gate 104 constitutes a portion of the first thin film transistor, and the gate 104, the second gate insulating layer 105 and the second active layer 107 constitute a portion of the second thin film transistor, and the second active layer 107 and the first have
  • the source layer 102 is electrically connected such that the first thin film transistor and the second thin film transistor are connected in series.
  • the first thin film transistor and the second thin film transistor stacked on each other share the gate electrode 104, and their channel lengths are respectively L and their total effective channel length is 2L, which is compatible with existing thin film transistors.
  • the channel length is the same, but the footprint on the substrate is reduced, thereby facilitating high-resolution array substrates and display panels.
  • the two thin film transistors connected in series can effectively reduce the leakage current in the off state and increase the stability of the thin film transistor.
  • the drain regions of one of the two active layers 102, 107 are electrically coupled to the source region of the other to effect a series connection of the two thin film transistors.
  • the source electrode layer 101 is formed on the base substrate 100, and the source region in the first active layer 102 partially covers or contacts the source electrode layer 101, realizing the source region in the first active layer 102.
  • Electrical connection with the source electrode layer 101, and the drain region in the first active layer 102 is electrically connected to the source region of the second active layer 107, and the drain region of the second active layer 107 may be electrically connected to the pixel electrode layer 109.
  • the pixel electrode layer 109 may be disposed on the planarization layer 108 covering the second active layer 107 and the second gate insulating layer 105.
  • the TFT array substrate is provided with a through hole 106 penetrating the first gate insulating layer 103 and the second gate insulating layer 105 to expose a drain region of the first active layer 102 (see FIG. 4c), and the second The source layer 107 may include a connection portion 1071 located within the via 106 to electrically connect the drain region of the first active layer 102 and the source region of the second active layer 107.
  • the connection portion 1071 may be formed of the same material as the second active layer 107, and preferably, the connection portion 1071 is doped to increase the carrier concentration therein, and reduce the active layer in the on state. The on resistance between.
  • FIG. 3 illustrates a structure of a portion of a TFT array substrate in accordance with another exemplary embodiment of the present invention.
  • the TFT array substrate includes a base substrate 200, a first gate 201 formed on the base substrate 200, a first gate insulating layer 202 covering the first gate 201, and a first gate.
  • the first active layer 204 on the insulating layer 202 An interlayer insulating layer 205 covering the first active layer 204, a second active layer 206 formed on the interlayer insulating layer 205, a second gate insulating layer 207 covering the second active layer 206, and being disposed in the second a second gate 209 on the gate insulating layer 207, wherein the first gate 201, the first gate insulating layer 202, and the first active layer 204 constitute a portion of the first thin film transistor, and the second active layer 206
  • the second gate insulating layer 207 and the second gate 209 form part of the second thin film transistor, and the second active layer 206 is electrically connected to the first active layer 204 such that the first thin film transistor is connected in series with the second thin film transistor connection.
  • the first thin film transistor and the second thin film transistor stacked on each other have a channel length of L and their total effective channel length is 2L, which is the same as the channel length of the conventional thin film transistor, but The footprint on the substrate is reduced, thereby facilitating the realization of high resolution array substrates and display panels.
  • the two thin film transistors connected in series can effectively reduce the leakage current in the off state and increase the stability of the thin film transistor.
  • the drain regions of one of the two active layers 204, 206 are electrically coupled to the source region of the other to effect a series connection of the two thin film transistors.
  • the source electrode layer 203 is formed on the first gate insulating layer 202, and the source region in the first active layer 204 partially overlaps or contacts with the source electrode layer 203 to implement the first active layer 204.
  • the source region is electrically connected to the source electrode layer 203, and the drain region in the first active layer 204 is electrically connected to the source region of the second active layer 206, and the drain region of the second active layer 206 can be connected to the pixel electrode
  • the layer 210 is electrically connected; as shown in FIG. 3, the pixel electrode layer 210 may be disposed on the planarization layer 208 covering the second gate electrode 209 and the second gate insulating layer 207.
  • the TFT array substrate is provided with a via hole (not shown) penetrating the interlayer insulating layer 205 to expose a drain region of the first active layer 204, and the second active layer 206 may be disposed in the via hole
  • a connection portion electrically connecting the drain region of the first active layer 204 and the source region of the second active layer 206, for example, extending from the source region of the second active layer 206 to the first active layer 204 as shown in the drawing The vertical part of the drain area.
  • the connection portion may be formed of the same material as the second active layer 206, and preferably, the connection portion is doped to increase the carrier concentration therein, and reduce the active layer in the on state. The on resistance between.
  • embodiments of the present invention also provide a method of fabricating a TFT array substrate, including providing a substrate substrate, and forming two thin film transistors on the substrate substrate, The two active layers of the two thin film transistors are stacked on each other in a direction perpendicular to the substrate, each thin film transistor including an active layer having a source region and a drain region, and in the two active layers One drain region is electrically connected to the other source region, thereby connecting the two thin film transistors in series.
  • a method of fabricating a TFT array substrate according to an exemplary embodiment of the present invention will be specifically described below by way of example with reference to FIGS. 4a-4d.
  • a substrate substrate 100 may be provided, which may be a transparent substrate such as pre-cleaned glass, and may include a buffer layer formed of silicon oxide, silicon nitride or a combination thereof to prevent the transparent substrate from being formed.
  • the metal ion impurities diffuse into the active layer to affect the operating characteristics of the thin film transistor.
  • a first layer of semiconductor material is formed on the base substrate 100, and the first layer of semiconductor material is patterned using a first mask to form the first active layer 102.
  • a first gate insulating layer 103 covering the first active layer 102 is formed, and a gate material layer is formed on the first gate insulating layer 103, and the gate material layer is formed by using a second mask. Patterning to form a gate 104 over the first active layer 102.
  • the gate may be a single layer, two layers or more layers, and may be composed of a metal or a metal alloy, such as molybdenum, aluminum, molybdenum tungsten, etc., and the thickness may be Within the range, the preferred thickness is
  • a second gate insulating layer 105 covering the gate electrode 104 and the first gate insulating layer 103 is formed.
  • the first and/or second gate insulating layer may employ a single layer of silicon oxide, silicon nitride, or a combination of both, and the invention is not limited thereto; PECVD, LPCVD, APCVD, or ECR may be used.
  • a via hole 106 penetrating the second gate insulating layer 105 and the first gate insulating layer 103 to expose a drain region of the first active layer 102 is formed using a third mask.
  • the first and/or second active layer may be a polysilicon layer formed by converting an amorphous silicon layer by an amorphous silicon layer by excimer laser crystallization, metal induced crystallization, solid phase crystallization, or the like.
  • a low temperature polysilicon array substrate can be formed.
  • the specific process and the structure of the thin film transistor will be different by different crystallization methods.
  • heat treatment dehydrogenation, deposition induction metal, heat treatment crystallization, excimer laser need to be added according to the situation.
  • the crystallization, the doping of the source and drain regions (P-type or N-type doping), and the activation of dopant impurities, etc. do not affect the implementation of the present invention, and the present invention also has a beneficial effect.
  • the thickness of the first and/or second active layer may be Preferred thickness is
  • the formation method may be PECVD, LPCVD or sputtering, and the deposition temperature is below 600 °C.
  • the lining may also be included.
  • a conductive material layer is formed on the base substrate, and the conductive material layer is patterned into the source electrode layer 101 using a fourth mask, wherein a portion of the first active layer 102 overlaps with a portion of the source electrode layer 101.
  • the first ion implantation process may be performed with the gate 104 as an occlusion mask to the source and drain regions of the first active layer 102. Performing ion doping; after forming the second active layer 107, performing a second ion implantation process using the second mask as another occlusion mask to ionize the source and drain regions of the second active layer 107 Doping.
  • an ion implantation process may be performed using the second mask as an occlusion mask to source and drain the first active layer 102 and the second active layer 107.
  • the region is ion doped. It can be understood that when the second active layer is ion-doped, the portion of the second active layer located in the via hole may also be doped to increase the carrier concentration therein and reduce the active layer in the on state. The on resistance between.
  • the ion implantation process may employ ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid state diffusion implantation.
  • the mainstream ion cloud implantation method is adopted, and the implantation may be performed by using a mixed gas containing boron such as B 2 H 6 /H 2 or phosphorus such as PH 3 /H 2 according to design requirements, and the ion implantation energy may be 10 to 200 keV.
  • the energy is between 40 and 100 keV.
  • the implantation dose may be in the range of 1 ⁇ 10 11 to 1 ⁇ 10 20 atoms/cm 3 , and preferably the dose is 1 ⁇ 10 14 to 1 ⁇ 10 18 atoms / cm 3 .
  • a planarization layer 108 covering the second active layer 107 and the second gate insulating layer 105 may be formed using a fifth mask, and a pixel electrode layer 109 may be formed on the planarization layer 108 by using a sixth mask.
  • the pixel electrode layer 109 may be electrically connected to the drain region of the second active layer 107.
  • the planarization layer can be made of an organic material, and an organic photoresist material such as polyimide or acrylic can be used, and the thickness can be
  • the pixel electrode layer may be a single layer, two layers or two or more layers, and is composed of a transparent conductive material such as indium tin oxide, indium zinc oxide, or the like, or a metal, a metal alloy such as silver or a silver alloy, and the thickness may be Within the range, the preferred thickness is
  • the method provided by the embodiment of the present invention also fabricates the TFT array substrate through six masks, which does not increase the number of masks compared with the prior art, and does not add additional process complexity in the process implementation, and The characteristics of the prepared device are better.
  • an embodiment of the present invention further provides a display device comprising the TFT array substrate described in any of the above embodiments, or a TFT array substrate manufactured according to the method of any of the above embodiments.
  • display devices may be liquid crystal panels, electronic paper, OLED panels, cell phones, notebook computers, tablets, displays, digital photo frames, navigators, identification devices, or any other product or component having display functionality.

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Abstract

一种TFT阵列基板及其制造方法，以及包括该TFT阵列基板的显示装置。该TFT阵列基板包括衬底基板（100）和位于衬底基板上的两个薄膜晶体管，每个薄膜晶体管包括具有源区和漏区的有源层（102、107），两个薄膜晶体管的两个有源层在垂直于衬底基板的方向上相互叠置，且两个有源层中的一个有源层的漏区与另一个有源层的源区电连接，使得两个薄膜晶体管串联连接，由此能够在保持总的有效沟道长度不变的同时，减小或节省每个薄膜晶体管在基板上所占的面积，有利于显示面板的高分辨率设计。

Description

TFT阵列基板及其制造方法、显示装置 技术领域
本发明的实施例一般地涉及显示技术领域，并且具体地，涉及能够提高显示面板的分辨率的TFT阵列基板及其制造方法、包括该TFT阵列基板的显示装置。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)阵列基板广泛地应用于显示器的显示面板中，特别是低温多晶硅阵列基板拥有高迁移率的优点，并且反应速度快，是近年来逐渐被看好的一种用在显示面板中的阵列基板，在高分辨率、高画质的有机电致发光显示和液晶显示面板上被越来越多地采用。在高分辨率的显示面板中，需要多个很小尺寸的薄膜晶体管，对薄膜晶体管阵列基板的工艺实现、电学性能、可靠性的要求更高。特别是现有的低温多晶硅薄膜晶体管阵列基板应用于有机电致发光二极管显示技术中时，其驱动薄膜晶体管一般需要较长的沟道，从而会占用较大的基板面积，对高分辨的设计是一个限制。
图1为现有的一种低温多晶硅薄膜晶体管阵列基板的结构示意图，包含基板1、有源层2、栅极绝缘层3、栅极层4、中间绝缘层5、穿透中间绝缘层及栅极绝缘层的过孔、源和漏电极层6和7、平坦化层8和像素电极层9。实现这种现有的阵列基板至少需要用于形成有源层、栅极层、过孔、源和漏电极层、平坦化层和像素电极层的六道掩膜版。在高分辨率的阵列基板制备过程中，沟道长度是一个关键因素，特别是对有机电致发光二极管显示器件中的驱动薄膜晶体管来说，其沟道长度2L可达几十微米，将占用较大的面积，不利于高分辨的实现。
发明内容
为了克服现有技术存在的上述和其它问题和缺陷中的至少一种，提出了本发明。
根据本发明的一个方面，提出了一种TFT阵列基板，包括：衬底基板；和位于衬底基板上的两个薄膜晶体管，每个薄膜晶体管包括具有源区和漏区的有源层，所述两个薄膜晶体管的两个有源层在垂直于衬底基板的方向上相互叠置，且所述两个有源层中的一个有源层的漏区与另一个有源层的源区电连接，使得所述两个薄膜晶体管串联连接。
在一个实施例中，所述两个有源层可以包括形成在衬底基板上的第一有源层和位于第一有源层上方的第二有源层，所述两个薄膜晶体管还可以包括至少位于第一有源层和第二有源层之间的覆盖在第一有源层上的第一栅极绝缘层、覆盖在第一栅极绝缘层上的第二栅极绝缘层、和一个栅极，该栅极位于第一栅极绝缘层和第二栅极绝缘层之间以用作所述两个薄膜晶体管的公共栅极，且第二有源层设置在第二栅极绝缘层上。
在一个实施例中，该TFT阵列基板设置有贯穿第一栅极绝缘层和第二栅极绝缘层以露出第一有源层的漏区的通孔，并且第二有源层可以包括位于该通孔内以电连接第一有源层的漏区和第二有源层的源区的连接部分。
在一个实施例中，所述两个薄膜晶体管中的一个薄膜晶体管可以包括位于衬底基板上的第一栅极、覆盖在第一栅极上的第一栅极绝缘层和位于第一栅极绝缘层上的第一有源层，所述两个薄膜晶体管中的另一个薄膜晶体管可以包括位于第一有源层上方的第二有源层、覆盖第二有源层的第二栅极绝缘层和位于第二栅极绝缘层上的第二栅极，并且第二有源层的源区可以与第一有源层的漏区电连接。
在一个实施例中，上述TFT阵列基板还可以包括覆盖在所述一个薄膜晶体管上的层间绝缘层，其中第二有源层位于层间绝缘层上。
在一个实施例中，上述TFT阵列基板设置有贯穿层间绝缘层以露出第一有源层的漏区的通孔，并且第二有源层可以包括位于该通孔内以电连接第一有源层的漏区和第二有源层的源区的连接部分。
在一个实施例中，上述TFT阵列基板还可以包括与第一有源层的源区电连接的源电极层和与第二有源层的漏区电连接的像素电 极层。
在一个实施例中，所述连接部分可以包括由与第二有源层相同的材料形成并掺杂的部分。
在一个实施例中，所述有源层可以包括低温多晶硅层。
根据本发明的另一个方面，提供了一种制造TFT阵列基板的方法，包括下述步骤：
提供衬底基板；以及
在衬底基板上形成两个薄膜晶体管，其中每个薄膜晶体管包括具有源区和漏区的有源层，使得所述两个薄膜晶体管的两个有源层在垂直于衬底基板的方向上相互叠置，且所述两个有源层中的一个的漏区与另一个的源区电连接，由此串联连接所述两个薄膜晶体管。
在一个实施例中，形成薄膜晶体管的步骤可以包括：
在衬底基板上形成第一半导体材料层，并采用第一掩模对第一半导体材料层进行图案化以形成第一有源层；
形成覆盖第一有源层的第一栅极绝缘层；
在第一栅极绝缘层上形成栅极材料层，并采用第二掩模对栅极材料层进行图案化以形成位于第一有源层上方的栅极；
形成覆盖栅极和第一栅极绝缘层的第二栅极绝缘层；
采用第三掩模形成贯穿第二栅极绝缘层和第一栅极绝缘层以露出第一有源层的漏区的通孔；以及
在第二栅极绝缘层上形成第二半导体材料层，并采用所述第一掩模对第二半导体材料层进行图案化以形成第二有源层，第二有源层的一部分位于通孔内形成连接部分，以电连接第一有源层的漏区和第二有源层的源区。
在一个实施例中，形成第一半导体材料层和/或第二半导体材料层的步骤可以分别包括：形成非晶硅层；以及采用准分子激光晶化、金属诱导晶化或固相晶化工艺将非晶硅层转变成多晶硅层。
在一个实施例中，在形成第一有源层之前，或者在形成第一有源层之后且在形成第一栅极绝缘层之前，该方法还可以包括：在衬底基板上形成导电材料层，并采用第四掩模将导电材料层图案化为源电极层，其中第一有源层的一部分与源电极层的一部分重叠。
在一个实施例中，该方法还可以包括：
在形成栅极之后且在形成第二栅极绝缘层之前，以栅极为遮挡掩模进行第一离子注入工艺，以对第一有源层的源区和漏区进行离子掺杂；以及
在形成第二有源层之后，以所述第二掩模为另一遮挡掩模进行第二离子注入工艺，以对第二有源层的源区和漏区进行离子掺杂。
在一个实施例中，该方法还可以包括：在形成第二有源层之后，以所述第二掩模为遮挡掩模进行离子注入工艺，以对第一有源层和第二有源层的源区和漏区进行离子掺杂。
在一个实施例中，在对第二有源层进行离子掺杂时，第二有源层位于通孔内的连接部分也可以被掺杂。
在一个实施例中，该方法还可以包括：
采用第五掩模在衬底基板上形成覆盖第二有源层和第二栅极绝缘层的平坦化层；以及
采用第六掩模在平坦化层上形成像素电极层，像素电极层与第二有源层的漏区电连接。
根据本发明的又一个方面，提供了一种显示装置，包括上述任一实施例中的TFT阵列基板，或包括根据上述任一实施例中的方法制造的TFT阵列基板。
本发明的实施例，提供了一种TFT阵列基板及其制造方法、显示装置。该TFT阵列基板，包括在垂直于衬底基板的方向上相互叠置的两个有源层，这两个有源层相互电连接，如一个有源层中的漏区与另一个有源层中的源区电连接，以形成在垂直方向上层叠且串联连接的两个薄膜晶体管，使得能够在保持总的有效沟道长度不变的同时，减小或节省每个薄膜晶体管在基板上所占的面积，有利于显示面板的高分辨率设计，从而满足薄膜晶体管在高分辨显示面板的应用中对沟道长度较为敏感的需求。
附图说明
通过参考附图能够更加清楚地理解本发明的特征和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1为示出现有技术中的一种TFT阵列基板的一部分的结构的剖视图；
图2为示出根据本发明的一个示例性实施例的TFT阵列基板的一部分的结构的剖视图；
图3为示出根据本发明的另一个示例性实施例的TFT阵列基板的一部分的结构的剖视图；以及
图4a-4d为示出根据本发明的一个示例性实施例的制造TFT阵列基板的方法的步骤的示意图。
具体实施方式
下面将结合附图，对本发明的实施例进行详细的描述。在本说明书中，相同或相似的部件由相同或类似的附图标号指示。下述参照附图对本发明的各实施方式的说明旨在阐述本发明的总体构思，而不应当理解为对本发明的一种限制。
另外，在下面的详细描述中，为便于说明，阐述了许多具体的细节以提供对本发明的实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其它情况下，公知的结构和装置以图示的方式体现以简化附图。
根据本发明的一个总的发明构思，提供了一种TFT阵列基板，包括在垂直于衬底基板的方向上相互叠置的两个有源层，这两个有源层相互电连接，如一个有源层中的漏区与另一个有源层中的源区电连接，以形成在垂直方向上层叠且串联连接的两个薄膜晶体管，使得能够在保持总的有效沟道长度不变的同时，减小或节省每个薄膜晶体管在基板上所占的面积，有利于显示面板的高分辨率设计，从而满足薄膜晶体管在高分辨显示面板的应用中对沟道长度较为敏感的需求。优选地，该TFT阵列基板为低温多晶硅阵列基板。
图2示出了根据本发明的一个示例性实施例的TFT阵列基板的一部分的结构。如图所示，该TFT阵列基板包括衬底基板100、形成在衬底基板100上的第一有源层102、覆盖第一有源层102的第一栅极绝缘层103、形成在第一栅极绝缘层103上的栅极104、至 少覆盖栅极104的第二栅极绝缘层105和至少部分地设置在第二栅极绝缘层105上的第二有源层107，其中第一有源层102、第一栅极绝缘层103和栅极104构成第一薄膜晶体管的部分，而栅极104、第二栅极绝缘层105和第二有源层107构成第二薄膜晶体管的部分，并且第二有源层107与第一有源层102电连接，使得第一薄膜晶体管与第二薄膜晶体管串联连接。
在该实施例中，彼此叠置的第一薄膜晶体管和第二薄膜晶体管共用栅极104，它们的沟道长度分别为L且它们的总有效沟道长度为2L，与现有的薄膜晶体管的沟道长度相同，但在基板上的占用面积降低，从而有利于实现高分辨率的阵列基板和显示面板。另一方面，这两个串联连接的薄膜晶体管能够有效地降低关态时的泄漏电流，增加薄膜晶体管的稳定性。
在一个示例中，这两个有源层102、107中的一个的漏区与另一个的源区电连接，实现这两个薄膜晶体管的串联连接。例如，在图2中，源电极层101形成在衬底基板100上，第一有源层102中的源区部分地覆盖或接触源电极层101，实现第一有源层102中的源区与源电极层101的电连接，而第一有源层102中的漏区与第二有源层107的源区电连接，第二有源层107的漏区可以与像素电极层109电连接；如图2所示，像素电极层109可以设置在覆盖第二有源层107和第二栅极绝缘层105的平坦化层108上。
示例性地，该TFT阵列基板设置有贯穿第一栅极绝缘层103和第二栅极绝缘层105以露出第一有源层102的漏区的通孔106(参见图4c)，第二有源层107可以包括位于通孔106内以电连接第一有源层102的漏区和第二有源层107的源区的连接部分1071。在一个示例中，连接部分1071可以由与第二有源层107相同的材料形成，并且优选地，连接部分1071被掺杂，以提高其中的载流子浓度，减小开态时有源层之间的导通电阻。
图3示出根据本发明的另一个示例性实施例的TFT阵列基板的一部分的结构。如图所示，该TFT阵列基板包括衬底基板200、形成在衬底基板200上的第一栅极201、覆盖第一栅极201的第一栅极绝缘层202、设置在第一栅极绝缘层202上的第一有源层204、 覆盖第一有源层204的层间绝缘层205、形成在层间绝缘层205上的第二有源层206、覆盖第二有源层206的第二栅极绝缘层207和设置在第二栅极绝缘层207上的第二栅极209，其中，第一栅极201、第一栅极绝缘层202和第一有源层204构成第一薄膜晶体管的部分，而第二有源层206、第二栅极绝缘层207和第二栅极209构成第二薄膜晶体管的部分，并且第二有源层206与第一有源层204电连接，使得第一薄膜晶体管与第二薄膜晶体管串联连接。
在该实施例中，彼此叠置的第一薄膜晶体管和第二薄膜晶体管的沟道长度分别为L且它们的总有效沟道长度为2L，与现有的薄膜晶体管的沟道长度相同，但在基板上的占用面积降低，从而有利于实现高分辨率的阵列基板和显示面板。另一方面，这两个串联连接的薄膜晶体管能够有效地降低关态时的泄漏电流，增加薄膜晶体管的稳定性。
在一个示例中，这两个有源层204、206中的一个的漏区与另一个的源区电连接，实现这两个薄膜晶体管的串联连接。例如，在图3中，源电极层203形成在第一栅极绝缘层202上，第一有源层204中的源区与源电极层203部分地重叠或接触，实现第一有源层204中的源区与源电极层203的电连接，而第一有源层204中的漏区与第二有源层206的源区电连接，第二有源层206的漏区可以与像素电极层210电连接；如图3所示，像素电极层210可以设置在覆盖第二栅极209和第二栅极绝缘层207的平坦化层208上。
示例性地，该TFT阵列基板设置有贯穿层间绝缘层205以露出第一有源层204的漏区的通孔(未示出)，第二有源层206可以包括位于该通孔内以电连接第一有源层204的漏区和第二有源层206的源区的连接部分，例如，图中所示的从第二有源层206的源区延伸至第一有源层204的漏区的竖直部分。在一个示例中，该连接部分可以由与第二有源层206相同的材料形成，并且优选地，该连接部分被掺杂，以提高其中的载流子浓度，减小开态时有源层之间的导通电阻。
另一方面，本发明的实施例还提供了一种制造TFT阵列基板的方法，包括提供衬底基板，以及在衬底基板上形成两个薄膜晶体管， 使得这两个薄膜晶体管的两个有源层在垂直于衬底基板的方向上相互叠置，每个薄膜晶体管包括具有源区和漏区的有源层，且这两个有源层中的一个的漏区与另一个的源区电连接，由此串联连接这两个薄膜晶体管。
下面将参照图4a-4d，通过示例具体描述本发明的一个示例性实施例的制造TFT阵列基板的方法。
首先，提供一衬底基板100，该衬底基板可为预先清洗的玻璃等透明基板，在其上可包含采用氧化硅、氮化硅或者二者叠层形成的缓冲层，以防止透明基板中的金属离子杂质扩散至有源层中而影响薄膜晶体管的工作特性。
如图4a所示，在衬底基板100上形成第一半导体材料层，并采用第一掩模对第一半导体材料层进行图案化以形成第一有源层102。
如图4b所示，形成覆盖第一有源层102的第一栅极绝缘层103，并在第一栅极绝缘层103上形成栅极材料层，采用第二掩模对栅极材料层进行图案化以形成位于第一有源层102上方的栅极104。栅极可为单层、两层或两层以上结构，可以由金属、金属合金构成，如由钼、铝、钼钨等制成，厚度可以在
Figure PCTCN2016084947-appb-000001
范围内，优选厚度为
Figure PCTCN2016084947-appb-000002
如图4c所示，形成覆盖栅极104和第一栅极绝缘层103的第二栅极绝缘层105。示例性地，第一和/或第二栅极绝缘层可采用单层的氧化硅、氮化硅或者二者的叠层，且本发明不限于此；可使用采用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积第一和/或第二栅极绝缘层，其沉积厚度为
Figure PCTCN2016084947-appb-000003
可根据具体的设计需要选择合适的厚度，优选厚度为
Figure PCTCN2016084947-appb-000004
接着，采用第三掩模形成贯穿第二栅极绝缘层105和第一栅极绝缘层103以露出第一有源层102的漏区的通孔106。
然后，如图4d所示，在第二栅极绝缘层105上形成第二半导体材料层，并采用上述第一掩模对第二半导体材料层进行图案化以形成第二有源层107，第二有源层的一部分位于通孔内形成连接部分1071，以电连接第一有源层102的漏区和第二有源层107的源区。 在一个示例中，第一和/或第二有源层可为非晶硅层通过准分子激光晶化、金属诱导晶化、固相晶化等方法将非晶硅层转变而成的多晶硅层，从而可以形成低温多晶硅阵列基板。需要说明的是，采用不同的晶化方法，其具体的工艺过程及薄膜晶体管的结构会有所不同，在制备过程中需要根据情况增加热处理脱氢、沉积诱导金属、热处理晶化、准分子激光照射晶化、源漏区的掺杂(P型或者N型掺杂)及掺杂杂质的激活等工艺，但不影响本发明的实施，本发明同样会起到有益的效果。示例性地，第一和/或第二有源层的厚度可以为
Figure PCTCN2016084947-appb-000005
优选厚度为
Figure PCTCN2016084947-appb-000006
其形成方法可以为PECVD、LPCVD或者溅射方法，沉积温度在600℃以下。
在一个实施例中，还如图4a所示，在形成第一有源层102之前，或者在形成第一有源层102之后且在形成第一栅极绝缘层103之前，还可以包括在衬底基板上形成导电材料层，并采用第四掩模将导电材料层图案化为源电极层101，其中第一有源层102的一部分与源电极层101的一部分重叠。
此外，在形成栅极104之后且在形成第二栅极绝缘层105之前，可以以栅极104为遮挡掩模进行第一离子注入工艺，以对第一有源层102的源区和漏区进行离子掺杂；在形成第二有源层107之后，以上述第二掩模为另一遮挡掩模进行第二离子注入工艺，以对第二有源层107的源区和漏区进行离子掺杂。可替换地，可以在形成第二有源层107之后，以上述第二掩模为遮挡掩模进行离子注入工艺，以对第一有源层102和第二有源层107的源区和漏区进行离子掺杂。可以理解，在对第二有源层进行离子掺杂时，第二有源层位于通孔内的部分也可以被掺杂，以提高其中的载流子浓度，减小开态时有源层之间的导通电阻。
离子注入工艺可采用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子注入或者固态扩散式注入等方法。优选地，采用主流的离子云式注入方法，可根据设计需要采用含硼如B2H6/H2或者含磷如PH3/H2的混合气体进行注入，离子注入能量可为10～200keV，优选能量在40～100keV。注入剂量可在1×1011～1×1020atoms/cm3范围内，优选剂量为1×1014～1×1018atoms/cm3。
如图2所示，可以采用第五掩模形成覆盖第二有源层107和第二栅极绝缘层105的平坦化层108，采用第六掩模在平坦化层108上形成像素电极层109，像素电极层109可以与第二有源层107的漏区电连接。平坦化层可以由有机材料制成，可选用聚酰亚胺、亚克力等有机光阻材料，厚度可为
Figure PCTCN2016084947-appb-000007
像素电极层可为单层、两层或两层以上结构，由透明导电材料如氧化铟锡、氧化铟锌等构成，或由金属、金属合金如银或银合金等构成，厚度可在
Figure PCTCN2016084947-appb-000008
范围内，优选厚度为
Figure PCTCN2016084947-appb-000009
可以看出，根据本发明的实施例提供的方法也通过六道掩模制造TFT阵列基板，与现有工艺相比不增加掩膜版数量，在工艺实现上并不增加额外的工艺复杂度，且所制备器件的特性更优。
进一步，本发明的实施例还提供了一种显示装置，其包括在上述任一实施例中描述的TFT阵列基板，或包括根据上述任一实施例的方法制造的TFT阵列基板。这种显示装置可以为液晶面板、电子纸、OLED面板、手机、笔记本电脑、平板电脑、显示器、数码相框、导航仪、身份识别设备或任何其它具有显示功能的产品或部件。
尽管已经示出和描述了本发明的示例性实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (18)

  1. 一种TFT阵列基板，包括：
    衬底基板；和
    位于衬底基板上的两个薄膜晶体管，每个薄膜晶体管包括具有源区和漏区的有源层，所述两个薄膜晶体管的两个有源层在垂直于衬底基板的方向上相互叠置，且所述两个有源层中的一个有源层的漏区与另一个有源层的源区电连接，使得所述两个薄膜晶体管串联连接。
  2. 根据权利要求1所述的TFT阵列基板，其中，所述两个有源层包括形成在衬底基板上的第一有源层和位于第一有源层上方的第二有源层，
    所述两个薄膜晶体管还包括至少位于第一有源层和第二有源层之间的覆盖在第一有源层上的第一栅极绝缘层、覆盖在第一栅极绝缘层上的第二栅极绝缘层、和一个栅极，该栅极位于第一栅极绝缘层和第二栅极绝缘层之间以用作所述两个薄膜晶体管的公共栅极，且第二有源层设置在第二栅极绝缘层上。
  3. 根据权利要求2所述的TFT阵列基板，其中，该TFT阵列基板设置有贯穿第一栅极绝缘层和第二栅极绝缘层以露出第一有源层的漏区的通孔，并且第二有源层包括位于该通孔内以电连接第一有源层的漏区和第二有源层的源区的连接部分。
  4. 根据权利要求1所述的TFT阵列基板，其中，
    所述两个薄膜晶体管中的一个薄膜晶体管包括位于衬底基板上的第一栅极、覆盖在第一栅极上的第一栅极绝缘层和位于第一栅极绝缘层上的第一有源层，
    所述两个薄膜晶体管中的另一个薄膜晶体管包括位于第一有源层上方的第二有源层、覆盖第二有源层的第二栅极绝缘层和位于第二栅极绝缘层上的第二栅极，并且
    第二有源层的源区与第一有源层的漏区电连接。
  5. 根据权利要求4所述的TFT阵列基板，还包括覆盖在所述一个薄膜晶体管上的层间绝缘层，其中第二有源层位于层间绝缘层上。
  6. 根据权利要求5所述的TFT阵列基板，其中，该TFT阵列基板设置有贯穿层间绝缘层以露出第一有源层的漏区的通孔，并且第二有源层包括位于该通孔内以电连接第一有源层的漏区和第二有源层的源区的连接部分。
  7. 根据权利要求2-6中任一项所述的TFT阵列基板，还包括与第一有源层的源区电连接的源电极层和与第二有源层的漏区电连接的像素电极层。
  8. 根据权利要求3或6所述的TFT阵列基板，其中所述连接部分包括由与第二有源层相同的材料形成并掺杂的部分。
  9. 根据权利要求1-6中任一项所述的TFT阵列基板，所述有源层包括低温多晶硅层。
  10. 一种制造TFT阵列基板的方法，包括下述步骤：
    提供衬底基板；以及
    在衬底基板上形成两个薄膜晶体管，其中每个薄膜晶体管包括具有源区和漏区的有源层，使得所述两个薄膜晶体管的两个有源层在垂直于衬底基板的方向上相互叠置，且所述两个有源层中的一个的漏区与另一个的源区电连接，由此串联连接所述两个薄膜晶体管。
  11. 根据权利要求10所述的方法，其中形成薄膜晶体管的步骤包括：
    在衬底基板上形成第一半导体材料层，并采用第一掩模对第一 半导体材料层进行图案化以形成第一有源层；
    形成覆盖第一有源层的第一栅极绝缘层；
    在第一栅极绝缘层上形成栅极材料层，并采用第二掩模对栅极材料层进行图案化以形成位于第一有源层上方的栅极；
    形成覆盖栅极和第一栅极绝缘层的第二栅极绝缘层；
    采用第三掩模形成贯穿第二栅极绝缘层和第一栅极绝缘层以露出第一有源层的漏区的通孔；以及
    在第二栅极绝缘层上形成第二半导体材料层，并采用所述第一掩模对第二半导体材料层进行图案化以形成第二有源层，第二有源层的一部分位于通孔内形成连接部分，以电连接第一有源层的漏区和第二有源层的源区。
  12. 根据权利要求11所述的方法，形成第一半导体材料层和/或第二半导体材料层的步骤分别包括：
    形成非晶硅层；以及
    采用准分子激光晶化、金属诱导晶化或固相晶化工艺将非晶硅层转变成多晶硅层。
  13. 根据权利要求11所述的方法，其中，在形成第一有源层之前，或者在形成第一有源层之后且在形成第一栅极绝缘层之前，该方法还包括：
    在衬底基板上形成导电材料层，并采用第四掩模将导电材料层图案化为源电极层，其中第一有源层的一部分与源电极层的一部分重叠。
  14. 根据权利要求11所述的方法，该方法还包括：
    在形成栅极之后且在形成第二栅极绝缘层之前，以栅极为遮挡掩模进行第一离子注入工艺，以对第一有源层的源区和漏区进行离子掺杂；以及
    在形成第二有源层之后，以所述第二掩模为另一遮挡掩模进行第二离子注入工艺，以对第二有源层的源区和漏区进行离子掺杂。
  15. 根据权利要求11所述的方法，该方法还包括：
    在形成第二有源层之后，以所述第二掩模为遮挡掩模进行离子注入工艺，以对第一有源层和第二有源层的源区和漏区进行离子掺杂。
  16. 根据权利要求14或15所述的方法，其中在对第二有源层进行离子掺杂时，第二有源层位于通孔内的连接部分也被掺杂。
  17. 根据权利要求11-15中任一项所述的方法，还包括：
    采用第五掩模在衬底基板上形成覆盖第二有源层和第二栅极绝缘层的平坦化层；以及
    采用第六掩模在平坦化层上形成像素电极层，像素电极层与第二有源层的漏区电连接。
  18. 一种显示装置，包括权利要求1-9中任一项所述的TFT阵列基板，或包括根据权利要求10-17中任一项所述的方法制造的TFT阵列基板。
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