WO2020118920A1 - 有机发光二极管阵列基板及其制造方法 - Google Patents

有机发光二极管阵列基板及其制造方法 Download PDF

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Publication number
WO2020118920A1
WO2020118920A1 PCT/CN2019/077182 CN2019077182W WO2020118920A1 WO 2020118920 A1 WO2020118920 A1 WO 2020118920A1 CN 2019077182 W CN2019077182 W CN 2019077182W WO 2020118920 A1 WO2020118920 A1 WO 2020118920A1
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layer
metal pattern
insulating layer
gate
forming
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PCT/CN2019/077182
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English (en)
French (fr)
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白思航
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武汉华星光电半导体显示技术有限公司
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Priority to US16/464,225 priority Critical patent/US11251253B2/en
Publication of WO2020118920A1 publication Critical patent/WO2020118920A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the invention relates to the field of display, in particular to an organic light emitting diode array substrate and a method for manufacturing the same.
  • OLED display panels Compared with LCD panels, OLED display panels have the advantages of self-illumination, simple structure, wide viewing angle, high color saturation, fast response speed, light and thin, etc. More and more products with displays have begun to adopt OLED panels, such as smart phones and mobile devices. Wear devices, etc. With the large-scale commercial application of OLED panels, people have higher requirements for OLED performance, such as high brightness, high efficiency, low energy consumption, and high stability.
  • the mainstream OLED array is a pixel circuit using 7T1C (seven thin film transistors and a capacitor), as shown in FIG. 1, wherein the prior art uses the gate electrode of the thin film transistor T1 as the lower plate of the capacitor C1.
  • the capacitor C1 may be required to have a larger capacitance value.
  • the capacitance value of the capacitor C1 is proportional to the capacitance area and dielectric constant, and inversely proportional to the distance between the electrode plates. If you want to increase the capacitance value, the prior art usually uses the following three methods: increase the storage capacitor area, increase the dielectric constant or reduce the distance between the electrode plates. Reducing the distance between the electrode plates will lead to a reduction in the thickness of the dielectric layer, and there is a risk of breakdown; the dielectric constant is mainly related to the material, so the most feasible way is to increase the capacitor area.
  • the low-temperature polysilicon active layer of the thin film transistor T1 and the area of the gate electrode are limited. If the gate electrode of the thin film transistor T1 is used as the lower plate of the capacitor, the area of the capacitor will be limited by the area of the gate electrode of the lower layer. Therefore, it is necessary to develop a new type of OLED array structure, which can not only meet the design of high pixel density, but also provide a larger capacitor area to meet more excellent storage capacity.
  • the main object of the present invention is to provide an organic light emitting diode array substrate and a method of manufacturing the same, so that the capacitance in the pixel circuit of the 7T1C is no longer limited by the gate area of the driving transistor, It is more conducive to the improvement of storage capacity.
  • the present invention provides a method for manufacturing an organic light emitting diode array substrate, including the steps
  • the semiconductor layer includes an active region, a source region, and a drain region;
  • An organic light emitting diode and a pixel definition layer are formed on the flat layer.
  • the step of forming an organic light emitting diode and a pixel definition layer on the flat layer includes:
  • the pixel definition layer is formed on the flat layer, wherein the pixel definition layer has an opening exposing the first electrode.
  • the area of the second metal pattern and the first metal pattern is larger than the area of the gate.
  • the method before the step of sequentially forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate, the method further includes the following steps:
  • the third metal pattern connecting the source region and the drain region, the gate, and the semiconductor layer constitute a first transistor.
  • the present invention also provides another method for manufacturing an organic light emitting diode array substrate, which includes the steps of: sequentially forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate, the semiconductor layer includes an active layer A source region and a drain region; forming a through hole in the first insulating layer to partially expose the gate; forming a first metal pattern on the first insulating layer corresponding to the position of the gate, Connecting the first metal pattern to the gate through the through hole; forming a second insulating layer on the first insulating layer to cover the first metal pattern; and on the second insulating layer A second metal pattern is formed corresponding to the position of the first metal pattern, so that the second metal pattern and the first metal pattern overlap and parallel to each other to form a capacitor.
  • the method for manufacturing an organic light emitting diode array substrate further includes the following steps: forming an interlayer dielectric layer on the second insulating layer to cover the second metal pattern; and A third metal pattern is formed on the interlayer dielectric layer.
  • the step of forming a third metal pattern on the interlayer dielectric layer includes forming a gate insulation through the gate electrode at a position corresponding to the source region and the drain region A first via of the layer, the first insulating layer, the second insulating layer, and the interlayer dielectric layer; and forming at least two third metal patterns on the interlayer dielectric layer to pass the third metal pattern
  • the first via is connected to the source region and the drain region, respectively.
  • the method for manufacturing an organic light emitting diode array substrate further includes the following steps: forming a flat layer on the interlayer dielectric layer to cover the third metal pattern; and An organic light emitting diode and a pixel definition layer are formed on the flat layer.
  • the step of forming the organic light emitting diode and the pixel definition layer on the flat layer includes: forming a second via hole through the flat layer to barely connect the drain region The third metal pattern; forming the first electrode of the organic light emitting diode on the flat layer, so that the first electrode is connected to the third metal pattern through the second via; forming the pixel definition A layer is on the flat layer, wherein the pixel definition layer has an opening exposing the first electrode.
  • the area of the second metal pattern and the first metal pattern is larger than the area of the gate.
  • the step of sequentially forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate further includes the following steps: forming a first flexible layer on the substrate , An inorganic film layer, a second flexible layer, and a buffer layer; wherein the semiconductor layer is formed on the buffer layer.
  • the third metal pattern connecting the source region and the drain region, the gate, and the semiconductor layer constitute a first transistor.
  • the present invention also provides an organic light emitting diode array substrate, which includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a first insulating layer, a first metal pattern, a second insulating layer, and a second metal pattern;
  • the semiconductor layer is provided on the substrate and includes an active region, a source region and a drain region;
  • the gate insulating layer is provided on the semiconductor layer
  • the gate is provided on the gate insulating layer and corresponds to the position of the semiconductor layer;
  • the first insulating layer covers the gate and has a through hole, and the through hole partially exposes the gate;
  • the first metal pattern is provided on the first insulating layer and corresponds to the position of the gate; the first metal pattern is connected to the gate through the through hole;
  • the second insulating layer is disposed on the first insulating layer to cover the first metal pattern
  • the second metal pattern is disposed on the second insulating layer and corresponds to the position of the first metal pattern; the second metal pattern and the first metal pattern overlap and parallel to each other to form a capacitor.
  • the organic light emitting diode array substrate includes the first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first transistor in a pixel unit Six transistors, a seventh transistor, the capacitor and the organic light emitting diode.
  • the double-layer metal pattern layer can be used as the upper and lower electrodes of the capacitor in the 7T1C pixel circuit board.
  • the area of the two-layer electrode plates forming the capacitor is no longer limited by the size of the gate area of the driving transistor, which is more conducive to improving the capacity of the storage capacitor.
  • FIG. 1 is a circuit schematic diagram of a 7T1C (seven transistor and a capacitor) pixel circuit used in a conventional organic light emitting diode array substrate.
  • FIG. 2 is a partial cross-sectional view of an organic light emitting diode array substrate according to an embodiment of the invention.
  • 3A to 3C are schematic diagrams of a manufacturing process of an organic light emitting diode array substrate according to an embodiment of the invention.
  • FIG. 4 is a flowchart of a method for manufacturing an organic light emitting diode array substrate according to an embodiment of the invention.
  • FIG. 2 is a partial cross-sectional view of an organic light emitting diode array substrate according to an embodiment of the present invention
  • FIGS. 3A to 3C are manufacturing of an organic light emitting diode array substrate according to an embodiment of the present invention. Schematic diagram of the process.
  • the organic light emitting diode array substrate of the present invention may be a pixel driving circuit using 7T1C (seven thin film transistors and a capacitor), which includes a first transistor, a second transistor, a third transistor, a first Four transistors, a fifth transistor, a sixth transistor, a seventh transistor, a capacitor and an organic light emitting diode, wherein the first transistor is mainly used as a driving transistor for driving the organic light emitting diode to emit light.
  • 7T1C seven thin film transistors and a capacitor
  • the organic light emitting diode array substrate mainly improves on the first transistor and the capacitor, so the partial cross-sectional view of the organic light emitting diode array substrate shown in FIG. 2 mainly illustrates the structure of the first transistor and the capacitor in one pixel unit, It mainly includes a substrate 10, a first transistor T1 and a capacitor.
  • the substrate 10 may be a glass substrate, and a first flexible layer 11, an inorganic film layer 12, a second flexible layer 13, and an M/B layer may be further provided in this order on the substrate 10 14 ⁇ Buffer layer 15.
  • the first flexible layer 11 and the second flexible layer 13 may be flexible plastic substrates.
  • the inorganic film layer 12 may be a silicon dioxide film layer.
  • the buffer layer 15 may be an inorganic material, for example, may be one or a combination of one or more of silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, and silicon carbonitride.
  • the first transistor T1 specifically includes a semiconductor layer 16, a gate insulating layer 18, a gate 17, a source 173, and a drain 174.
  • the semiconductor layer 16 is specifically disposed on the substrate 10, and may be disposed on the buffer layer 15, and includes an active region 160, a source region 161, and a drain region 162.
  • the gate insulating layer 18 is formed on the buffer layer 15 to cover the semiconductor layer 16.
  • the gate 17 is formed on the gate insulating layer 18 and is correspondingly located above the active region 160 of the semiconductor layer 16.
  • the source electrode 173 and the drain electrode 174 are respectively connected to the source region 161 and the drain region 162 of the semiconductor layer 16 through the through hole 200, thereby forming the first transistor T1.
  • the capacitor is disposed above the first transistor T1, wherein the capacitor includes a lower plate 171 and an upper plate 172.
  • the lower plate 171 is disposed above the gate 17 of the first transistor T1 and connected to the gate 17 so that the lower plate 171 and the gate 17 form an equipotential.
  • the upper pole plate 172 is disposed in parallel above the lower pole plate 171.
  • a first insulating layer 19 is first disposed on the gate 17 and has a through hole 190 to partially expose the gate 17, and then a first metal pattern is formed on the first insulating layer 19
  • the upper electrode plate 171 serves as the lower electrode plate 171, and the lower electrode plate 171 (the first metal pattern) is connected to the gate electrode 17 through the through hole 190.
  • a second insulating layer 20 is then disposed on the first insulating layer 19 to cover the lower plate 171 (the first metal pattern), and then a second metal pattern is formed on the second insulating layer 20 Upper and corresponding to the position of the lower plate 171 (the first metal pattern) to serve as the upper plate 172, the upper plate 172 (the second metal pattern) and the lower plate 171 (the The first metal pattern) further constitutes the capacitor.
  • the area of the lower plate 171 and the upper plate 172 may be larger than the area of the grid 17.
  • the area of the lower plate 171 is no longer limited by the gate area of the driving transistor, and can be designed to be larger than The area of the gate 17 is more conducive to the improvement of the storage capacitance.
  • the present invention provides the following manufacturing method, which mainly includes the following steps S100 to S104:
  • Step S100 forming a semiconductor layer 16, a gate insulating layer 18, a gate 17, and a first insulating layer 19 on a substrate 10 in sequence, wherein the semiconductor layer 16 includes an active region 160, a source region 161, and a drain Area 162, as shown in FIG. 3A;
  • Step S101 forming a through hole 190 in the first insulating layer 19 to partially expose the gate electrode 17, as shown in FIG. 3B;
  • Step S102 forming a first metal pattern 171 on the first insulating layer 19 corresponding to the position of the gate 17, so that the first metal pattern 171 is connected to the gate 17 through the through hole 190, as shown in FIG. 3C shown;
  • Step S103 forming a second insulating layer 20 on the first insulating layer 19 to cover the first metal pattern 171, as shown in FIG. 3C;
  • Step S104 forming a second metal pattern 172 on the second insulating layer 20 corresponding to the first metal pattern 171, so that the second metal pattern 172 and the first metal pattern 171 overlap and parallel to each other to form a capacitor, as shown in picture 2.
  • step S100 the following steps are further included:
  • a first flexible layer 11, an inorganic film layer 12, a second flexible layer 13, and a buffer layer 15 are formed on the substrate 10; wherein the semiconductor layer 16 is formed on the buffer layer 15.
  • the manufacturing method further includes the following steps:
  • a third metal pattern (173, 174, 175) is formed on the interlayer dielectric layer 21.
  • the interlayer dielectric layer 21 may be an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx) or a stacked structure composed of silicon oxide and silicon nitride (SiOx/SiNx or SiNx/SiOx ).
  • the step of forming the third metal pattern (173, 174, 175) on the interlayer dielectric layer 21 includes:
  • a first via 200 is formed through the gate insulating layer 18, the first insulating layer 19, the second insulating layer 20, and the interlayer dielectric layer 21 at positions corresponding to the source region 161 and the drain region 162 ;as well as
  • At least two third metal patterns (173, 174) are formed on the interlayer dielectric layer 21, so that the third metal patterns (173, 174) are respectively connected to the source via the first via 200 ⁇ 161 ⁇ 162.
  • the third metal pattern connecting the source region 161 and the drain region 162 constitutes the source electrode 173 and the drain electrode 174, and forms a first transistor T1 with the gate electrode 17 and the semiconductor layer 16 .
  • the manufacturing method further includes the following steps:
  • the flat layer 30 may be a single-layer or multi-layer structure, and the material may include inorganic materials, organic materials, or other suitable materials, where inorganic materials include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride; organic Materials include but are not limited to epoxy resins, for example.
  • the step of forming the organic light emitting diode, the pixel definition layer 40 and the support 50 on the flat layer 30 includes:
  • first electrode 60 of the organic light emitting diode Forming a first electrode 60 of the organic light emitting diode on the flat layer 30, so that the first electrode 60 is connected to the third metal pattern 174 (ie, the drain) through the second via 300;
  • the pixel definition layer 40 is formed on the flat layer 30, wherein the pixel definition layer 40 has an opening 400 exposing the first electrode 60.
  • the subsequent forming steps of the organic light emitting diode are similar to the prior art, and will not be repeated here.
  • the area of the second metal pattern 172 and the first metal pattern 171 may be larger than the area of the gate 17 to increase the storage capacity.
  • the present invention is mainly to deposit a double-layer metal pattern layer on the gate of the driving transistor in the 7T1C pixel circuit, so that the double-layer metal pattern layer can be used in the 7T1C pixel circuit
  • the upper and lower plates of the capacitor In this way, the area of the two electrode plates forming the capacitor is no longer limited by the size of the gate area of the driving transistor, the storage capacitor area increases, and the storage capacity increases, which is more conducive to improving the response rate and the signal transmission is more timely.

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Abstract

一种有机发光二极管阵列基板及其制造方法，所述制造方法包括：于基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层；于所述第一绝缘层上形成第一金属图案，所述第一金属图案通过通孔连接所述栅极；于所述第一绝缘层上形成覆盖所述第一金属图案的第二绝缘层；以及于所述第二绝缘层上形成一第二金属图案，使第二金属图案与第一金属图案相互重叠平行而构成一电容。

Description

有机发光二极管阵列基板及其制造方法 技术领域
本发明涉及显示领域，特别是涉及一种有机发光二极管阵列基板及其制造方法。
 背景技术
由于OLED显示面板相对于LCD面板具有自发光、结构简单、广视角、色饱和度高、反应速度快、轻薄等优点，越来越多的具备显示器的产品开始采用OLED面板，如智能手机及可穿戴装置等。随着OLED面板的大规模商业应用，人们对OLED的性能要求更高，例如要求高亮度、高效率、低能耗、高稳定性等。
基于上述对OLED的要求，提高OLED阵列布局的电学性能显得尤为重要。目前，主流的OLED阵列是采用7T1C(七个薄膜晶体管与一电容)的像素电路，如图1所示，其中现有技术是采用薄膜晶体管T1的栅电极作为电容C1的下极板。为满足更优的电学性能，会需要电容C1具有较大的电容值。电容C1的电容值与电容面积以及介电常数成正比，与电极板之间距离成反比。若想增加电容值，现有技术通常是通过以下三种方式进行：增大存储电容面积、增加介电常数或缩小电极板之间距离。缩小电极板之间距离会导致介电层厚度减小，有击穿风险；介电常数则主要与材料相关，因此最可行的办法为增大电容面积。
 技术问题
然而，现有的像素结构由于对高像素密度(PPI)的需求，薄膜晶体管T1的低温多晶硅有源层以及栅电极面积有所限制。若采用薄膜晶体管T1的栅电极作为电容的下极板，那么电容的面积就会受限于下层的栅电极的面积。因此需要开发一种新型的OLED阵列结构，既能满足高像素密度的设计，又能提供更大的电容面积，以满足更优异的存储能力。
故，有必要提供一种有机发光二极管阵列基板及其制造方法，以解决现有技术所存在的问题。
 技术解决方案
有鉴于现有技术的缺点，本发明的主要目的在于提供一种有机发光二极管阵列基板及其制造方法，可以使7T1C的像素电路中的电容不再受限于驱动晶体管的栅极面积的大小，更有利于存储电容能力的提升。
为达成本发明的前述目的，本发明提供一种有机发光二极管阵列基板的制造方法，包括步骤：
于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层，所述半导体层包含有源区、源极区和漏极区；
于所述第一绝缘层形成通孔，以局部裸露所述栅极；
于所述第一绝缘层上对应所述栅极的位置形成第一金属图案，使所述第一金属图案通过所述通孔连接所述栅极；
于所述第一绝缘层上形成第二绝缘层，以覆盖所述第一金属图案；
于所述第二绝缘层上对应所述第一金属图案的位置形成一第二金属图案，使第二金属图案与第一金属图案相互重叠平行而构成一电容；
于所述第二绝缘层上形成层间介电层，以覆盖所述第二金属图案；
在对应所述源极区和漏极区的位置形成穿过所述栅极绝缘层、第一绝缘层、第二绝缘层及层间介电层的第一过孔；
于所述层间介电层上形成至少两个第三金属图案，使所述第三金属图案通过所述第一过孔分别连接所述源极区和漏极区；
于所述层间介电层上形成平坦层，以覆盖所述第三金属图案；以及
于所述平坦层上形成有机发光二极管及像素定义层。
在本发明的一实施例中，所述于所述平坦层上形成有机发光二极管及像素定义层的步骤包括：
形成穿过所述平坦层的第二过孔，以裸露连接所述漏极区的所述第三金属图案；
形成所述有机发光二极管的第一电极于所述平坦层，使所述第一电极通过所述第二过孔连接所述第三金属图案；
形成所述像素定义层于所述平坦层上，其中所述像素定义层具有裸露所述第一电极的开口。
在本发明的一实施例中，所述第二金属图案与第一金属图案的面积大于所述栅极的面积。
在本发明的一实施例中，在所述于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层的步骤之前还进一步包括下列步骤：
在所述基板上形成第一柔性层、无机膜层、第二柔性层以及缓冲层；其中所述半导体层形成于所述缓冲层上。
在本发明的一实施例中，所述连接所述源极区和漏极区的第三金属图案、所述栅极、所述半导体层构成一第一晶体管。
本发明还提供另一种有机发光二极管阵列基板的制造方法，其包括步骤：于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层，所述半导体层包含有源区、源极区和漏极区；于所述第一绝缘层形成通孔，以局部裸露所述栅极；于所述第一绝缘层上对应所述栅极的位置形成第一金属图案，使所述第一金属图案通过所述通孔连接所述栅极；于所述第一绝缘层上形成第二绝缘层，以覆盖所述第一金属图案；以及于所述第二绝缘层上对应所述第一金属图案的位置形成一第二金属图案，使第二金属图案与第一金属图案相互重叠平行而构成一电容。
在本发明的一实施例中，所述的有机发光二极管阵列基板的制造方法进一步包含下列步骤：于所述第二绝缘层上形成层间介电层，以覆盖所述第二金属图案；以及于所述层间介电层上形成第三金属图案。
在本发明的一实施例中，所述于所述层间介电层上形成第三金属图案的步骤包括：在对应所述源极区和漏极区的位置形成穿过所述栅极绝缘层、第一绝缘层、第二绝缘层及层间介电层的第一过孔；以及于所述层间介电层上形成至少两个第三金属图案，使所述第三金属图案通过所述第一过孔分别连接所述源极区和漏极区。
在本发明的一实施例中，所述的有机发光二极管阵列基板的制造方法进一步包含下列步骤：于所述层间介电层上形成平坦层，以覆盖所述第三金属图案；以及于所述平坦层上形成有机发光二极管及像素定义层。
在本发明的一实施例中，所述于所述平坦层上形成有机发光二极管及像素定义层的步骤包括：形成穿过所述平坦层的第二过孔，以裸露连接所述漏极区的所述第三金属图案；形成所述有机发光二极管的第一电极于所述平坦层，使所述第一电极通过所述第二过孔连接所述第三金属图案；形成所述像素定义层于所述平坦层上，其中所述像素定义层具有裸露所述第一电极的开口。
在本发明的一实施例中，所述第二金属图案与第一金属图案的面积大于所述栅极的面积。
在本发明的一实施例中，在于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层的步骤之前还进一步包括下列步骤：在所述基板上形成第一柔性层、无机膜层、第二柔性层以及缓冲层；其中所述半导体层形成于所述缓冲层上。
在本发明的一实施例中，所述连接所述源极区和漏极区的第三金属图案、所述栅极、所述半导体层构成一第一晶体管。
本发明还提供一种有机发光二极管阵列基板，其包括基板、半导体层、栅极绝缘层、栅极、第一绝缘层、第一金属图案、第二绝缘层及第二金属图案；
所述半导体层设于所述基板上并包含有源区、源极区和漏极区；
所述栅极绝缘层设于所述半导体层上；
所述栅极设于所述栅极绝缘层上且对应所述半导体层的位置；
所述第一绝缘层覆盖所述栅极且具有通孔，所述通孔局部裸露所述栅极；
所述第一金属图案设于所述第一绝缘层上且对应所述栅极的位置；所述第一金属图案通过所述通孔连接所述栅极；
所述第二绝缘层设于所述第一绝缘层上而覆盖所述第一金属图案；
所述第二金属图案设于所述第二绝缘层上且对应所述第一金属图案的位置；所述第二金属图案与第一金属图案相互重叠平行而构成一电容。
在本发明的一实施例中，所述有机发光二极管阵列基板在一个像素单元中包括所述第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管、一第五晶体管、一第六晶体管、一第七晶体管、所述电容及所述有机发光二极管。
 有益效果
在形成有机发光二极管阵列基板的过程中，通过在作为7T1C像素电路中的驱动晶体管的栅极上方沉积双层金属图案层，使双层金属图案层能作为7T1C的像素电路中的电容的上下极板。如此，构成电容的两层电极板面积不再受限于驱动晶体管的栅极面积的大小，更有利于存储电容能力的提升。
 附图说明
图1是现有有机发光二极管阵列基板采用7T1C(七晶体管及一电容)像素电路的电路示意图。
图2是本发明一实施例的有机发光二极管阵列基板的局部剖视图。
图3A至图3C是本发明一实施例的有机发光二极管阵列基板的制造流程示意图。
图4是本发明一实施例的有机发光二极管阵列基板的制造方法的流程图。
 本发明的实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参考图2及图3A至图3C所示，图2是本发明一实施例的有机发光二极管阵列基板的局部剖视图；图3A至图3C是本发明一实施例的有机发光二极管阵列基板的制造流程示意图。
本发明的有机发光二极管阵列基板可以是采用7T1C(七个薄膜晶体管与一电容)的像素驱动电路，其在一个像素单元中包括一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管、一第五晶体管、一第六晶体管、一第七晶体管、一电容及一有机发光二极管，其中所述第一晶体管主要作为驱动有机发光二极管发光的驱动晶体管。
所述有机发光二极管阵列基板主要是针对第一晶体管与电容进行改进，故图2所示的有机发光二极管阵列基板的局部剖视图主要绘示了在一个像素单元中的第一晶体管与电容的结构，其主要包括一基板10、第一晶体管T1与一电容。
具体而言，所述基板10可为一玻璃基板，且所述基板10上可进一步依序设有一第一柔性层11、一无机膜层12、一第二柔性层13、一M/B层14以及一缓冲层15。所述第一柔性层11和第二柔性层13可以是柔性塑料基板。所述无机膜层12可以是二氧化硅膜层。所述缓冲层15可为无机材料，例如，可为氮化硅、氧化硅、碳氧化硅、氮氧化硅和碳氮化硅中的一种或多种的组合。
所述第一晶体管T1具体包括半导体层16、栅极绝缘层18、栅极17、源极173及漏极174。所述半导体层16具体是设置于所述基板10上，且可以是设置于所述缓冲层15上，并且包括有源区160、源极区161和漏极区162。所述栅极绝缘层18形成于所述缓冲层15上，以覆盖所述半导体层16。所述栅极17形成于所述栅极绝缘层18上，且对应位于所述半导体层16的有源区160上方。所述源极173及漏极174分别通过通孔200连接至所述半导体层16的源极区161和漏极区162，进而构成所述第一晶体管T1。
在本发明的有机发光二极管阵列基板中，所述电容是设置于所述第一晶体管T1的上方，其中所述电容包括一下极板171和一上极板172。所述下极板171设置于所述第一晶体管T1的栅极17上方，并连接所述栅极17，使下极板171与所述栅极17形成等电位。所述上极板172则平行设于所述下极板171的上方。具体而言，一第一绝缘层19先设置于所述栅极17上，并且具有通孔190，以局部裸露所述栅极17，接着一第一金属图案形成于所述第一绝缘层19上，以作为所述下极板171，并且所述下极板171(所述第一金属图案)通过所述通孔190连接所述栅极17。一第二绝缘层20接着设于所述第一绝缘层19上而覆盖所述下极板171(所述第一金属图案)，接着一第二金属图案再形成于所述第二绝缘层20上且对应所述下极板171(所述第一金属图案)的位置，以作为所述上极板172，所述上极板172(第二金属图案)与所述下极板171(所述第一金属图案)进而构成所述电容。
所述下极板171与上极板172的面积可以大于所述栅极17的面积。
从上述结构可知，由于构成电容的下极板171是额外的沉积于栅极17的上方，故下极板171的面积不再受限于驱动晶体管的栅极面积的大小，可设计成较大于所述栅极17的面积，更有利于存储电容能力的提升。
请参考图3A至图3C及图4所示，为了提供上述的有机发光二极管阵列基板，本发明提供了如下的制造方法，主要包括下列步骤S100~S104：
步骤S100：于一基板10上依序形成半导体层16、栅极绝缘层18、栅极17、第一绝缘层19，其中所述半导体层16包含有源区160、源极区161和漏极区162，如图3A所示；
步骤S101：于所述第一绝缘层19形成通孔190，以局部裸露所述栅极17，如图3B所示；
步骤S102：于所述第一绝缘层19上对应所述栅极17的位置形成第一金属图案171，使所述第一金属图案171通过所述通孔190连接所述栅极17，如图3C所示；
步骤S103：于所述第一绝缘层19上形成第二绝缘层20，以覆盖所述第一金属图案171，如图3C所示；以及
步骤S104：于所述第二绝缘层20上对应所述第一金属图案171的位置形成一第二金属图案172，使第二金属图案172与第一金属图案171相互重叠平行而构成一电容，如图2所示。
在一实施例中，在步骤S100之前还进一步包括下列步骤：
在所述基板10上形成第一柔性层11、无机膜层12、第二柔性层13以及缓冲层15；其中所述半导体层16形成于所述缓冲层15上。
在一实施例中，所述制造方法还进一步包含下列步骤：
于所述第二绝缘层20上形成层间介电层21，以覆盖所述第二金属图案172；
于所述层间介电层21上形成第三金属图案(173, 174, 175)。
所述层间介电层21可以是无机材料，像是氧化硅(SiOx)、氮化硅(SiNx)或是由氧化硅及氮化硅共同组成的堆迭结构(SiOx/SiNx或SiNx/SiOx)。
具体而言，所述于所述层间介电层21上形成第三金属图案(173, 174, 175)的步骤包括：
在对应所述源极区161和漏极区162的位置形成穿过所述栅极绝缘层18、第一绝缘层19、第二绝缘层20及层间介电层21的第一过孔200；以及
于所述层间介电层21上形成至少两个第三金属图案(173, 174)，使所述第三金属图案(173, 174)通过所述第一过孔200分别连接所述源极区161和漏极区162。所述连接所述源极区161和漏极区162的第三金属图案即构成所述源极173及漏极174，并与所述栅极17、所述半导体层16构成一第一晶体管T1。
在一实施例中，所述制造方法还进一步包含下列步骤：
于所述层间介电层21上形成平坦层30，以覆盖所述第三金属图案(173, 174, 175)；以及
于所述平坦层30上形成有机发光二极管、像素定义层40及支撑件50。所述平坦层30可为单层或多层结构，且材质可包括无机材料、有机材料、或其它合适的材料，其中无机材料例如包括但不限于氧化硅、氮化硅或氮氧化硅；有机材料例如包括但不限于环氧树脂。
具体而言，所述于所述平坦层30上形成有机发光二极管、像素定义层40及支撑件50的步骤包括：
形成穿过所述平坦层30的第二过孔300，以裸露连接所述漏极区162的所述第三金属图案174；
形成所述有机发光二极管的第一电极60于所述平坦层30，使所述第一电极60通过所述第二过孔300连接所述第三金属图案174(即所述漏极)；
形成所述像素定义层40于所述平坦层30上，其中所述像素定义层40具有裸露所述第一电极60的开口400。
在形成所述有机发光二极管的第一电极60(即阳极)之后，所述有机发光二极管的后续成形步骤与现有技术相似，在此不再赘述。
具体而言，所述第二金属图案172与第一金属图案171的面积可大于所述栅极17的面积，以增加存储能力。
综上所述，相较于现有技术，本发明主要是通过在作为7T1C像素电路中的驱动晶体管的栅极上方沉积双层金属图案层，使双层金属图案层能作为7T1C的像素电路中的电容的上下极板。如此，构成电容的两层电极板面积不再受限于驱动晶体管的栅极面积的大小，存储电容面积增加，存储能力增加，更有利于提升响应速率，信号传输更及时。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (15)

  1. 一种有机发光二极管阵列基板的制造方法，包括步骤：
    于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层，所述半导体层包含有源区、源极区和漏极区；
    于所述第一绝缘层形成通孔，以局部裸露所述栅极；
    于所述第一绝缘层上对应所述栅极的位置形成第一金属图案，使所述第一金属图案通过所述通孔连接所述栅极；
    于所述第一绝缘层上形成第二绝缘层，以覆盖所述第一金属图案；
    于所述第二绝缘层上对应所述第一金属图案的位置形成一第二金属图案，使第二金属图案与第一金属图案相互重叠平行而构成一电容；
    于所述第二绝缘层上形成层间介电层，以覆盖所述第二金属图案；
    在对应所述源极区和漏极区的位置形成穿过所述栅极绝缘层、第一绝缘层、第二绝缘层及层间介电层的第一过孔；
    于所述层间介电层上形成至少两个第三金属图案，使所述第三金属图案通过所述第一过孔分别连接所述源极区和漏极区；
    于所述层间介电层上形成平坦层，以覆盖所述第三金属图案；以及
    于所述平坦层上形成有机发光二极管及像素定义层。
  2. 如权利要求1所述的有机发光二极管阵列基板的制造方法，其中，所述于所述平坦层上形成有机发光二极管及像素定义层的步骤包括：
    形成穿过所述平坦层的第二过孔，以裸露连接所述漏极区的所述第三金属图案；
    形成所述有机发光二极管的第一电极于所述平坦层，使所述第一电极通过所述第二过孔连接所述第三金属图案；
    形成所述像素定义层于所述平坦层上，其中所述像素定义层具有裸露所述第一电极的开口。
  3. 如权利要求1所述的有机发光二极管阵列基板的制造方法，其中，所述第二金属图案与第一金属图案的面积皆大于所述栅极的面积。
  4. 如权利要求1所述的有机发光二极管阵列基板的制造方法，其中，在于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层的步骤之前还进一步包括下列步骤：
    在所述基板上形成第一柔性层、无机膜层、第二柔性层以及缓冲层；其中所述半导体层形成于所述缓冲层上。
  5. 如权利要求1所述的有机发光二极管阵列基板的制造方法，其中，所述连接所述源极区和漏极区的第三金属图案、所述栅极、所述半导体层构成一第一晶体管。
  6. 一种有机发光二极管阵列基板的制造方法，包括步骤：
    于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层，所述半导体层包含有源区、源极区和漏极区；
    于所述第一绝缘层形成通孔，以局部裸露所述栅极；
    于所述第一绝缘层上对应所述栅极的位置形成第一金属图案，使所述第一金属图案通过所述通孔连接所述栅极；
    于所述第一绝缘层上形成第二绝缘层，以覆盖所述第一金属图案；以及
    于所述第二绝缘层上对应所述第一金属图案的位置形成一第二金属图案，使第二金属图案与第一金属图案相互重叠平行而构成一电容。
  7. 如权利要求6所述的有机发光二极管阵列基板的制造方法，其中，所述制造方法进一步包含下列步骤：
    于所述第二绝缘层上形成层间介电层，以覆盖所述第二金属图案；以及
    于所述层间介电层上形成第三金属图案。
  8. 如权利要求7所述的有机发光二极管阵列基板的制造方法，其中，所述于所述层间介电层上形成第三金属图案的步骤包括：
    在对应所述源极区和漏极区的位置形成穿过所述栅极绝缘层、第一绝缘层、第二绝缘层及层间介电层的第一过孔；以及
    于所述层间介电层上形成至少两个第三金属图案，使所述第三金属图案通过所述第一过孔分别连接所述源极区和漏极区。
  9. 如权利要求7所述的有机发光二极管阵列基板的制造方法，其中，所述制造方法进一步包含下列步骤：
    于所述层间介电层上形成平坦层，以覆盖所述第三金属图案；以及
    于所述平坦层上形成有机发光二极管及像素定义层。
  10. 如权利要求9所述的有机发光二极管阵列基板的制造方法，其中，所述于所述平坦层上形成有机发光二极管及像素定义层的步骤包括：
    形成穿过所述平坦层的第二过孔，以裸露连接所述漏极区的所述第三金属图案；
    形成所述有机发光二极管的第一电极于所述平坦层，使所述第一电极通过所述第二过孔连接所述第三金属图案；
    形成所述像素定义层于所述平坦层上，其中所述像素定义层具有裸露所述第一电极的开口。
  11. 如权利要求6所述的有机发光二极管阵列基板的制造方法，其中，所述第二金属图案与第一金属图案的面积大于所述栅极的面积。
  12. 如权利要求6所述的有机发光二极管阵列基板的制造方法，其中，在于一基板上依序形成半导体层、栅极绝缘层、栅极、第一绝缘层的步骤之前还进一步包括下列步骤：
    在所述基板上形成第一柔性层、无机膜层、第二柔性层以及缓冲层；其中所述半导体层形成于所述缓冲层上。
  13. 如权利要求8所述的有机发光二极管阵列基板的制造方法，其中，所述连接所述源极区和漏极区的第三金属图案、所述栅极、所述半导体层构成一第一晶体管。
  14. 一种有机发光二极管阵列基板，其包括基板、半导体层、栅极绝缘层、栅极、第一绝缘层、第一金属图案、第二绝缘层及第二金属图案；
    所述半导体层设于所述基板上并包含有源区、源极区和漏极区；
    所述栅极绝缘层覆盖所述半导体层；
    所述栅极设于所述栅极绝缘层上且对应位于所述半导体层的有源区上方；
    所述第一绝缘层设于所述栅极上且具有通孔，所述通孔局部裸露所述栅极；
    所述第一金属图案设于所述第一绝缘层上；所述第一金属图案通过所述通孔连接所述栅极；
    所述第二绝缘层设于所述第一绝缘层上而覆盖所述第一金属图案；
    所述第二金属图案设于所述第二绝缘层上且对应所述第一金属图案的位置；所述第二金属图案与第一金属图案相互重叠平行而构成一电容。
  15. 如权利要求14所述的有机发光二极管阵列基板，其中，所述有机发光二极管阵列基板在一个像素单元中包括所述第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管、一第五晶体管、一第六晶体管、一第七晶体管、所述电容及所述有机发光二极管。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11374035B2 (en) 2019-07-25 2022-06-28 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and display panel
CN110190073B (zh) * 2019-07-25 2019-11-19 武汉华星光电半导体显示技术有限公司 阵列基板
CN111599750A (zh) * 2020-05-29 2020-08-28 福建华佳彩有限公司 一种提升容值的补偿电容结构及制作方法
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103985736A (zh) * 2014-04-30 2014-08-13 京东方科技集团股份有限公司 Amoled阵列基板及制作方法和显示装置
CN203850301U (zh) * 2014-04-30 2014-09-24 京东方科技集团股份有限公司 有源矩阵有机电致发光器件阵列基板和显示装置
US20170025492A1 (en) * 2015-07-23 2017-01-26 Samsung Display Co., Ltd. Organic light-emitting diode display
US9871094B2 (en) * 2014-10-08 2018-01-16 Samsung Display Co., Ltd. Organic light emitting diode display and method for manufacturing organic light emitting diode display

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140672A (en) * 1999-03-05 2000-10-31 Symetrix Corporation Ferroelectric field effect transistor having a gate electrode being electrically connected to the bottom electrode of a ferroelectric capacitor
JP2003060054A (ja) * 2001-08-10 2003-02-28 Rohm Co Ltd 強誘電体キャパシタを有する半導体装置
KR100426031B1 (ko) * 2001-12-29 2004-04-03 엘지.필립스 엘시디 주식회사 능동행렬 유기전기발광소자 및 그의 제조 방법
US6730950B1 (en) * 2003-01-07 2004-05-04 Texas Instruments Incorporated Local interconnect using the electrode of a ferroelectric
KR100796654B1 (ko) * 2006-06-02 2008-01-22 삼성에스디아이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN202905716U (zh) * 2012-10-31 2013-04-24 四川虹视显示技术有限公司 一种amoled像素电容
US9276050B2 (en) * 2014-02-25 2016-03-01 Lg Display Co., Ltd. Organic light emitting display device
CN105590580A (zh) * 2014-10-21 2016-05-18 张学一 一种有源矩阵有机发光二极管的像素电路
CN205609526U (zh) * 2016-05-13 2016-09-28 京东方科技集团股份有限公司 一种显示基板及柔性显示器件
KR20180041793A (ko) * 2016-10-14 2018-04-25 삼성디스플레이 주식회사 유기 발광 표시 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103985736A (zh) * 2014-04-30 2014-08-13 京东方科技集团股份有限公司 Amoled阵列基板及制作方法和显示装置
CN203850301U (zh) * 2014-04-30 2014-09-24 京东方科技集团股份有限公司 有源矩阵有机电致发光器件阵列基板和显示装置
US9871094B2 (en) * 2014-10-08 2018-01-16 Samsung Display Co., Ltd. Organic light emitting diode display and method for manufacturing organic light emitting diode display
US20170025492A1 (en) * 2015-07-23 2017-01-26 Samsung Display Co., Ltd. Organic light-emitting diode display

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