WO2021217840A1 - 显示面板及显示面板的制作方法 - Google Patents

显示面板及显示面板的制作方法 Download PDF

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Publication number
WO2021217840A1
WO2021217840A1 PCT/CN2020/097806 CN2020097806W WO2021217840A1 WO 2021217840 A1 WO2021217840 A1 WO 2021217840A1 CN 2020097806 W CN2020097806 W CN 2020097806W WO 2021217840 A1 WO2021217840 A1 WO 2021217840A1
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WIPO (PCT)
Prior art keywords
layer
area
base substrate
via hole
display panel
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PCT/CN2020/097806
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English (en)
French (fr)
Inventor
赵慧慧
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US17/057,710 priority Critical patent/US11825701B2/en
Publication of WO2021217840A1 publication Critical patent/WO2021217840A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method of the display panel.
  • a flexible display device is a display device formed based on a flexible base material. Since the flexible display device has the characteristics of rollability, wide viewing angle, and portability, it has broad application prospects and good market potential in portable products and most display application fields.
  • Flexible organic light emitting diode (OLED) display panels have a complicated manufacturing process and require a large number of masks, resulting in low production yields and high prices.
  • Existing flexible OLED display panels have at least 12 to mask manufacturing processes. Among them, the via holes connecting the source and drain electrodes with the active layer and the via holes used to relieve bending stress in the display area require a separate mask manufacturing process, which makes the manufacturing process of the display panel more complicated and costly. In addition, poor products may appear in each manufacturing process, resulting in a decrease in the production yield of the display panel. At the same time, the display panel still has a certain thickness of inorganic material film. Inorganic materials with poor flexibility make the flexible display panel in the bending process. There will be a risk of cracks.
  • the existing display panel has the problems of complicated manufacturing process of via holes, high cost and low production yield. Therefore, it is necessary to provide a display panel and a manufacturing method of the display panel to improve this defect.
  • the embodiments of the present disclosure provide a display panel and a manufacturing method of the display panel, which are used to solve the problems of complicated manufacturing process, high cost, and low production yield of the existing display panel with via holes.
  • An embodiment of the present disclosure provides a display panel including a display area and a non-display area surrounding the display area, the non-display area includes a binding area, and the display panel further includes:
  • the barrier layer is arranged on the base substrate
  • the buffer layer is arranged on the side of the barrier layer away from the base substrate;
  • the thin film transistor array layer is arranged on the side of the buffer layer away from the base substrate, and includes a plurality of thin film transistors and at least two layers of insulating layers for blocking the stacked arrangement of devices in the thin film transistor;
  • the display device layer is arranged on the side of the thin film transistor array layer away from the base substrate;
  • the display area is provided with a plurality of first vias arranged at intervals
  • the binding area is provided with a plurality of second vias arranged at intervals, the first vias and the second vias Both pass through the insulating layer to the side of the base substrate close to the barrier layer, and both the first via hole and the second via hole are filled with a flexible material.
  • the second via hole includes a first area and a second area, the bottom surface of the second area is in contact with the side of the base substrate close to the barrier layer, and the first area It communicates with the second area on the side of the buffer layer away from the base substrate.
  • the first via includes a first portion and a second portion, the first portion and the first region of the second via are provided in the same layer, and the second portion is The second region of the second via is arranged in the same layer.
  • the aperture of the first part is larger than the aperture of the second part.
  • the aperture of the first part and the aperture of the second part are gradually reduced along the direction from the insulating layer to the base substrate.
  • angles formed by the side walls of the first via hole and the side walls of the second via hole with the first direction are both in the range of 40° to 80°.
  • An embodiment of the present disclosure further provides a display panel, including a display area and a non-display area surrounding the display area, the non-display area includes a binding area, and the display panel further includes:
  • the barrier layer is arranged on the base substrate
  • the buffer layer is arranged on the side of the barrier layer away from the base substrate;
  • the thin film transistor array layer is arranged on the side of the buffer layer away from the base substrate, and includes a plurality of thin film transistors and at least two layers of insulating layers for blocking the stacked arrangement of devices in the thin film transistor;
  • the display device layer is arranged on the side of the thin film transistor array layer away from the base substrate;
  • the display area is provided with a plurality of first vias arranged at intervals
  • the binding area is provided with a plurality of second vias arranged at intervals, the first vias and the second vias
  • the insulating layer penetrates to the side of the base substrate close to the barrier layer
  • the second via hole includes a first area and a second area
  • the bottom surface of the second area is connected to the base substrate
  • the side close to the base substrate is in contact, the first area and the second area are communicated on the side of the buffer layer away from the base substrate
  • the first via hole includes The first part arranged in the same layer as the region and the second part arranged in the same layer as the second region, and both the first via hole and the second via hole are filled with a flexible material.
  • the aperture of the first part is larger than the aperture of the second part.
  • the aperture of the first part and the aperture of the second part are gradually reduced along the direction from the insulating layer to the base substrate.
  • angles formed by the side walls of the first via hole and the side walls of the second via hole with the first direction are both in the range of 40° to 80°.
  • the embodiment of the present disclosure also provides a manufacturing method of a display panel, including:
  • a base substrate on which a barrier layer, a buffer layer, an active layer, a gate insulating layer, a gate line layer, and an interlayer insulating layer are formed;
  • the base substrate includes a display area and a non-display area surrounding the display area, the non-display area includes a binding area, a plurality of the first via holes are arranged at intervals in the display area, and a plurality of The second via holes are arranged at intervals in the binding area.
  • first portion and the first region are formed by etching using the first mask, a plurality of first portions penetrating the interlayer insulating layer and the gate insulating layer are formed at the same time. Three vias to expose part of the active layer.
  • the aperture of the first part is larger than the aperture of the second part.
  • the angle formed by the sidewalls of the first part and the second part and the first direction is between 40° and 80°.
  • a plurality of first vias arranged at intervals are arranged in the display area of the display panel, and a plurality of second vias arranged at intervals are arranged in the binding area, the first via and the second via
  • the holes are all penetrated from the insulating layer to the side of the base substrate close to the barrier layer, so that the second via process can be used to form the first via at the same time, eliminating the need to separately fabricate the first via
  • the manufacturing process and the mask can improve the production yield and reduce the production cost.
  • the first via can be used to remove part of the inorganic insulating material in the buffer layer and the barrier layer, and fill it with a flexible material to improve the display panel’s performance. Anti-bending performance to reduce the risk of cracks.
  • FIG. 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the cross-sectional structure of the display panel provided in FIG. 1 along the C-C direction in the disclosed embodiment
  • 3A to 3C are schematic diagrams of the cross-sectional structure of the display panel in FIG. 1 along the direction C-C in the display panel manufacturing method provided by the embodiments of the present disclosure;
  • FIG. 4 is a schematic diagram of a cross-sectional structure of the display panel in FIG. 1 along the C-C direction in another method for manufacturing a display panel provided by an embodiment of the disclosure.
  • FIG. 1 is a schematic diagram of a plan structure of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a display area A and a non-display area B surrounding the display area A.
  • the non-display area B includes The binding area B1 and the binding area B1 can be bent to the back of the display panel, thereby reducing the frame width of the display panel and increasing the screen-to-body ratio.
  • FIG. 2 is a schematic cross-sectional structure view of the display panel in FIG.
  • the buffer layer 13 on one side of the base substrate 11, the thin film transistor array layer 14 provided on the side of the buffer layer 13 away from the base substrate 11, and the thin film transistor array layer 14 provided on the side away from the base substrate 11 Display device layer 15.
  • the material used for the barrier layer 12 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon, which is mainly used to block water and oxygen and prevent external water vapor or oxygen from corroding.
  • the material used for the buffer layer 13 includes one or two of silicon nitride and silicon oxide, and is mainly used for buffering and protection.
  • the thin film transistor array layer 14 includes a plurality of thin film transistors 141.
  • the thin film transistor 141 in the embodiment of the present disclosure is a thin film transistor with a double gate structure, and includes an active layer 1411, a first gate line layer 1412, and a second The gate line layer 1413 and the source and drain electrode layer 1414.
  • the thin film transistor array layer 14 further includes a first gate insulating layer 142 disposed on the side of the buffer layer 13 away from the base substrate 11 and stacked on the first gate.
  • a flexible layer 16 is provided between the source and drain electrode layer 1414 and the interlayer insulating layer 144.
  • the source and drain electrode layer 1414 penetrates the flexible layer 16, the interlayer insulating layer 144, the second gate insulating layer 143 and the first gate electrode.
  • the via hole of the insulating layer 142 is electrically connected to the active layer 1411.
  • the thin film transistor 141 may also be a thin film transistor containing only one gate line layer.
  • the thin film transistor 141 may also have a top gate or a bottom gate structure, which can be applied to the embodiments of the present disclosure. , There is no restriction here.
  • a flat layer 17 is provided on the side of the flexible layer 16 away from the base substrate 11.
  • the display device layer 15 is provided on the flat layer 17, and includes an anode 151, a light-emitting layer 152 and a cathode (not shown in the figure). (Shown), the anode 151 is connected to the source and drain electrode layer 1414 through a via hole penetrating the planarization layer 17.
  • the flat layer 17 is also provided with a pixel definition layer 18, which covers the anode 151, and the pixel definition layer 18 is provided with grooves, which expose part of the anode 151, and the light-emitting layer 152 is arranged in the grooves Inside.
  • a plurality of spacers 19 arranged at intervals are provided on the side of the pixel defining layer 18 away from the array substrate 11.
  • a plurality of first via holes V1 arranged at intervals are provided in the display area A
  • a plurality of second via holes V2 arranged at intervals are provided in the binding area B1
  • the first via holes V1 and the second via holes V1 are arranged at intervals.
  • the two via holes V2 both penetrate from the interlayer insulating layer 144 to the side of the base substrate 11 close to the barrier layer 12, and both have the same height in the direction perpendicular to the thickness of the display panel, and both expose part of the base substrate 11 to This removes part of the inorganic insulating material in the buffer layer 13 and the barrier layer 12 to improve the bending resistance of the display panel.
  • both the first via hole V1 and the second via hole V2 are filled with the flexible material in the flexible layer 16.
  • the first via hole V1 is used to relieve the stress generated in the bending process of the display area A, so that the display area is in It is not easy to produce cracks during bending
  • the second via hole V2 is used to release the stress generated in the bonding area B1 during the bending process, so as to prevent the multiple data lines L located above it from breaking.
  • the second via V2 includes a first area V21 and a second area V22.
  • the first region V21 penetrates the interlayer insulating layer 144, the second gate insulating layer 143 and the first gate insulating layer 142
  • the second region V22 penetrates the buffer layer 13 and the barrier layer 12, and the bottom surface of the second region V22 and the liner
  • the side of the base substrate 11 close to the barrier layer 12 is in contact, and the first area V21 and the second area V22 are connected on the side of the buffer layer 13 away from the base substrate 11.
  • the first area V21 and the second area V22 are formed by etching twice due to different film layers and different aperture sizes.
  • the first via hole V1 also includes a first portion V11 and a second portion V12.
  • the first portion V11 and the first region V21 of the second via hole V2 are arranged in the same layer, that is, the first portion V11 penetrates the interlayer insulating layer 144 and the second gate electrode.
  • the insulating layer 143 and the first gate insulating layer 142, and the first portion V11 and the first region V21 have the same height along the thickness direction of the display panel; the second portion V12 is provided in the same layer as the second region V22 of the second via V2, That is, the second part V12 penetrates through the buffer layer 13 and the barrier layer 12, so that the second part V12 can not only be used to remove the inorganic insulating material in the barrier layer 12 and the buffer layer 13 to increase the bending resistance of the display panel, but also Using the manufacturing process of forming the second via hole V2, the first via hole V1 is formed at the same time as the second via hole V2 is formed, so as to save the manufacturing process and the mask of the first via hole V1 separately, thereby improving the production yield. And reduce production costs.
  • the aperture of the first part V11 of the first via hole V1 should be larger than the aperture of the second part V12, so as to form a stepped buffer angle at the connection between the first part V11 and the second part V12 of the buffer layer 13, which can slow down
  • the slope of the first via hole V1 reduces the bending stress of the display area A during the bending process.
  • the aperture of the first part V11 and the aperture of the second part V12 of the first via hole V1 are gradually reduced along the direction from the interlayer insulating layer 144 to the base substrate 11, that is, the first part V11 and the second part V12 are
  • the shape of the cross-sectional structure shown in FIG. 1 is an inverted trapezoid, and the angles formed by the side walls of the first part V11 and the side walls of the second part V12 and the first direction are both acute angles, and the first direction is an acute angle with the display The horizontal direction perpendicular to the thickness of the panel.
  • the angles formed by the side walls of the first part V11 and the side walls of the second part V12 with the first direction are both between 40° and 80°, and the angle of the included angle is too large, resulting in the first transition.
  • the slope of the hole V1 is too large, which is not conducive to reducing the bending stress in the display area. If the angle of the included angle is too small, the opening area of the first via hole V1 will be too large, which is not conducive to increasing the opening area of the pixel.
  • the characteristics of the first region V21 and the second region V21 of the second via V2 are the same as those of the above-mentioned first via V1, and will not be repeated here.
  • the display panel provided by the embodiment of the present disclosure is provided with a plurality of first via holes arranged at intervals in the display area, and a plurality of second via holes arranged at intervals in the binding area,
  • the first via hole and the second via hole are both penetrated from the insulating layer to the side of the base substrate close to the barrier layer, so that the second via process can be used to simultaneously form the first via hole, saving The process of making the first via hole and the mask separately, which improves the production yield and reduces the production cost.
  • the first via hole can be used to remove part of the inorganic insulating material in the buffer layer 13 and the barrier layer 12, and fill the inside of it There are flexible materials to improve the bending resistance of the display panel and reduce the risk of cracks.
  • FIGS. 3A to 3C are the display panel of FIG. Schematic diagram of the cross-sectional structure, the manufacturing method includes:
  • Step S1 Provide a base substrate 11, on which a barrier layer 12, a buffer layer 13, an active layer 1411, a first gate insulating layer 142, a first gate line layer 1412, and a second gate are formed Polar insulating layer 143, second gate line layer 1413 and interlayer insulating layer 144;
  • Step S2 Using the first mask, etching to form the first part of the first via hole V1 penetrating the interlayer insulating layer 144, the first gate insulating layer 143 and the second gate insulating layer 142 as shown in FIG. 3A V11 and the first area V21 of the second via V2;
  • Step S3 Using a second mask, continue to etch on the basis of the first portion V11 and the first region V21 to form a penetrating through the buffer layer 13 and the barrier layer 12 as shown in FIG. 3B The second portion V12 of the first via V1 and the second area V22 of the second via V2;
  • Step S4 Using a third mask, etch to form a plurality of third via holes V3 passing through the interlayer insulating layer 144, the first gate insulating layer 143 and the second gate insulating layer 142 as shown in FIG. 3C.
  • the bottom surface of the third via hole V3 is in contact with the active layer 1411, and a part of the active layer 1411 is exposed;
  • Step S5 As shown in FIG. 2, a flexible layer 16 is formed on the surface of the interlayer insulating layer 144 away from the base substrate 11, and the flexible material of the flexible layer 16 fills the first via hole V1 and the second via hole V2;
  • Step S6 forming a source-drain electrode layer 1414 and a plurality of data lines L on the flexible layer 16, the source-drain electrode layer 1414 is in contact with the active layer 1411 through the third via V3;
  • Step S7 forming a stacked flat layer 17, a pixel definition layer 18, a display device layer 15 and a plurality of spacers 19 on the side of the flexible layer 16 away from the base substrate 11.
  • the structure of the display device layer 15 is the same as the structure of the display device layer in the display panel provided in the foregoing embodiment, and will not be repeated here.
  • the first mask can be used to form the first region V21 of the second via V2 while forming the first part V11 of the first via V1, and in step S3, the second mask can be used in The second region V22 of the second via hole V2 is formed at the same time as the second portion V12 of the first via hole V1, which not only reduces the mask and related processes required to form the first via hole V1 separately, but also Reduce product defect rate and reduce production costs.
  • the second part V12 of the buffer layer 13 and the barrier layer 12 part of the inorganic insulating material in the buffer layer 13 and the barrier layer 12 can be removed, thereby improving the resistance of the display area A of the display panel. Bending performance.
  • the hole diameter of the first part V11 of the first via hole V1 is larger than the hole diameter of the second part V12, so that a stepped shape is formed at the connection between the first part V11 and the second part V12 of the buffer layer 13
  • the buffer angle can slow down the slope of the first via hole V1, thereby reducing the bending stress of the display area A during the bending process.
  • the aperture of the first part V11 and the aperture of the second part V12 of the first via hole V1 are gradually reduced along the direction from the interlayer insulating layer 144 to the base substrate 11, that is, the first part V11 and the second part V12 are
  • the shape of the cross-sectional structure shown in FIG. 1 is an inverted trapezoid.
  • the angles formed by the side walls of the first part V11 and the side walls of the second part V12 and the first direction are both acute angles, and the first direction is an acute angle with the display The horizontal direction perpendicular to the thickness of the panel.
  • the angles formed by the side walls of the first part V11 and the side walls of the second part V12 with the first direction are both between 40° and 80°, and the angle of the included angle is too large, resulting in the first transition.
  • the slope of the hole V1 is too large, which is not conducive to reducing the bending stress in the display area. If the angle of the included angle is too small, the opening area of the first via hole V1 will be too large, which is not conducive to increasing the opening area of the pixel.
  • FIG. 4 is the display panel of FIG. 1 along the CC direction in the manufacturing method of the display panel provided by the embodiment of the disclosure. Schematic diagram of the cross-sectional structure.
  • the manufacturing method of the display panel includes:
  • Step S1 As shown in FIG. 4, a base substrate 11 is provided, and a barrier layer 12, a buffer layer 13, an active layer 1411, a first gate insulating layer 142, and a first gate line are formed on the base substrate 11. Layer 1412, second gate insulating layer 143, second gate line layer 1413, and interlayer insulating layer 144;
  • Step S2 Using the first mask, etching to form the first part of the first via hole V1 penetrating the interlayer insulating layer 144, the first gate insulating layer 143 and the second gate insulating layer 142 as shown in FIG. 4 V11, the first region V21 of the second via hole V2, and a plurality of third via holes V3 that penetrate the first insulating layer 143 and the second insulating layer 142 and expose a part of the active layer 1411;
  • Step S3 Using a second mask, continue to etch on the basis of the first portion V11 and the first region V21 to form a penetrating through the buffer layer 13 and the barrier layer 12 as shown in FIG. 3C The second portion V12 of the first via V1 and the second area V22 of the second via V2;
  • Step S4 As shown in FIG. 2, a flexible layer 16 is formed on the surface of the interlayer insulating layer 144 away from the base substrate 11, and the flexible material of the flexible layer 16 fills the first via hole V1 and the second via hole V2;
  • Step S5 forming a source-drain electrode layer 1414 and a plurality of data lines L on the flexible layer 16, the source-drain electrode layer 1414 is in contact with the active layer 1411 through the third via V3;
  • Step S6 forming a stacked flat layer 17, a pixel definition layer 18, a display device layer 15 and a plurality of spacers 19 on the side of the flexible layer 16 away from the base substrate 11.
  • the structure of the display device layer 15 is the same as the structure of the display device layer in the display panel provided in the foregoing embodiment, and will not be repeated here.
  • the manufacturing method of the display panel provided by the embodiments of the present disclosure differs in that the manufacturing process of the third via V3 is different from the first portion V11 and the second via V1 of the first via V1.
  • the manufacturing process of the first region V21 of V2 it is necessary to etch the interlayer insulating layer 144, the second gate insulating layer 143 and the first gate insulating layer 142 by using the three via holes, and the active layer can block the first gate insulating layer.
  • the continued etching of the three vias V3, thereby reducing the mask and related processes required to form the first vias V1 and the third vias V3 by separate etching, can be compared with the manufacturing method provided in the above embodiments. Save two masks and related processes.
  • the beneficial effects of the embodiments of the present disclosure combine the manufacturing process of the first via hole V1 with the manufacturing process of the two regions of the second via hole V2, thereby reducing the need to separately fabricate the first via hole V1.
  • Mask and related processes, and reduce the defect rate of products and reduce production costs, through the buffer layer 13 and the second part V12 of the barrier layer 12 can also remove part of the buffer layer 13 and the inorganic insulating material in the barrier layer 12 to This improves the bending resistance of the display area A of the display panel.

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Abstract

本揭示提供一种显示面板及显示面板的制作方法，显示面板包括衬底基板、阻隔层、缓冲层、薄膜晶体管阵列层，显示区内设置多个间隔第一过孔，绑定区内设有多个第二过孔，第一过孔和第二过孔均由绝缘层贯穿至衬底基板靠近阻隔层的一侧，并在其内部填充有柔性材料，以此提高显示面板的抗弯折性能，减少裂纹发生的风险。

Description

显示面板及显示面板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及显示面板的制作方法。
 背景技术
柔性显示装置是一种基于柔性基底材料形成的显示装置。由于柔性显示装置具有可卷曲、宽视角、便于携带等特点，因此，在便携产品、多数显示应用领域，柔性显示装置具有广阔的应用前景以及良好的市场潜力。
 技术问题
柔性有机发光二极管（organic light emitting diode, OLED）显示面板由于其制程复杂、需要掩膜板数量多，导致生产良率偏低，造成其价格高居不下。现有柔性OLED显示面板至少有12到掩膜板制程。其中，在源漏电极与有源层连接的过孔以及显示区内用于释放弯折应力的过孔都需要单独的一道掩膜板制程，使得显示面板的制作工艺变得复杂、成本也大幅提高，并且每一道制程都可能出现不良的产品，导致显示面板的生产良率降低，同时显示面板还存在一定厚度的无机材料的膜层，柔性较差的无机材料使得柔性显示面板在弯折过程中会产生裂纹的风险。
综上所述，现有显示面板存在过孔的制作工艺复杂、成本高并且生产良率较低的问题。故，有必要提供一种显示面板及显示面板的制作方法来改善这一缺陷。
 技术解决方案
本揭示实施例提供一种显示面板及显示面板的制作方法，用于解决现有显示面板存在过孔的制作工艺复杂、成本高并且生产良率较低的问题。
本揭示实施例提供一种显示面板，包括显示区和围绕所述显示区的非显示区，所述非显示区包括绑定区，所述显示面板还包括：
衬底基板；
阻隔层，设置于所述衬底基板上；
缓冲层，设置于所述阻隔层远离所述衬底基板的一侧上；
薄膜晶体管阵列层，设置于所述缓冲层远离所述衬底基板的一侧上，包括多个薄膜晶体管以及至少两层用于阻隔所述薄膜晶体管内各器件的层叠设置的绝缘层；以及
显示器件层，设置于所述薄膜晶体管阵列层远离所述衬底基板的一侧上；
其中，所述显示区内设有多个间隔排列的第一过孔，所述绑定区内设有多个间隔排列的第二过孔，所述第一过孔和所述第二过孔均由所述绝缘层贯穿至所述衬底基板靠近所述阻隔层的一侧，且所述第一过孔和所述第二过孔内均填充有柔性材料。
根据本揭示一实施例，所述第二过孔包括第一区域和第二区域，所述第二区域的底面与所述衬底基板靠近所述阻隔层的一侧接触，所述第一区域和所述第二区域在所述缓冲层远离所述衬底基板的一侧连通。
根据本揭示一实施例，所述第一过孔包括第一部分和第二部分，所述第一部分与所述第二过孔的所述第一区域同层设置，所述第二部分与所述第二过孔的所述第二区域同层设置。
根据本揭示一实施例，所述第一部分的孔径大于所述第二部分的孔径。
根据本揭示一实施例，所述第一部分的孔径和所述第二部分的孔径沿所述绝缘层至所述衬底基板的方向均逐渐减小。
根据本揭示一实施例，所述第一过孔的侧壁和所述第二过孔的侧壁分别与第一方向形成的夹角的取值均介于40°至80°之间。
本揭示实施例还提供一种显示面板，包括显示区和围绕所述显示区的非显示区，所述非显示区包括绑定区，所述显示面板还包括：
衬底基板；
阻隔层，设置于所述衬底基板上；
缓冲层，设置于所述阻隔层远离所述衬底基板的一侧上；
薄膜晶体管阵列层，设置于所述缓冲层远离所述衬底基板的一侧上，包括多个薄膜晶体管以及至少两层用于阻隔所述薄膜晶体管内各器件的层叠设置的绝缘层；以及
显示器件层，设置于所述薄膜晶体管阵列层远离所述衬底基板的一侧上；
其中，所述显示区内设有多个间隔排列的第一过孔，所述绑定区内设有多个间隔排列的第二过孔，所述第一过孔和所述第二过孔均由所述绝缘层贯穿至所述衬底基板靠近所述阻隔层的一侧，所述第二过孔包括第一区域和第二区域，所述第二区域的底面与所述衬底基板靠近所述衬底基板的一侧接触，所述第一区域和所述第二区域在所述缓冲层远离所述衬底基板的一侧连通，所述第一过孔包括与所述第一区域同层设置的第一部分和与所述第二区域同层设置的第二部分，且所述第一过孔和所述第二过孔内均填充有柔性材料。
根据本揭示一实施例，所述第一部分的孔径大于所述第二部分的孔径。
根据本揭示一实施例，所述第一部分的孔径和所述第二部分的孔径沿所述绝缘层至所述衬底基板的方向均逐渐减小。
根据本揭示一实施例，所述第一过孔的侧壁和所述第二过孔的侧壁分别与第一方向形成的夹角的取值均介于40°至80°之间。
本揭示实施例还提供一种显示面板的制作方法，包括：
提供衬底基板，所述衬底基板上形成有阻隔层、缓冲层、有源层、栅极绝缘层、栅极线层以及层间绝缘层；
采用第一掩膜板，刻蚀形成贯穿所述层间绝缘层和所述栅极绝缘层的第一过孔的第一部分以及第二过孔的第一区域；
采用第二掩膜板，在所述第一部分和所述第一区域的基础上继续刻蚀，形成贯穿所述缓冲层和所述阻隔层的所述第一过孔的第二部分和所述第二过孔的第二区域；以及
在所述层间绝缘层表面形成柔性层，所述柔性层的柔性材料填充所述第一过孔和所述第二过孔；
其中，所述衬底基板包括显示区和围绕所述显示区的非显示区，所述非显示区包括绑定区，多个所述第一过孔间隔排列于所述显示区内，多个所述第二过孔间隔排列于所述绑定区内。
根据本揭示一实施例，采用所述第一掩膜板刻蚀形成所述第一部分和所述第一区域的同时，形成多个贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔以暴露出部分所述有源层。
根据本揭示一实施例，所述第一部分的孔径大于所述第二部分的孔径。
根据本揭示一实施例，所述第一部分和所述第二部分的侧壁与第一方向形成的夹角的取值均介于40°至80°之间。
 有益效果
本揭示实施例通过在显示面板的显示区内设置多个间隔排布的第一过孔，并在绑定区内设有多个间隔排列的第二过孔，第一过孔和第二过孔均由所述绝缘层贯穿至所述衬底基板靠近所述阻隔层的一侧，以此可以利用第二过孔的工艺同时制作形成第一过孔，省去单独制作第一过孔的制程以及掩膜板，提高生产良率并降低生产成本，同时利用第一过孔可去除缓冲层和阻隔层中的部分无机绝缘材料，并在其内部填充有柔性材料，以此提高显示面板的抗弯折性能，减少裂纹发生的风险。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示实施例提供的显示面板的平面结构示意图；
图2为本揭示实施例图1提供的显示面板沿C-C方向的截面结构示意图；
图3A至图3C为本揭示实施例提供的显示面板制作方法中图1的显示面板沿C-C方向的截面结构示意图；
图4为本揭示实施例提供的另一种显示面板的制作方法中图1的显示面板沿C-C方向的截面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本揭示实施例提供一种显示面板，下面结合图1进行详细说明。如图1所示，图1为本揭示实施例提供的显示面板的平面结构示意图，所述显示面板包括显示区域A和围绕所述显示区域A的非显示区域B，所述非显示区域B包括绑定区B1，绑定区B1可弯折至显示面板背面，以此减小显示面板的边框宽度，提高屏占比。
如图2所示，图2为图1中的显示面板沿C-C方向的截面结构示意图，显示面板包括衬底基板11、设置于衬底基板11上的阻隔层12、设置于阻隔层12远离衬底基板11的一侧上的缓冲层13、设置于缓冲层13远离衬底基板11的一侧上的薄膜晶体管阵列层14以及设置于薄膜晶体管阵列层14远离衬底基板11的一侧上的显示器件层15。
在本揭示实施例中，阻隔层12所用的材料包括氧化硅、氮化硅、氮氧化硅和非晶硅中的一种或几种，主要用于阻隔水氧，防止外部的水汽或者氧气侵蚀所述显示面板。缓冲层13所用的材料包括氮化硅和氧化硅中的一种或两种，主要用于缓冲和保护的作用。
具体地，薄膜晶体管阵列层14包括多个薄膜晶体管141，其中本揭示实施例中的薄膜晶体管141为双栅极结构的薄膜晶体管，包括有源层1411、第一栅极线层1412、第二栅极线层1413以及源漏电极层1414，薄膜晶体管阵列层14还包括设置于缓冲层13远离衬底基板11一侧上的第一栅极绝缘层142以及层叠设置于所述第一栅极绝缘层142上的第二栅极绝缘层143和层间绝缘层144。源漏电极层1414与层间绝缘层144之间设有柔性层16，源漏电极层1414通过贯穿所述柔性层16、层间绝缘层144、第二栅极绝缘层143以及第一栅极绝缘层142的过孔与有源层1411电性连接。当然，在一些实施例中，薄膜晶体管141也可以为仅含有一层栅极线层的薄膜晶体管，此外，薄膜晶体管141也可以为顶栅或者是底栅结构，均可适用于本揭示实施例，此处不做限制。
如图1所示，柔性层16远离衬底基板11的一侧上设有平坦层17，显示器件层15设置于所述平坦层17上，包括阳极151、发光层152以及阴极（图中未示出），阳极151通过贯穿平坦层17的过孔与源漏电极层1414连接。平坦层17上还设有像素定义层18，像素定义层18覆盖阳极151，同时像素定义层18上设有凹槽，所述凹槽暴露出部分阳极151，发光层152设置于所述凹槽内。像素定义层18远离阵列基板11的一侧设有多个间隔排列的隔垫物19。
在本揭示实施例中，显示区A内设有多个间隔排列的第一过孔V1，绑定区B1内设有多个间隔排列的第二过孔V2，并且第一过孔V1和第二过孔V2均由层间绝缘层144贯穿至衬底基板11靠近阻隔层12的一侧，且两者沿垂直于显示面板厚度方向的高度相同，并均暴露出部分衬底基板11，以此去除缓冲层13和阻隔层12中的部分无机绝缘材料，提高显示面板的抗弯折性能。同时，第一过孔V1和第二过孔V2中均填充有柔性层16中的柔性材料，第一过孔V1用于释放显示区A在弯折过程中所产生的应力，使得显示区在弯折时不易产生裂纹，第二过孔V2则用于释放绑定区B1在弯折过程中所产生的应力，以防止位于其上方的多条数据线L发生断裂。
具体地，第二过孔V2包括第一区域V21和第二区域V22。其中，第一区域V21贯穿层间绝缘层144、第二栅极绝缘层143和第一栅极绝缘层142，第二区域V22贯穿缓冲层13和阻隔层12，第二区域V22的底面与衬底基板11靠近阻隔层12的一侧接触，第一区域V21和第二区域V22在缓冲层13远离衬底基板11的一侧连通。在制作形成所述第二过孔V2时，第一区域V21和第二区域V22由于所在膜层不同以及孔径大小也不同，需要分别使用两张掩膜板进行两次刻蚀形成。
第一过孔V1同样也包括第一部分V11和第二部分V12，第一部分V11与第二过孔V2的第一区域V21同层设置，即第一部分V11贯穿层间绝缘层144、第二栅极绝缘层143和第一栅极绝缘层142，且第一部分V11和第一区域V21沿显示面板厚度方向的高度相同；第二部分V12与第二过孔V2的的第二区域V22同层设置，即第二部分V12贯穿缓冲层13和阻隔层12，从而不仅可以利用第二部分V12去除阻隔层12和缓冲层13中的无机绝缘材料以此增大显示面板的抗弯折性能，同时还可以利用形成第二过孔V2的制作工艺，在形成第二过孔V2的同时形成第一过孔V1，以此省去单独制作第一过孔V1的制程以及掩膜板，从而提高生产良率并降低生产成本。
进一步的，第一过孔V1的第一部分V11的孔径应大于第二部分V12的孔径，以此在缓冲层13的第一部分V11和第二部分V12的连通处形成台阶状的缓冲角，可减缓第一过孔V1的坡度，从而减小显示区A在弯折过程中的弯折应力。
更进一步的，第一过孔V1的第一部分V11的孔径和第二部分V12的孔径沿层间绝缘层144至衬底基板11的方向均逐渐减小，即第一部分V11和第二部分V12在如图1所示的截面结构图中的形状为倒置梯形，第一部分V11的侧壁和第二部分V12的侧壁分别与第一方向形成的夹角均为锐角，其中第一方向为与显示面板厚度方向垂直的水平方向。
优选的，第一部分V11的侧壁和第二部分V12的侧壁分别与第一方向形成的夹角的取值均介于40°至80°之间，夹角的角度过大会导致第一过孔V1的坡度过大，不利于减小显示区内的弯折应力，夹角的角度过小则会导致第一过孔V1的开孔面积过大，不利于提高像素的开口面积。此外，第二过孔V2的第一区域V21和第二区域V21与上述第一过孔V1的特性相同，此处不再赘述。
本揭示实施例的有益效果：本揭示实施例提供的显示面板在显示区内设置多个间隔排布的第一过孔，并在绑定区内设有多个间隔排列的第二过孔，第一过孔和第二过孔均由所述绝缘层贯穿至所述衬底基板靠近所述阻隔层的一侧，以此可以利用第二过孔的工艺同时制作形成第一过孔，省去单独制作第一过孔的制程以及掩膜板，提高生产良率并降低生产成本，同时利用第一过孔可去除缓冲层13和阻隔层12中的部分无机绝缘材料，并在其内部填充有柔性材料，以此提高显示面板的抗弯折性能，减少裂纹发生的风险。
本揭示实施例还提供一种显示面板的制作方法，下面结合图1至图3C进行详细说明，图3A至图3C为本揭示实施例提供的显示面板制作方法中图1的显示面板沿C-C方向的截面结构示意图，所述制作方法包括：
步骤S1：提供衬底基板11，在所述衬底基板11上形成阻隔层12、缓冲层13、有源层1411、第一栅极绝缘层142、第一栅极线层1412、第二栅极绝缘层143、第二栅极线层1413以及层间绝缘层144；
步骤S2：采用第一掩膜板，刻蚀形成如图3A所示的贯穿层间绝缘层144、第一栅极绝缘层143和第二栅极绝缘层142的第一过孔V1的第一部分V11以及第二过孔V2的第一区域V21；
步骤S3：采用第二掩膜板，在所述第一部分V11和所述第一区域V21的基础上继续刻蚀，形成如图3B所示的贯穿所述缓冲层13和所述阻隔层12的第一过孔V1的第二部分V12和第二过孔V2的第二区域V22；
步骤S4：采用第三掩膜板，刻蚀形成如图3C所示的多个贯穿层间绝缘层144、第一栅极绝缘层143和第二栅极绝缘层142的第三过孔V3,所述第三过孔V3底面与有源层1411接触，并暴露出部分有源层1411；
步骤S5：如图2所示，在层间绝缘层144远离衬底基板11的一侧表面形成柔性层16，所述柔性层16的柔性材料填充第一过孔V1和第二过孔V2；
步骤S6：在柔性层16上形成源漏电极层1414以及多条数据线L，源漏电极层1414通过第三过孔V3与有源层1411接触；以及
步骤S7：在所述柔性层16远离衬底基板11一侧形成层叠设置的平坦层17、像素定义层18、显示器件层15以及多个隔垫物19。其中，显示器件层15的结构与上述实施例所提供的显示面板中的显示器件层的结构相同，此处不再赘述。
步骤S2中，采用第一掩膜板可以在形成第二过孔V2的第一区域V21的同时形成第一过孔V1的第一部分V11，并且在步骤S3中，采用第二掩膜板可以在形成第二过孔V2的第二区域V22的同时形成第一过孔V1的第二部分V12，以此不仅可以减少单独制作形成第一过孔V1所需要的掩膜板以及相关工艺制程，并降低产品的不良率和减少生产成本，贯穿缓冲层13和阻隔层12的第二部分V12还可以去除部分缓冲层13和阻隔层12中的无机绝缘材料，以此提高显示面板显示区A的抗弯折性能。
进一步的，如图3C所示，第一过孔V1的第一部分V11的孔径大于第二部分V12的孔径，以此在缓冲层13的第一部分V11和第二部分V12的连通处形成台阶状的缓冲角，可减缓第一过孔V1的坡度，从而减小显示区A在弯折过程中的弯折应力。
更进一步的，第一过孔V1的第一部分V11的孔径和第二部分V12的孔径沿层间绝缘层144至衬底基板11的方向均逐渐减小，即第一部分V11和第二部分V12在如图1所示的截面结构图中的形状为倒置梯形，第一部分V11的侧壁和第二部分V12的侧壁分别与第一方向形成的夹角均为锐角，其中第一方向为与显示面板厚度方向垂直的水平方向。
优选的，第一部分V11的侧壁和第二部分V12的侧壁分别与第一方向形成的夹角的取值均介于40°至80°之间，夹角的角度过大会导致第一过孔V1的坡度过大，不利于减小显示区内的弯折应力，夹角的角度过小则会导致第一过孔V1的开孔面积过大，不利于提高像素的开口面积。
本揭示实施例还提供另一种显示面板的制作方法，下面结合图3C至图4进行详细说明，图4为本揭示实施例提供的显示面板的制作方法中图1的显示面板沿C-C方向的截面结构示意图。所述显示面板的制作方法包括：
步骤S1：如图4所示，提供衬底基板11，在所述衬底基板11上形成阻隔层12、缓冲层13、有源层1411、第一栅极绝缘层142、第一栅极线层1412、第二栅极绝缘层143、第二栅极线层1413以及层间绝缘层144；
步骤S2：采用第一掩膜板，刻蚀形成如图4所示的贯穿层间绝缘层144、第一栅极绝缘层143和第二栅极绝缘层142的第一过孔V1的第一部分V11、第二过孔V2的第一区域V21以及多个贯穿第一绝缘层143、第二绝缘层142并暴露出部分有源层1411的第三过孔V3；
步骤S3：采用第二掩膜板，在所述第一部分V11和所述第一区域V21的基础上继续刻蚀，形成如图3C所示的贯穿所述缓冲层13和所述阻隔层12的第一过孔V1的第二部分V12和第二过孔V2的第二区域V22；
步骤S4：如图2所示，在层间绝缘层144远离衬底基板11的一侧表面形成柔性层16，所述柔性层16的柔性材料填充第一过孔V1和第二过孔V2；
步骤S5：在柔性层16上形成源漏电极层1414以及多条数据线L，源漏电极层1414通过第三过孔V3与有源层1411接触；以及
步骤S6：在所述柔性层16远离衬底基板11一侧形成层叠设置的平坦层17、像素定义层18、显示器件层15以及多个隔垫物19。其中，显示器件层15的结构与上述实施例所提供的显示面板中的显示器件层的结构相同，此处不再赘述。
本揭示实施例所提供的显示面板的制作方法相较于上述实施例所提供的制作方法，区别在于将第三过孔V3的制作过程与第一过孔V1的第一部分V11以及第二过孔V2的第一区域V21的制作过程结合，利用三个过孔均需要刻蚀层间绝缘层144、第二栅极绝缘层143和第一栅极绝缘层142，而有源层则可以阻挡第三过孔V3的继续刻蚀，以此减少单独刻蚀形成第一过孔V1以及第三过孔V3所需要的掩膜板以及相关工艺制程，相较于上述实施例提供的制作方法，可以节省两张掩膜板以及相关工艺制程。
本揭示实施例的有益效果：本揭示实施例通过将第一过孔V1的制作工艺与第二过孔V2的两个区域的制作工艺结合，以此减少单独制作第一过孔V1所需要的掩膜板以及相关工艺制程，并降低产品的不良率和减少生产成本，贯穿缓冲层13和阻隔层12的第二部分V12还可以去除部分缓冲层13和阻隔层12中的无机绝缘材料，以此提高显示面板显示区A的抗弯折性能。
综上所述，虽然本揭示以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为基准。

Claims (14)

  1. 一种显示面板，包括显示区和围绕所述显示区的非显示区，所述非显示区包括绑定区，所述显示面板还包括：
    衬底基板；
    阻隔层，设置于所述衬底基板上；
    缓冲层，设置于所述阻隔层远离所述衬底基板的一侧上；
    薄膜晶体管阵列层，设置于所述缓冲层远离所述衬底基板的一侧上，包括多个薄膜晶体管以及至少两层用于阻隔所述薄膜晶体管内各器件的层叠设置的绝缘层；以及
    显示器件层，设置于所述薄膜晶体管阵列层远离所述衬底基板的一侧上；
    其中，所述显示区内设有多个间隔排列的第一过孔，所述绑定区内设有多个间隔排列的第二过孔，所述第一过孔和所述第二过孔均由所述绝缘层贯穿至所述衬底基板靠近所述阻隔层的一侧，且所述第一过孔和所述第二过孔内均填充有柔性材料。
  2. 如权利要求1所述的显示面板，其中，所述第二过孔包括第一区域和第二区域，所述第二区域的底面与所述衬底基板靠近所述阻隔层的一侧接触，所述第一区域和所述第二区域在所述缓冲层远离所述衬底基板的一侧连通。
  3. 如权利要求2所述的显示面板，其中，所述第一过孔包括第一部分和第二部分，所述第一部分与所述第二过孔的所述第一区域同层设置，所述第二部分与所述第二过孔的所述第二区域同层设置。
  4. 如权利要求3所述的显示面板，其中，所述第一部分的孔径大于所述第二部分的孔径。
  5. 如权利要求4所述的显示面板，其中，所述第一部分的孔径和所述第二部分的孔径沿所述绝缘层至所述衬底基板的方向均逐渐减小。
  6. 如权利要求1所述的显示面板，其中，所述第一过孔的侧壁和所述第二过孔的侧壁分别与第一方向形成的夹角的取值均介于40°至80°之间。
  7. 一种显示面板，包括显示区和围绕所述显示区的非显示区，所述非显示区包括绑定区，所述显示面板还包括：
    衬底基板；
    阻隔层，设置于所述衬底基板上；
    缓冲层，设置于所述阻隔层远离所述衬底基板的一侧上；
    薄膜晶体管阵列层，设置于所述缓冲层远离所述衬底基板的一侧上，包括多个薄膜晶体管以及至少两层用于阻隔所述薄膜晶体管内各器件的层叠设置的绝缘层；以及
    显示器件层，设置于所述薄膜晶体管阵列层远离所述衬底基板的一侧上；
    其中，所述显示区内设有多个间隔排列的第一过孔，所述绑定区内设有多个间隔排列的第二过孔，所述第一过孔和所述第二过孔均由所述绝缘层贯穿至所述衬底基板靠近所述阻隔层的一侧，所述第二过孔包括第一区域和第二区域，所述第二区域的底面与所述衬底基板靠近所述衬底基板的一侧接触，所述第一区域和所述第二区域在所述缓冲层远离所述衬底基板的一侧连通，所述第一过孔包括与所述第一区域同层设置的第一部分和与所述第二区域同层设置的第二部分，且所述第一过孔和所述第二过孔内均填充有柔性材料。
  8. 如权利要求7所述的显示面板，其中，所述第一部分的孔径大于所述第二部分的孔径。
  9. 如权利要求8所述的显示面板，其中，所述第一部分的孔径和所述第二部分的孔径沿所述绝缘层至所述衬底基板的方向均逐渐减小。
  10. 如权利要求7所述的显示面板，其中，所述第一过孔的侧壁和所述第二过孔的侧壁分别与第一方向形成的夹角的取值均介于40°至80°之间。
  11. 一种显示面板的制作方法，包括：
    提供衬底基板，所述衬底基板上形成有阻隔层、缓冲层、有源层、栅极绝缘层、栅极线层以及层间绝缘层；
    采用第一掩膜板，刻蚀形成贯穿所述层间绝缘层和所述栅极绝缘层的第一过孔的第一部分以及第二过孔的第一区域；
    采用第二掩膜板，在所述第一部分和所述第一区域的基础上继续刻蚀，形成贯穿所述缓冲层和所述阻隔层的所述第一过孔的第二部分和所述第二过孔的第二区域；以及
    在所述层间绝缘层表面形成柔性层，所述柔性层的柔性材料填充所述第一过孔和所述第二过孔；
    其中，所述衬底基板包括显示区和围绕所述显示区的非显示区，所述非显示区包括绑定区，多个所述第一过孔间隔排列于所述显示区内，多个所述第二过孔间隔排列于所述绑定区内。
  12. 如权利要求11所述的显示面板的制作方法，其中，采用所述第一掩膜板刻蚀形成所述第一部分和所述第一区域的同时，形成多个贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔以暴露出部分所述有源层。
  13. 如权利要求11所述的显示面板的制作方法，其中，所述第一部分的孔径大于所述第二部分的孔径。
  14. 如权利要求13所述的显示面板的制作方法，其中，所述第一部分和所述第二部分的侧壁与第一方向形成的夹角的取值均介于40°至80°之间。
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