WO2020172966A1 - 一种oled阵列基板及oled显示装置 - Google Patents

一种oled阵列基板及oled显示装置 Download PDF

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Publication number
WO2020172966A1
WO2020172966A1 PCT/CN2019/082859 CN2019082859W WO2020172966A1 WO 2020172966 A1 WO2020172966 A1 WO 2020172966A1 CN 2019082859 W CN2019082859 W CN 2019082859W WO 2020172966 A1 WO2020172966 A1 WO 2020172966A1
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Prior art keywords
sub
signal line
pixels
metal layer
array substrate
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PCT/CN2019/082859
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English (en)
French (fr)
Inventor
王威
黄情
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武汉华星光电半导体显示技术有限公司
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Priority to US16/496,439 priority Critical patent/US11195897B2/en
Publication of WO2020172966A1 publication Critical patent/WO2020172966A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to the field of display technology, in particular to an OLED array substrate and an OLED display device.
  • OLED Organic Light Emitting Diode
  • AMOLED(Active-Matrix Organic Light Emitting Diode (active matrix organic light-emitting diode) display device is a display device that uses current to drive OLED devices to emit light to form a picture. In order to obtain better image uniformity, a more accurate current control capability is required. Therefore, two methods of external compensation and internal compensation are generally used to obtain the above effects.
  • FIG. 1A is a schematic diagram of a layered structure of a conventional OLED array substrate
  • FIG. 1B is a schematic diagram of a pixel structure of a 7T1C circuit corresponding to FIG. 1A.
  • the array substrate includes a substrate substrate 111, a barrier layer (M/B) 112, a buffer layer (Buffer) 113, an active layer (Act) 114, a first gate insulating layer (GI1) 115, First gate layer (GE1) 116, second gate insulating layer (GI2) 117, second gate layer (GE2) 118, first dielectric insulating layer (ILD1) 119, second dielectric insulating layer (ILD2) 120, source and drain layer (SD) 121, flat layer (PLN) 122, anode (ANO) 123, OLED124, pixel defined layer (Pixel Defined Layer (PDL for short) 125, photoresist layer (Photo Spacer, referred to as PS) 126, cathode (Cathode) 127, TFE encapsulation layer 128, polarizing layer (Polorization, referred to as POL) 129, and an external touch screen (TP) 130.
  • GI1 gate insulating layer
  • GE1 First
  • the first gate layer 116 includes a scan line (Scan line) and the gate of the driver TFT M1 of the 7T1C circuit.
  • the driver TFT M1 The gate of the 7T1C circuit also serves as the bottom plate of the storage capacitor Cst; the second gate layer 118 includes a reset signal line (VI line) and the upper plate of the storage capacitor Cst; the source and drain layer 121 Including power signal line (VDD line) and data signal line (Data line).
  • the reset signal line formed on the second gate layer 118 and the power signal line formed on the source-drain layer 121 extend in different directions (ie, cross).
  • the size of sub-pixels is restricted to be further reduced, and the increase in pixel density (Pixels Per Inch, PPI) is restricted.
  • the gate of the driving thin film transistor of the first gate layer also serves as the bottom plate of the storage capacitor, which is not conducive to the design of larger PPI circuits.
  • the reset signal line crosses the power signal line, the number of lines and vias (CNT) are large, and the density is large, and it is difficult to further improve the PPI.
  • the purpose of the present invention is to provide an OLED array substrate and an OLED display device in view of the problems existing in the prior art, which can facilitate the design of larger pixel density circuits, improve the uniformity of the screen display, and reduce the coupling between traces.
  • Storage capacitor and can form a larger storage capacitor.
  • the present invention provides an OLED array substrate including a plurality of sub-pixels, each sub-pixel includes a driving circuit to control the light-emitting brightness and time of the sub-pixel; the OLED array substrate also includes a reset signal line and a power signal The reset signal line and the power signal line extend in the same direction; the drive circuits of the multiple sub-pixels are arranged in multiple columns, and the drive circuits of the two adjacent columns of sub-pixels adopt a mirror-symmetrical structure.
  • the driving circuits of two sub-pixels in the same row in two adjacent columns of sub-pixels share the reset signal line and the first via, and two sub-pixels in the same row in the other two adjacent columns of sub-pixels
  • the driving circuits share one power signal line and the second via.
  • the present invention also provides an OLED array substrate including a plurality of sub-pixels, each sub-pixel includes a driving circuit to control the light-emitting brightness and time of the sub-pixel, and the driving circuits of the plurality of sub-pixels are arranged into Multiple columns, among which the driving circuits of two adjacent columns of sub-pixels adopt a mirror-symmetric structure.
  • the present invention also provides an OLED display device, the OLED display device includes an OLED array substrate, the OLED array substrate includes a plurality of sub-pixels, each sub-pixel includes a driving circuit to control the light-emitting brightness of the sub-pixels And time; the multiple sub-pixel drive circuits are arranged in multiple columns, wherein the drive circuits of two adjacent columns of sub-pixels adopt a mirror-symmetric structure.
  • the driving circuit of the sub-pixels of the OLED array substrate of the present invention adopts a mirror-symmetrical structure.
  • the reset signal line and the power signal line extend in the same direction, and the reset signal line and the first via are shared, and the power signal line and the second via are shared. About half of the power signal lines, reset signal lines, and vias can be saved, thereby providing space for the improvement of PPI and facilitating the realization of high PPI panel design.
  • the metal wiring adopts the GE1/SD1/SD2 three-layer structure design.
  • GE1 is used as the gate electrode and scan driving line of the driving thin film transistor
  • SD1 is used as the source and drain electrode of the driving thin film transistor, the data signal line, the reset signal line and the lower electrode of the storage capacitor
  • the SD2 is used as the power signal line and the upper plate of the storage capacitor, which can facilitate the design of larger PPI circuits and improve the uniformity of the screen display.
  • FIG. 1A is a schematic diagram of the layered structure of a conventional OLED array substrate
  • FIG. 1B is a schematic diagram of the pixel structure of the 7T1C circuit corresponding to FIG. 1A;
  • FIG. 2 is a schematic diagram of a pixel structure of an embodiment of an OLED array substrate of the present invention.
  • FIG. 3 is a schematic diagram of the layered structure of an embodiment of the OLED array substrate of the present invention.
  • the "above” or “below” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the first feature has a lower level than the second feature.
  • the OLED array substrate of the present invention includes a plurality of sub-pixels, and each sub-pixel includes a driving circuit to control the light-emitting brightness and time of the sub-pixel.
  • the driving circuits of the plurality of sub-pixels are arranged in multiple columns, wherein two adjacent columns of sub-pixels
  • the driving circuit adopts a mirror symmetrical structure.
  • the improved layout structure of the present invention can provide space for the improvement of PPI, which is beneficial to realize high PPI panel design.
  • the improved pixel structure layout can save about half of the reset signal Wire routing and vias provide space for PPI improvement and facilitate the realization of high PPI panel design.
  • the drive circuits of the two sub-pixels in the same row that is, the two adjacent sub-pixels
  • the drive circuits of the two adjacent sub-pixels in the first column of sub-pixels and the second column of sub-pixels share the reset signal line and reset vias.
  • the driving circuits of the two adjacent sub-pixels on the left and right share the reset signal line and the reset via, but the second column of sub-pixels and the third column of sub-pixels do not share the reset signal line and the reset via.
  • the improved pixel structure layout can save about half of the power signal Wire routing and vias provide space for PPI improvement and facilitate the realization of high PPI panel design.
  • the driving circuits of the two sub-pixels in the same row that is, the two adjacent sub-pixels on the left and right
  • the third column of sub-pixels share the power supply signal line and the power supply via.
  • the driving circuits of the two adjacent sub-pixels share power signal lines and power vias, but the first column of sub-pixels and the second column of sub-pixels, and the third column of sub-pixels and the fourth column of sub-pixels do not share power signal lines and power vias.
  • the OLED array substrate further includes a reset signal line and a power signal line, and the reset signal line and the power signal line extend in the same direction (that is, parallel). More preferably, in three adjacent columns of sub-pixels, the drive circuits of two sub-pixels in the same row in two adjacent columns of sub-pixels share the reset signal line and the first via hole, and in the other two adjacent columns of sub-pixels The driving circuits of two sub-pixels in the same row share the same power signal line and the second via.
  • the improved pixel structure layout can save about half of the reset signal line, power signal line traces and corresponding vias, thereby providing PPI The improvement provides space for the realization of high PPI panel design.
  • Each of the sub-pixels of the OLED array substrate includes a plurality of thin film transistors (for example, including driver TFTs and switching thin film transistors). TFT)) and at least one storage capacitor (Cst); the OLED array substrate further includes a first metal layer, a second metal layer, and a third metal layer.
  • TFT driver TFTs and switching thin film transistors
  • Cst storage capacitor
  • the first metal layer includes a scan line (Scan line) and a gate electrode (Gate) of the thin film transistor;
  • the second metal layer includes a data signal line (Data line), a reset signal line (VI line, used to reset the storage capacitor and anode), the source and drain electrodes (S/D) of the thin film transistor, and the bottom plate of the storage capacitor;
  • the third metal layer includes a power supply Signal line (Power(Vdd) Line) and the upper plate of the storage capacitor, and the power signal line and the upper plate of the storage capacitor are electrically connected.
  • the first metal layer may be a gate metal layer (GE1)
  • the second metal layer may be a first source-drain metal layer (SD1)
  • the third metal layer may be a second source-drain metal layer (SD2) .
  • the second metal layer and the third metal layer are used to fabricate the upper and lower plates of the storage capacitor, and only the gate electrode of the thin film transistor and the scan driving line are fabricated on the first metal layer, which facilitates the design of
  • the reset signal line on the second metal layer and the power signal line on the third metal layer extend in the same direction, so as to reduce the wiring density and the number of vias and increase the PPI.
  • the power signal lines on the third metal layer can also be electrically connected to each other in a horizontal direction, thereby forming a mesh structure.
  • This structure design can reduce the size without adding a mask. The voltage drop of the power signal line.
  • the OLED array substrate of the present invention adopts a mirror symmetry structure.
  • the reset signal line and the power signal line extend in the same direction.
  • Power signal lines, reset signal lines and vias provide space for the improvement of PPI and facilitate the realization of high PPI panel design.
  • the metal wiring adopts the GE1/SD1/SD2 three-layer structure design.
  • GE1 is used as the gate electrode and scan driving line of the driving thin film transistor
  • SD1 is used as the source and drain electrode of the driving thin film transistor, the data signal line, the reset signal line and the lower electrode of the storage capacitor
  • the SD2 is used as the power signal line and the upper plate of the storage capacitor, which can facilitate the design of larger PPI circuits and improve the uniformity of the screen display.
  • CNT1 is the contact hole between the active layer and the second metal layer (Poly-SD1), namely the first via hole
  • CNT2 is the active layer and the second metal layer (Poly-SD1).
  • the contact hole of the second metal layer and the third metal layer (Poly-SD1-SD2) is the second via hole
  • CNT3 is the contact hole of the third metal layer and the anode metal (SD2-PE), that is, the third via hole.
  • the OLED array substrate includes a scan drive line (marked as Scan in the figure), a light-emitting signal drive line (marked as EM in the figure), and a data signal line (marked as Data in the figure).
  • Each sub-pixel includes a driving circuit to control the light-emitting brightness and time of the sub-pixel, and the driving circuits of the plurality of sub-pixels are arranged in multiple columns.
  • the driving circuit of the sub-pixel is a 7T1C circuit, which includes 7 thin film transistors (M1 to M7) and a storage capacitor (Cst), wherein the thin film transistor (M1) is a driver TFT.
  • the driving circuits of the two adjacent columns of sub-pixels adopt a mirror symmetrical structure.
  • the driving circuits of sub-pixel n and sub-pixel n+1 are mirror-symmetrical
  • the driving circuits of sub-pixel n+1 and sub-pixel n+2 are mirror-symmetrical.
  • the drive circuits of two sub-pixels in the same row in sub-pixel n and sub-pixel n+1 share the reset signal line VI (n, n+1) and the first via CNT1.
  • VDD power signal line
  • the driving circuits of the two sub-pixels in the same row in sub-pixel n+1 and sub-pixel n+2 share the power supply signal line VDD(n+1, n+2) and the second via CNT2.
  • the driving circuits of two sub-pixels in the same row in two adjacent columns of sub-pixels share a reset signal line and the first via, and the two adjacent columns of sub-pixels in the same row
  • the driving circuits of the two sub-pixels share a power signal line and the second via.
  • the driving circuit of two sub-pixels in the same row in two adjacent columns of sub-pixel n and sub-pixel n+1 The reset signal line VI(n, n+1) and the first via CNT1 are shared, and the driving circuits of the two sub-pixels in the same row in the other two adjacent columns of sub-pixel n+1 and sub-pixel n+2 share the power supply signal line VDD( n+1, n+2) and the second via CNT2.
  • the OLED array substrate further includes a reset signal line and a power supply signal line.
  • the reset signal line (VI) and the power supply signal line (VDD) extend in the same direction (that is, parallel), so that three adjacent columns of the sub-pixels
  • the sub-pixels in the first two columns share a reset signal line (VI) and the first via CNT1
  • the sub-pixels in the last two columns share a power signal line (VDD) and the second via CNT2.
  • the common reset signal line VI (n, n+1) and the first via CNT1 of the sub-pixel n and the sub-pixel n+1, the sub-pixel n+1 and the sub-pixel n+2 share the power supply signal line VDD(n+ 1, n+2) and the second via CNT2.
  • the improved layout structure of the present invention can save about half of the power signal lines, reset signal lines and vias, thereby providing space for improvement of PPI and facilitating the realization of high PPI panel design.
  • the array substrate of the present invention includes a display area (Active Area) 301, a fan-out area (Fanout) and a bending area (Pad Bending) (peripheral circuit area, not shown in the figure).
  • the display area 301 includes the driving of the sub-pixels of the array substrate.
  • the array substrate includes: a substrate substrate 311, a barrier layer (M/B) 312, a buffer layer (Buffer) 313, an active layer (active layer) 314, First gate insulating layer (GI1) 315, first gate metal layer (GE1) 316, first passivation layer (PV1) 317, organic dielectric insulating layer (OILD) 318, first source and drain metal layer (SD1) 319 , The second passivation layer (PV2) 320, the first flat layer (PLN1) 321, the second source and drain metal layer (SD2) 322, the second flat layer (PLN2) 323, the anode (ANO) 324, the pixel definition layer ( PDL) 325 and photoresist layer (PS) 326.
  • the substrate substrate 311 may be a glass substrate or an organic substrate made of a colorless and transparent polyimide (PI) material, and may be a single or double substrate.
  • PI colorless and transparent polyimide
  • the first gate metal layer 316 includes a gate electrode (Gate) 3161 and a scan line (Scan line) 3162 of the thin film transistor.
  • the first passivation layer 317 is an inorganic insulating layer covering the first gate metal layer 316; the organic dielectric insulating layer 318 is an organic insulating layer and is disposed on the first passivation layer 317. That is, between the first gate metal layer 316 and the first source drain metal layer 319 includes an inorganic insulating layer and an organic insulating layer, which can reduce the coupling effect between the two layers of wiring.
  • the first source-drain metal layer 319 includes source-drain electrodes (S/D) 3191 of the thin film transistor, a data signal line (Data line) 3192, a reset signal line (VI line) 3193 and the bottom plate 3194 of the storage capacitor.
  • the second passivation layer 320 is an inorganic insulating layer covering the first source and drain metal layer 319; the first flat layer 321 is an organic insulating layer and is disposed on the second passivation layer 320. That is, there is an inorganic insulating layer and an organic insulating layer above the data signal line 3192 on the first source drain metal layer 319, which can reduce the coupling capacitance between the data signal line and the power signal line.
  • the storage capacitor area can be thinned by an exposure process to reduce the thickness of the first flat layer 321, thereby reducing the thickness of the dielectric insulating layer of the storage capacitor, which can form a larger storage capacitor while ensuring organic insulation in other areas.
  • the layer thickness is not affected.
  • the second source-drain metal layer 322 includes a power signal line (Power(Vdd) Line) 3221 and the upper plate 3222 of the storage capacitor, and the power signal line 3221 and the upper plate 3222 of the storage capacitor are electrically connected (the connection relationship is not shown in the figure).
  • the power signal line 3221 and the reset signal line 3193 extend in the same direction to reduce the wiring density and the number of vias, which can facilitate the design of larger PPI circuits and improve the uniformity of the picture display.
  • the second flat layer 323 (organic insulating layer) covers the second source and drain metal layer 322, and then an anode metal (PE) is deposited and patterned to form the anode 324.
  • PE anode metal
  • the power signal lines 3221 on the second source-drain metal layer 322 may also be electrically connected to each other in a horizontal direction, thereby forming a mesh structure.
  • This structure design does not increase the photomask. In this case, the voltage drop of the power signal line can be reduced.
  • the first source-drain metal layer 319 and the second source-drain metal layer 322 are used to form the upper and lower plates of the storage capacitor, respectively, and only the gate of the thin film transistor is formed on the first gate metal layer 316 Electrodes and scan driving lines can facilitate the design of larger PPI circuits.
  • an inorganic insulating layer and an organic insulating layer are included between the two source and drain metal layers, which can reduce the coupling effect between the two layers of wiring.
  • the exposure process can be used to reduce the thickness of the dielectric insulating layer in the storage capacitor area to achieve the purpose of increasing the storage capacitor.
  • a groove 3211 is provided on the first flat layer 321 corresponding to the lower plate 3194 of the storage capacitor, and the upper plate 3222 of the storage capacitor is formed in the groove.
  • Slot 3211 That is, the dielectric insulating layer of the storage capacitor is composed of the first flat layer 321 and the second passivation layer 320 remaining under the trench 3211.
  • the depth of the trench 3211 can be adjusted by a partial exposure process of the first flat layer 321 through a half-tone mask process. Therefore, the size of the storage capacitor can be adjusted by the overlap area of the upper and lower plates and the depth of the trench 3211.
  • the present invention also provides an OLED display device, which includes the above-mentioned OLED array substrate of the present invention.
  • the OLED array substrate adopts a mirror-symmetrical structure.
  • the reset signal line and the power signal line extend in the same direction. By sharing the reset signal line and the first via, the power signal line and the second via can be omitted. About half of the power signal lines, reset signal lines and vias provide space for the improvement of PPI and facilitate the realization of high PPI panel design.
  • the metal wiring of the OLED array substrate adopts the GE1/SD1/SD2 three-layer structure design.
  • GE1 is used as the gate electrode and scan driving line of the driving thin film transistor
  • SD1 is used as the source and drain electrode of the driving thin film transistor, data signal line, reset signal line and storage
  • the lower plate of the capacitor, SD2 is used as the power signal line and the upper plate of the storage capacitor, which can facilitate the design of larger PPI circuits and improve the uniformity of the screen display.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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Abstract

本发明揭露一种OLED阵列基板及OLED显示装置，OLED阵列基板的子像素的驱动电路采用镜像对称结构，复位信号线和电源信号线沿相同方向延伸，通过共用复位信号线及第一过孔，共用电源信号线及第二过孔，可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。

Description

一种OLED阵列基板及OLED显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED阵列基板及OLED显示装置。
 背景技术
近年来OLED(Organic Light Emitting Diode，有机发光二极管)显示技术的快速发展，推动曲面和柔性显示产品迅速进入市场，相关领域技术更新也是日新月异。OLED是指利用有机半导体材料和发光材料在电场驱动下，通过载流子注入和复合导致发光的二极管。OLED显示装置由于重量轻、自发光、广视角、驱动电压低、发光效率高、功耗低、响应速度快等优点，应用范围越来越广泛。
AMOLED(Active-Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)显示装置是采用电流驱动OLED器件发光形成画面的显示器件。为了获得较优的画面均匀度，需获得较精准的电流控制能力。因此，一般采用外部补偿和内部补偿两种方法来获得上述效果。内部补偿，即针对每个子像素均采用7T1C(7 transistor 1 capacitance，即七个薄膜晶体管加一个存储电容的结构)或6T1C(6 transistor 1 capacitance，即六个薄膜晶体管加一个存储电容的结构)或 6T2C(6 transistor 2 capacitance，即六个薄膜晶体管加两个存储电容的结构)等电路结构对驱动开关进行输出电流调控。
 技术问题
参考图1A-1B，其中图1A为现有的OLED阵列基板的层状结构示意图，图1B为图1A对应的7T1C电路的像素结构示意图。
如图1A所示，所述阵列基板包括基板衬底111，阻挡层(M/B)112，缓冲层(Buffer)113，有源层(Act)114，第一栅绝缘层(GI1)115，第一栅极层(GE1)116，第二栅绝缘层(GI2)117，第二栅极层(GE2)118，第一介电绝缘层(ILD1)119，第二介电绝缘层(ILD2)120，源漏极层(SD)121，平坦层(PLN)122，阳极(ANO)123，OLED124，像素定义层(Pixel Defined Layer，简称PDL)125、光阻层 (Photo Spacer，简称PS)126，阴极(Cathode)127、TFE封装层128，偏光层(Polorization，简称POL)129以及外挂触控屏(TP)130。
结合图1A-1B可以看出，所述第一栅极层116包括扫描驱动线(Scan line)以及7T1C电路的驱动薄膜晶体管(Driver TFT)M1的栅极(Gate)，所述驱动薄膜晶体管M1的栅极同时作为7T1C电路的存储电容Cst的下极板；所述第二栅极层118包括复位信号线(VI line)以及所述存储电容Cst的上极板；所述源漏极层121包括电源信号线(VDD line)以及数据信号线(Data line)。其中，所述第二栅极层118上形成的所述复位信号线与所述源漏极层121上形成的所述电源信号线沿不同方向延伸(即交叉)。
现有的OLED阵列基板，由于7T1C、6T1C、6T2C元器件的布局限制了子像素的尺寸进一步缩小，限制了像素密度(Pixels Per Inch ，简称PPI)的提升。第一栅极层的驱动薄膜晶体管的栅极同时还要作为存储电容的下极板，不利于更大PPI电路设计。像素结构中，复位信号线与电源信号线交叉，走线(line)和过孔(CNT)数量多、密度大，PPI进一步提升的难度大。
 技术解决方案
本发明的目的在于，针对现有技术存在的问题，提供一种OLED阵列基板及OLED显示装置，可以便于更大像素密度电路设计，提高画面显示均匀度，还可以减小走线之间的耦合存储电容，并可以形成较大存储电容。
为实现上述目的，本发明提供了一种OLED阵列基板，包括多个子像素，每个子像素包含一个驱动电路来控制子像素的发光亮度和时间；所述OLED阵列基板还包括复位信号线以及电源信号线，所述复位信号线和所述电源信号线沿相同方向延伸；所述的多个子像素的驱动电路排布成多列，其中相邻的两列子像素的驱动电路采用镜像对称结构，在相邻的三列子像素中，相邻的两列子像素中同一行的两个子像素的驱动电路共用一条所述复位信号线及第一过孔，相邻的另两列子像素中同一行的两个子像素的驱动电路共用一条所述电源信号线及第二过孔。
为实现上述目的，本发明还提供了一种OLED阵列基板，包括多个子像素，每个子像素包含一个驱动电路来控制子像素的发光亮度和时间，所述的多个子像素的驱动电路排布成多列，其中相邻的两列子像素的驱动电路采用镜像对称结构。
为实现上述目的，本发明还提供了一种OLED显示装置，所述OLED显示装置包括OLED阵列基板，所述OLED阵列基板包括多个子像素，每个子像素包含一个驱动电路来控制子像素的发光亮度和时间；所述的多个子像素的驱动电路排布成多列，其中相邻的两列子像素的驱动电路采用镜像对称结构。
 有益效果
本发明OLED阵列基板的子像素的驱动电路，采用镜像对称结构，复位信号线和电源信号线沿相同方向延伸，通过共用复位信号线及第一过孔，共用电源信号线及第二过孔，可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。金属走线采用GE1/SD1/SD2三层结构设计，GE1作为驱动薄膜晶体管的栅电极以及扫描驱动线，SD1作为驱动薄膜晶体管的源漏电极、数据信号线、复位信号线以及存储电容的下极板，SD2 作为电源信号线以及存储电容上极板，可便于更大PPI电路设计，提高画面显示均匀度。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A为现有的OLED阵列基板的层状结构示意图；
图1B为图1A对应的7T1C电路的像素结构示意图；
图2为本发明OLED阵列基板一实施例的像素结构示意图；
图3为本发明OLED阵列基板一实施例的层状结构示意图。
 本发明的实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明OLED阵列基板，包括多个子像素，每个子像素包含一个驱动电路来控制子像素的发光亮度和时间，所述的多个子像素的驱动电路排布成多列，其中相邻的两列子像素的驱动电路采用镜像(Mirror)对称结构，相对于现有的7T1C布局结构，本发明改进的布局结构可以为PPI的提高提供空间，利于实现高PPI面板设计。
优选的，至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条复位信号线及第一过孔(复位过孔)，改进的像素结构布局可以省去一半左右的复位信号线走线以及过孔，从而为PPI的提高提供空间，利于实现高PPI面板设计。例如，第一列子像素与第二列子像素中同一行的两个子像素(即左右相邻的两个子像素)的驱动电路共用复位信号线及复位过孔，第三列子像素与第四列子像素中左右相邻的两个子像素的驱动电路共用复位信号线及复位过孔，但第二列子像素与第三列子像素并不共用复位信号线及复位过孔。
优选的，至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条电源信号线及第二过孔(电源过孔)，改进的像素结构布局可以省去一半左右的电源信号线走线以及过孔，从而为PPI的提高提供空间，利于实现高PPI面板设计。例如，第二列子像素与第三列子像素中同一行的两个子像素(即左右相邻的两个子像素)的驱动电路共用电源信号线及电源过孔，第四列子像素与第五列子像素中左右相邻的两个子像素的驱动电路共用电源信号线及电源过孔，但第一列子像素与第二列子像素、第三列子像素与第四列子像素并不共用电源信号线及电源过孔。
优选的，所述OLED阵列基板还包括复位信号线以及电源信号线，所述复位信号线和所述电源信号线沿相同方向延伸(即平行)。更优选的，在相邻的三列子像素中，相邻的两列子像素中同一行的两个子像素的驱动电路共用一条所述复位信号线及第一过孔，相邻的另两列子像素中同一行的两个子像素的驱动电路共用一条所述电源信号线及第二过孔，改进的像素结构布局可以省去一半左右的复位信号线、电源信号线走线以及相应过孔，从而为PPI的提高提供空间，利于实现高PPI面板设计。
所述OLED阵列基板的每一所述子像素包括多个薄膜晶体管(例如，包括驱动薄膜晶体管(Driver TFT)以及开关薄膜晶体管(Switch TFT))以及至少一个存储电容(Cst)；所述OLED阵列基板还包括第一金属层、第二金属层以及第三金属层。所述第一金属层包括扫描驱动线(Scan line)以及所述薄膜晶体管的栅电极(Gate)；所述第二金属层包括数据信号线(Data line)、复位信号线(VI line，用于复位存储电容和阳极)、所述薄膜晶体管的源漏电极(S/D)以及所述存储电容的下极板；所述第三金属层包括电源信号线(Power(Vdd) Line)以及所述存储电容的上极板，且电源信号线和存储电容上极板电学连接。所述第一金属层可以为栅金属层(GE1)，所述第二金属层可以为第一源漏金属层(SD1)，所述第三金属层可以为第二源漏金属层(SD2)。采用第二金属层与第三金属层制作存储电容上、下极板，第一金属层上只制作驱动薄膜晶体管的栅电极以及扫描驱动线，可便于更大PPI电路设计。
可选的，所述第二金属层上的所述复位信号线和所述第三金属层上的所述电源信号线沿相同方向延伸，以减小走线密度和过孔数量，提高PPI。
可选的，所述第三金属层上的所述电源信号线也可以在水平方向上相互电学连接，从而形成网状(Mesh)结构，此种结构设计在不增加光罩的情况下可以降低电源信号线的压降。
本发明OLED阵列基板，采用镜像对称结构，复位信号线和电源信号线沿相同方向延伸，通过共用复位信号线及第一过孔，共用电源信号线及第二过孔，可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。金属走线采用GE1/SD1/SD2三层结构设计，GE1作为驱动薄膜晶体管的栅电极以及扫描驱动线，SD1作为驱动薄膜晶体管的源漏电极、数据信号线、复位信号线以及存储电容的下极板，SD2 作为电源信号线以及存储电容上极板，可便于更大PPI电路设计，提高画面显示均匀度。
参考图2，本发明OLED阵列基板一实施例的像素结构示意图，图中CNT1为有源层与第二金属层(Poly-SD1)的接触孔即第一过孔，CNT2为有源层与第二金属层以及第三金属层(Poly-SD1-SD2)的接触孔即第二过孔，CNT3为第三金属层与阳极金属(SD2-PE)的接触孔即第三过孔。所述OLED阵列基板包括扫描驱动线(图中标记为Scan)、发光信号驱动线(图中标记为EM)与数据信号线(图中标记为Data)，由所述扫描驱动线(Scan)、发光信号驱动线(EM)与数据信号线(Data)形成的像素部分以及设置在所述像素部分中的多个子像素。每个子像素包含一个驱动电路来控制子像素的发光亮度和时间，所述的多个子像素的驱动电路排布成多列。本实施例中，所述子像素的驱动电路为7T1C电路，包括7个薄膜晶体管(M1~ M7)以及1个存储电容(Cst)，其中薄膜晶体管(M1)为驱动薄膜晶体管(Driver TFT)。
相邻的两列子像素的驱动电路采用镜像(Mirror)对称结构。如图2中子像素n和子像素n+1的驱动电路呈镜像对称，子像素n+1和子像素n+2的驱动电路呈镜像对称。
至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条复位信号线(图中标记为VI)及第一过孔CNT1。如图2中子像素n和子像素n+1中同一行的两个子像素的驱动电路共用复位信号线VI(n, n+1)和第一过孔CNT1。
至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条电源信号线(图中标记为VDD)及第二过孔CNT2。如图2中子像素n+1和子像素n+2中同一行的两个子像素的驱动电路共用电源信号线VDD(n+1, n+2)和第二过孔CNT2。
也即，在相邻的三列子像素中，相邻的两列子像素中同一行的两个子像素的驱动电路共用一条复位信号线及第一过孔，相邻的另两列子像素中同一行的两个子像素的驱动电路共用一条电源信号线及第二过孔。如图2中相邻的三列子像素(子像素n、子像素n+1和子像素n+2)中，相邻的两列子像素n和子像素n+1中同一行的两个子像素的驱动电路共用复位信号线VI(n, n+1)和第一过孔CNT1，相邻的另两列子像素n+1和子像素n+2中同一行的两个子像素的驱动电路共用电源信号线VDD(n+1, n+2)和第二过孔CNT2。
所述OLED阵列基板还包括复位信号线以及电源信号线，所述复位信号线(VI)和所述电源信号线(VDD)沿相同方向延伸(即平行)，从而相邻三列所述子像素的前两列所述子像素共用一条复位信号线(VI)及第一过孔CNT1，后两列所述子像素共用一条电源信号线(VDD)及第二过孔CNT2。如图2中子像素n和子像素n+1的共用复位信号线VI(n, n+1)和第一过孔CNT1，子像素n+1和子像素n+2共用电源信号线VDD(n+1, n+2)和第二过孔CNT2。
相对于现有的7T1C布局结构，本发明改进的布局结构可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。
参考图3，本发明OLED阵列基板一实施例的层状结构示意图。本发明阵列基板包括显示区(Active Area)301、扇出区(Fanout)以及弯折区(Pad Bending)(外围电路区，未示于图中)，显示区301包括阵列基板的子像素的驱动电路的多个薄膜晶体管(TFT)以及至少一个存储电容(Cst)。具体的，所述阵列基板包括：基板衬底311，依次设于所述基板衬底311上的阻挡层(M/B)312、缓冲层(Buffer)313、有源层(active layer)314、第一栅绝缘层(GI1)315、第一栅金属层(GE1)316、第一钝化层(PV1)317、有机介电绝缘层(OILD)318、第一源漏金属层(SD1)319、第二钝化层(PV2)320、第一平坦层(PLN1)321、第二源漏金属层(SD2)322、第二平坦层(PLN2)323、阳极(ANO)324、像素定义层(PDL)325以及光阻层(PS)326。基板衬底311可以采用玻璃(Glass)基板或采用无色透明聚酰亚胺(PI)材料制备的有机基板，可以为单层衬底(single)或双层(double)衬底。
具体的，所述第一栅金属层316包括所述薄膜晶体管的栅电极(Gate)3161和扫描驱动线(Scan line)3162。所述第一钝化层317为无机绝缘层，覆盖所述第一栅金属层316；所述有机介电绝缘层318为有机绝缘层，设于所述第一钝化层317上。也即，所述第一栅金属层316与所述第一源漏金属层319之间包括一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应。
具体的，所述第一源漏金属层319包括所述薄膜晶体管的源漏电极(S/D)3191、数据信号线(Data line)3192、复位信号线(VI line)3193以及所述存储电容的下极板3194。所述第二钝化层320为无机绝缘层，覆盖所述第一源漏金属层319；所述第一平坦层321为有机绝缘层，设于所述第二钝化层320上。也即，在第一源漏金属层319上的数据信号线3192上方存在一层无机绝缘层和一层有机绝缘层，可以减小数据信号线与电源信号线的耦合电容。所述存储电容区域可以通过曝光制程减薄所述第一平坦层321的厚度，从而减薄所述存储电容的介电绝缘层的厚度，可以形成较大存储电容，同时可保证其它区域有机绝缘层厚度不受影响。
具体的，所述第二源漏金属层322包括电源信号线(Power(Vdd) Line)3221以及所述存储电容的上极板3222，且电源信号线3221和存储电容的上极板3222电学连接(图中未示出连接关系)。电源信号线3221与复位信号线3193沿相同方向延伸，以减小走线密度和过孔数量，可便于更大PPI电路设计，提高画面显示均匀度。所述第二平坦层323(有机绝缘层)覆盖所述第二源漏金属层322，之后沉积阳极金属(PE)并进行图案化，形成所述阳极324。
可选的，所述第二源漏金属层322上的所述电源信号线3221也可以在水平方向上相互电学连接，从而形成网状(Mesh)结构，此种结构设计在不增加光罩的情况下可以降低电源信号线的压降。
采用所述第一源漏金属层319与所述第二源漏金属层322分别制作所述存储电容的上、下极板，所述第一栅金属层316上只制作所述薄膜晶体管的栅电极以及扫描驱动线，可便于更大PPI电路设计。同时，两层源漏金属层之间包括一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应。可以采用曝光制程减薄存储电容区域介电绝缘层厚度减薄，达到增大存储电容的目的。
优选的，在本实施例中，所述第一平坦层321上与所述存储电容的下极板3194对应的位置设有一沟槽3211，所述存储电容的上极板3222形成在所述沟槽3211内。也即，所述存储电容的介电绝缘层由沟槽3211下方剩余的第一平坦层321和第二钝化层320组成。所述沟槽3211深度可以通过半色调(half-tone)掩膜工艺对第一平坦层321进行部分曝光制程进行调整。从而，所述存储电容的大小可以通过上、下极板重叠区域面积及沟槽3211的深度进行调整。
本发明还提供了一种OLED显示装置，所述OLED显示装置包括本发明上述的OLED阵列基板。本发明OLED显示装置，OLED阵列基板采用镜像对称结构，复位信号线和电源信号线沿相同方向延伸，通过共用复位信号线及第一过孔，共用电源信号线及第二过孔，可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。OLED阵列基板的金属走线采用GE1/SD1/SD2三层结构设计，GE1作为驱动薄膜晶体管的栅电极以及扫描驱动线，SD1作为驱动薄膜晶体管的源漏电极、数据信号线、复位信号线以及存储电容的下极板，SD2 作为电源信号线以及存储电容上极板，可便于更大PPI电路设计，提高画面显示均匀度。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (20)

  1. 一种OLED阵列基板，包括多个子像素，每个子像素包含一个驱动电路来控制子像素的发光亮度和时间；其中，所述OLED阵列基板还包括复位信号线以及电源信号线，所述复位信号线和所述电源信号线沿相同方向延伸；所述的多个子像素的驱动电路排布成多列，其中相邻的两列子像素的驱动电路采用镜像对称结构，在相邻的三列子像素中，相邻的两列子像素中同一行的两个子像素的驱动电路共用一条所述复位信号线及第一过孔，相邻的另两列子像素中同一行的两个子像素的驱动电路共用一条所述电源信号线及第二过孔。
  2. 如权利要求1所述的OLED阵列基板，其中，每一所述子像素的驱动电路包括多个薄膜晶体管以及至少一个存储电容；所述OLED阵列基板还包括：第一金属层，所述第一金属层包括扫描驱动线以及所述薄膜晶体管的栅电极；第二金属层，所述第二金属层包括数据信号线、复位信号线、所述薄膜晶体管的源漏电极以及所述存储电容的下极板；第三金属层，所述第三金属层包括电源信号线以及所述存储电容的上极板，所述电源信号线和所述存储电容上极板电学连接。
  3. 一种OLED阵列基板，包括多个子像素，每个子像素包含一个驱动电路来控制子像素的发光亮度和时间；其中，所述的多个子像素的驱动电路排布成多列，其中相邻的两列子像素的驱动电路采用镜像对称结构。
  4. 如权利要求3所述的OLED阵列基板，其中，至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条复位信号线及第一过孔。
  5. 如权利要求3所述的OLED阵列基板，其中，至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条电源信号线及第二过孔。
  6. 如权利要求3所述的OLED阵列基板，其中，所述OLED阵列基板还包括复位信号线以及电源信号线；所述复位信号线和所述电源信号线沿相同方向延伸。
  7. 如权利要求6所述的OLED阵列基板，其中，在相邻的三列子像素中，相邻的两列子像素中同一行的两个子像素的驱动电路共用一条所述复位信号线及第一过孔，相邻的另两列子像素中同一行的两个子像素的驱动电路共用一条所述电源信号线及第二过孔。
  8. 如权利要求3所述的OLED阵列基板，其中，每一所述子像素的驱动电路包括多个薄膜晶体管以及至少一个存储电容；所述OLED阵列基板还包括：第一金属层，所述第一金属层包括扫描驱动线以及所述薄膜晶体管的栅电极；第二金属层，所述第二金属层包括数据信号线、复位信号线、所述薄膜晶体管的源漏电极以及所述存储电容的下极板；第三金属层，所述第三金属层包括电源信号线以及所述存储电容的上极板，所述电源信号线和所述存储电容上极板电学连接。
  9. 如权利要求8所述的OLED阵列基板，其中，所述第二金属层上的所述复位信号线和所述第三金属层上的所述电源信号线沿相同方向延伸。
  10. 如权利要求8所述的OLED阵列基板，其中，所述第三金属层上的所述电源信号线在水平方向上相互电学连接，从而形成网状结构。
  11. 如权利要求8所述的OLED阵列基板，其中，所述第一金属层为栅金属层，所述第二金属层为第一源漏金属层，所述第三金属层为第二源漏金属层。
  12. 一种OLED显示装置，所述OLED显示装置包括OLED阵列基板，所述OLED阵列基板包括多个子像素，每个子像素包含一个驱动电路来控制子像素的发光亮度和时间；其中，所述的多个子像素的驱动电路排布成多列，其中相邻的两列子像素的驱动电路采用镜像对称结构。
  13. 如权利要求12所述的OLED显示装置，其中，至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条复位信号线及第一过孔。
  14. 如权利要求12所述的OLED显示装置，其中，至少存在相邻的两列子像素中同一行的两个子像素的驱动电路共用一条电源信号线及第二过孔。
  15. 如权利要求12所述的OLED显示装置，其中，所述OLED阵列基板还包括复位信号线以及电源信号线；所述复位信号线和所述电源信号线沿相同方向延伸。
  16. 如权利要求15所述的OLED显示装置，其中，在相邻的三列子像素中，相邻的两列子像素中同一行的两个子像素的驱动电路共用一条所述复位信号线及第一过孔，相邻的另两列子像素中同一行的两个子像素的驱动电路共用一条所述电源信号线及第二过孔。
  17. 如权利要求12所述的OLED显示装置，其中，每一所述子像素的驱动电路包括多个薄膜晶体管以及至少一个存储电容；所述OLED阵列基板还包括：第一金属层，所述第一金属层包括扫描驱动线以及所述薄膜晶体管的栅电极；第二金属层，所述第二金属层包括数据信号线、复位信号线、所述薄膜晶体管的源漏电极以及所述存储电容的下极板；第三金属层，所述第三金属层包括电源信号线以及所述存储电容的上极板，所述电源信号线和所述存储电容上极板电学连接。
  18. 如权利要求17所述的OLED显示装置，其中，所述第二金属层上的所述复位信号线和所述第三金属层上的所述电源信号线沿相同方向延伸。
  19. 如权利要求17所述的OLED显示装置，其中，所述第三金属层上的所述电源信号线在水平方向上相互电学连接，从而形成网状结构。
  20. 如权利要求17所述的OLED显示装置，其中，所述第一金属层为栅金属层，所述第二金属层为第一源漏金属层，所述第三金属层为第二源漏金属层。
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