WO2021012095A1 - 显示面板及电子装置 - Google Patents

显示面板及电子装置 Download PDF

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Publication number
WO2021012095A1
WO2021012095A1 PCT/CN2019/096801 CN2019096801W WO2021012095A1 WO 2021012095 A1 WO2021012095 A1 WO 2021012095A1 CN 2019096801 W CN2019096801 W CN 2019096801W WO 2021012095 A1 WO2021012095 A1 WO 2021012095A1
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WIPO (PCT)
Prior art keywords
metal layer
display panel
layer
signal line
signal
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Application number
PCT/CN2019/096801
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English (en)
French (fr)
Inventor
张祖强
邱昌明
谭桂财
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201980090112.1A priority Critical patent/CN113366650B/zh
Priority to PCT/CN2019/096801 priority patent/WO2021012095A1/zh
Publication of WO2021012095A1 publication Critical patent/WO2021012095A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • This application relates to the field of display panels, in particular to a display panel and an electronic device.
  • An electronic device usually includes a display panel, and the display panel is used to display videos, pictures, or text. Then, when a traditional display panel displays videos, pictures, or text, due to the coupling between circuits and devices, the display screen often appears poor.
  • the embodiment of the application discloses a display panel.
  • the display panel includes a substrate, a plurality of data lines, a driving circuit, and a light-emitting unit, the plurality of data lines are arranged at intervals on one side of the substrate, the driving circuit is located on one side of the substrate, and the driving The circuit is electrically connected to the data line.
  • the driving circuit drives the light-emitting unit to work when receiving the data signal transmitted by the data line.
  • the display panel includes a first metal layer and a second metal layer. The first metal layer is insulated from the second metal layer, and the second metal layer is provided adjacent to the light emitting unit compared to the first metal layer. At least part of the data line is located in the first metal layer. Metal layer.
  • the embodiment of the present application also discloses an electronic device including the display panel.
  • the distance from the first metal layer to the light emitting unit is longer than the distance from the second metal layer to the second light emitting unit.
  • the data line of the present application is at least partially disposed on the first metal layer, so the distance between the data line located in the first metal layer and the light-emitting unit is compared with the data line located in the second metal layer.
  • the data line located on the first metal layer is far away from the light emitting unit.
  • the coupling capacitance generated between the data line located in the first metal layer and the cathode of the light emitting unit is small, thereby reducing the display panel caused by the coupling capacitance between the data line and the cathode of the light emitting unit
  • the problem of poor display screen improves the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by the first embodiment of this application.
  • FIG. 2 is a schematic diagram of a circuit structure of a display panel provided by an embodiment of the application.
  • FIG. 3 is a top view of a display panel provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the structure of the display panel provided by the second embodiment of this application.
  • FIG. 5 is a schematic diagram of the structure of the light emitting unit in the display panel of the present application.
  • FIG. 6 is a schematic structural diagram of a display panel provided by the third embodiment of this application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the fourth embodiment of this application.
  • FIG. 8 is a schematic structural diagram of a thin film transistor included in a driving circuit in a display panel in an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a thin film transistor included in a driving circuit of a display panel in another embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a display panel provided by a fifth embodiment of this application.
  • FIG. 11 is a schematic structural diagram of a display panel provided by a sixth embodiment of this application.
  • FIG. 12 is a schematic structural diagram of a display panel provided by a seventh embodiment of this application.
  • FIG. 13 is a schematic structural diagram of a thin film transistor included in a driving circuit in a display panel in another embodiment of this application.
  • FIG. 14 is a schematic diagram of the electronic device provided by this application.
  • FIG. 1 is a schematic diagram of the structure of the display panel provided by the first embodiment of the application
  • FIG. 2 is a schematic diagram of the circuit structure of the display panel provided by an embodiment of the application.
  • the display panel 100 includes a substrate 110, a plurality of data lines 120, a driving circuit 130, and a light emitting unit 140.
  • the plurality of data lines 120 are arranged on one side of the substrate 110 at intervals.
  • the driving circuit 130 is located on one side of the substrate 110 and the driving circuit 130 is electrically connected to the data line 120.
  • the driving circuit 130 drives the light emitting device when the data signal transmitted by the data line 120 is received.
  • Unit 140 works.
  • the display panel 100 includes a first metal layer 100a and a second metal layer 100b.
  • the first metal layer 100a and the second metal layer 100b are arranged to be insulated from each other, and the second metal layer 100b is arranged adjacent to the light emitting unit 140 compared to the first metal layer 100a, and the data line 120 At least part of is located in the first metal layer 100a.
  • An insulating layer 100d may be provided between the first metal layer 100a and the second metal layer 100b, so that the first metal layer 100a and the second metal layer 100b are spaced and insulated.
  • the distance from the first metal layer 100 a to the light emitting unit 140 is longer than the distance from the second metal layer 100 b to the second light emitting unit 140.
  • the data line 120 of the present application is at least partially disposed on the first metal layer 100a. Then, the distance between the data line 120 and the light emitting unit 140 in the first metal layer 100a is greater than that of the data line 120 in the first metal layer 100a. For the second metal layer 100b, the data line 120 located on the first metal layer 100a is far away from the light emitting unit 140.
  • the coupling capacitance generated between the data line 120 of the first metal layer 100a and the cathode 145 of the light emitting unit 140 is small, thereby reducing the coupling capacitance between the data line 120 and the cathode 145 of the light emitting unit 140
  • FIG. 3 is a top view of a display panel provided by an embodiment of the application.
  • the display panel 100 further includes a plurality of scan lines 150, the scan lines 150 are arranged at intervals, and the scan lines 150 and the data lines 120 are cross-insulated and arranged.
  • the data lines 120 are all located in the first metal layer 100a, and the scan lines 150 are all located in the second metal layer 100b.
  • the plurality of scan lines 150 are spaced and insulated, and the plurality of data lines 120 are spaced insulated. Two adjacent scan lines 150 and two adjacent data lines 120 define a sub-pixel area 150a.
  • the sub-pixel area 150 a is provided with the driving circuit 130 and the light emitting unit 140.
  • the data lines 120 are all located in the first metal layer 100a. Compared with the data lines 120 being partly located in the first metal layer 100a and partly located in the second metal layer 100b, it can be further reduced.
  • the coupling capacitance generated between the data line 120 and the introduction of the light-emitting unit 140 further improves the display effect of the display panel 100.
  • FIG. 4 is a schematic structural diagram of a display panel provided by a second embodiment of this application.
  • the display panel provided in this embodiment mode is basically the same as the display panel provided in the first embodiment mode. The difference is that, in this embodiment mode, the light-emitting unit 140 includes an anode 141 and a cathode 145.
  • the display panel 100 further includes a first signal line 160 and a second signal line 170.
  • the first signal line 160 is used to transmit a first signal
  • the second signal line 170 is used to transmit a second signal.
  • the light emitting unit 140 is driven to emit light.
  • the first signal line 160 is located on the first metal layer 100a, and the first signal line 160 is spaced apart from the data line 120, the second signal line 170 is located on the second metal layer 100b, and The second signal line 170 and the scan line 150 are spaced apart.
  • the first signal line 160 may also be referred to as a VDD line.
  • the function of the first signal line 160 is to transmit a first signal to the anode 141, and the first signal line 160 and the anode 141 are Two components, the first signal line 160 cannot be equivalent to the anode 141.
  • the second signal line 170 can also become a Vinit line.
  • the function of the second signal line 170 is to transmit a second signal to the cathode 145.
  • the second signal line 170 and the cathode 145 are two components.
  • the second signal line 170 cannot be equivalent to the cathode 145.
  • the projections of the first signal line 160 and the second signal line 170 in the direction perpendicular to the substrate 110 do not overlap, so as to reduce the size of the first signal line 160 and the second signal line. 170 between the coupling capacitance.
  • FIG. 5 is a schematic diagram of the structure of the light-emitting unit in the display panel of the present application.
  • the light emitting principle of the light emitting unit 140 is introduced as follows.
  • the light emitting unit 140 includes an anode 141, a hole injection and transport layer 142, a light emitting layer 143, an electron injection and transport layer 144, and a cathode 145.
  • the anode 141, the hole injection and transport layer 142, the light-emitting layer 143, the electron injection and transport layer 144, and the cathode 145 are thus stacked.
  • the anode 141 is electrically connected to the first signal line 160 to receive the first signal, the anode 141 generates holes, and the holes generated by the anode 141 are transported through the hole injection and transport layer 142 To the light-emitting layer 143.
  • the cathode 145 is electrically connected to the second signal line 170 to receive the second signal.
  • the cathode 145 generates electrons, and the electrons generated by the cathode 145 are transferred to the electron injection and transport layer 144.
  • the holes and electrons entering the light-emitting layer 143 recombine in the light-emitting layer 143 to generate light.
  • FIG. 6 is a schematic structural diagram of a display panel provided by the third embodiment of this application.
  • the display panel 100 includes a substrate 110, a plurality of data lines 120, a driving circuit 130, and a light emitting unit 140.
  • the plurality of data lines 120 are arranged on one side of the substrate 110 at intervals.
  • the driving circuit 130 is located on one side of the substrate 110 and the driving circuit 130 is electrically connected to the data line 120.
  • the driving circuit 130 drives the light emitting device when the data signal transmitted by the data line 120 is received.
  • Unit 140 works.
  • the display panel 100 includes a first metal layer 100a and a second metal layer 100b.
  • the first metal layer 100a and the second metal layer 100b are arranged to be insulated from each other, and the second metal layer 100b is arranged adjacent to the light emitting unit 140 compared to the first metal layer 100a, and the data line 120 At least part of is located in the first metal layer 100a.
  • An insulating layer 100d may be provided between the first metal layer 100a and the second metal layer 100b, so that the first metal layer 100a and the second metal layer 100b are spaced and insulated.
  • the display panel 100 further includes a plurality of scan lines 150.
  • the plurality of scan lines 150 are arranged at intervals, and the plurality of scan lines 150 are located on the first metal layer 100a.
  • At least one data line 120 includes a first portion 121 and a second portion 122 connected to each other. The first portion 121 is located on the first metal layer 100a, and the second portion 122 is located on the second metal layer 100b.
  • the projection of the second portion 122 on the substrate 110 and the projection of the scan line 150 on the substrate 110 at least partially overlap.
  • the scan line 150 and the data line 120 are cross-insulated.
  • the insulating layer is provided with a first through hole, and the first part 121 and the second part 122 are connected via a connecting portion 123 provided in the first through hole.
  • the length of the first part 121 is greater than the length of the second part 122.
  • most of the data line 120 is located in the first metal layer 100a, so that the data line 120 and the light emitting unit 140 The coupling capacitance between the cathodes 145 is small.
  • the first part 121 includes a plurality of first sub-parts 1211, two adjacent first sub-parts 1211 are spaced apart, the scan line 150 is located between two adjacent first sub-parts 1211, and the scan The wire 150 is spaced and insulated from the two adjacent first sub-parts 1211.
  • the second part 122 includes a plurality of second sub-parts 1221, and the second sub-part 1221 is electrically connected to two adjacent first sub-parts 1211. Further, for the non-edge first sub-part 1211, both ends of the non-edge first sub-part 1211 respectively correspond to a first through hole, and each first through hole is provided with a connecting portion 123, and each connection The parts 123 are respectively connected to the second sub-part 1221 through the first through holes.
  • the first scan line 150 and the N scan line 150 are both scan lines located at the edge of the display panel 100 150, and the remaining scan lines 150 are scan lines 150 located on non-edges.
  • N is a positive integer.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the fourth embodiment of this application.
  • the display panel 100 provided in this embodiment is basically the same as the display panel 100 provided in the third embodiment of the present application. The difference is that in this embodiment, the light-emitting unit 140 includes an anode 141 and a cathode 145.
  • the display panel 100 further includes a first signal line 160 and a second signal line 170.
  • the first signal line 160 is used to transmit a first signal
  • the second signal line 170 is used to transmit a second signal.
  • the light emitting unit 140 is driven to emit light.
  • the first signal line 160 is located on the second metal layer 100b
  • the second signal line 170 is located on the first metal layer 100a
  • the second signal line 170 is spaced apart from the scan line 150.
  • the projection of the second portion 122 on the substrate 110 and the projection of the second signal line 170 on the substrate 110 at least partially overlap.
  • the first part 121 includes a plurality of first sub-parts 1211, adjacent first sub-parts 1211 are arranged at intervals, the scan line 150 is located between two adjacent first sub-parts 1211, and the The scan line 150 is spaced apart from two adjacent first sub-parts 1211.
  • the second signal line 170 is located between two adjacent first sub-parts 1211, and the second signal line 170 and the scan line 150 are spaced and insulated.
  • the extension direction of the two signal lines is the same as the extension direction of the scan line 150.
  • FIG. 8 is a structural diagram of a thin film transistor included in a driving circuit in a display panel in an embodiment of the application.
  • the structure of the thin film transistor 131 can be combined with any one of the foregoing first to fourth embodiments.
  • the driving circuit 130 includes a thin film transistor 131 which includes a gate 1311, a gate insulating layer 1312, a semiconductor layer 1313, a source 1315, a drain 1314, and a flat layer 1316.
  • the gate 1311 is disposed on one side of the substrate 110, the gate insulating layer 1312 covers the gate 1311, and the semiconductor layer 1313 is located on the surface of the gate insulating layer 1312 away from the gate 1311 .
  • the source electrode 1315 and the drain electrode 1314 are respectively connected to the semiconductor layer 1313, and the source electrode 1315 and the drain electrode 1314 are spaced apart.
  • the flat layer 1316 covers the source electrode 1315 and the drain electrode 1314.
  • the gate 1311 is located on the first metal layer 100a, and the source 1315 and the drain 1314 are located on the second metal layer 100b.
  • the thin film transistor 131 can be equivalent to a switch, and the signal loaded on the gate 1311 is used to control the degree of conduction between the source 1315 and the drain 1314.
  • the signal loaded on the gate 1311 controls the source 1315 and the drain 1314 to be turned on
  • the signal loaded on the drain 1314 can be transmitted to the source 1315; when the gate 1311
  • the loaded signal controls the source 1315 and the drain 1314 to be disconnected, the channel between the loaded source 1315 and the drain 1314 is cut off, and the signal loaded on the drain 1314 cannot be Transmission to the source 1315.
  • FIG. 9 is a schematic structural diagram of a thin film transistor included in a driving circuit of a display panel in another embodiment of this application.
  • the structure of the thin film transistor 131 can be incorporated into any of the first to third embodiments of the present application.
  • the driving circuit 130 includes a thin film transistor 131, which includes a light shielding layer 1317, a first insulating layer 1318, a semiconductor layer 1313, a second insulating layer 1319, a gate 1311, an insulating layer, a third insulating layer 1320, and a source. 1315, and drain 1314.
  • the light shielding layer 1317 is disposed on one side of the substrate 110.
  • the first insulating layer 1318 covers the light shielding layer 1317, and the semiconductor layer 1313 is disposed on the surface of the first insulating layer 1318 away from the light shielding layer 1317 and corresponding to the light shielding layer 1317.
  • the second insulating layer 1319 covers the semiconductor layer 1313
  • the gate 1311 is disposed on the surface of the second insulating layer 1319 away from the semiconductor layer 1313
  • the third insulating layer 1320 covers the gate 1311
  • the source electrode 1315 and the drain electrode 1314 are disposed on the surface of the third insulating layer 1320 away from the gate electrode 1311, and the source electrode 1315 and the drain electrode 1314 are respectively connected to the through holes The opposite ends of the semiconductor layer 1313.
  • the light-shielding layer 1317 is located on the first metal layer 100a and the gate 1311 is located on the second metal layer 100b; or, the light-shielding layer 1317 is located on the first metal layer 100a and the source electrode 1315 and the drain 1314 are both located in the second metal layer 100b; or, the gate 1311 is located in the first metal layer 100a, and the source 1315 and the drain 1314 are both located in the second metal layer 100a.
  • the metal layer 100b is located on the first metal layer 100a and the gate 1311 is located on the second metal layer 100b; or, the light-shielding layer 1317 is located on the first metal layer 100a and the source electrode 1315 and the drain 1314 are both located in the second metal layer 100b; or, the gate 1311 is located in the first metal layer 100a, and the source 1315 and the drain 1314 are both located in the second metal layer 100a.
  • the metal layer 100b is located on the first metal layer 100a and the gate 1311 is located on the second metal layer 100
  • the thin film transistor 131 further includes a flat layer 1316, and the flat layer 1316 covers the source 1315 and the drain 1314.
  • FIG. 10 is a schematic structural diagram of a display panel provided by a fifth embodiment of this application.
  • the display panel 100 includes a substrate 110, a plurality of data lines 120, a driving circuit 130, and a light emitting unit 140.
  • the plurality of data lines 120 are arranged on one side of the substrate 110 at intervals.
  • the driving circuit 130 is located on one side of the substrate 110 and the driving circuit 130 is electrically connected to the data line 120.
  • the driving circuit 130 drives the light emitting device when the data signal transmitted by the data line 120 is received.
  • Unit 140 works.
  • the display panel 100 includes a first metal layer 100a and a second metal layer 100b.
  • the first metal layer 100a and the second metal layer 100b are arranged to be insulated from each other, and the second metal layer 100b is arranged adjacent to the light emitting unit 140 compared to the first metal layer 100a, and the data line 120 At least part of is located in the first metal layer 100a.
  • An insulating layer 100d may be provided between the first metal layer 100a and the second metal layer 100b, so that the first metal layer 100a and the second metal layer 100b are spaced and insulated.
  • the display panel 100 further includes a third metal layer 100c, and the third metal layer 100c is disposed adjacent to the light emitting unit 140 compared to the second metal layer 100b, and the third metal layer 100c and the second metal layer 100c
  • the two metal layers 100b are insulated.
  • At least one data line 120 includes a first portion 121 and a second portion 122 connected to each other. The first portion 121 is located on the first metal layer 100a, and the second portion 122 is located on the third metal layer 100c.
  • An insulating layer 100e may be provided between the third metal layer 100c and the second metal layer 100b, so that the third metal layer 100c and the second metal layer 100b are insulated and arranged at intervals.
  • the display panel 100 further includes a plurality of scan lines 150, the plurality of scan lines 150 are arranged at intervals, the plurality of scan lines 150 are located on the second metal layer 100b, and the scan lines 150 are located on the second metal layer 100b.
  • the projection on the substrate 110 and the projection of the first part 121 on the substrate 110 at least partially overlap.
  • the scan line 150 and the data line 120 are cross-insulated.
  • the insulating layer 100d between the first metal layer 100a and the second metal layer 100b is provided with a first through hole v1
  • the second metal layer 100b is provided with a second through hole v2
  • the insulating layer 100e between the metal layer 100b and the third metal layer 100c is provided with a third through hole v3, the first through hole v1, the second through hole v2, and the third through hole v3 Connect to form a connecting hole.
  • the first part 121 and the second part 122 are connected via a connecting part 123 arranged in the connecting hole.
  • the length of the second portion 122 is greater than the length of the first portion 121.
  • the length of the first portion 121 is greater than the length of the second portion 122, and when the length of the first portion 121 is greater than the length of the second portion 122, the Most of the data line 120 is located in the first metal layer 100a, so that the coupling capacitance between the data line 120 and the cathode 145 of the light-emitting unit 140 is small. It is illustrated in FIG. 10 that the length of the first part 121 is greater than the length of the second part 122.
  • the first part 121 includes a plurality of first sub-parts 1211, two adjacent first sub-parts 1211 are spaced apart, the scan line 150 is located between two adjacent first sub-parts 1211, and the scan The wire 150 is spaced and insulated from the two adjacent first sub-parts 1211.
  • the second part 122 includes a plurality of second sub-parts 1221, and the second sub-part 1221 is electrically connected to two adjacent first sub-parts 1211. Further, for the non-edge first sub-part 1211, both ends of the non-edge first sub-part 1211 correspond to a connecting hole, and each connecting hole is provided with a connecting portion 123, and each connecting portion 123 passes through The connecting hole connects the second sub-part 1221.
  • FIG. 11 is a schematic structural diagram of a display panel provided by a sixth embodiment of this application.
  • the display panel 100 provided in this embodiment is basically the same as the display panel 100 provided in the fifth embodiment of the present application. The difference is that in this embodiment, the light-emitting unit 140 includes an anode 141 and a cathode 145.
  • the display panel 100 further includes a first signal line 160 and a second signal line 170. The first signal line 160 is used to transmit a first signal, and the second signal line 170 is used to transmit a second signal.
  • the first signal line 160 is located on the third metal layer 100c, The first signal line 160 and the second portion 122 are spaced apart, the second signal line 170 is located in the second metal layer 100b, and the second signal line 170 is spaced apart from the scan line 150 .
  • FIG. 12 is a schematic structural diagram of a display panel provided by a seventh embodiment of this application.
  • the display panel 100 includes a substrate 110, a plurality of data lines 120, a driving circuit 130, and a light emitting unit 140.
  • the plurality of data lines 120 are arranged on one side of the substrate 110 at intervals.
  • the driving circuit 130 is located on one side of the substrate 110 and the driving circuit 130 is electrically connected to the data line 120.
  • the driving circuit 130 drives the light emitting device when the data signal transmitted by the data line 120 is received.
  • Unit 140 works.
  • the display panel 100 includes a first metal layer 100a and a second metal layer 100b.
  • the first metal layer 100a and the second metal layer 100b are arranged to be insulated from each other, and the second metal layer 100b is arranged adjacent to the light emitting unit 140 compared to the first metal layer 100a, and the data line 120 At least part of is located in the first metal layer 100a.
  • An insulating layer 100d may be provided between the first metal layer 100a and the second metal layer 100b, so that the first metal layer 100a and the second metal layer 100b are spaced and insulated.
  • the display panel 100 further includes a third metal layer 100c, the third metal layer 100c is disposed adjacent to the light emitting unit 140 compared to the second metal layer 100b, and the third metal layer 100c is The second metal layer 100b is insulated, and an insulating layer 100e is provided between the third metal layer 100c and the second metal layer 100b. All the data lines 120 are located on the first metal layer 100a.
  • the data lines 120 are all located on the first metal layer 100a, so that the distance between the data line 120 and the cathode 145 of the light emitting unit 140 is as long as possible, so that the data
  • the coupling capacitance between the line 120 and the cathode 145 of the light emitting unit 140 is small, thereby reducing the display image of the display panel 100 caused by the coupling capacitance between the data line 120 and the cathode 145 of the light emitting unit 140
  • the poor problem improves the display effect of the display panel 100.
  • the display panel 100 further includes a first signal line 160 and a second signal line 170.
  • the first signal line 160 is used to transmit a first signal
  • the second signal line 170 is used to transmit a second signal.
  • the cathode 145 is used to drive the light-emitting unit 140 to emit light
  • the first signal line 160 is located on the third metal layer 100c
  • the second signal line 170 is located on the second metal layer 100b.
  • the display panel 100 further includes a plurality of scan lines 150, the plurality of scan lines 150 are located on the second metal layer 100b, the plurality of scan lines 150 are arranged at intervals, and the plurality of scan lines 150 It is spaced apart from the second signal line 170.
  • FIG. 13 is a schematic structural diagram of a thin film transistor included in a driving circuit in a display panel in another embodiment of this application.
  • the structure of the thin film transistor 131 can be incorporated into any one of the fifth to seventh embodiments of the present application.
  • the driving circuit 130 includes a thin film transistor 131, which includes a light shielding layer 1317, a first insulating layer 1318, a semiconductor layer 1313, a second insulating layer 1319, a gate 1311, an insulating layer, a third insulating layer 1320, and a source. 1315, and drain 1314.
  • the light shielding layer 1317 is disposed on one side of the substrate 110.
  • the first insulating layer 1318 covers the light shielding layer 1317, and the semiconductor layer 1313 is disposed on the surface of the first insulating layer 1318 away from the light shielding layer 1317 and corresponding to the light shielding layer 1317.
  • the second insulating layer 1319 covers the semiconductor layer 1313
  • the gate 1311 is disposed on the surface of the second insulating layer 1319 away from the semiconductor layer 1313
  • the third insulating layer 1320 covers the gate 1311
  • the source electrode 1315 and the drain electrode 1314 are disposed on the surface of the third insulating layer 1320 away from the gate electrode 1311, and the source electrode 1315 and the drain electrode 1314 are respectively connected to the through holes The opposite ends of the semiconductor layer 1313.
  • the light shielding layer 1317 is located on the first metal layer 100a, the gate 1311 is located on the second metal layer 100b, and the source electrode 1315 and the drain electrode 1314 are located on the third metal layer 100c.
  • the thin film transistor 131 of the present application further includes a flat layer 1316, and the flat layer 1316 covers the source 1315 and the drain 1314.
  • the cathode 145 is arranged away from the data line 120 compared to the anode 141.
  • the cathode 145 is set away from the data line 120 compared with the anode 141 as an example for illustration.
  • the cathode 145 Compared with the anode 141 being arranged away from the data line 120, the cathode 145 further increases the distance between the cathode 145 and the data line 120.
  • the coupling capacitance generated between the data line 120 and the cathode 145 of the light emitting unit 140 is small, thereby reducing the coupling capacitance between the data line 120 and the cathode 145 of the light emitting unit 140 and the display panel 100
  • the problem of the poor display picture of the display improves the display effect of the display panel 100.
  • FIG. 14 is a schematic diagram of the electronic device provided by this application.
  • the electronic device 10 of the present application includes the display panel 100 described in any of the foregoing embodiments.
  • the electronic device 10 may be, but is not limited to, a smart phone, a tablet computer, etc.

Abstract

一种显示面板（100）及包括显示面板（100）的电子装置（10）。显示面板（100）包括基板（110）、多条数据线（120）、驱动电路（130）、及发光单元（140）。多条数据线（120）间隔设置在基板（110）的一侧，驱动电路（130）位于基板（110）的一侧且驱动电路（130）与数据线（120）电连接，驱动电路（130）在接收到数据线（120）传输的数据信号时驱动发光单元（140）工作，显示面板（100）包括第一金属层（100a）、及第二金属层（100b），第一金属层（100a）与第二金属层（100b）间隔绝缘设置，且第二金属层（100b）相较于第一金属层（100a）邻近发光单元（140）设置，数据线（120）的至少部分位于第一金属层（100a）。显示面板（100）具有较佳的显示效果。

Description

显示面板及电子装置 技术领域
本申请涉及显示面板领域，特别是涉及一种显示面板及电子装置。
背景技术
随着技术的进步，具有显示功能的电子装置逐渐进入到人们的生活当中。电子装置通常包括显示面板，所述显示面板用于显示视频、图片、或者文字。然后，传统显示面板在显示视频、图片或者文字的时候，由于线路、器件间的耦合作用，常常会出现显示画面不佳的情况。
发明内容
本申请实施方式公开了一种显示面板。所述显示面板包括基板、多条数据线、驱动电路、及发光单元，所述多条数据线间隔设置在所述基板的一侧，所述驱动电路位于所述基板的一侧且所述驱动电路与所述数据线电连接，所述驱动电路在接收到所述数据线传输的数据信号时驱动所述发光单元工作，所述显示面板包括第一金属层、及第二金属层，所述第一金属层与所述第二金属层间隔绝缘设置，且所述第二金属层相较于所述第一金属层邻近所述发光单元设置，所述数据线的至少部分位于所述第一金属层。
本申请实施方式还公开了一种电子装置，所述电子装置包括所述显示面板。
在本实施方式中，所述第一金属层到所述发光单元的距离比所述第二金属层到所述第二发光单元的距离远。本申请的数据线至少部分设置在所述第一金属层，那么，位于第一金属层的所述数据线与所述发光单元之间的距离相较于数据线位于第二金属层而言，位于第一金属层的数据线距离所述发光单元的距离较远。位于所述第一金属层的数据线与所述发光单元的阴极之间产生的耦合电容较小，从而减小了因为数据线与发光单元的阴极之间的耦合电容的产生而导致的显示面板的显示画面不佳的问题，提升了所述显示面板的显示效果。
附图说明
为了更清楚地说明本申请实施方式中的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施方式提供的显示面板的结构示意图。
图2为本申请一实施方式提供的显示面板的电路结构示意图。
图3为本申请一实施方式提供的显示面板的俯视图。
图4为本申请第二实施方式提供的显示面板的结构示意图。
图5为本申请显示面板中的发光单元的结构示意图。
图6为本申请第三实施方式提供的显示面板的结构示意图。
图7为本申请第四实施方式提供的显示面板的结构示意图。
图8为本申请一实施方式中显示面板中驱动电路中所包括的薄膜晶体管的结构示意图。
图9为本申请另一实施方式中显示面板中驱动电路中所包括的薄膜晶体管的结构示意图。
图10为本申请第五实施方式提供的显示面板的结构示意图。
图11为本申请第六实施方式提供的显示面板的结构示意图。
图12为本申请第七实施方式提供的显示面板的结构示意图。
图13为本申请又一实施方式中显示面板中的驱动电路中所包括的薄膜晶体管的结构示意图。
图14为本申请提供的电子装置的示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
请一并参阅图1及图2，图1为本申请第一实施方式提供的显示面板的结构示意图；图2为本申请一实施方式提供的显示面板的电路结构示意图。所述显示面板100包括基板110、多条数据线120、驱动电路130、及发光单元140。所述多条数据线120间隔设置在所述基板110的一侧。所述驱动电路130位于所述基板110的一侧且所述驱动电路130与所述数据线120电连接，所述驱动电路130在接收到所述数据线120传输的数据信号时驱动所述发光单元140工作。所述显示面板100包括第一金属层100a、及第二金属层100b。所述第一金属层100a与所述第二金属层100b间隔绝缘设置，且所述第二金属层100b相较于所述第一金属层100a邻近所述发光单元140设置，所述数据线120的至少部分位于所述第一金属层100a。
所述第一金属层100a及所述第二金属层100b之间可设置绝缘层100d以使得所述第一金属层100a及所述第二金属层100b间隔绝缘设置。
在本实施方式中，所述第一金属层100a到所述发光单元140的距离比所述第二金属层100b到所述第二发光单元140的距离远。本申请的数据线120至少部分设置在所述第一金属层100a，那么，位于第一金属层100a的所述数据线120与所述发光单元140之间的距离相较于数据线120位于第二金属层100b而言，位于第一金属层100a的数据线120距离所 述发光单元140的距离较远。位于所述第一金属层100a的数据线120与所述发光单元140的阴极145之间产生的耦合电容较小，从而减小了因为数据线120与发光单元140的阴极145之间的耦合电容的产生而导致的显示面板100的显示画面不佳的问题，提升了所述显示面板100的显示效果。
进一步地，请一并参阅图3，图3为本申请一实施方式提供的显示面板的俯视图。所述显示面板100还包括多条扫描线150，所述多条扫描线150间隔设置，且所述扫描线150与所述数据线120交叉绝缘设置。所述数据线120全部位于所述第一金属层100a，所述扫描线150全部位于所述第二金属层100b。
所述多条扫描线150间隔绝缘设置，所述多条数据线120间隔绝缘设置，相邻的两条扫描线150与相邻的两条数据线120之间限定一个子像素区150a。所述子像素区150a设置有所述驱动电路130及所述发光单元140。
在本实施方式中，所述数据线120全部位于所述第一金属层100a，相较于数据线120部分位于第一金属层100a另外部分位于第二金属层100b而言，可进一步减小所述数据线120与所述发光单元140的引进之间的产生的耦合电容，进一步提升显示面板100的显示效果。
请参阅图4，图4为本申请第二实施方式提供的显示面板的结构示意图。本实施方式提供的显示面板与第一实施方式提供的显示面板基本相同，不同之处在于，在本实施方式中，所述发光单元140包括阳极141及阴极145。所述显示面板100还包括第一信号线160及第二信号线170，所述第一信号线160用于传输第一信号，所述第二信号线170用于传输第二信号。当所述第一信号加载在所述阳极141且所述第二信号加载在所述阴极145时以驱动所述发光单元140发光。所述第一信号线160位于所述第一金属层100a，且所述第一信号线160与所述数据线120间隔设置，所述第二信号线170位于所述第二金属层100b，且所述第二信号线170与所述扫描线150间隔设置。需要说明的是，所述第一信号线160也可以称为VDD线，所述第一信号线160的作用是传输第一信号至所述阳极141，所述第一信号线160和阳极141是两个部件，所述第一信号线160不能等同为阳极141。所述第二信号线170也可以成为Vinit线，所述第二信号线170的作用是传输第二信号至所述阴极145，所述第二信号线170和所述阴极145是两个部件，所述第二信号线170不能等同为阴极145。
可选地，所述第一信号线160与所述第二信号线170在垂直于所述基板110方向上的投影不重叠，以减小所述第一信号线160与所述第二信号线170之间的耦合电容。
请一并参阅图5，图5为本申请显示面板中的发光单元的结构示意图。所述发光单元140的发光原理介绍如下。所述发光单元140包括阳极141、空穴注入及传输层142、发光层143、电子注入及传输层144、及阴极145。所述阳极141、所述空穴注入及传输层142、所述发光层143、所述电子注入及传输层144、及所述阴极145因此层叠设置。所述阳极141与所述第一信号线160电连接，以接收所述第一信号，所述阳极141产生空穴，所述阳极141产生的空穴经由所述空穴注入及传输层142传输至所述发光层143。所述阴极145 与所述第二信号线170电连接，以接收所述第二信号，所述阴极145产生电子，所述阴极145产生的电子经由所述电子注入及传输层144传输至所述发光层143，进入所述发光层143中的所述空穴及所述电子在所述发光层143中复合以产生光线。
请一并参阅图图2、图3及图6，图6为本申请第三实施方式提供的显示面板的结构示意图。所述显示面板100包括基板110、多条数据线120、驱动电路130、及发光单元140。所述多条数据线120间隔设置在所述基板110的一侧。所述驱动电路130位于所述基板110的一侧且所述驱动电路130与所述数据线120电连接，所述驱动电路130在接收到所述数据线120传输的数据信号时驱动所述发光单元140工作。所述显示面板100包括第一金属层100a、及第二金属层100b。所述第一金属层100a与所述第二金属层100b间隔绝缘设置，且所述第二金属层100b相较于所述第一金属层100a邻近所述发光单元140设置，所述数据线120的至少部分位于所述第一金属层100a。
所述第一金属层100a及所述第二金属层100b之间可设置绝缘层100d以使得所述第一金属层100a及所述第二金属层100b间隔绝缘设置。
进一步地，所述显示面板100还包括多条扫描线150。所述多条扫描线150间隔设置，所述多条扫描线150位于所述第一金属层100a。至少一条数据线120包括相连的第一部分121及第二部分122，所述第一部分121位于所述第一金属层100a，所述第二部分122位于第二金属层100b。
进一步地，所述第二部分122在所述基板110上的投影与所述扫描线150在所述基板110上的投影至少部分重叠。
具体地，所述扫描线150与所述数据线120交叉绝缘设置。所述绝缘层上开设有第一通孔，所述第一部分121及所述第二部分122经由设置在所述第一通孔内的连接部123相连。可选地，所述第一部分121的长度大于所述第二部分122的长度。当所述第一部分121的长度大于所述第二部分122的长度时，使得所述数据线120的大部分位于所述第一金属层100a，进而使得所述数据线120与所述发光单元140的阴极145之间耦合的电容较小。
所述第一部分121包括多个第一子部分1211，相邻的两个第一子部分1211间隔设置，所述扫描线150位于相邻的两个第一子部分1211之间，且所述扫描线150与相邻的两个第一子部分1211间隔绝缘设置。所述第二部分122包括多个第二子部分1221，所述第二子部分1221电连接相邻的两个第一子部分1211。进一步地，对于非边缘的第一子部分1211而言，非边缘的第一子部分1211的两端分别对应一个第一通孔，每个第一通孔内设置一个连接部123，每个连接部123分别通过所述第一通孔连接所述第二子部分1221。
假设所述显示面板100中包括依次排列的第1～N条扫描线150，所述第1条扫描线150及所述第N条扫描线150均为位于所述显示面板100的边缘的扫描线150，而其余的扫描线150为位于非边缘的扫描线150。其中，N为正整数。
进一步地，请参阅图7，图7为本申请第四实施方式提供的显示面板的结构示意图。本实施方式提供的显示面板100与本申请第三实施方式提供的显示面板100基本相同，不同之处在于，在本实施方式中，所述发光单元140包括阳极141及阴极145。所述显示面 板100还包括第一信号线160及第二信号线170，所述第一信号线160用于传输第一信号，所述第二信号线170用于传输第二信号。当所述第一信号加载在所述阳极141且所述第二信号加载在所述阴极145时以驱动所述发光单元140发光。所述第一信号线160位于所述第二金属层100b，所述第二信号线170位于所述第一金属层100a，且所述第二信号线170与所述扫描线150间隔设置。
进一步地，所述第二部分122在所述基板110上的投影与所述第二信号线170在所述基板110上的投影至少部分重叠。
具体地，所述第一部分121包括多个第一子部分1211，相邻的第一子部分1211间隔设置，所述扫描线150位于相邻的两个第一子部分1211之间，且所述扫描线150与相邻的两个第一子部分1211间隔设置。所述第二信号线170位于相邻的两个第一子部分1211之间，且所述第二信号线170与所述扫描线150间隔绝缘设置。可选地，所述二信号线的延伸方向与所述扫描线150的延伸方向相同。
下面结合显示面板100中驱动电路130中所包括的薄膜晶体管131的结构对本申请的显示面板100进行进一步介绍。请一并参阅图8，图8为本申请一实施方式中显示面板中驱动电路中所包括的薄膜晶体管的结构示意图。所述薄膜晶体管131的结构可结合前面第一至第四实施方式中的任意一种实施方式中。所述驱动电路130包括薄膜晶体管131，所述薄膜晶体管131包括栅极1311、栅极绝缘层1312、半导体层1313、源极1315、漏极1314、及平坦层1316。所述栅极1311设置在所述基板110的一侧，所述栅极绝缘层1312覆盖所述栅极1311，所述半导体层1313位于所述栅极绝缘层1312背离所述栅极1311的表面。所述源极1315与所述漏极1314分别与所述半导体层1313相连，且所述源极1315与所述漏极1314间隔设置。所述平坦层1316覆盖所述源极1315及所述漏极1314。其中，所述栅极1311位于所述第一金属层100a，所述源极1315及所述漏极1314位于所述第二金属层100b。
所述薄膜晶体管131可以等效为一个开关，所述栅极1311上加载的信号用于控制所述源极1315及所述漏极1314之间的导通程度。当所述栅极1311上加载的信号控制所述源极1315及所述漏极1314导通时，加载在所述漏极1314的信号可传输到所述源极1315；当所述栅极1311上加载的信号控制所述源极1315和漏极1314断开时，所加载所述源极1315及所述漏极1314之间的通道被切断，加载在所述漏极1314的信号不可以被传输到所述源极1315。
下面结合显示面板100中的驱动电路130所包括的薄膜晶体管131的结构对本申请的显示面板100进行进一步介绍。请一并参阅图9，图9为本申请另一实施方式中显示面板中驱动电路中所包括的薄膜晶体管的结构示意图。所述薄膜晶体管131的结构可结合到本申请第一至第三实施方式中的任意实施方式中。所述驱动电路130包括薄膜晶体管131，所述薄膜晶体管131包括遮光层1317、第一绝缘层1318、半导体层1313、第二绝缘层1319、栅极1311、绝缘层第三绝缘层1320、源极1315、及漏极1314。所述遮光层1317设置在所述基板110的一侧。所述第一绝缘层1318覆盖所述遮光层1317，所述半导体层1313设置 在所述第一绝缘层1318背离所述遮光层1317的表面且对应所述遮光层1317设置。所述第二绝缘层1319覆盖所述半导体层1313，所述栅极1311设置在所述第二绝缘层1319背离所述半导体层1313的表面，所述第三绝缘层1320覆盖所述栅极1311，所述源极1315与所述漏极1314设置在所述第三绝缘层1320背离所述栅极1311的表面，且所述源极1315及所述漏极1314分别通过通孔连接于所述半导体层1313相对的两端。其中，所述遮光层1317位于所述第一金属层100a且所述栅极1311位于所述第二金属层100b；或者，所述遮光层1317位于所述第一金属层100a且所述源极1315及所述漏极1314均位于所述第二金属层100b；或者，所述栅极1311位于所述第一金属层100a且所述源极1315及所述漏极1314均位于所述第二金属层100b。
进一步地，所述薄膜晶体管131还包平坦层1316，所述平坦层1316覆盖所述源极1315及所述漏极1314。
进一步地，请一并参阅图2、图3及图10，图10为本申请第五实施方式提供的显示面板的结构示意图。所述显示面板100包括基板110、多条数据线120、驱动电路130、及发光单元140。所述多条数据线120间隔设置在所述基板110的一侧。所述驱动电路130位于所述基板110的一侧且所述驱动电路130与所述数据线120电连接，所述驱动电路130在接收到所述数据线120传输的数据信号时驱动所述发光单元140工作。所述显示面板100包括第一金属层100a、及第二金属层100b。所述第一金属层100a与所述第二金属层100b间隔绝缘设置，且所述第二金属层100b相较于所述第一金属层100a邻近所述发光单元140设置，所述数据线120的至少部分位于所述第一金属层100a。
所述第一金属层100a及所述第二金属层100b之间可设置绝缘层100d以使得所述第一金属层100a及所述第二金属层100b间隔绝缘设置。
所述显示面板100还包括第三金属层100c，所述第三金属层100c相较于所述第二金属层100b邻近所述发光单元140设置，且所述第三金属层100c与所述第二金属层100b绝缘设置。至少一条数据线120包括相连的第一部分121及第二部分122，所述第一部分121位于所述第一金属层100a，所述第二部分122位于所述第三金属层100c。
所述第三金属层100c与所述第二金属层100b之间可设置绝缘层100e以使得所述第三金属层100c及所述第二金属层100b间隔绝缘设置。
进一步地，所述显示面板100还包括多条扫描线150，所述多条扫描线150间隔设置，所述多条扫描线150位于所述第二金属层100b，所述扫描线150在所述基板110上的投影与所述第一部分121在所述基板110上的投影至少部分重叠。
具体地，所述扫描线150与所述数据线120交叉绝缘设置。所述第一金属层100a与所述第二金属层100b之间的绝缘层100d上开设有第一通孔v1，所述第二金属层100b上开设有第二通孔v2，所述第二金属层100b与所述第三金属层100c之间的绝缘层100e上开设有第三通孔v3，所述第一通孔v1、所述第二通孔v2、及所述第三通孔v3连通以形成连接孔。所述第一部分121及所述第二部分122经由设置在所述连接孔内的连接部123相连。由于所述第二通v2孔开设在所述第二金属层100b上，所述第二通孔v2内还设置有绝缘层 100f，以使得所述连接部123与所述第二金属层100b绝缘。可选地，在一实施方式中，所述第二部分122的长度大于所述第一部分121的长度。可选地，在另一实施方式中，所述第一部分121的长度大于所述第二部分122的长度，当所述第一部分121的长度大于所述第二部分122的长度时，使得所述数据线120的大部分位于所述第一金属层100a，进而使得所述数据线120与所述发光单元140的阴极145之间的耦合电容较小。在图10中示意出来的是第一部分121的长度大于所述第二部分122的长度。
所述第一部分121包括多个第一子部分1211，相邻的两个第一子部分1211间隔设置，所述扫描线150位于相邻的两个第一子部分1211之间，且所述扫描线150与相邻的两个第一子部分1211间隔绝缘设置。所述第二部分122包括多个第二子部分1221，所述第二子部分1221电连接相邻的两个第一子部分1211。进一步地，对于非边缘的第一子部分1211而言，非边缘的第一子部分1211的两端分别对应一个连接孔，每个连接孔内设置一个连接部123，每个连接部123分别通过所述连接孔连接所述第二子部分1221。
进一步地，请参阅图11，图11为本申请第六实施方式提供的显示面板的结构示意图。本实施方式提供的显示面板100与本申请第五实施方式提供的显示面板100基本相同，不同之处在于，在本实施方式中，所述发光单元140包括阳极141及阴极145。所述显示面板100还包括第一信号线160及第二信号线170，所述第一信号线160用于传输第一信号，所述第二信号线170用于传输第二信号。当所述第一信号加载在所述阳极141且所述第二信号加载在所述阴极145时以驱动所述发光单元140发光，所述第一信号线160位于所述第三金属层100c，且所述第一信号线160与所述第二部分122间隔设置，所述第二信号线170位于所述第二金属层100b，且所述第二信号线170与所述扫描线150间隔设置。
请一并参阅图2、图3及图12，图12为本申请第七实施方式提供的显示面板的结构示意图。所述显示面板100包括基板110、多条数据线120、驱动电路130、及发光单元140。所述多条数据线120间隔设置在所述基板110的一侧。所述驱动电路130位于所述基板110的一侧且所述驱动电路130与所述数据线120电连接，所述驱动电路130在接收到所述数据线120传输的数据信号时驱动所述发光单元140工作。所述显示面板100包括第一金属层100a、及第二金属层100b。所述第一金属层100a与所述第二金属层100b间隔绝缘设置，且所述第二金属层100b相较于所述第一金属层100a邻近所述发光单元140设置，所述数据线120的至少部分位于所述第一金属层100a。
所述第一金属层100a及所述第二金属层100b之间可设置绝缘层100d以使得所述第一金属层100a及所述第二金属层100b间隔绝缘设置。
进一步地，所述显示面板100还包括第三金属层100c，所述第三金属层100c相较于所述第二金属层100b邻近所述发光单元140设置，且所述第三金属层100c与所述第二金属层100b绝缘设置，所述第三金属层100c与所述第二金属层100b之间设置绝缘层100e。所述数据线120全部位于所述第一金属层100a。
在本实施方式中，所述数据线120全部位于所述第一金属层100a，从而使得所述数据线120与所述发光单元140阴极145之间的距离尽可能地拉长，使得所述数据线120与所 述发光单元140的阴极145之间的耦合电容较小，从而减小了因为数据线120与发光单元140的阴极145之间的耦合电容的产生而导致的显示面板100的显示画面不佳的问题，提升了显示面板100的显示效果。
进一步地，所述显示面板100还包括第一信号线160及第二信号线170。所述第一信号线160用于传输第一信号，所述第二信号线170用于传输第二信号，当所述第一信号加载在所述阳极141且所述第二信号加载在所述阴极145时以驱动所述发光单元140发光，所述第一信号线160位于所述第三金属层100c，所述第二信号线170位于所述第二金属层100b。
进一步地，所述显示面板100还包括多条扫描线150，所述多条扫描线150位于所述第二金属层100b，所述多条扫描线150间隔设置，且所述多条扫描线150与所述第二信号线170间隔设置。
进一步地，请一并参阅图13，图13为本申请又一实施方式中显示面板中的驱动电路中所包括的薄膜晶体管的结构示意图。所述薄膜晶体管131的结构可结合到本申请第五至第七实施方式中的任意一实施方式中。所述驱动电路130包括薄膜晶体管131，所述薄膜晶体管131包括遮光层1317、第一绝缘层1318、半导体层1313、第二绝缘层1319、栅极1311、绝缘层第三绝缘层1320、源极1315、及漏极1314。所述遮光层1317设置在所述基板110的一侧。所述第一绝缘层1318覆盖所述遮光层1317，所述半导体层1313设置在所述第一绝缘层1318背离所述遮光层1317的表面且对应所述遮光层1317设置。所述第二绝缘层1319覆盖所述半导体层1313，所述栅极1311设置在所述第二绝缘层1319背离所述半导体层1313的表面，所述第三绝缘层1320覆盖所述栅极1311，所述源极1315与所述漏极1314设置在所述第三绝缘层1320背离所述栅极1311的表面，且所述源极1315及所述漏极1314分别通过通孔连接于所述半导体层1313相对的两端。其中，所述遮光层1317位于所述第一金属层100a，所述栅极1311位于所述第二金属层100b，所述源极1315及所述漏极1314位于所述第三金属层100c。本申请的薄膜晶体管131中还包括平坦层1316，所述平坦层1316覆盖所述源极1315及所述漏极1314。
进一步地，结合到前面任意实施方式中所述的显示面板100，所述阴极145相较于所述阳极141背离所述数据线120设置。且在相应附图中均以所述阴极145相较于所述阳极141背离所述数据线120设置为例进行示意。
所述阴极145相较于所述阳极141背离所述数据线120设置，进一步增大了所述阴极145与所述数据线120之间的距离。数据线120与所述发光单元140的阴极145之间产生的耦合电容较小，从而减小了数据线120与所述发光单元140的阴极145之间的耦合电容的产生而导致的显示面板100的显示画面不佳的问题，提升了所述显示面板100的显示效果。
进一步地，请一并参阅图14，图14为本申请提供的电子装置的示意图。本申请的电子装置10包前面任意实施方式介绍的显示面板100。所述电子装置10可以为但不仅限于为智能手机，平板电脑等。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请的核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种显示面板，其特征在于，所述显示面板包括基板、多条数据线、驱动电路、及发光单元，所述多条数据线间隔设置在所述基板的一侧，所述驱动电路位于所述基板的一侧且所述驱动电路与所述数据线电连接，所述驱动电路在接收到所述数据线传输的数据信号时驱动所述发光单元工作，所述显示面板包括第一金属层、及第二金属层，所述第一金属层与所述第二金属层间隔绝缘设置，且所述第二金属层相较于所述第一金属层邻近所述发光单元设置，所述数据线的至少部分位于所述第一金属层。
  2. 如权利要求1所述的显示面板，其特征在于，所述显示面板还包括多条扫描线，所述多条扫描线间隔设置，且所述扫描线与所述数据线交叉绝缘设置，所述数据线全部位于所述第一金属层，所述扫描线全部位于所述第二金属层。
  3. 如权利要求2所述的显示面板，其特征在于，所述发光单元包括阳极及阴极，所述显示面板还包括第一信号线及第二信号线，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述第一信号加载在所述阳极且所述第二信号加载在所述阴极时以驱动所述发光单元发光，所述第一信号线位于所述第一金属层，且所述第一信号线与所述数据线间隔设置，所述第二信号线位于所述第二金属层，且所述第二信号线与所述扫描线间隔设置。
  4. 如权利要求1所述的显示面板，其特征在于，所述显示面板还包括多条扫描线，所述多条扫描线间隔设置，所述多条扫描线位于所述第一金属层，至少一条数据线包括相连的第一部分及第二部分，所述第一部分位于所述第一金属层，所述第二部分位于第二金属层。
  5. 如权利要求4所述的显示面板，其特征在于，所述第二部分在所述基板上的投影与所述扫描线在所述基板上的投影至少部分重叠。
  6. 如权利要求4或5所述的显示面板，其特征在于，所述发光单元包括阳极及阴极，所述显示面板还包括第一信号线及第二信号线，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述第一信号加载在所述阳极且所述第二信号加载在所述阴极时以驱动所述发光单元发光，所述第一信号线位于所述第二金属层，所述第二信号线位于所述第一金属层，且所述第二信号线与所述扫描线间隔设置。
  7. 如权利要求6所述的显示面板，其特征在于，所述第二部分在所述基板上的投影与所述第二信号线在所述基板上的投影至少部分重叠。
  8. 如权利要求1-7任意一项所述的显示面板，其特征在于，所述驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极、栅极绝缘层、半导体层、源极、漏极、及平坦层，所述栅极设置在所述基板的一侧，所述栅极绝缘层覆盖所述栅极，所述半导体层位于所述栅极绝缘层背离所述栅极的表面，所述源极与所述漏极分别与所述半导体层相连，且所述源极与所述漏极间隔设置，所述平坦层覆盖所述源极及所述漏极，其中，所述栅极位于所述第一金属层，所述源极及所述漏极位于所述第二金属层。
  9. 如权利要求1-7任意一项所述的显示面板，其特征在于，所述驱动电路包括薄膜晶体管，所述薄膜晶体管包括遮光层、第一绝缘层、半导体层、第二绝缘层、栅极、第三绝缘层、源极、及漏极，所述遮光层设置在所述基板的一侧，所述第一绝缘层覆盖所述遮光层，所述半导体层设置在所述第一绝缘层背离所述遮光层的表面且对应所述遮光层设置，所述第二绝缘层覆盖所述半导体层，所述栅极设置在所述第二绝缘层背离所述半导体层的表面，所述第三绝缘层覆盖所述栅极，所述源极与所述漏极设置在所述第三绝缘层背离所述栅极的表面，且所述源极及所述漏极分别通过通孔连接于所述半导体层相对的两端，其中，所述遮光层位于所述第一金属层且所述栅极位于所述第二金属层；或者，所述遮光层位于所述第一金属层且所述源极及所述漏极均位于所述第二金属层；或者，所述栅极位于所述第一金属层且所述源极及所述漏极均位于所述第二金属层。
  10. 如权利要求1所述的显示面板，其特征在于，所述显示面板还包括第三金属层，所述第三金属层相较于所述第二金属层邻近所述发光单元设置，且所述第三金属层与所述第二金属层绝缘设置，至少一条数据线包括相连的第一部分及第二部分，所述第一部分位于所述第一金属层，所述第二部分位于所述第三金属层。
  11. 如权利要求10所述的显示面板，其特征在于，所述显示面板还包括多条扫描线，所述多条扫描线间隔设置，所述多条扫描线位于所述第二金属层，所述扫描线在所述基板上的投影与所述第一部分在所述基板上的投影至少部分重叠。
  12. 如权利要求10或11所述的显示面板，其特征在于，所述发光单元包括阳极及阴极，所述显示面板还包括第一信号线及第二信号线，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述第一信号加载在所述阳极且所述第二信号加载在所述阴极时以驱动所述发光单元发光，所述第一信号线位于所述第三金属层，且所述第一信号线与所述第二部分间隔设置，所述第二信号线位于所述第二金属层，且所述第二信号线与所述扫描线间隔设置。
  13. 如权利要求1所述的显示面板，其特征在于，所述显示面板还包括第三金属层，所 述第三金属层相较于所述第二金属层邻近所述发光单元设置，且所述第三金属层与所述第二金属层绝缘设置，所述数据线全部位于所述第一金属层。
  14. 如权利要求13所述的显示面板，其特征在于，所述显示面板还包括第一信号线及第二信号线，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述第一信号加载在所述阳极且所述第二信号加载在所述阴极时以驱动所述发光单元发光，所述第一信号线位于所述第三金属层，所述第二信号线位于所述第二金属层。
  15. 如权利要求14所述的显示面板，其特征在于，所述显示面板还包括多条扫描线，所述多条扫描线位于所述第二金属层，所述多条扫描线间隔设置，且所述多条扫描线与所述第二信号线间隔设置。
  16. 如权利要求10-15任意一项所述的显示面板，其特征在于，所述驱动电路包括薄膜晶体管，所述薄膜晶体管包括遮光层、第一绝缘层、半导体层、第二绝缘层、栅极、第三绝缘层、源极、及漏极，所述遮光层设置在所述基板的一侧，所述第一绝缘层覆盖所述遮光层，所述半导体层设置在所述第一绝缘层背离所述遮光层的表面且对应所述遮光层设置，所述第二绝缘层覆盖所述半导体层，所述栅极设置在所述第二绝缘层背离所述半导体层的表面，所述第三绝缘层覆盖所述栅极，所述源极与所述漏极设置在所述第三绝缘层背离所述栅极的表面，且所述源极及所述漏极分别通过通孔连接于所述半导体层相对的两端，其中，所述遮光层位于所述第一金属层，所述栅极位于所述第二金属层，所述源极及所述漏极位于所述第三金属层。
  17. 如权利要求3、6、12中的任意一项所述的显示面板，其特征在于，所述阴极相较于所述阳极背离所述数据线设置。
  18. 一种电子装置，其特征在于，所述电子装置包括如权利要求1-17任意一项所述的显示面板。
PCT/CN2019/096801 2019-07-19 2019-07-19 显示面板及电子装置 WO2021012095A1 (zh)

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