WO2021012094A1 - 显示面板及电子装置 - Google Patents

显示面板及电子装置 Download PDF

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Publication number
WO2021012094A1
WO2021012094A1 PCT/CN2019/096799 CN2019096799W WO2021012094A1 WO 2021012094 A1 WO2021012094 A1 WO 2021012094A1 CN 2019096799 W CN2019096799 W CN 2019096799W WO 2021012094 A1 WO2021012094 A1 WO 2021012094A1
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WO
WIPO (PCT)
Prior art keywords
signal
line
display panel
layer
insulating layer
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Application number
PCT/CN2019/096799
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English (en)
French (fr)
Inventor
张祖强
谭桂财
邱昌明
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2019/096799 priority Critical patent/WO2021012094A1/zh
Priority to CN201980090118.9A priority patent/CN113383424A/zh
Publication of WO2021012094A1 publication Critical patent/WO2021012094A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • This application relates to the field of display panels, in particular to a display panel and an electronic device.
  • An electronic device usually includes a display panel, and the display panel is used to display videos, pictures, or text. Then, when a traditional display panel displays videos, pictures, or text, due to the coupling between circuits and devices, the display screen often appears poor.
  • An embodiment of the present application discloses a display panel.
  • the display panel includes a substrate, a plurality of data lines, a light emitting unit, and a shielding layer.
  • the plurality of data lines are arranged at intervals on one side of the substrate, and the light emitting unit Comprising a cathode, and there is an overlapping area between the cathode and the data line, the shielding layer is located between the cathode and the data line, and the shielding layer is at least partially located in the overlapping area, so The shielding layer is used to reduce the coupling between the cathode and the data line.
  • the application also provides an electronic device including a display panel.
  • the display panel of the present application is provided with a shielding layer in at least part of the overlapping area between the cathode and the data line.
  • the shielding layer can reduce the coupling between the cathode and the data line, thereby weakening or even weakening. Eliminate the crosstalk phenomenon of the display panel caused by the coupling effect between the cathode and the data line. Therefore, the display panel of the present application has higher display quality.
  • FIG. 1 is a top view of a display panel provided by the first embodiment of the application.
  • Fig. 2 is a cross-sectional view taken along line I-I in Fig. 1.
  • Fig. 3 is a schematic diagram of the structure of a light-emitting unit.
  • FIG. 4 is a top view of the display panel provided by the second embodiment of this application.
  • Fig. 5 is a cross-sectional view taken along line II-II in Fig. 4.
  • FIG. 6 is a top view of the display panel provided by the third embodiment of this application.
  • Fig. 7 is a cross-sectional view taken along line III-III in Fig. 6.
  • FIG. 8 is a top view of the display panel provided by the fourth embodiment of this application.
  • Fig. 9 is a cross-sectional view taken along the line IV-IV in Fig. 8.
  • FIG. 10 is a top view of the display panel provided by the fifth embodiment of this application.
  • Fig. 11 is a sectional view taken along the line V-V in Fig. 10;
  • FIG. 12 is a top view of the display panel provided by the sixth embodiment of this application.
  • Fig. 13 is a sectional view taken along the line VI-VI in Fig. 12;
  • FIG. 14 is a top view of the display panel provided by the seventh embodiment of this application.
  • FIG. 15 is a schematic diagram of the structure of the thin film transistor in the driving circuit in FIG. 14.
  • FIG. 16 is a schematic diagram of a circuit structure of a driving circuit for driving a light-emitting unit in a display panel in an embodiment of the application.
  • FIG. 17 is a top view of the display panel provided by the eighth embodiment of this application.
  • FIG. 18 is a schematic diagram of the structure of a thin film transistor in the driving circuit.
  • FIG. 19 is a schematic diagram of an electronic device provided by an embodiment of the application.
  • FIG. 1 is a top view of the display panel provided by the first embodiment of the application;
  • FIG. 2 is a cross-sectional view along the line I-I in FIG. 1. It is understandable that since the topmost layer in FIG. 1 is the cathode 141 of the light-emitting unit 140, in order to illustrate the layer structure under the cathode 141, the cathode 141 is omitted in FIG.
  • the display panel 10 includes a substrate 110, a plurality of data lines 120, a light emitting unit 140, and a shielding layer 193.
  • the plurality of data lines 120 are arranged on one side of the substrate 110 at intervals.
  • the light emitting unit 140 includes a cathode 141, and there is an overlapping area between the cathode 141 and the data line 120.
  • the shielding layer 193 is located between the cathode 141 and the data line 120, and the shielding layer 193 is at least partially located in the overlapping area.
  • the shielding layer 193 is used to reduce the cathode 141 and the data line 120. The coupling between the data lines 120.
  • the cathode 141 and the data line 120 will generate a coupling capacitance.
  • the coupling effect of the coupling capacitance is sufficiently large
  • the pixel voltage in the display panel 10 changes instantaneously, it will affect the voltage of the common electrode in the display panel 10, so that the voltage of the common electrode deviates from the set potential and the time for the common voltage to deviate from the set potential is longer, and the recovery The time to the original potential is longer.
  • the time for the voltage of the common electrode to return to the original potential is longer than the time for signal writing in one scan line in the display panel 10. Therefore, the display panel 10 may cause serious errors when displaying images.
  • the phenomenon is called crosstalk.
  • the material of the shielding layer 193 is metal or conductive metal oxide.
  • the display panel 10 of the present application is provided with a shielding layer 193 in at least a part of the overlapping area between the cathode 141 and the data line 120.
  • the shielding layer 193 can reduce the coupling between the cathode 141 and the data line 120, thereby weakening Even the crosstalk phenomenon of the display panel 10 caused by the coupling effect between the cathode 141 and the data line 120 is eliminated. Therefore, the display panel 10 of the present application has a higher display quality.
  • the light-emitting unit 140 further includes an anode 145, and the shielding layer 193 and the anode 145 are arranged in the same layer and spaced apart.
  • the manufacturing process of the display panel 10 can be simplified.
  • the shielding layer 193 and the anode 145 are arranged to be insulated from each other. Compared with the shielding layer 193 and the anode 145 are connected or electrically connected, in this embodiment, the shielding layer 193 and the anode 145 are arranged to be insulated from each other, which can prevent the shielding layer 193 from being exposed to the The light emission of the light emitting unit 140 causes an influence.
  • FIG. 3 is a schematic diagram of the structure of the light-emitting unit.
  • the light emitting unit 140 includes an anode 145, a hole injection and transport layer 144, a light emitting layer 143, an electron injection and transport layer 142, and a cathode 141 which are stacked.
  • the light-emitting unit 140 may be directly disposed on the substrate 110 or may be disposed on the substrate 110 through other layer structures.
  • the light-emitting unit 140 is disposed on the substrate 110 through an insulating layer 193 as an example. .
  • the anode 145 is used to load a first signal and generate holes under the action of the first signal, and the hole injection and transport layer 144 is used to transport the holes generated by the anode 145 to the light-emitting layer 143 .
  • the cathode 141 is used to load a second signal and generate electrons under the action of the second signal, and the electron injection and transport layer 142 is used to transport the electrons generated by the cathode 141 to the light-emitting layer 143. The electrons and the holes recombine in the light-emitting layer 143 to generate light.
  • FIG. 4 is a top view of the display panel provided by the second embodiment of this application;
  • FIG. 5 is a cross-sectional view along the line II-II in FIG. 4.
  • the display panel 10 provided in this embodiment is basically the same as the display panel 10 provided in the first embodiment. The difference is that in this embodiment, the light-emitting unit 140 further includes an anode 145.
  • the display panel 10 further includes a first signal line 150 and a second signal line 160.
  • the first signal line 150 is used to transmit a first signal
  • the second signal line 160 is used to transmit a second signal.
  • the shielding layer 193 is electrically connected to the first signal line 150.
  • the first signal line 150 may also be referred to as a VDD line.
  • the function of the first signal line 150 is to transmit a first signal to the anode 145.
  • the first signal line 150 and the anode 145 are two Component, the first signal line 150 cannot be equivalent to the anode 145.
  • the second signal line 160 may also become a Vinit line.
  • the function of the second signal line 160 is to transmit a second signal to the cathode 141.
  • the second signal line 160 and the cathode 141 are two components, The second signal line 160 cannot be equivalent to the cathode 141. Please also refer to FIG. 3 and related descriptions.
  • the first signal is loaded on the anode 145, the anode 145 generates holes under the action of the first signal, and the holes generated by the anode 145 pass through all the holes.
  • the hole injection and transport layer 144 is transported to the light emitting layer 143.
  • the cathode 141 generates electrons under the action of the second signal, and the electrons generated by the cathode 141 are transmitted to the light-emitting layer 143 through the electron injection and transport layer 142.
  • the electrons and the holes recombine in the light-emitting layer 143 to emit light.
  • the shielding layer 193 of the present application is electrically connected to the first signal line 150, which can weaken or even avoid the coupling of the data line 120 to the cathode 141, thereby weakening or even eliminating the coupling between the cathode 141 and the data line 120.
  • an insulating layer 194 is provided between the first signal line 150 and the shielding layer 193, the insulating layer 194 is provided with a through hole, and the shielding layer 193 is filled with the conductive material in the through hole and the second A signal line 150 is electrically connected.
  • the shielding layer 193 includes a first shielding portion 193a, a second shielding portion 193b, and a connecting portion 193c connected between the first shielding portion 193a and the second shielding portion 193b.
  • the projection of the first shielding portion 193a on the substrate 110 at least partially covers the projection of the data line 120 on the substrate 110
  • the projection of the second shielding portion 193b on the substrate 110 at least partially covers The projection of the first signal line 150 on the substrate 110
  • the second shielding portion 193 b is electrically connected to the first signal line 150.
  • the insulating layer 194 is provided between the first signal line 150 and the shielding layer 193, the insulating layer 194 is provided at a location corresponding to the second shielding portion 193b and the first signal line 150. Through holes, the second shielding portion 193b is electrically connected to the first signal line 150 through a conductive material filled in the through holes.
  • the display panel 10 includes a plurality of spaced data lines 120, the display panel 10 also includes a plurality of spaced scan lines 130, two adjacent data lines 120 and two adjacent A pixel region 10c is formed between the scan lines 130.
  • the pixel area 10c is used for arranging the light emitting unit 140.
  • the first signal line 150 is disposed between the data line 120 and the light emitting unit 140, and the extension direction of the first signal line 150 is the same or substantially the same as the extension direction of the data line 120.
  • the second signal line 160 is disposed between the scan line 130 and the light emitting unit 140, and the extension direction of the second signal line 160 is the same or substantially the same as the extension direction of the scan line 130.
  • FIG. 6 is a top view of the display panel provided by the third embodiment of this application;
  • FIG. 7 is a cross-sectional view along the line III-III in FIG. 6.
  • the display panel 10 provided in this embodiment is basically the same as the display panel 10 provided in the second embodiment. The difference is that in this embodiment, the display panel 10 further includes a first signal line 150 and a second signal line 160. .
  • the first signal line 150 is used to transmit a first signal
  • the second signal line 160 is used to transmit a second signal.
  • the shielding layer 193 is electrically connected to the second signal line 160.
  • the first signal line 150 may also be referred to as a VDD line
  • the second signal line 160 may also be referred to as a Vinit line.
  • the first signal is loaded on the anode 145, the anode 145 generates holes under the action of the first signal, and the holes generated by the anode 145 pass through all the holes.
  • the hole injection and transport layer 144 is transported to the light emitting layer 143.
  • the cathode 141 generates electrons under the action of the second signal, and the electrons generated by the cathode 141 are transmitted to the light-emitting layer 143 through the electron injection and transport layer 142.
  • the electrons and the holes recombine in the light-emitting layer 143 to emit light.
  • the shielding layer 193 of the present application is electrically connected to the second signal line 160, which can weaken or even avoid the coupling of the data line 120 to the cathode 141, thereby weakening or even eliminating the coupling between the cathode 141 and the data line 120.
  • an insulating layer 194 is provided between the second signal line 160 and the shielding layer 193.
  • the insulating layer 194 is provided with a through hole, and the shielding layer 193 is electrically connected to the second signal line 160 through a conductive material filled in the through hole.
  • an insulating layer 194 is provided between the data line 120 and the second signal line 160, and the data line 120 and the second signal line 160 are cross-insulated by the insulating layer 194.
  • the insulating layer 194 is used to insulate and isolate the data line 120 from the second signal.
  • FIG. 8 is a top view of the display panel provided by the fourth embodiment of the present application
  • FIG. 9 is a cross-sectional view along the line IV-IV in FIG. 8.
  • the display panel 10 provided in this embodiment is basically the same as the display panel 10 provided in the third embodiment. The difference is that in this embodiment, an insulating layer is provided at the intersection of the data line 120 and the second signal line 160. 194. The rest of the data line 120 and the rest of the second signal line 160 are located on the same layer. In this embodiment, an insulating layer 194 is provided at the intersection of the data line 120 and the second signal line 160 to achieve insulation isolation between the data line 120 and the second signal line 160. The rest of the data line 120 and the rest of the second signal line 160 are located on the same layer, which facilitates the thinning of the display panel 10.
  • FIG. 10 is a top view of a display panel provided by a fifth embodiment of the present application;
  • FIG. 11 is a cross-sectional view along the line V-V in FIG. 10.
  • the display panel 10 provided in this embodiment is basically the same as the display panel 10 provided in the first embodiment. The difference is that in this embodiment, the display panel 10 further includes a common electrode line 170.
  • the common electrode line 170 is loaded with a power supply voltage, the common electrode line 170 and the data line 120 are crossed and insulated, and the shielding layer 193 is electrically connected to the common electrode line 170.
  • the coupling of the data line 120 to the cathode 141 can be weakened or even avoided, thereby weakening or even eliminating the difference between the cathode 141 and the data line 120.
  • the display panel 10 includes a plurality of data lines 120 arranged at intervals, and the display panel 10 further includes a plurality of scan lines 130 arranged at intervals. Two adjacent data lines 120 are connected to each other. A pixel area 10c is formed between two adjacent scan lines 130. The pixel area 10c is used for arranging the light emitting unit 140.
  • the display panel 10 further includes a first signal line 150 and a second signal line 160. The first signal line 150 is used to transmit a first signal, and the second signal line 160 is used to transmit a second signal. When the first signal is applied to the anode 145 and the second signal is applied to the The cathode 141 is used to drive the light-emitting unit 140 to emit light.
  • the first signal line 150 is disposed between the data line 120 and the light emitting unit 140, and the extension direction of the first signal line 150 is the same or substantially the same as the extension direction of the data line 120.
  • the second signal line 160 is disposed between the scan line 130 and the light-emitting unit 140, and the extension direction of the second signal line 160 is the same or substantially the same as the extension direction of the scan line 130.
  • the common electrode line 170 is crossed and insulated from the first signal line 150 and the data line 120, and the common electrode line 170 is spaced apart from the second signal line 160 and the scan line 130, respectively.
  • the extension direction of the common electrode line 170 is the same or substantially the same as the extension direction of the data line 120.
  • the common electrode line 170 is disposed on the side of the second signal line 160 away from the scan line 130. It can be understood that, in other embodiments, the positional relationship between the common electrode line 170 and the second signal line 160 and the scan line 130 only needs to satisfy the requirements of the common electrode line 170 and the second signal line.
  • the line 160 and the scan line 130 may be insulated at intervals.
  • the common electrode line 170 and the second signal line 160 are provided in the same layer. When the common electrode line 170 and the second signal line 160 are arranged in the same layer, the common electrode line 170 and the second signal line 160 are prepared in the same process, which can save the manufacturing process.
  • the common electrode and the second signal line 160 are spaced and insulated. Compared with the electrical connection between the common electrode and the second signal line 160, in this embodiment, the common electrode and the second signal line 160 are spaced apart and insulated, so that the shielding layer 193 is electrically connected to the second signal line 160.
  • the second signal lines 160 are arranged at intervals and insulated to avoid the influence of the shielding layer 193 on the light emission of the light emitting unit 140.
  • an insulating layer 194 is provided at the intersection of the common electrode line 170 and the data line 120, and the rest of the data line 120 and the rest of the common electrode line 170 are located on the same layer.
  • an insulating layer 194 is provided between the common electrode line 170 and the data line 120, and the common electrode line 170 and the data line 120 are cross-insulated by the insulating layer 194.
  • an insulating layer 194 is provided between the common electrode line 170 and the data line 120 as an example.
  • FIG. 12 is a top view of a display panel provided by a sixth embodiment of this application;
  • FIG. 13 is a cross-sectional view along line VI-VI in FIG. 12.
  • the structure of the display panel 10 provided in this embodiment is basically the same as that of the display panel 10 provided in the first embodiment. The difference is that in this embodiment, the display panel 10 includes a display area 10a and is arranged in the display area 10a. The non-display area 10b at the periphery of 10a.
  • the display panel 10 further includes a power line 195, the power line 195 is loaded with a power supply voltage, the power line 195 is disposed corresponding to the non-display area 10b, and the shielding layer 193 is electrically connected to the power line 195.
  • the shielding layer 193 is electrically connected to the power line 195 located in the non-display area 10b, so as to avoid the influence and interference of the additional power line 195 in the display area 10a on other circuits in the display area 10a.
  • an insulating layer 194 is provided between the power line 195 and the shielding layer 193, the insulating layer 194 is provided with a through hole, and the power line 195 is connected to the conductive material filled in the through hole.
  • the shielding layer 193 is electrically connected.
  • the power cord 195 and the shielding layer 193 are located on the same layer, and the power cord 195 and the shielding layer 193 are directly electrically connected.
  • the power line 195 is electrically connected to the shielding layer 193 through the conductive material filled in the through hole as an example for illustration.
  • FIG. 14 is a top view of a display panel provided by a seventh embodiment of this application;
  • FIG. 15 is a schematic structural diagram of a thin film transistor in the driving circuit in FIG. 14.
  • the driving circuit 180 in the display panel 10 can be combined with the display panel 10 provided in any one of the first to sixth embodiments.
  • the driving circuit 180 is combined with the first
  • the display panel 10 provided in the sixth embodiment is taken as an example for illustration.
  • the display panel 10 further includes a driving circuit 180, a first signal line 150 and a second signal line 160.
  • the light emitting unit 140 further includes an anode 145, the first signal line 150 is used for transmitting a first signal, and the second signal line 160 is used for transmitting a second signal.
  • the driving circuit 180 When the driving circuit 180 is turned on, the first signal is applied to the anode 145 and the second signal is applied to the cathode 141 to drive the light-emitting unit 140 to emit light.
  • the driving circuit 180 includes a thin film transistor Q, and the thin film transistor Q includes a gate 181, a gate insulating layer 182, a semiconductor layer 183, a source 184, a drain 185, and a flat layer 186.
  • the gate electrode 181 is disposed on one side of the substrate 110, the gate insulating layer 182 covers the gate electrode 181, and the semiconductor layer 183 is located on the surface of the gate insulating layer 182 away from the gate electrode 181
  • the source electrode 184 and the drain electrode 185 are respectively connected to the semiconductor layer 183, and the source electrode 184 and the drain electrode 185 are spaced apart.
  • the flat layer 186 covers the source electrode 184 and the drain electrode 185, the flat layer 186 has a through hole corresponding to the drain electrode 185, and the data line 120 is disposed on the flat layer 186 away from the substrate
  • the data line 120 is covered with a data line insulating layer 196, and the shielding layer 193 is disposed on the surface of the data line insulating layer 196 away from the data line 120.
  • FIG. 16 is a schematic diagram of a circuit structure of a driving circuit for driving a light emitting unit in a display panel in an embodiment of the application.
  • the display panel 10 includes a plurality of scan lines 130 arranged at intervals, and a plurality of data lines 120 arranged at intervals, and the data lines 120 and the scan lines 130 are arranged crosswise and insulated.
  • the scan lines 130 are used to transmit scan signals
  • the data lines 120 are used to transmit data signals.
  • Two adjacent data lines 120 and two adjacent scan lines 130 define a pixel area 10c, and the pixel area 10c
  • the pixel area 10c is further provided with a first thin film transistor Q1 and a second thin film transistor Q2.
  • the first signal is applied to the light emitting unit
  • the anode of 140 and the cathode of the light-emitting unit 140 are used to receive the second signal.
  • the first signal is applied to the anode of the light-emitting unit 140
  • the second signal is applied to the cathode of the light-emitting unit 140 as an example for illustration. At this time, the first signal is high. Level, the second signal is low level.
  • the pixel region 10c is further provided with a first capacitor C1, the first thin film transistor Q1 includes a first gate g1, a first terminal p1, and a second terminal p2, and the second thin film transistor Q2 includes a first The second gate g2, the third terminal p3, and the fourth terminal p4.
  • the first gate g1 is electrically connected to the scan line 130120 to receive the scan signal
  • the first terminal p1 is electrically connected to the data line 120130 to receive the data signal
  • the second terminal p2 is electrically connected to the The second gate g2
  • the third terminal p3 is used to receive the first signal
  • the fourth terminal p4 is electrically connected to the anode of the light-emitting unit 140
  • one end of the first capacitor C1 is electrically connected to the Two gates g2, and the other end of the first capacitor C1 is electrically connected to the third terminal p3;
  • the first terminal p1 is the source and the second terminal p2 is the drain, or the One end p1 is the drain and the second end p2 is the source
  • the third end p3 is the source and the fourth end p4 is the drain, or the third end p3 is the drain and the The fourth terminal p4 is the source.
  • the driving circuit 180 includes a first thin film transistor Q1, a second thin film transistor Q2, and a first capacitor C1.
  • the first thin film transistor Q1 may be an N-type thin film transistor or a P-type thin film transistor; correspondingly, the second thin film transistor Q2 may be an N-type thin film transistor or a P-type thin film transistor.
  • the first thin film transistor Q1 and the second thin film transistor Q2 are both N-type thin film transistors for illustration.
  • the source 184 and drain 185 of the N-type thin film transistor are turned on; when the gate 181 of the N-type thin film transistor receives a low-level signal, N The source electrode 184 and the drain electrode 185 of the type thin film transistor are disconnected.
  • the gate 181 of the P-type thin film transistor receives a low-level signal
  • the source 184 and drain 185 of the P-type thin film transistor are turned on; when the gate 181 of the P-type thin film transistor receives a high-level signal, the P The source electrode 184 and the drain electrode 185 of the type thin film transistor are disconnected.
  • FIG. 17 is a top view of a display panel provided by an eighth embodiment of this application;
  • FIG. 18 is a schematic diagram of a thin film transistor in the driving circuit.
  • the driving circuit 180 in the display panel 10 can be combined with the display panel 10 provided in any one of the first to sixth embodiments.
  • the driving circuit 180 is combined with the first
  • the display panel 10 provided in the sixth embodiment is taken as an example for illustration.
  • the display panel 10 further includes a driving circuit 180, a first signal line 150 and a second signal line 160.
  • the light emitting unit 140 further includes an anode 145, the first signal line 150 is used for transmitting a first signal, and the second signal line 160 is used for transmitting a second signal.
  • the driving circuit 180 When the driving circuit 180 is turned on, the first signal is applied to the anode 145 and the second signal is applied to the cathode 141 to drive the light-emitting unit 140 to emit light.
  • the driving circuit 180 includes a thin film transistor including a light shielding layer 187, a first insulating layer 188, a semiconductor layer 183, a second insulating layer 189, a gate electrode 181, a third insulating layer 190, a source electrode 184, and a drain electrode. 185, and a fourth insulating layer 191.
  • the light shielding layer 187 is provided on one side of the substrate 110, the first insulating layer 188 covers the light shielding layer 187, and the semiconductor layer 183 is provided on the first insulating layer 188 away from the light shielding layer 187.
  • the surface is provided corresponding to the light shielding layer 187, and the second insulating layer 189 covers the semiconductor layer 183.
  • the gate 181 is disposed on the surface of the second insulating layer 189 away from the semiconductor layer 183, the third insulating layer 190 covers the gate 181, the source 184, the drain 185, and the
  • the data lines 120 are all disposed on the surface of the third insulating layer 190 away from the gate 181, and the source electrode 184 and the drain electrode 185 respectively pass through the first insulating layer 190 opened on the third insulating layer 190.
  • the through hole and the second through hole are connected to opposite ends of the semiconductor layer 183, and the fourth insulating layer 191 covers the source electrode 184 and the drain electrode 185.
  • the shielding layer 193 is disposed on the surface of the fourth insulating layer 191 away from the substrate 110.
  • FIG. 19 is a schematic diagram of the electronic device provided by an embodiment of the application.
  • the electronic device 1 includes a display panel 10.
  • the electronic device 1 includes, but is not limited to, a smart phone, an Internet device (mobile internet device, MID), an e-book, a portable play station (Play Station Portable, PSP), or a personal digital assistant (Personal Digital Assistant, PDA).

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Abstract

一种显示面板(10)及电子装置(1)。显示面板(10)包括基板(110)、多条数据线(120)、发光单元(140)、及屏蔽层(193)，多条数据线(120)间隔设置在基板(110)的一侧，发光单元(140)包括阴极(141)，且阴极(141)与数据线(120)之间具有交叠区域，屏蔽层(193)位于阴极(141)与数据线(120)之间，且屏蔽层(193)至少部分位于交叠区域，屏蔽层(193)用于减小阴极(141)与数据线(120)之间的耦合。显示面板(10)在阴极(141)与数据线(120)之间的至少部分交叠区域内设置了屏蔽层(193)，屏蔽层(193)可减小阴极(141)与数据线(120)之间的耦合，从而消弱甚至消除阴极(141)与数据线(120)之间由于耦合作用而造成的显示面板(10)的串扰现象。因此，显示面板(10)具有较高的显示质量。

Description

显示面板及电子装置 技术领域
本申请涉及显示面板领域，特别是涉及一种显示面板及电子装置。
背景技术
随着技术的进步，具有显示功能的电子装置逐渐进入到人们的生活当中。电子装置通常包括显示面板，所述显示面板用于显示视频、图片、或者文字。然后，传统显示面板在显示视频、图片或者文字的时候，由于线路、器件间的耦合作用，常常会出现显示画面不佳的情况。
发明内容
本申请实施例公开了一种显示面板，所述显示面板包括基板、多条数据线、发光单元、及屏蔽层，所述多条数据线间隔设置在所述基板的一侧，所述发光单元包括阴极，且所述阴极与所述数据线之间具有交叠区域，所述屏蔽层位于所述阴极与所述数据线之间，且所述屏蔽层至少部分位于所述交叠区域，所述屏蔽层用于减小所述阴极与所述数据线之间的耦合。
本申请还提供了一种电子装置，所述电子装置包括显示面板。
相较于现有技术，本申请的显示面板在阴极与所述数据线之间的至少部分交叠区域内设置了屏蔽层，屏蔽层可减小阴极与数据线间的耦合，从而消弱甚至消除阴极与数据线之间由于耦合作用而造成的显示面板的串扰现象。因此，本申请的显示面板具有较高的显示质量。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施方式提供的显示面板的俯视图。
图2为图1中沿I-I线的剖视图。
图3为发光单元的结构示意图。
图4为本申请第二实施方式提供的显示面板的俯视图。
图5为图4中沿II-II线的剖视图。
图6为本申请第三实施方式提供的显示面板的俯视图。
图7为图6中沿III-III线的剖视图。
图8为本申请第四实施方式提供的显示面板的俯视图。
图9为图8中沿IV-IV线的剖视图。
图10为本申请第五实施方式提供的显示面板的俯视图。
图11为图10中沿V-V线的剖视图。
图12为本申请第六实施方式提供的显示面板的俯视图。
图13为图12中沿VI-VI线的剖视图。
图14为本申请第七实施方式提供的显示面板的俯视图。
图15为图14中驱动电路中的薄膜晶体管的结构示意图。
图16为本申请一实施方式中显示面板中驱动发光单元的驱动电路的电路架构示意图。
图17为本申请第八实施方式提供的显示面板的俯视图。
图18为中驱动电路中的薄膜晶体管的结构示意图。
图19为本申请实施例提供的电子装置的示意。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请一并参阅图1及图2，图1为本申请第一实施方式提供的显示面板的俯视图；图2为图1中沿I-I线的剖视图。可以理解地，由于在图1中的最顶层为发光单元140的阴极141，为了示意出阴极141下面的层结构，在图1中忽略了阴极141。所述显示面板10包括基板110、多条数据线120、发光单元140、及屏蔽层193。所述多条数据线120间隔设置在所述基板110的一侧。所述发光单元140包括阴极141，且所述阴极141与所述数据线120之间具有交叠区域。所述屏蔽层193位于所述阴极141与所述数据线120之间，且所述屏蔽层193至少部分位于所述交叠区域，所述屏蔽层193用于减小所述阴极141与所述数据线120之间的耦合。
相关技术中，所述阴极141与显示面板10中的数据线120之间具有交叠区域，因此，所述阴极141与所述数据线120会产生耦合电容，当耦合电容的耦合效应足够大时，在显示面板10中的像素电压瞬间变化时，会影响到显示面板10中的公共电极的电压，使得公共电极的电压偏离设定的电位且公共电压偏离设定电位的时间较长，且回复到原始电位的时间较长。通常情况下，公共电极的电压回复到原始电位的时间大于显示面板10中的一条扫描线中的信号写入的时间，因此，显示面板10在显示画面时，会产生严重错误的现象，此种现象称为串扰(crosstalk)。
通常而言，所述屏蔽层193的材质为金属，或者为导电的金属氧化物。本申请的显示面板10在阴极141与所述数据线120之间的至少部分交叠区域内设置了屏蔽层193，屏蔽 层193可减小阴极141与数据线120之间的耦合，从而消弱甚至消除阴极141与数据线120之间由于耦合作用而造成的显示面板10的串扰现象。因此，本申请的显示面板10具有较高的显示质量。
进一步地，在本实施方式中，所述发光单元140还包括阳极145，所述屏蔽层193与所述阳极145同层且间隔设置。
在本实施方式中，通过将屏蔽层193与阳极145同层且间隔设置，从而可以简化所述显示面板10的制备工序。
进一步地，在一实施方式中，所述屏蔽层193与所述阳极145间隔绝缘设置。相较于所述屏蔽层193与所述阳极145相连或者电连接而言，在本实施方式中，所述屏蔽层193与所述阳极145间隔绝缘设置，可避免所述屏蔽层193对所述发光单元140的发光造成影响。
请一并参阅图3，图3为发光单元的结构示意图。所述发光单元140包括层叠设置的阳极145、空穴注入及传输层144、发光层143、电子注入及传输层142、及阴极141。所述发光单元140可直接设置在基板110上或者通过其他层结构设置在所述基板110上，在图2中以所述发光单元140通过绝缘层193设置在所述基板110上为例进行示意。所述阳极145用于加载第一信号，并在所述第一信号的作用下产生空穴，所述空穴注入及传输层144用于将阳极145产生的空穴传输至所述发光层143。所述阴极141用于加载第二信号，并在所述第二信号的作用下产生电子，所述电子注入及传输层142用于将阴极141产生的电子传输至所述发光层143。所述电子及所述空穴在所述发光层143中复合以产生光线。
进一步地，请一并参阅图4及图5，图4为本申请第二实施方式提供的显示面板的俯视图；图5为图4中沿II-II线的剖视图。本实施方式提供的显示面板10与第一实施方式提供的显示面板10基本相同，不同之处在于，在本实施方式中，所述发光单元140还包括阳极145。所述显示面板10还包括第一信号线150及第二信号线160，所述第一信号线150用于传输第一信号，所述第二信号线160用于传输第二信号。当所述第一信号加载在所述阳极145且所述第二信号加载在所述阴极141时以驱动所述发光单元140发光，所述屏蔽层193与所述第一信号线150电连接。
具体地，所述第一信号线150也可以称为VDD线，所述第一信号线150的作用是传输第一信号至所述阳极145，所述第一信号线150和阳极145是两个部件，所述第一信号线150不能等同为阳极145。所述第二信号线160也可以成为Vinit线，所述第二信号线160的作用是传输第二信号至所述阴极141，所述第二信号线160和所述阴极141是两个部件，所述第二信号线160不能等同为阴极141。请一并参阅图3及其相关描述，所述第一信号加载在所述阳极145，所述阳极145在所述第一信号的作用下产生空穴，所述阳极145产生的空穴经过所述空穴注入及传输层144传输到所述发光层143。所述阴极141在所述第二信号的作用下产生电子，所述阴极141产生的电子经过所述电子注入及传输层142传输到所述发光层143。所述电子及所述空穴在所述发光层143中复合以发光。本申请的屏蔽层193与所述第一信号线150电连接，可消弱甚至避免所述数据线120对所述阴极141的 耦合，从而消弱甚至消除阴极141与数据线120之间由于耦合作用而造成的显示面板10的串扰现象。因此，本申请的显示面板10具有较高的显示质量。
进一步地，所述第一信号线150与所述屏蔽层193之间设置绝缘层194，所述绝缘层194上开设通孔，所述屏蔽层193通过填充通孔内的导电材料与所述第一信号线150电连接。
进一步地，所述屏蔽层193包括第一屏蔽部193a、第二屏蔽部193b、以及连接在所述第一屏蔽部193a及所述第二屏蔽部193b之间的连接部193c。所述第一屏蔽部193a在所述基板110上的投影至少部分覆盖所述数据线120在所述基板110上的投影，所述第二屏蔽部193b在所述基板110上的投影至少部分覆盖所述第一信号线150在所述基板110上的投影，所述第二屏蔽部193b与所述第一信号线150电连接。具体地，当所述第一信号线150与所述屏蔽层193之间设置有绝缘层194时，所述绝缘层194对应所述第二屏蔽部193b与所述第一信号线150处设置有通孔，所述第二屏蔽部193b通过填充在所述通孔内的导电材料与所述第一信号线150电连接。
在本实施方式中，所述显示面板10包括多条间隔设置的数据线120，所述显示面板10还包括多条间隔设置的扫描线130，相邻的两条数据线120与相邻的两条扫描线130之间形成像素区10c。所述像素区10c用于设置所述发光单元140。所述第一信号线150设置在所述数据线120与所述发光单元140之间，所述第一信号线150的延伸方向与所述数据线120的延伸方向相同或大致相同。所述第二信号线160设置在所述扫描线130与所述发光单元140之间，所述第二信号线160的延伸方向与所述扫描线130的延伸方向相同或大致相同。
请一并参阅图6及图7，图6为本申请第三实施方式提供的显示面板的俯视图；图7为图6中沿III-III线的剖视图。本实施方式提供的显示面板10与第二实施方式提供的显示面板10基本相同，不同之处在于，在本实施方式中，所述显示面板10还包括第一信号线150及第二信号线160。所述第一信号线150用于传输第一信号，所述第二信号线160用于传输第二信号。当所述第一信号加载在所述阳极145且所述第二信号加载在所述阴极141时以驱动所述发光单元140发光，所述屏蔽层193与所述第二信号线160电连接。
具体地，所述第一信号线150也可以称为VDD线，所述第二信号线160也可以称为Vinit线。请一并参阅图3及其相关描述，所述第一信号加载在所述阳极145，所述阳极145在所述第一信号的作用下产生空穴，所述阳极145产生的空穴经过所述空穴注入及传输层144传输到所述发光层143。所述阴极141在所述第二信号的作用下产生电子，所述阴极141产生的电子经过所述电子注入及传输层142传输到所述发光层143。所述电子及所述空穴在所述发光层143中复合以发光。本申请的屏蔽层193与所述第二信号线160电连接，可消弱甚至避免所述数据线120对所述阴极141的耦合，从而消弱甚至消除阴极141与数据线120之间由于耦合作用而造成的显示面板10的串扰现象。因此，本申请的显示面板10具有较高的显示质量。
进一步地，所述第二信号线160与所述屏蔽层193之间设置有绝缘层194。所述绝缘 层194上开设有通孔，所述屏蔽层193通过填充在所述通孔内的导电材料与所述第二信号线160电连接。
进一步地，所述数据线120与所述第二信号线160之间设置有绝缘层194，所述数据线120与所述第二信号线160通过所述绝缘层194交叉绝缘设置。所述绝缘层194用于将所述数据线120与所述第二信号进行绝缘隔离。
请一并参阅图8及图9，图8为本申请第四实施方式提供的显示面板的俯视图；图9为图8中沿IV-IV线的剖视图。本实施方式提供的显示面板10与第三实施方式提供的显示面板10基本相同，不同之处在于，在本实施方式中，所述数据线120与所述第二信号线160交叉处设置绝缘层194，所述数据线120的其余部分与所述第二信号线160的其余部分位于同一层。本实施方式中通过在所述数据线120与所述第二信号线160的交叉处设置绝缘层194，实现将所述数据线120与所述第二信号线160的绝缘隔离即可，所述数据线120的其余部分与所述第二信号线160的其余部分位于同一层，有利于所述显示面板10的薄型化。
请一并参阅图10及图11，图10为本申请第五实施方式提供的显示面板的俯视图；图11为图10中沿V-V线的剖视图。本实施方式提供的显示面板10与第一实施方式提供的显示面板10基本相同，不同之处在于，在本实施方式中，所述显示面板10还包括公共电极线170。所述公共电极线170加载电源电压，所述公共电极线170与数据线120交叉绝缘设置，所述屏蔽层193与所述公共电极线170电连接。
本实施方式通过单独设置公共电极线170为所述屏蔽层193提供电源电压，可消弱甚至避免所述数据线120对所述阴极141的耦合，从而消弱甚至消除阴极141与数据线120之间由于耦合作用而造成的显示面板10的串扰现象。因此，本申请的显示面板10具有较高的显示质量。
进一步地，在本实施方式中，所述显示面板10包括多条间隔设置的数据线120，所述显示面板10还包括多条间隔设置的扫描线130，相邻的两条数据线120与相邻的两条扫描线130之间形成像素区10c。所述像素区10c用于设置所述发光单元140。所述显示面板10还包括第一信号线150及第二信号线160。所述第一信号线150用于传输第一信号，所述第二信号线160用于传输第二信号，当所述第一信号加载在所述阳极145且所述第二信号加载在所述阴极141时以驱动所述发光单元140发光。所述第一信号线150设置在所述数据线120与所述发光单元140之间，所述第一信号线150的延伸方向与所述数据线120的延伸方向相同或者大致相同。所述第二信号线160设置在所述扫描线130与所述发光单元140之间，所述第二信号线160的延伸方向与所述扫描线130的延伸方向相同或者大致相同。所述公共电极线170与所述第一信号线150及所述数据线120分别交叉绝缘设置，且所述公共电极线170分别与所述第二信号线160及所述扫描线130间隔设置。所述公共电极线170的延伸方向与所述数据线120的延伸方向相同或者大致相同。在本实施方式中，所述公共电极线170设置在第二信号线160背离所述扫描线130的一侧。可以理解地，在其他实施方式中，所述公共电极线170与所述第二信号线160及所述扫描线130之间的位 置关系只需要满足所述公共电极线170、所述第二信号线160及所述扫描线130间隔绝缘设置即可。可选地，所述公共电极线170与所述第二信号线160同层设置。当所述公共电极线170与所述第二信号线160同层设置时，所述公共电极线170和和所述第二信号线160同一工序制备而成，可节约制备工序。
进一步地，所述公共电极与所述第二信号线160间隔绝缘设置。相较于所述公共电极与所述第二信号线160电连接而言，在本实施方式中，所述公共电极与所述第二信号线160间隔绝缘设置，从而使得所述屏蔽层193与所述第二信号线160间隔绝缘设置，可避免所述屏蔽层193对所述发光单元140的发光造成的影响。
进一步地，所述公共电极线170与所述数据线120的交叉处设置绝缘层194，所述数据线120的其余部分与所述公共电极线170的其余部分位于同一层。或者，所述公共电极线170与所述数据线120之间设置有绝缘层194，所述公共电极线170与所述数据线120通过所述绝缘层194交叉绝缘设置。在本实施方式中的示意图中，以所述公共电极线170与所述数据线120之间设置有绝缘层194为例进行示意。
请一并参阅图12及图13，图12为本申请第六实施方式提供的显示面板的俯视图；图13为图12中沿VI-VI线的剖视图。本实施方式提供的显示面板10与第一实施方式提供的显示面板10的结构基本相同，不同之处在于，在本实施方式中，所述显示面板10包括显示区10a及设置在所述显示区10a外围的非显示区10b。所述显示面板10还包括电源线195，所述电源线195加载电源电压，所述电源线195对应所述非显示区10b设置，所述屏蔽层193电连接所述电源线195。
在本实施方式中，将所述屏蔽层193与位于非显示区10b的电源线195电连接，从而避免显示区10a增加电源线195对显示区10a中的其他电路的影响和干扰。
进一步地，所述电源线195与所述屏蔽层193之间设置有绝缘层194，所述绝缘层194开设有通孔，所述电源线195通过填充在所述通孔内的导电材料与所述屏蔽层193电连接。或者，所述电源线195与所述屏蔽层193位于同一层，所述电源线195与所述屏蔽层193直接电连接。在本实施方式中，以所述电源线195通过填充在所述通孔内的导电材料与所述屏蔽层193电连接为例进行示意。
请一并参阅图14及图15，图14为本申请第七实施方式提供的显示面板的俯视图；图15为图14中驱动电路中的薄膜晶体管的结构示意图。本实施方式中显示面板10中的驱动电路180可结合到第一至第六实施方式中任意一种实施方式提供的显示面板10中，在本实施方式中，以所述驱动电路180结合到第六实施方式中提供的显示面板10为例进行示意。所述显示面板10还包括驱动电路180、第一信号线150、及第二信号线160。所述发光单元140还包括阳极145，所述第一信号线150用于传输第一信号，所述第二信号线160用于传输第二信号。当所述驱动电路180导通时，所述第一信号被加载在所述阳极145且所述第二信号被加载在所述阴极141以驱动所述发光单元140发光。所述驱动电路180包括薄膜晶体管Q，所述薄膜晶体管Q包括栅极181、栅极绝缘层182、半导体层183、源极184、漏极185、及平坦层186。所述栅极181设置在所述基板110的一侧，所述栅极绝缘层182 覆盖所述栅极181，所述半导体层183位于所述栅极绝缘层182背离所述栅极181的表面，所述源极184与所述漏极185分别与所述半导体层183相连，且所述源极184与所述漏极185间隔设置。所述平坦层186覆盖所述源极184及所述漏极185，所述平坦层186对应所述漏极185开设有贯孔，所述数据线120设置在所述平坦层186背离所述基板110的一侧，所述数据线120上覆盖有数据线绝缘层196，所述屏蔽层193设置在所述数据线绝缘层196背离所述数据线120的表面。
请一并参阅图16，图16为本申请一实施方式中显示面板中驱动发光单元的驱动电路的电路架构示意图。所述显示面板10包括间隔设置的多个扫描线130、以及多个间隔设置的数据线120，所述数据线120与所述扫描线130交叉绝缘设置。所述扫描线130用于传输扫描信号，所述数据线120用于传输数据信号，相邻的两个数据线120及相邻的两个扫描线130定义一个像素区10c，所述像素区10c用于设置所述发光单元140，所述像素区10c还设置第一薄膜晶体管Q1及第二薄膜晶体管Q2。当所述第一薄膜晶体管Q1在扫描信号的控制下导通时，且所述第二薄膜晶体管Q2在所述数据信号的控制下导通时，所述第一信号被加载至所述发光单元140的阳极，所述发光单元140的阴极用于接收所述第二信号。本实施方式的示意图中以第一信号加载在所述发光单元140的阳极，且所述第二信号加载在所述发光单元140的阴极为例进行示意，此时，所述第一信号为高电平，所述第二信号为低电平。
进一步地，所述像素区10c还设置有第一电容C1，所述第一薄膜晶体管Q1包括第一栅极g1、第一端p1、及第二端p2，所述第二薄膜晶体管Q2包括第二栅极g2、第三端p3、及第四端p4。所述第一栅极g1电连接所述扫描线130120以接收所述扫描信号，所述第一端p1电连接至所述数据线120130以接收数据信号，所述第二端p2电连接所述第二栅极g2，所述第三端p3用于接收所述第一信号，所述第四端p4电连接所述发光单元140的阳极，所述第一电容C1的一端电连接所述第二栅极g2，所述第一电容C1的另一端电连接所述第三端p3；其中，所述第一端p1为源极且所述第二端p2为漏极，或者，所述第一端p1为漏极且所述第二端p2为源极；所述第三端p3为源极且所述第四端p4为漏极，或者，所述第三端p3为漏极且所述第四端p4为源极。
在本实施方式中，所述驱动电路180包括第一薄膜晶体管Q1、第二薄膜晶体管Q2、及第一电容C1。所述第一薄膜晶体管Q1可以为N型薄膜晶体管，也可以为P型薄膜晶体管；相应地，所述第二薄膜晶体管Q2可以为N型薄膜晶体管，也可以为P型薄膜晶体管。在图12中以第一薄膜晶体管Q1及第二薄膜晶体管Q2均为N型薄膜晶体管为例进行示意。当N型薄膜晶体管的栅极181接收高电平信号的时候，N型薄膜晶体管的源极184和漏极185导通；当N型薄膜晶体管的栅极181接收低电平信号的时候，N型薄膜晶体管的源极184和漏极185断开。当P型薄膜晶体管的栅极181接收低电平信号的时候，P型薄膜晶体管的源极184和漏极185导通；当P型薄膜晶体管的栅极181接收高电平信号的时候，P型薄膜晶体管的源极184和漏极185断开。
可以理解地，上述驱动电路180仅仅为驱动电路180的一种方式，所述驱动电路180 也可以为其他结构。
请一并参阅图17及图18，图17为本申请第八实施方式提供的显示面板的俯视图；图18为中驱动电路中的薄膜晶体管的结构示意图。本实施方式中显示面板10中的驱动电路180可结合到第一至第六实施方式中任意一种实施方式提供的显示面板10中，在本实施方式中，以所述驱动电路180结合到第六实施方式中提供的显示面板10为例进行示意。所述显示面板10还包括驱动电路180、第一信号线150、及第二信号线160。所述发光单元140还包括阳极145，所述第一信号线150用于传输第一信号，所述第二信号线160用于传输第二信号。当所述驱动电路180导通时，所述第一信号被加载在所述阳极145且所述第二信号被加载在所述阴极141以驱动所述发光单元140发光。所述驱动电路180包括薄膜晶体管，所述薄膜晶体管包括遮光层187、第一绝缘层188、半导体层183、第二绝缘层189、栅极181、第三绝缘层190、源极184、漏极185、及第四绝缘层191。所述遮光层187设置在所述基板110的一侧，所述第一绝缘层188覆盖所述遮光层187，所述半导体层183设置在所述第一绝缘层188背离所述遮光层187的表面且对应所述遮光层187设置，所述第二绝缘层189覆盖所述半导体层183。所述栅极181设置在所述第二绝缘层189背离所述半导体层183的表面，所述第三绝缘层190覆盖所述栅极181，所述源极184、所述漏极185及所述数据线120均设置在所述第三绝缘层190背离所述栅极181的表面，且所述源极184及所述漏极185分别通过开设在所述第三绝缘层190上的第一贯孔及所述第二贯孔连接于所述半导体层183相对的两端，所述第四绝缘层191覆盖所述源极184及所述漏极185。所述屏蔽层193设置在所述第四绝缘层191背离所述基板110的表面。
本实施方式中的驱动电路180可参照图16及其相关描述中所述的驱动电路180，在此不再赘述。
进一步地，本申请还提供了一种电子装置1，请一并参阅图19，图19为本申请实施例提供的电子装置的示意。所述电子装置1包括显示面板10。所述显示面板10请参阅前面描述，在此不再赘述。所述电子装置1包括但不仅限于智能手机、互联网设备(mobile internet device，MID)、电子书、便携式播放站(Play Station Portable,PSP)或个人数字助理(Personal DigitalAssistant，PDA)。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其特征在于，所述显示面板包括基板、多条数据线、发光单元、及屏蔽层，所述多条数据线间隔设置在所述基板的一侧，所述发光单元包括阴极，且所述阴极与所述数据线之间具有交叠区域，所述屏蔽层位于所述阴极与所述数据线之间，且所述屏蔽层至少部分位于所述交叠区域，所述屏蔽层用于减小所述阴极与所述数据线之间的耦合。
  2. 如权利要求1所述的显示面板，其特征在于，所述发光单元还包括阳极，所述屏蔽层与所述阳极同层且间隔设置。
  3. 如权利要求1所述的显示面板，其特征在于，所述发光单元还包括阳极，所述显示面板还包括第一信号线及第二信号线，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述第一信号加载在所述阳极且所述第二信号加载在所述阴极时以驱动所述发光单元发光，所述屏蔽层与所述第一信号线电连接。
  4. 如权利要求3所述的显示面板，其特征在于，所述第一信号线与所述屏蔽层之间设置绝缘层，所述绝缘层上开设通孔，所述屏蔽层通过填充通孔内的导电材料与所述第一信号线电连接。
  5. 如权利要求3所述的显示面板，其特征在于，所述屏蔽层包括第一屏蔽部、第二屏蔽部、以及连接在所述第一屏蔽部及所述第二屏蔽部之间的连接部，所述第一屏蔽部在所述基板上的投影至少部分覆盖所述数据线在所述基板上的投影，所述第二屏蔽部在所述基板上的投影至少部分覆盖所述第一信号线在所述基板上的投影，所述第二屏蔽部与所述第一信号线电连接。
  6. 如权利要求1所述的显示面板，其特征在于，所述显示面板还包括第一信号线及第二信号线，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述第一信号加载在所述阳极且所述第二信号加载在所述阴极时以驱动所述发光单元发光，所述屏蔽层与所述第二信号线电连接。
  7. 如权利要求6所述的显示面板，其特征在于，所述第二信号线与所述屏蔽层之间设置有绝缘层，所述绝缘层上开设有通孔，所述屏蔽层通过填充在所述通孔内的导电材料与所述第二信号线电连接。
  8. 如权利要求7所述的显示面板，其特征在于，所述数据线与所述第二信号线之间设 置有绝缘层，所述数据线与所述第二信号线通过所述绝缘层交叉绝缘设置。
  9. 如权利要求7所述的显示面板，所述数据线与所述第二信号线交叉处设置绝缘层，所述数据线的其余部分与所述第二信号线的其余部分位于同一层。
  10. 如权利要求1所述的显示面板，其特征在于，所述显示面板还包括公共电极线，所述公共电极线加载电源电压，所述公共电极线与数据线交叉绝缘设置，所述屏蔽层与所述公共电极线电连接。
  11. 如权利要求10所述的显示面板，其特征在于，所述公共电极线与所述数据线的交叉处设置绝缘层，所述数据线的其余部分与所述公共电极线的其余部分位于同一层。
  12. 如权利要求10所述的显示面板，其特征在于，所述公共电极线与所述数据线之间设置有绝缘层，所述公共电极线与所述数据线通过所述绝缘层交叉绝缘设置。
  13. 如权利要求12所述的显示面板，其特征在于，所述发光单元还包括阳极，所述显示面板还包括第一信号线及第二信号线，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述第一信号加载在所述阳极且所述第二信号加载在所述阴极时以驱动所述发光单元发光，所述公共电极线与所述第二信号线间隔设置。
  14. 如权利要求13所述的显示面板，其特征在于，所述公共电极线与所述第二信号线同层设置。
  15. 如权利要求1所述的显示面板，其特征在于，所述显示面板包括显示区及设置在所述显示区外围的非显示区，所述显示面板还包括电源线，所述电源线加载电源电压，所述电源线对应所述非显示区设置，所述屏蔽层电连接所述电源线。
  16. 如权利要求15所述的显示面板，其特征在于，所述电源线与所述屏蔽层之间设置有绝缘层，所述绝缘层开设有通孔，所述电源线通过填充在所述通孔内的导电材料与所述屏蔽层电连接。
  17. 如权利要求15所述的显示面板，其特征在于，所述电源线与所述屏蔽层位于同一层，所述电源线与所述屏蔽层直接电连接。
  18. 如权利要求1-17任意一项所述的显示面板，其特征在于，所述显示面板还包括驱动电路、第一信号线、及第二信号线，所述发光单元还包括阳极，所述第一信号线用于传输 第一信号，所述第二信号线用于传输第二信号，当所述驱动电路导通时，所述第一信号被加载在所述阳极且所述第二信号被加载在所述阴极以驱动所述发光单元发光，所述驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极、栅极绝缘层、半导体层、源极、漏极、及平坦层，所述栅极设置在所述基板的一侧，所述栅极绝缘层覆盖所述栅极，所述半导体层位于所述栅极绝缘层背离所述栅极的表面，所述源极与所述漏极分别与所述半导体层相连，且所述源极与所述漏极间隔设置，所述平坦层覆盖所述源极及所述漏极，所述平坦层对应所述漏极开设有贯孔，所述数据线设置在所述平坦层背离所述基板的一侧，所述数据线上覆盖有数据线绝缘层，所述屏蔽层设置在所述数据线绝缘层背离所述数据线的表面。
  19. 如权利要求1-17任意一项所述的显示面板，其特征在于，所述显示面板还包括驱动电路、第一信号线、及第二信号线，所述发光单元还包括阳极，所述第一信号线用于传输第一信号，所述第二信号线用于传输第二信号，当所述驱动电路导通时，所述第一信号被加载在所述阳极且所述第二信号被加载在所述阴极以驱动所述发光单元发光，所述驱动电路包括薄膜晶体管，所述薄膜晶体管包括遮光层、第一绝缘层、半导体层、第二绝缘层、栅极、第三绝缘层、源极、漏极、及第四绝缘层，所述遮光层设置在所述基板的一侧，所述第一绝缘层覆盖所述遮光层，所述半导体层设置在所述第一绝缘层背离所述遮光层的表面且对应所述遮光层设置，所述第二绝缘层覆盖所述半导体层，所述栅极设置在所述第二绝缘层背离所述半导体层的表面，所述第三绝缘层覆盖所述栅极，所述源极、所述漏极及所述数据线均设置在所述第三绝缘层背离所述栅极的表面，且所述源极及所述漏极分别通过开设在所述第三绝缘层上的第一贯孔及所述第二贯孔连接于所述半导体层相对的两端，所述第四绝缘层覆盖所述源极及所述漏极，所述屏蔽层设置在所述第四绝缘层背离所述基板的表面。
  20. 一种电子装置，其特征在于，所述电子装置包括如权利要求1-19任意一项所述的显示面板。
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