WO2021213046A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2021213046A1
WO2021213046A1 PCT/CN2021/079922 CN2021079922W WO2021213046A1 WO 2021213046 A1 WO2021213046 A1 WO 2021213046A1 CN 2021079922 W CN2021079922 W CN 2021079922W WO 2021213046 A1 WO2021213046 A1 WO 2021213046A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
dam
layer
projection
display panel
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Application number
PCT/CN2021/079922
Other languages
English (en)
French (fr)
Inventor
郭晓亮
张跳梅
董中飞
胡岩
袁洪光
孙加冕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/638,845 priority Critical patent/US20220407032A1/en
Publication of WO2021213046A1 publication Critical patent/WO2021213046A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8428—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, in particular, to a display panel and a manufacturing method thereof, and also to a display device.
  • OLED organic light-emitting display panels
  • OLED organic light-emitting diode
  • OLED organic light-emitting diode
  • the purpose of the present disclosure is to provide a display panel, a manufacturing method, and a display device to solve one or more problems in the prior art.
  • a display panel including:
  • the base substrate includes a display area and a peripheral area surrounding the display area;
  • At least one encapsulation dam located on a side of the insulating layer away from the base substrate, the encapsulation dam is located in a peripheral area of the base substrate and arranged around the display area;
  • At least one groove is formed in the insulating layer, and the groove is arranged around the display area; wherein, the projection of the at least one groove on the base substrate is located on the packaging dam on the base substrate Within the projection.
  • the number of the encapsulation dams is two, and the two encapsulation dams surround the display area and are arranged at intervals; the projection of the groove on the base substrate is located At least one of the packaging dams is in the projection of the base substrate.
  • the projection of the groove on the base substrate is located within the projection of the packaging dam farthest from the display area on the base substrate.
  • the display panel further includes: a crack detection line located in the peripheral area of the base substrate and arranged around the display area, and the crack detection line is located on the substrate
  • the projection of the base substrate is located between the projections of the two adjacent packaging dams on the base substrate.
  • it further includes: a crack detection line located in the peripheral area of the substrate and arranged around the display area, and the projection of the crack detection line on the base substrate is located at the base substrate.
  • the packaging dam is in the projection of the base substrate.
  • the insulating layer covers the crack detection line; in the projection coverage area of the packaging dam, the crack detection line is located near or far from the display groove. Side of the area.
  • the crack detection line is located on a side of the insulating layer away from the base substrate, and the crack detection line is located between two adjacent grooves.
  • the number of the crack detection lines is multiple, and the projection of the crack detection lines on the base substrate is located on one of the package dams on the base substrate. Or distributed in the projection of the multiple packaging dams on the base substrate.
  • the insulating layer has a single-layer structure, and the groove is formed in the single-layer structure; or, the insulating layer has a multilayer structure, and the groove penetrates through At least one layer and the bottom surface of the groove is located in the layer closest to the base substrate.
  • the display panel further includes a pixel defining layer formed in the display area;
  • the encapsulation dam includes a first barrier layer, the first barrier layer and the pixel defining layer The layers are arranged in the same layer with the same material.
  • the display panel further includes a flat layer formed in the display area; the packaging dam further includes a side of the first barrier layer facing the base substrate The second barrier layer, the second barrier layer and the flat layer are arranged in the same layer with the same material.
  • the encapsulation dam includes a first encapsulation dam and a second encapsulation dam, the second encapsulation dam surrounds a side of the first encapsulation dam away from the display area,
  • the first encapsulation dam includes a first barrier layer, and the second encapsulation dam includes a first barrier layer and a second barrier layer.
  • a display device including the display panel described in any one of the above.
  • a method for manufacturing a display panel including:
  • At least one packaging dam is formed on the side of the insulating layer away from the base substrate, and the packaging dam is located in the peripheral area of the base substrate and surrounds the display area;
  • At least one groove is formed on the insulating layer, and the grooves are arranged around the display area and arranged at intervals; wherein, the projection of at least one groove on the base substrate is located in the encapsulation dam. In the projection of the base substrate.
  • the method further includes: forming a crack detection line in a peripheral area of the base substrate and surrounding the display area, and a projection of the crack detection line on the base substrate It is located between the projections of two adjacent packaging dams on the base substrate, or the projection of the crack detection line on the base substrate is located within the projection of the packaging dam on the base substrate.
  • the insulating layer in the peripheral area of the display panel of the present disclosure has a groove structure. Once a crack appears on the edge of the panel, the crack prevention part can change the crack extension direction and increase the crack extension path to slow down or resist the extension of the crack in the direction of the display area. It can prevent damage to the structure of the display area and improve the packaging effect.
  • an encapsulation dam is arranged above the insulating layer, and the groove is located below the encapsulation dam, which can reduce the width of the peripheral area, thereby increasing the screen-to-body ratio.
  • FIG. 1 is a schematic top view of a display panel of this embodiment
  • FIG. 2 is a schematic cross-sectional view of the display panel of this embodiment
  • FIG. 3 is another schematic cross-sectional view of the display panel of this embodiment.
  • Fig. 4 is a first partial enlarged perspective view of part B of the dashed-line frame in the peripheral area of Fig. 1;
  • Fig. 5 is a second partial enlarged perspective view of part B of the dashed-line frame in the peripheral area in Fig. 1;
  • Fig. 6 is a schematic cross-sectional view of Fig. 5;
  • Fig. 7 is a third partial enlarged perspective view of part B of the dashed-line frame in the peripheral area in Fig. 1;
  • Fig. 8 is a schematic cross-sectional view of Fig. 7;
  • Fig. 9 is a fourth partial enlarged perspective view of part B of the dashed-line frame in the peripheral area in Fig. 1;
  • Fig. 10 is a schematic cross-sectional view of Fig. 9;
  • Fig. 11 is a fifth partial enlarged perspective view of part B of the dashed-line frame in the peripheral area in Fig. 1;
  • Fig. 12 is a schematic cross-sectional view of Fig. 11;
  • Fig. 13 is a sixth partial enlarged perspective view of part B of the dashed-line frame in the peripheral area in Fig. 1;
  • Figure 14 is a schematic cross-sectional view of Figure 13;
  • FIG. 15 is a production flow chart of the display panel of this embodiment.
  • FIG. 1 is a schematic top view of the display panel of this embodiment
  • AA represents the display area
  • the outside of the AA area is the peripheral area
  • Figure 2 is a partial structural diagram of a cross-sectional view of the display panel of this embodiment.
  • the vertical dashed line is used to distinguish the display area from the peripheral area.
  • the right is the display area
  • the left is the peripheral area.
  • the main structure related to the present disclosure is shown.
  • 3 is a partially enlarged perspective view of part B of the dashed-line frame in the peripheral area of FIG. 1, corresponding to the cross-sectional structure of FIG. 2.
  • the display panel includes a base substrate 10, and the base substrate 10 includes a display area and a peripheral area surrounding the display area.
  • the peripheral area is provided with an insulating layer 9, and the side of the insulating layer 9 away from the base substrate 10 is provided with an encapsulation dam 110, and the extension direction of the encapsulation dam 110 is the same as the edge direction of the display area.
  • At least one groove 131 is also formed on the insulating layer 9.
  • the groove 131 is provided in the peripheral area of the base substrate 10 and surrounds the display area, and the groove 131 is located between the packaging dam 110 and the base substrate 10; wherein, at least The projection of a groove 131 on the base substrate 10 is located within the projection of the package dam 110 on the base substrate 10.
  • the packaging dam 110 is a ring-shaped protrusion arranged around the display area, which can prevent the organic packaging material from overflowing and affecting the pads provided in the peripheral area during film packaging.
  • a groove 131 is provided on the insulating layer 9. Once a crack appears on the edge of the panel, the groove 131 can change the crack extension direction and increase the crack extension path to slow down or prevent the crack from extending in the direction of the display area and prevent display The zone structure is damaged, and the packaging effect is improved. Disposing the groove 131 under the packaging dam 110 can reduce the occupied area and the width of the peripheral area, thereby increasing the screen-to-body ratio.
  • the display area of the base substrate 10 is used to set up structures such as organic light-emitting devices, thin film transistors, and pixel capacitors, and the non-display area is used to set up drive circuits, packaging structures, and the like.
  • the base substrate 10 may be any transparent substrate, such as a glass substrate, a quartz substrate, a plastic substrate, or other transparent hard or flexible substrates, and it may be a single-layer or multi-layer structure.
  • the base substrate 10 has a multilayer structure, which includes a first PI (polyimide) layer 101, a first protective layer 102, and a second PI ( The polyimide) layer 103, the second protective layer 104, and the two protective layers are used to protect the PI layer and prevent damage to the PI layer by subsequent processes.
  • the second protective layer 104 is also covered with a buffer layer 105, which can block water and oxygen and block alkaline ions.
  • the thin film transistor may be a top gate or a bottom gate structure.
  • the top gate structure as an example, referring to FIG. 2, it at least includes an active layer 91, a gate insulating layer 92, a gate layer 93, a dielectric layer 94, a source drain layer 95, and a flat layer 96.
  • the active layer 91 is provided on the base substrate 10, the gate insulating layer 92 covers the active layer 91, the gate layer 93 is provided on the surface of the gate insulating layer 92 away from the base substrate 10, and the dielectric layer 94 covers the gate insulating layer 92 and The gate layer 93; the source-drain layer 95 is provided on the surface of the insulating layer away from the base substrate 10, and the source-drain layer 95 includes source and drain electrodes connected to both ends of the active layer 91; the flat layer 96 covers the source-drain layer 95 and Dielectric layer 94.
  • the thin film transistor can be further optimized, such as adding a second gate, and other structures, but the basic film layer is as described above, and the present disclosure does not specifically limit the specific structure of the thin film transistor.
  • the organic light emitting device includes an anode layer 80, a pixel defining layer 81 provided on the anode layer 80 and having an opening capable of exposing part of the anode layer, a light emitting layer 82 provided in the opening and covering the anode layer 80, and The cathode layer 83 covering the light emitting layer 82 and the pixel defining layer 81.
  • the anode layer 80 of the organic light emitting device and the drain electrode of the thin film transistor are electrically connected through a via hole, so that the organic light emitting device can emit light or be turned off under the control of the thin film transistor.
  • the organic layer may include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer.
  • the display panel may further include an encapsulation film layer for preventing external moisture or oxygen from penetrating into the organic light emitting device that is susceptible to external moisture or oxygen.
  • the encapsulation film layer may include two inorganic encapsulation layers and an organic encapsulation layer arranged between the two inorganic encapsulation layers, that is, above the organic light-emitting device, the first inorganic encapsulation layer 151 and the organic encapsulation layer 151 and the organic encapsulation layer are arranged in order from bottom to top.
  • Layer 152, a second inorganic encapsulation layer 153 may be included in order from bottom to top.
  • the two inorganic encapsulation layers function to isolate water and oxygen intrusion, and the organic encapsulation layer serves as a buffer to reduce the stress between the various layers caused by the bending of the display panel and enhance the planarization characteristics.
  • the organic encapsulation layer 152 covers at least the display area and is blocked by the encapsulation dam 11, and the two inorganic encapsulation layers cover the display area and part of the non-display area.
  • the encapsulation dam 11 on the right side in FIG. 2 is taken as an example for description.
  • the encapsulation dam 110 includes a first barrier layer 111, and the first barrier layer 111 and the pixel defining layer 81 of the display area may be provided with the same material and the same layer.
  • the same-layer arrangement refers to formation through the same patterning process, and the same filling line is used for filling in the following figures.
  • the pixel defining layer 81 in the display area can be formed at the same time as the pixel defining layer 81 in the peripheral area, and then the pixel defining layer 81 in the peripheral area can be patterned through the same patterning process to form the pixel defining layer 81 in the peripheral area as shown in FIG. 2
  • the first barrier layer 111 in the convex structure is shown in FIG.
  • the encapsulation dam 110 may also include a second barrier layer 112, and the second barrier layer 112 is provided on the side of the first barrier layer 111 facing the base substrate 10, namely The second barrier layer 112 is disposed under the first barrier layer 111, and the two barrier layers increase the height of the entire encapsulation dam, so that the anti-overflow effect is better.
  • the second barrier layer 112 can be arranged in the same layer with the same material as the flat layer in the display area.
  • the flat layer 96 in the peripheral area can be formed at the same time as the flat layer 96 in the display area is formed, and then the flat layer 96 in the peripheral area is patterned through the same patterning process to form a convex surface as shown in FIG. 2
  • the second barrier layer 112 of the structure can be formed at the same time as the flat layer 96 in the display area is formed, and then the flat layer 96 in the peripheral area is patterned through the same patterning process to form a convex surface as shown in FIG. 2
  • the second barrier layer 112 of the structure can be formed at the same time as the flat layer 96 in the display area is formed, and then the flat layer 96 in the peripheral area is patterned through the same patterning process to form a convex surface as shown in FIG. 2
  • the second barrier layer 112 of the structure can be formed at the same time as the flat layer 96 in the display area is formed, and then the flat layer 96 in the peripheral area is patterned through the same patterning process to form a convex surface as shown
  • the insulating layer 9 has a single-layer structure.
  • the insulating layer and the dielectric layer 94 in the display area can be arranged in the same layer with the same material.
  • the dielectric layer 94 in the display area can be formed at the same time as the insulating layer 9 in the peripheral area, and then the dielectric layer 94 in the peripheral area can be patterned through the same patterning process to remove the target Part of the dielectric layer 94 in the region forms a groove 131 in the target region, and a strip structure formed of insulating material is formed between adjacent grooves 131.
  • the insulating layer 9 has a multilayer structure, that is, in addition to the dielectric layer 94, it can also include more film layers.
  • the groove penetrates the upper film layer and the bottom surface of the groove is located closest to the base substrate.
  • the insulating layer 9 includes two layers, the lower layer is a gate insulating layer 92, and the upper layer is a dielectric layer 94. The groove penetrates through the dielectric layer 94 and the bottom surface of the groove is located in the gate insulating layer 92.
  • the groove formation process of this structure can be specifically as follows: while forming the dielectric layer and the gate insulating layer in the display area, the dielectric layer and the gate insulating layer are also formed in the peripheral area, and then the corresponding patterning process is performed on the peripheral area. The dielectric layer and the gate insulating layer are patterned, and the grooves 131 can also be formed.
  • the insulating layer may further include other insulating material layers, and the gate insulating layer 92 may further include multiple gate insulating layers, which will not be repeated here.
  • the groove 131 is located under the package dam 110, when the package dam 110 is formed, the material of the package dam 110 will be automatically filled in the groove 131. This structure will not affect the function of the groove 131 to prevent cracks from extending. On the contrary, it will increase the barriers to crack extension and effectively prevent crack extension.
  • the cross-sectional shapes of the package dam 110 and the groove 131 shown in the figure are only examples.
  • the cross-sectional shapes of the two can be rectangular, arc, trapezoidal or any other structure. Forming protrusions on the bottom can achieve a blocking effect, and as long as there is a gap between the grooves 131, the cracks can be blocked from extending.
  • the number of grooves 131 can be one or more. If there are multiple grooves 131, the grooves 131 are arranged at intervals. The specific number of grooves 131 can be set according to requirements, and this application is not specifically limited. .
  • the number of encapsulation dams 110 may be multiple, and each encapsulation dam 110 is an annular protrusion arranged at intervals from the inside to the outside around the display area, which plays a role in improving the anti-overflow effect.
  • the number of the grooves 131 can also be multiple, and they are arranged in parallel with each other around the display area, so as to improve the effect of preventing cracks from spreading.
  • multiple refers to two or more than two.
  • Figures 5, 7, 9, 11, and 13 are partial enlarged perspective views of the other five structures in the dashed frame B of the peripheral area in Figure 1 (the reference numerals 11 and 12 in the figure indicate the projected coverage area of the package dam).
  • Figures 6, 8, 10, 12, and 14 are corresponding cross-sectional schematic diagrams.
  • the encapsulation dams each include a first encapsulation dam 11 and a second encapsulation dam 12, and the second encapsulation dam 12 is located on the side of the first encapsulation dam 11 away from the display area.
  • the first packaging dam 11 only includes the first barrier layer 111
  • the second packaging dam 12 includes the first barrier layer 111 and the second barrier layer 112
  • the distance from the upper surface of the second packaging dam 12 to the base substrate 10 is It is greater than the distance from the upper surface of the first packaging dam 11 to the base substrate 10, that is, the second packaging dam 12 is higher than the first packaging dam 11, which can better prevent the organic packaging material from overflowing.
  • the insulating layer has four grooves 131 arranged in parallel.
  • the projections of the four grooves 131 on the base substrate 10 are all located within the projections of the second packaging dam 12 on the base substrate 10, that is, the four recesses 131 are all located directly below the second packaging dam 12.
  • the area of the surrounding area can be saved to the greatest extent, and the effects of anti-crack and anti-overflow can also be achieved.
  • the projections of the four grooves 131 on the base substrate 10 can also all be located within the projections of the first packaging dam 11 on the base substrate 10, that is, the four grooves 131 are all located on the first package dam 11 on the base substrate 10.
  • a similar effect can be achieved directly below the encapsulation dam 11.
  • arranging the groove 131 under the second encapsulation dam 12, compared to arranging it under the first encapsulation part, can prevent the crack from spreading from the outermost side, and delay or prevent the crack to the inside to the greatest extent. extend.
  • each groove 131 on the base substrate 10 is located in the projection of the package dam farthest from the display area in the projection of the base substrate 10, that is, the concave
  • the groove 131 is arranged under the outermost encapsulation dam, which can prevent the crack from spreading to the greatest extent.
  • the packaging dam includes a first packaging dam 11 and a second packaging dam 12, and the second packaging dam 12 is located on a side of the first packaging dam 11 away from the display area.
  • the insulating layer has eight grooves 131 arranged in parallel.
  • the projections of four grooves 131 on the base substrate 10 are located within the projections of the second packaging dam 12 on the base substrate 10, and the projections of the other four recesses 131 on the base substrate 10 are located on the first packaging dam 11 on the substrate.
  • the projection of the substrate 10. That is, four of the grooves 131 are all located directly below the second packaging dam 12, and the other four grooves 131 are all located directly below the first packaging dam 11. In this way, more grooves 131 can be provided to further improve the anti-cracking effect, and it can also avoid increasing the extra peripheral area.
  • the eight grooves 131 can also be distributed in the two packaging dams according to other distribution methods, and similar effects can also be achieved.
  • the projections of the grooves 131 on the base substrate 10 are distributed within the projections of the package dams on the base substrate 10, and the projection of any package dam on the base substrate 10 All of them contain the projection of at least one groove 131, that is, the groove 131 is provided under each encapsulation dam, which can prevent the crack from spreading to the greatest extent without increasing the area of the peripheral area.
  • the number of grooves 131 per unit area and the larger the surface area of the grooves 131, the more difficult it is for the crack to extend. Therefore, the number of grooves 131 can be set according to product design requirements and structural strength.
  • the display panel further includes a crack detection (PCD, Panel Crack Detect) line 14.
  • the crack detection line 14 is used to detect cracks in the display panel.
  • the crack detection line 14 is usually a metal wire and is arranged around the display area. Several data lines connected to the display area, when the crack detection line 14 breaks, the broken detection line will increase its own resistance, making the connected data line insufficient to write, and eventually show several non-bright lines, so as to reach the detection film. The purpose of the break.
  • the crack detection line 14 may be formed of the same material as at least one of the gate layer 93, the source electrode or the drain electrode of the thin film transistor and formed through a one-step patterning process.
  • the display panel includes a crack detection line 14, and the projection of the crack detection line 14 on the base substrate 10 is outside the projections of the first package dam 11 and the second package dam 12
  • the crack detection line 14 is located on the side of the second package dam 12 away from the display area.
  • the projection of the crack detection line 14 on the base substrate 10 is located between the projections of the first package dam 11 and the second package dam 12 on the base substrate 10, that is, the crack
  • the detection line 14 is provided between the first encapsulation dam 11 and the second encapsulation dam 12.
  • the projection of the crack detection line 14 on the base substrate 10 is located between the projections of two adjacent package dams on the base substrate 10, that is, the crack detection line 14 can be Set between any two adjacent encapsulation dams.
  • the display panel includes a crack detection line 14, and the projection of the crack detection line 14 on the base substrate 10 is located within the projection of the second package dam 12 on the base substrate 10. , That is, the crack detection line 14 is set directly below the second encapsulation dam 12. Therefore, on the basis of realizing crack detection, the distance between the two package dams may not be occupied, and the area of the peripheral area may be minimized.
  • the projection of the crack detection line 14 on the base substrate 10 can also be located within the projection of the first package dam 11 on the base substrate 10, that is, the crack detection line 14 is located on the first package dam 11 The same effect can be achieved directly below.
  • the projection of the crack detection line 14 on the base substrate 10 is located between the projections of any package dam on the base substrate 10.
  • the insulating layer 9 covers the crack detection line 14, and the crack detection line 14 does not overlap with the projections of the four grooves 131 on the base substrate 10, that is, the crack detection
  • the line 14 and the four grooves 131 are arranged in parallel on the horizontal surface of the base substrate 10.
  • the crack detection line 14 under the second packaging dam 12 is located on the right side of the four grooves 131, of course, the crack detection line 14 can also be located on the left side of the four grooves 131.
  • the crack detection line 14 and the gate layer 93 are provided in the same layer, when the structure is formed, the crack detection line 14 is formed first, and then the insulating layer 9 and the groove 131 are formed, so the crack detection line 14 is covered by the insulating layer 94.
  • the crack detection line 14 is located on the side of the insulating layer 9 away from the base substrate 10, and the crack detection line 14 is located between the two grooves 131 on the right side. That is, the crack detection line 14 is located above the insulating layer between the two grooves 131 on the right.
  • the structure occupies a smaller lateral area, which can reduce the size of the package dam, thereby further reducing the size of the peripheral area.
  • the crack detection line 14 can also be arranged above the insulating layer between any two other grooves 131.
  • each crack detection line 14 is arranged above the insulating layer between adjacent grooves 131.
  • the embodiments of the present disclosure also provide a display device, which includes the display panel of the above-mentioned embodiment. Since the display device has the above-mentioned display panel, it has the same beneficial effects, which will not be repeated in this disclosure.
  • the present disclosure does not specifically limit the application of display devices, which can be TVs, laptops, tablet computers, wearable display devices, mobile phones, car displays, navigation, e-books, digital photo frames, advertising light boxes, etc., which have display functions. Products or parts.
  • This embodiment also provides a method for manufacturing the above-mentioned display panel, referring to FIG. 15 and FIG. 2, including:
  • Step S100 a base substrate 10 is provided, and a display area and a peripheral area surrounding the display area are divided on the base substrate 10;
  • Step S200 forming an insulating layer 9 on the peripheral area of the base substrate 10;
  • step S300 at least one packaging dam 110 is formed on the side of the insulating layer 9 away from the base substrate 10, and the packaging dam 110 is located in the peripheral area of the base substrate 10 and surrounds the display area;
  • step S400 at least one groove 131 is formed on the insulating layer 9, and the grooves 131 surround the display area and are arranged at intervals; wherein, the projection of the at least one groove 131 on the base substrate 10 is located on the package dam 110 on the base substrate. Within the projection.
  • the method further includes forming a crack detection line 14 in the peripheral area of the base substrate 10 and surrounding the display area, and the projection of the crack detection line 14 on the base substrate 10 is located on two adjacent package dams on the base substrate 10. Or, the projection of the crack detection line 14 on the base substrate 10 is located within the projection of the package dam on the base substrate 10.

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  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

提供一种显示面板及其制备方法、显示装置。显示面板包括衬底基板（10），衬底基板（10）的周边区设置有绝缘层（9），绝缘层（9）远离衬底基板（10）的一侧设置有至少一个封装坝（110），封装坝（110）位于衬底基板（10）的周边区且围绕显示区设置，绝缘层（9）上设置有至少一个凹槽（131），凹槽（131）围绕显示区设置；其中，至少一个凹槽（131）在衬底基板（10）的投影位于封装坝（110）在衬底基板（10）的投影内。凹槽（131）可以减缓或者阻止裂缝向显示区方向延伸，提高封装效果。同时，由于凹槽（131）设置在封装坝下方，可以缩小周边区宽度，提高屏占比。

Description

显示面板及其制备方法、显示装置
交叉引用
本公开要求于2020年4月24日提交的申请号为202010333434.9名称为“显示面板及其制备方法、显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及其制备方法，还涉及显示装置。
背景技术
有机发光显示面板(OLED，organic light-emitting diode)属于自发光显示器，具有诸如功耗低、响应速度快、发光效率高、亮度高、视角宽的优点，能满足薄型化、轻量化、便携性和高性能的要求。
随着用户对显示效果的追求越来越高，提高屏占比为主流设计方向之一，目前主要通过设计异形屏(例如齐刘海、美人尖等)来扩大显示区进而提高屏占比，还可以通过优化周边区的电路布局来缩小边框尺寸进而提高屏占比。然而这些方法对提高屏占比的效果有限，用户期待屏占比能够进一步提高。
需要说明的是，在上述背景技术部分发明的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种显示面板及制备方法、显示装置，解决现有技术存在的一种或多种问题。
根据本公开的一个方面，提供一种显示面板，包括：
衬底基板，包括显示区和围绕所述显示区的周边区；
绝缘层，至少覆盖所述衬底基板周边区；
至少一个封装坝，位于所述绝缘层远离所述衬底基板的一侧，所述封装坝位于所述衬底基板的周边区且围绕所述显示区设置；
至少一个凹槽，形成于所述绝缘层，所述凹槽围绕所述显示区设置；其中，至少一个所述凹槽在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
在本公开的一种示例性实施例中，所述封装坝的数量为两个，所述两个封装坝围绕所述显示区且间隔排列；所述凹槽在所述衬底基板的投影位于至少一个所述封装坝在所述衬底基板的投影内。
在本公开的一种示例性实施例中，所述凹槽在所述衬底基板的投影位于离所述显示区最远的所述封装坝在所述衬底基板的投影内。
在本公开的一种示例性实施例中，所述显示面板还包括：裂纹检测线，位于所述衬底基板的周边区且围绕所述显示区设置，且所述裂纹检测线在所述衬底基板的投影位于相邻两个所述封装坝在所述衬底基板的投影之间。
在本公开的一种示例性实施例中，还包括：裂纹检测线，位于所述基板的周边区且围绕所述显示区设置，且所述裂纹检测线在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
在本公开的一种示例性实施例中，所述绝缘层覆盖所述裂纹检测线；在所述封装坝的投影覆盖区域内，所述裂纹检测线位于所述凹槽靠近或远离所述显示区的一侧。
在本公开的一种示例性实施例中，所述裂纹检测线位于所述绝缘层远离衬底基板的一侧，且所述裂纹检测线位于相邻两个所述凹槽之间。
在本公开的一种示例性实施例中，所述裂纹检测线的数量为多条，且所述裂纹检测线在所述衬底基板的投影位于其中一个所述封装坝在所述衬底基板的投影内或分布于所述多个封装坝在所述衬底基板的投影内。
在本公开的一种示例性实施例中，所述绝缘层为单层结构，所述凹槽形成于所述单层结构中；或，所述绝缘层为多层结构，所述凹槽贯通至少一层且所述凹槽底面位于最靠近所述衬底基板的一层内。
在本公开的一种示例性实施例中，所述显示面板还包括形成于所述显示区的像素界定层；所述封装坝包括第一阻挡层，所述第一阻挡层与 所述像素界定层采用相同材料同层设置。
在本公开的一种示例性实施例中，所述显示面板还包括形成于所述显示区的平坦层；所述封装坝还包括设于所述第一阻挡层朝向所述衬底基板一侧的第二阻挡层，所述第二阻挡层与所述平坦层采用相同材料同层设置。
在本公开的一种示例性实施例中，所述封装坝包括第一封装坝和第二封装坝，所述第二封装坝围绕于所述第一封装坝远离所述显示区的一侧，所述第一封装坝包括第一阻挡层，所述第二封装坝包括第一阻挡层和第二阻挡层。
根据本公开的另一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
根据本公开的再一个方面，还提供一种显示面板的制备方法，包括：
提供一衬底基板，在所述衬底基板划分显示区和围绕所述显示区的周边区；
在所述衬底基板的周边区形成绝缘层；
在所述绝缘层远离所述衬底基板的一侧形成至少一个封装坝，且使所述封装坝位于所述衬底基板的周边区且围绕所述显示区；
在所述绝缘层上形成至少一个凹槽，且使所述凹槽围绕所述显示区且间隔排列；其中，至少一个所述凹槽在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
在本公开的一种示例性实施例中，该方法还包括：在所述衬底基板的周边区且围绕所述显示区形成裂纹检测线，所述裂纹检测线在所述衬底基板的投影位于相邻两个所述封装坝在所述衬底基板的投影之间，或，所述裂纹检测线在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
本公开的显示面板周边区的绝缘层具有凹槽结构，一旦面板边缘出现裂缝，防裂部可以改变裂缝延伸方向，还可以增加裂缝延伸路径，起到减缓或者阻值裂缝向显示区方向延伸的作用，防止显示区结构受损，提高封装效果。同时，绝缘层的上方设置封装坝，凹槽位于封装坝下方，可以缩小周边区宽度，进而提高屏占比。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本实施方式的显示面板的俯视示意图；
图2为本实施方式的显示面板的一种截面示意图；
图3为本实施方式的显示面板的另一种截面示意图；
图4为图1中周边区虚线框B部的第一种局部放大透视图；
图5为图1中周边区虚线框B部的第二种局部放大透视图；
图6为图5的截面示意图；
图7为图1中周边区虚线框B部的第三种局部放大透视图；
图8为图7的截面示意图；
图9为图1中周边区虚线框B部的第四种局部放大透视图；
图10为图9的截面示意图；
图11为图1中周边区虚线框B部的第五种局部放大透视图；
图12为图11的截面示意图；
图13为图1中周边区虚线框B部的第六种局部放大透视图；
图14为图13的截面示意图；
图15为本实施方式的显示面板的制备流程图。
图中：10、衬底基板；101、第一PI层；102、第一保护层；103、第二PI层；104、第二保护层；105、缓冲层；110、封装坝；11、第一封装坝；12、第二封装坝；111、第一阻挡层；112、第二阻挡层；131、凹槽；9、绝缘层；91、有源层；92、栅绝缘层；93、栅极层；94、介电层；95、源漏层；96、平坦层；80、阳极层；81、像素界定层；82、发光层；83、阴极层；14、裂纹检测线；151、第一无机封装层；152、 有机封装层；153、第二无机封装层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
本公开实施方式中提供了一种显示面板，参考图1，为本实施方式的显示面板的俯视示意图，AA表示显示区，AA区以外为周边区。图2为本实施方式显示面板截面图的部分结构示意图，图中竖向虚线用于区分显示区和周边区，右边为显示区，左边为周边区，显示区和非显示区都仅简要地示出了与本公开相关的主要结构。图3为图1中周边区虚线框B部的局部放大透视图，对应于图2的截面结构。由图可知，该显示面板包括衬底基板10，衬底基板10包括显示区和围绕显示区的周边区。周边区设置有绝缘层9，绝缘层9远离衬底基板10的一侧设置有封装坝110，封装坝110的延伸方向与显示区边缘方向相同。绝缘层9上还形成层有至少一个凹槽131，凹槽131设于衬底基板10的周边区且围绕显示区，且凹槽131位于封装坝110和衬底基板10之间；其中，至少一个凹槽131在衬底基板10的投影位于封装坝110在衬底基板10的投影内。
如图1所示，封装坝110为围绕显示区设置的环形凸起，能够在进行薄膜封装时防止有机封装材料溢出影响设于周边区的焊盘。
在显示面板的生产及使用过程中，受切割工艺、运输或者弯曲等因素的影响，在显示面板的边缘区域，无机材料层容易产生裂缝。如果该裂缝延伸至显示面板的内部，可能会破坏显示面板中的重要元件，并且使得外界水、氧等侵入显示面板的内部，从而影响产品良率，增加生产成本。本公开在绝缘层9上设置凹槽131，一旦面板边缘出现裂缝，凹槽131可以改变裂缝延伸方向，还可以增加裂缝延伸路径，起到减缓或者阻止裂缝向显示区方向延伸的作用，防止显示区结构受损，提高封装效果。将凹槽131设置在封装坝110下方，可以减小占用面积，缩小周 边区宽度，进而提高屏占比。
下面对本公开实施方式的显示面板进行详细说明：
本实施方式中，衬底基板10的显示区用于设置有机发光器件、薄膜晶体管、像素电容等结构，非显示区用于设置驱动电路、封装结构等。
衬底基板10可以为任意呈透明的基板，例如玻璃基板、石英基板、塑胶基板或其他透明的硬质或者可挠式基板，其可以是单层或多层结构。如图2所示的实施方式中，衬底基板10为多层结构，其包括由下至上依次层叠设置的第一PI(聚酰亚胺)层101、第一保护层102、第二PI(聚酰亚胺)层103、第二保护层104，两个保护层用于保护PI层，防止后续工艺对PI层的破坏。第二保护层104上还覆盖有缓冲层105，可以阻挡水氧和阻隔碱性离子。
在本公开实施方式中，薄膜晶体管可以是顶栅或底栅结构。以顶栅结构为例，参考图2，其至少包括有源层91、栅绝缘层92、栅极层93、介电层94、源漏层95、平坦层96。有源层91设于衬底基板10上，栅绝缘层92覆盖有源层91，栅极层93设于栅绝缘层92远离衬底基板10的表面，介电层94覆盖栅绝缘层92和栅极层93；源漏层95设于绝缘层远离衬底基板10的表面，且源漏层95包括连接于有源层91两端的源极和漏极；平坦层96覆盖源漏层95和介电层94。除此之外，为了进一步提高晶体管效率，薄膜晶体管还可以进一步优化，例如增加第二栅极,等其他结构，但其基本膜层如上所述，本公开不对薄膜晶体管的具体结构做特殊限定。
有机发光器件以顶发射器件为例，包括阳极层80、设置在阳极层80上且具有开口能够露出部分阳极层的像素界定层81、设于开口内且覆盖阳极层80的发光层82、以及覆盖发光层82和像素界定层81的阴极层83。其中，有机发光器件的阳极层80和薄膜晶体管的漏极通过过孔电连接，以使有机发光器件能够在薄膜晶体管的控制下发光或关闭。有机层可以包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等膜层。
显示面板还可以包括封装膜层，用于防止外部水分或氧气渗透到易 受外部水分或氧气影响的有机发光器件中。具体的，封装膜层可以包括两个无机封装层和一个设置在两个无机封装层之间的有机封装层，即在有机发光器件上方，由下至上依次设置第一无机封装层151、有机封装层152、第二无机封装层153。两个无机封装层起隔绝水氧入侵的作用，有机封装层用作缓冲部，以减小由于显示面板的弯曲而引起的各个层之间的应力，并且增强平坦化特性。有机封装层152至少覆盖显示区，并被封装坝11阻挡，两个无机封装层覆盖显示区和部分非显示区。
本实施方式中，以图2中右侧封装坝11为例进行说明，封装坝110包括第一阻挡层111，第一阻挡层111可以与显示区的像素界定层81采用相同材料同层设置。本公开中，同层设置是指通过同一步构图工艺形成，以下图中均采用同一填充线填充。具体的，可以在形成显示区的像素界定层81的同时在周边区也形成像素界定层81，然后通过同一步构图工艺对周边区的像素界定层81进行图案化处理，形成如图2所示的呈凸起结构的第一阻挡层111。
进一步地，以图2中左侧封装坝12为例进行说明，封装坝110还可以包括第二阻挡层112，第二阻挡层112设于第一阻挡层111朝向衬底基板10一侧，即第二阻挡层112设置在第一阻挡层111下方，两层阻挡层增加了整个封装坝的高度，使得防溢出效果更好。第二阻挡层112可以与显示区的平坦层采用相同材料同层设置。具体的，可以在形成显示区的平坦层96的同时在周边区也形成平坦层96，然后通过同一步构图工艺对周边区的平坦层96进行图案化处理，形成如图2所示的呈凸起结构的第二阻挡层112。
在本公开一种实施方式中，绝缘层9为单层结构，例如图2所示，绝缘层可以与显示区的介电层94采用相同材料同层设置。具体的，可以在形成显示区的介电层94的同时在周边区也形成介电层94作为绝缘层9，然后通过同一步构图工艺对周边区的介电层94进行图案化处理，去除目标区域的部分介电层94材料，使目标区域形成凹槽131，相邻凹槽131之间为绝缘材料所形成的条状结构。
在另一种实施方式中，绝缘层9为多层结构，即除了介电层94，还可以包括更多的膜层，此时凹槽贯通上方膜层且凹槽底面位于最靠近衬 底基板的一层内。例如图3所示，绝缘层9包括两层，下层为栅绝缘层92，上层为介电层94。凹槽贯通介电层94且凹槽底面位于栅绝缘层92内。该结构的凹槽形成工艺具体可以为，在形成显示区的介电层和栅绝缘层的同时，在周边区也形成介电层和栅绝缘层，然后通过相对应的构图工艺对周边区的介电层和栅绝缘层进行图案化处理，也可以使其形成凹槽131。当然，根据显示区的膜层结构，绝缘层也可以进一步包括其他绝缘材料层，栅绝缘层92也可以进一步包括多个栅绝缘层，此处不再赘述。
需要说明的是，由于凹槽131位于封装坝110下方，在形成封装坝110时，封装坝110的材料会自动填充于凹槽131内，该结构不会影响凹槽131防止裂纹延伸的作用，反而会增加裂纹延伸的障碍，有效阻止裂纹延伸。
还需要说明的是，图中所示的封装坝110和凹槽131的截面形状仅为示例，二者的截面形状可以为矩形、弧形、梯形或其他任意结构，封装坝110只要能够在衬底上形成凸起就可以实现阻挡效果，凹槽131之间只要具有间隔就可以阻挡裂纹延伸。另外，凹槽131的数量可以为一个或多个，若具有多个凹槽131，则多个凹槽131之间间隔排列，凹槽131的具体数量可根据需求设置，本申请不进行特殊限定。
在一些实施方式中，封装坝110的数量可以为多个，各封装坝110均为围绕显示区由内向外间隔设置的环形凸起，起到提高防溢出效果的作用。凹槽131的数量也可以为多个，且围绕显示区相互平行设置，以起到提高防止裂纹扩散的作用。本公开中，多个是指两个或两个以上的数量。
举例而言，图5、7、9、11、13均为图1中周边区虚线框B部的另外五种结构的局部放大透视图(图中标号11、12表示封装坝投影覆盖区域)，图6、8、10、12、14分别为相应的截面示意图。在这些实施方式中，封装坝均包括第一封装坝11和第二封装坝12，第二封装坝12位于第一封装坝11远离显示区的一侧。这些实施方式中，第一封装坝11仅包括第一阻挡层111，第二封装坝12包括第一阻挡层111和第二阻挡层112，第二封装坝12上表面到衬底基板10的距离大于第一封装坝11上 表面到衬底基板10的距离，即第二封装坝12高于第一封装坝11，可以更好的防止有机封装材料溢出。
具体的，在图2-图6所示的实施方式中，绝缘层有四个平行设置的凹槽131。四个凹槽131在衬底基板10的投影均位于第二封装坝12在衬底基板10的投影内，也就是说，四个凹槽131都位于第二封装坝12的正下方。可以最大程度上节约周边区的面积，还可以实现防裂纹以及防溢出的作用。当然，在其他实施方式中，四个凹槽131在衬底基板10的投影也可以均位于第一封装坝11在衬底基板10的投影内，也就是说，四个凹槽131都位于第一封装坝11的正下方，也能起到相似的效果。但将凹槽131设置在第二封装坝12的下方，相比将其设置在第一封装部的下方，能够从最外侧就起到阻挡裂纹扩散的目的，最大程度上延缓或阻止裂纹向内部延伸。
同理，当封装坝的数量大于两个时，各凹槽131在衬底基板10的投影均位于离显示区最远的封装坝在衬底基板10的投影内时，也就是说，将凹槽131设置在最外侧的封装坝下方，能够最大程度上阻挡裂纹扩散。
在如图7-图8所示的实施方式中，封装坝包括第一封装坝11和第二封装坝12，第二封装坝12位于第一封装坝11远离显示区的一侧。绝缘层有八个平行设置的凹槽131。
其中四个凹槽131在衬底基板10的投影位于第二封装坝12在衬底基板10的投影内，另外四个凹槽131在衬底基板10的投影位于第一封装坝11在衬底基板10的投影内。也就是说，其中四个凹槽131都位于第二封装坝12的正下方，另外四个凹槽131都位于第一封装坝11的正下方。由此既可以设置更多的凹槽131以进一步提高防裂效果，还能够避免增加额外的周边区面积。当然，在其他实施方式中，八个凹槽131也可以按照其他分布方式在两个封装坝中分布，也能起到相似的效果。
同理，当封装坝的数量大于两个时，各凹槽131在衬底基板10的投影分布于各封装坝在衬底基板10的投影内，且任一封装坝在衬底基板10的投影内均包含至少一个凹槽131的投影，也就是说，在每个封装坝下方都设置凹槽131，能够最大程度上阻挡裂纹扩散，同时不会增加周 边区面积。
需要说明的，单位面积中凹槽131的数量越多，凹槽131的表面积越大，裂纹延伸就越困难，因此，凹槽131的数量可以根据产品设计需求和结构强度进行设置。
在本公开实施方式中，显示面板进一步还包括裂纹检测(PCD，Panel Crack Detect)线14，裂纹检测线14用于检测显示面板裂纹，通常为金属线，围绕显示区设置，将裂纹检测线14连接至显示区的若干数据线，当裂纹检测线14出现断裂时，断裂的检测线将会增加自身电阻，使相连的数据线写入不足，最终呈现数条不亮线，从而到达检测膜层断裂的目的。
裂纹检测线14可以采用与薄膜晶体管的栅极层93、源极或漏极中至少一者相同的材料并通过通一步构图工艺形成。
在如图2-图4所示的实施方式中，显示面板包括一条裂纹检测线14，且裂纹检测线14在衬底基板10的投影位于第一封装坝11和第二封装坝12的投影以外的区域，且该裂纹检测线14位于第二封装坝12远离显示区的一侧。
在如图5-图8所示的实施方式中，裂纹检测线14在衬底基板10的投影位于第一封装坝11和第二封装坝12在衬底基板10的投影之间，即该裂纹检测线14设置在第一封装坝11和第二封装坝12之间。利用第一封装坝11和第二封装坝12之间现有的面积设置裂纹检测线14，在实现裂纹检测的基础上，也不会增加额外的周边区面积，达到缩小边框的目的。
同理，当封装坝的数量大于两个时，裂纹检测线14在衬底基板10的投影位于相邻两个封装坝在衬底基板10的投影之间，也就是说，裂纹检测线14可以设置在任意相邻的两个封装坝之间。
在如图9-图12所示的实施方式中，显示面板包括一条裂纹检测线14，且该裂纹检测线14在衬底基板10的投影位于第二封装坝12在衬底基板10的投影内，即该裂纹检测线14设置第二封装坝12正下方。由此，在实现裂纹检测的基础上，可以不占据两个封装坝之间的距离，最大程度上减小周边区的面积。当然，在其他实施方式中，裂纹检测线14在 衬底基板10的投影也可以位于第一封装坝11在衬底基板10的投影内，也就是说，裂纹检测线14位于第一封装坝11的正下方，也能起到相同的效果。
同理，当封装坝的数量大于两个时，裂纹检测线14在衬底基板10的投影位于任一封装坝在衬底基板10的投影之间。
在上述结构中，由于裂纹检测线14和凹槽131都设置在封装坝正下方，因此二者具体设置方式可以有以下两种。
在如图9和图10所示的一种实施方式中，绝缘层9覆盖裂纹检测线14，裂纹检测线14与四条凹槽131在衬底基板10的投影不重叠，也就是说，裂纹检测线14与四条凹槽131在衬底基板10水平面上平行排列。如图9所示，第二封装坝12下方的裂纹检测线14位于四条凹槽131的右侧，当然，裂纹检测线14也可以位于四条凹槽131的左侧。若裂纹检测线14与栅极层93同层设置，则在形成该结构时，先形成裂纹检测线14，再形成绝缘层9和凹槽131，因此裂纹检测线14被绝缘层94覆盖。
在如图11和图12所示另一种实施方式中，裂纹检测线14位于绝缘层9远离衬底基板10的一侧，且裂纹检测线14位于右侧两个凹槽131之间，也就是说，裂纹检测线14位于右侧两个凹槽131之间的绝缘层上方。相比上一实施方式，该结构占用的横向面积更小，可以使封装坝尺寸减小，由此进一步减小周边区尺寸。当然，裂纹检测线14还可以设置于另外任意两个凹槽131之间的绝缘层上方。在形成该结构时，由于裂纹检测线14位于绝缘层9上方，因此需要先形成绝缘层9。
在如图13和图14所示的再一种实施方式中，裂纹检测线14的数量为六条，各裂纹检测线14在衬底基板10的投影分布于两个封装坝在衬底基板10的投影内，既可以在多个位置进行检测或实现辅助检测，也可以最大程度减小周边区尺寸。图中各裂纹检测线14均设置在相邻凹槽131之间的绝缘层上方。
本公开实施方式还提供一种显示装置，该显示装置包括上述实施方式的显示面板。由于该显示装置具有上述显示面板，因此具有相同的有益效果，本公开在此不再赘述。
本公开对于显示装置的适用不做具体限制，其可以是电视机、笔记 本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有显示功能的产品或部件。
本实施方式还提供上述显示面板的制备方法，参考图15和图2，包括：
步骤S100，提供一衬底基板10，在衬底基板10上划分显示区和围绕显示区的周边区；
步骤S200，在衬底基板10的周边区形成绝缘层9；
步骤S300，在绝缘层9远离衬底基板10的一侧形成至少一个封装坝110，且使封装坝110位于衬底基板10的周边区且围绕显示区；
步骤S400，在绝缘层9上形成至少一个凹槽131，且使凹槽131围绕显示区且间隔排列；其中，至少一个凹槽131在衬底基板10的投影位于封装坝110在衬底基板的投影内。
进一步地，该方法还包括在衬底基板10的周边区且围绕显示区形成裂纹检测线14，所述裂纹检测线14在衬底基板10的投影位于相邻两个封装坝在衬底基板10的投影之间，或，裂纹检测线14在衬底基板10的投影位于封装坝在衬底基板10的投影内。
上述步骤中的各膜层和结构的形成方法已在显示面板结构部分进行说明，当然本领域技术人员知晓，上述膜层和结构还可以采用其他本领域常规技术手段制备，此处不再赘述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种显示面板，其中，包括：
    衬底基板，包括显示区和围绕所述显示区的周边区；
    绝缘层，至少覆盖所述衬底基板周边区；
    至少一个封装坝，位于所述绝缘层远离所述衬底基板的一侧，所述封装坝位于所述衬底基板的周边区且围绕所述显示区设置；
    至少一个凹槽，形成于所述绝缘层，所述凹槽围绕所述显示区设置；其中，至少一个所述凹槽在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
  2. 根据权利要求1所述的显示面板，其中，所述封装坝的数量为两个，所述两个封装坝围绕所述显示区且间隔排列；所述凹槽在所述衬底基板的投影位于至少一个所述封装坝在所述衬底基板的投影内。
  3. 根据权利要求2所述的显示面板，其中，所述凹槽在所述衬底基板的投影位于离所述显示区最远的所述封装坝在所述衬底基板的投影内。
  4. 根据权利要求2-3中任一项所述的显示面板，其中，所述显示面板还包括：
    裂纹检测线，位于所述衬底基板的周边区且围绕所述显示区设置，且所述裂纹检测线在所述衬底基板的投影位于相邻两个所述封装坝在所述衬底基板的投影之间。
  5. 根据权利要求2-3中任一项所述的显示面板，其中，还包括：
    裂纹检测线，位于所述基板的周边区且围绕所述显示区设置，且所述裂纹检测线在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
  6. 根据权利要求5所述的显示面板，其中，所述绝缘层覆盖所述裂纹检测线；在所述封装坝的投影覆盖区域内，所述裂纹检测线位于所述凹槽靠近或远离所述显示区的一侧。
  7. 根据权利要求5所述的显示面板，其中，所述裂纹检测线位于所述绝缘层远离衬底基板的一侧，且所述裂纹检测线位于相邻两个所述凹槽之间。
  8. 根据权利要求7所述的显示面板，其中，所述裂纹检测线的数量 为多条，且所述裂纹检测线在所述衬底基板的投影位于其中一个所述封装坝在所述衬底基板的投影内或分布于所述多个封装坝在所述衬底基板的投影内。
  9. 根据权利要求1所述的显示面板，其中，所述绝缘层为单层结构，所述凹槽形成于所述单层结构中；
    或，所述绝缘层为多层结构，所述凹槽贯通至少一层且所述凹槽底面位于最靠近所述衬底基板的一层内。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括形成于所述显示区的像素界定层；
    所述封装坝包括第一阻挡层，所述第一阻挡层与所述像素界定层采用相同材料同层设置。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括形成于所述显示区的平坦层；
    所述封装坝还包括设于所述第一阻挡层朝向所述衬底基板一侧的第二阻挡层，所述第二阻挡层与所述平坦层采用相同材料同层设置。
  12. 根据权利要求11所述的显示面板，其中，所述封装坝包括第一封装坝和第二封装坝，所述第二封装坝围绕于所述第一封装坝远离所述显示区的一侧，所述第一封装坝包括第一阻挡层，所述第二封装坝包括第一阻挡层和第二阻挡层。
  13. 一种显示装置，其中，包括权利要求1-12中任一项所述的显示面板。
  14. 一种显示面板的制备方法，其中，包括：
    提供一衬底基板，在所述衬底基板划分显示区和围绕所述显示区的周边区；
    在所述衬底基板的周边区形成绝缘层；
    在所述绝缘层远离所述衬底基板的一侧形成至少一个封装坝，且使所述封装坝位于所述衬底基板的周边区且围绕所述显示区；
    在所述绝缘层上形成至少一个凹槽，且使所述凹槽围绕所述显示区且间隔排列；其中，至少一个所述凹槽在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
  15. 根据权利要求14所述的显示面板的制备方法，其中，还包括：
    在所述衬底基板的周边区且围绕所述显示区形成裂纹检测线，所述裂纹检测线在所述衬底基板的投影位于相邻两个所述封装坝在所述衬底基板的投影之间，或，所述裂纹检测线在所述衬底基板的投影位于所述封装坝在所述衬底基板的投影内。
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