WO2022032704A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022032704A1
WO2022032704A1 PCT/CN2020/110375 CN2020110375W WO2022032704A1 WO 2022032704 A1 WO2022032704 A1 WO 2022032704A1 CN 2020110375 W CN2020110375 W CN 2020110375W WO 2022032704 A1 WO2022032704 A1 WO 2022032704A1
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WO
WIPO (PCT)
Prior art keywords
layer
width
electrode
display panel
hollow portion
Prior art date
Application number
PCT/CN2020/110375
Other languages
English (en)
French (fr)
Inventor
叶剑
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/254,268 priority Critical patent/US11954275B2/en
Publication of WO2022032704A1 publication Critical patent/WO2022032704A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0448—Details of the electrode shape, e.g. for enhancing the detection of touches, for generating specific electric field shapes, for enhancing display quality
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04112—Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the present application relates to the field of display technology, in particular to the field of touch technology, and in particular to a display panel and a display device.
  • OLED Organic Light-Emitting Diode
  • LCD Liquid Crystal Display, liquid crystal display
  • a pixel definition layer (PDL, pixel define layer), the surface of the pixel definition layer is set with uprights (PS, photo spacer).
  • PDL pixel definition layer
  • PS photo spacer
  • the column is used to support a high-precision metal mask (FMM, Fine Metal Mask). Therefore, the column has a certain height, so that the distance between the cathode layer on it and the touch electrode layer changes. Smaller, the parasitic capacitance is increased, the capacitive reactance and/or impedance of the touch signal is increased, and the delay is prolonged, which seriously affects the touch sensitivity and touch reporting rate of the column projection area and surrounding areas.
  • FMM Fine Metal Mask
  • the present application provides a display panel and a display device, which solve the problem of unbalanced parasitic capacitance caused by the reduction of the distance between the cathode layer and the touch function layer at the column.
  • the present application provides a display panel, comprising: a pixel definition layer; a cathode layer covering the pixel definition layer; a column located between the pixel definition layer and the cathode layer; and a side of the cathode layer and away from the pixel definition layer
  • the touch function layer of the touch control function layer is provided with electrode wiring; wherein, the electrode wiring is constructed with a winding structure with a hollow portion, and the hollow portion corresponds to the column, so as to reduce the cathode layer and the touch function at the corresponding position of the column. Parasitic capacitance between layers.
  • the orthographic projection of the column and the hollow portion at least partially overlap, or the orthographic projection of the hollow portion at least partially covers the column.
  • the winding structure is formed by electrode wires with a first width surrounding the hollow portion; the width of the electrode wires away from the hollow portion is configured to be the second width, and The first width is not greater than the second width.
  • the first width is not greater than 3 micrometers; the second width is not greater than 5 micrometers.
  • the winding structure is electrically connected to adjacent electrode wires.
  • the hollow portion is provided with a light shielding block insulated from the electrode wiring.
  • the cross-sectional shape of the light shielding block is the same as the cross-sectional shape of the column.
  • the cross-sectional area of the light-shielding block is not less than 80% of the cross-sectional area of the column, and is not greater than 120% of the cross-sectional area of the column. %.
  • the display panel further includes a plurality of sub-pixels; and the orthographic projections of the electrode lines are located between adjacent sub-pixels.
  • the present application provides a display device, which includes: a pixel definition layer; a cathode layer covering the pixel definition layer; a column located between the pixel definition layer and the cathode layer; and a column located on one side of the cathode layer and away from the pixel definition layer touch function layer, the touch function layer is provided with a first electrode wiring and a second electrode wiring; wherein, the first electrode wiring and/or the second electrode wiring is configured with a winding structure with a hollow portion, and The hollow part corresponds to the column, so as to reduce the parasitic capacitance between the cathode layer and the touch function layer corresponding to the column.
  • FIG. 1 is a schematic structural diagram of a display panel/display device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a touch function layer provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a projection position of a sub-pixel and a first electrode or a second electrode according to an embodiment of the present application.
  • FIG. 4 is one of the schematic diagrams of the projection positions of the sub-pixels and the winding structure provided by the embodiment of the present application.
  • FIG. 5 is the second schematic diagram of the projection positions of the sub-pixels and the winding structure according to the embodiment of the present application.
  • FIG. 6 is a schematic diagram of projection positions among sub-pixels, columns, and light-shielding blocks according to an embodiment of the present application.
  • FIG. 7 is a second schematic structural diagram of a display panel/display device provided by an embodiment of the present application.
  • FIG. 8 is a third schematic structural diagram of a display panel/display device according to an embodiment of the present application.
  • FIG. 9 is a partial enlarged schematic diagram shown at Y100 in FIG. 4 .
  • the display panel or the display device may include, but is not limited to, an anode layer 52 , a pixel definition layer 51 , a light-emitting layer 53 , a cathode layer 40 , and a touch-sensitive layer that are stacked in sequence.
  • Functional layer 20 The column 30 is disposed between the pixel definition layer 51 and the cathode layer 40 , and the column 30 raises the corresponding position of the cathode layer 40 to make the distance between the cathode layer 40 corresponding to the column 30 and the touch function layer 20 become smaller.
  • the touch functional layer 20 in this embodiment is provided with electrode traces, wherein the electrode traces are configured with a winding structure 26 with a hollow portion 261 , the hollow portion 261 corresponds to the column 30 , and the hollow portion 261 may form a
  • the non-electrical region can reduce the electrical coupling between the cathode layer 40 and the touch function layer 20 at the corresponding position of the column 30 , thereby reducing the parasitic capacitance generated thereby, so as to balance the relationship between the touch function layer 20 and the cathode layer 40 .
  • the overall consistency of the parasitic capacitance between them avoids the noise caused by the unbalanced parasitic capacitance, which is beneficial to improve the overall touch reporting rate and sensitivity.
  • the touch function layer 20 at least includes a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer.
  • the first conductive layer may include bridging traces 231 remaining after etching; the second conductive layer is provided with electrode traces remaining after etching, and the electrode traces include first electrode traces 23 and second electrode traces 24; bridging traces 231 can be used as a part of the first electrode trace 23 or the second electrode trace 24, and the first electrode trace 23 or the second electrode trace 23 is connected to the first electrode trace 23 or the second electrode trace 24 through a first via at the intersection of the first electrode trace 23 and the second electrode trace 24.
  • the electrode wiring 24 is used to electrically isolate the first electrode wiring 23 and the second electrode wiring 24 .
  • the electrode traces are structured with a winding structure 26 with a hollow portion 261 , and the hollow portion 261 corresponds to the column 30 to reduce the parasitic capacitance between the cathode layer 40 and the touch function layer 20 corresponding to the column 30 .
  • the electrical isolation in this embodiment means that there is no direct electrical connection, and it is not excluded that the two can be coupled through a third party, such as a human body or a stylus.
  • the winding structure 26 is formed by electrode traces with a first width D1 surrounding the hollow portion 261 ; the width of the electrode traces away from the hollow portion 261 is configured as the second width D2 , and the first width D1 not larger than the second width D2.
  • the first width D1 is not greater than 3 microns; the second width D2 is not greater than 5 microns.
  • the winding structure 26 is electrically connected to the adjacent electrode wires. Specifically, as shown in FIG. 9 , the wire winding structure 26 passes through the electrode wires of the first width D1 and the adjacent electrodes of the second width D2. When the traces are electrically connected, the etching process of the electrode traces of the first width D1 and the electrode traces of the second width D2 can be formed simultaneously. It can be understood that, in the entire process of forming the electrode traces, if a position corresponding to the post 30 is encountered, the electrode traces are divided into two and continuously arranged to avoid the orthographic position of the post 30 .
  • the orthographic projection of the column 30 and the hollow portion 261 at least partially overlap, and may also completely overlap.
  • the orthographic projection of the hollow portion 261 at least partially covers the upright column 30 , and may completely cover the upright column 30 .
  • the encapsulation layer 54 and the touch buffer layer 55 are selectively stacked and disposed between the cathode layer 40 and the touch function layer 20 .
  • the display panel or the display device may further include a passivation layer 56 optionally disposed on one side of the touch functional layer 20 and away from the cathode layer 40 .
  • the display panel or the display device may further include a first PI layer optionally stacked on one side of the anode layer 52 and/or the pixel definition layer 51 and away from the light-emitting layer 53 121, the first buffer layer 11, the second PI layer 122, the second buffer layer 13, the polysilicon layer 14, the first GI layer 15, the first gate layer 16, the second GI layer 17, the second gate layer 18, The interlayer insulating layer 19 and the flat layer 50 .
  • a first PI layer optionally stacked on one side of the anode layer 52 and/or the pixel definition layer 51 and away from the light-emitting layer 53 121, the first buffer layer 11, the second PI layer 122, the second buffer layer 13, the polysilicon layer 14, the first GI layer 15, the first gate layer 16, the second GI layer 17, the second gate layer 18, The interlayer insulating layer 19 and the flat layer 50 .
  • the polysilicon layer 14 can be connected to the flat layer 50 through a second via hole; the second via hole passes through the first GI layer 15, the second GI layer 17 and the interlayer insulating layer 19 in sequence; at least part of the second via hole passes through the
  • the third via hole of the flat layer 50 is connected to the anode layer 52 .
  • the anode layer 52 in the display panel or the display device is located on the side of the cathode layer 40 and away from the touch function layer 20 ; located between the cathode layer 40 and the anode layer 52
  • the light-emitting layer 53; wherein, the display panel or display device may further include a plurality of sub-pixels 531; wherein, the pixel definition layer 51 is provided with corresponding pixel openings for exposing the anode layers 52 constituting each sub-pixel 531 to define the sub-pixels 531 corresponds to the light-emitting position.
  • the light emitting layer 53 is located within the pixel opening.
  • the shape of the metal grid formed by the first electrode traces 23 and/or the second electrode traces 24 may correspond to the shape of the sub-pixels 531 .
  • the sub-pixel 531 is a polygonal structure
  • the polygonal structure may be a square or a rectangle, etc.
  • the metal formed by the first electrode wiring 23 and/or the second electrode wiring 24 is defined.
  • the line type of the grid includes at least straight lines, that is, the line types of the first electrode traces 23 and/or the second electrode traces 24 can be, but are not limited to, both straight lines or straight line segments.
  • the metal grid formed by an electrode trace 23 and/or a second electrode trace 24 also corresponds to a polygonal structure.
  • the first electrode traces 23 and/or are defined.
  • the line type of the metal grid formed by the second electrode traces 24 at least includes a curve, or both are curves, and the bending directions of the two are the same.
  • the orthographic projections of the first electrode traces 23 and/or the second electrode traces 24 do not overlap with the sub-pixels 531 . It should be noted that, in this embodiment, the first electrode traces 23 and/or the second electrode traces 24 are always located in the gaps between adjacent sub-pixels 531 and are located in the middle of the gaps.
  • the traces of the first electrode traces 23 and/or the second electrode traces 24 are always consistent with the outline of the sub-pixel 531, for example, when the sub-pixel 531 is a polygonal structure, for example, a hexagonal structure , the defined metal grid is a quadrilateral structure, then any side of the quadrilateral of the metal grid is always parallel to one of the sides of the hexagonal structure; when the sub-pixel 531 is the first curved-edge arc structure, correspondingly,
  • the metal mesh is also a second curved side arc structure, and the orthographic projection of the second curved side curved structure surrounds the first curved side curved structure, and the inner side of the orthographic projection of the second curved side curved structure reaches the first curved side
  • the distances to the outside of the arc structure are always equal or similar.
  • the pillars 30 and the pixel definition layer 51 are simultaneously formed by a halftone yellow light process, which can simplify the process and improve the process efficiency.
  • the pillars 30 are located between adjacent sub-pixels 531 and do not overlap with the light-emitting layer 53 . It should be noted that the columns 30 are not arranged between the adjacent sub-pixels 531, but one column 30 is arranged every multiple sub-pixels 531. Other integer numbers, such as 4, or 12, or 16, and so on.
  • FIG. 9 which is a partial enlarged schematic diagram shown at Y100 in FIG. 4 , the figure shows the orthographic projection of the hollow part 261 , the light-shielding block 27 and the column 30 on a certain plane.
  • the positional relationship, the orthographic projection of the column 30 and the hollow portion 261 may but not be limited to at least partially overlap, or may be completely overlapped; it may also be that the orthographic projection of the hollow portion 261 may at least partially cover the column 30, but may also completely cover , even the orthographic projection of the hollow portion 261 covers the column 30 and a part of its surrounding area; it should be noted that the cathode layer 40 can be adjusted correspondingly through the overlap or coverage of the hollow portion 261 and the column 30 on the corresponding orthographic projection. Parasitic capacitance with the touch function layer 20 .
  • the degree of overlap or coverage refers to the overlap area or coverage area between the winding structure 26 or the hollow portion 261 and the column 30 on the orthographic projection.
  • the larger the overlap area or coverage area the corresponding The parasitic capacitance between the cathode layer 40 and the touch function layer 20 is smaller; on the contrary, the smaller the overlapping area or the coverage area of the two, the parasitic capacitance between the cathode layer 40 and the touch function layer 20 corresponding to the column 30 is smaller. bigger.
  • the width D of the first electrode traces 23 and/or the second electrode traces 24 corresponding to the posts 30 can be configured to be smaller, so as to reduce the width of the first electrode traces 23 and/or the second electrode traces 24 corresponding to the posts 30 . /or parasitic capacitance between the second electrode trace 24 and the cathode layer 40 .
  • the width of the first electrode trace 23 and/or the second electrode trace 24 at the corresponding position of the column 30 can also be adjusted. The smaller the width of the second electrode trace 24 is, the smaller the parasitic capacitance is.
  • the larger the width of the first electrode trace 23 and/or the second electrode trace 24 is, the larger the parasitic capacitance is.
  • the DZ (Dead Zone, non-light-transmitting area) is the non-light-transmitting area of the adjacent sub-pixels 531 .
  • the hollow portion 261 is provided with a light shielding block 27 insulated from the first electrode wiring 23 and/or the second electrode wiring 24 .
  • the light-shielding block 27 may be located in the same film layer as the first electrode wiring 23 and/or the second electrode wiring 24, but is not limited to. After etching, the light-shielding block 27 and the first electrode wiring 23 and /or the second electrode wiring 24 forms electrical isolation, that is, the light shielding block 27 does not electrically flow through, therefore, the light shielding block 27 and other conductive layers, or the first electrode wiring 23 and/or the second electrode wiring There is no parasitic capacitance between lines 24, or, if there is, it is so weak that it can be ignored.
  • the light-shielding block 27 is placed in the hollow portion 261 , the light-shielding block 27 can be infinitely close to the winding structure 26 , or filled in the hollow portion 261 , but the light-shielding block 27 and the winding structure 26 are in an electrically isolated state. , so as to ensure that the light-shielding block 27 is in an insulating state, which can avoid the generation of parasitic capacitance by the light-shielding block 27 .
  • the cross-sectional shape of the light shielding block 27 is the same as the cross-sectional shape of the upright column 30 and is arranged correspondingly. It can be understood that the cross-sectional shapes of the two are the same and correspondingly arranged means that the shapes of the two are the same or similar, and the orthographic projection of one of them can be completely coincident or overlapped with the other after being scaled in an appropriate proportion. This arrangement can prevent the touch function layer 20 from having small holes that can transmit light, which may cause optical diffraction or optical interference problems in the touch function layer 20 above the pillars 30 .
  • the cross-sectional area of the light shielding block 27 is not less than 80% of the cross-sectional area of the upright post 30 , and is not larger than 120% of the cross-sectional area of the upright post 30 . It can be understood that the area relationship between the two can prevent the touch function layer 20 from having small holes that can transmit light, which may cause optical diffraction or optical interference problems in the touch function layer 20 above the pillars 30 .
  • the orthographic projection of the column 30 does not overlap with the sub-pixels 531; and the orthographic projections of the first electrode wiring 23 and/or the second electrode wiring 24 are located between adjacent sub-pixels 531, specifically, may be located in adjacent sub-pixels Right in the middle of 531.
  • a display panel or a display device may include a substrate 10 , a first buffer layer 104 , an active layer 601 , a first GI layer 15 , and a first gate layer that are stacked in sequence. 16.
  • the material of the first vapor deposition layer (CVD) 81 may be SiNx or SiON.
  • the material of the second vapor deposition layer (CVD) 83 may be SiNx or SiOx.
  • the material of the first passivation layer 203 may be SiNx.
  • a display panel or a display device may include a substrate 10 , a thin film transistor layer 60 , a light emitting functional layer 70 , an encapsulation layer 80 and a touch functional layer 90 that are stacked in sequence.
  • the substrate 10 includes a layered protective film 101 , a double PI layer 102 , a barrier layer (Barrier) 103 of SiNx/SiOx material, and a first buffer layer 104 of SiNx/SiOx material.
  • the thin film transistor layer 60 includes an active layer 601 , a gate insulating layer 602 , a gate layer 603 , an interlayer insulating layer 604 , and a source and drain layer 605 which are stacked.
  • the light-emitting functional layer 70 includes a pixel definition layer 51 , an anode layer 52 , a light-emitting layer 53 and a cathode layer 40 that are stacked.
  • the anode layer 52 includes at least one of indium tin oxide and silver.
  • the cathode layer 40 may be a lithium fluoride (LiF) material layer or a caprolactam (CPL) material layer.
  • the encapsulation layer 80 includes a first vapor deposition layer (CVD) 81 , a single inkjet layer 82 and a second vapor deposition layer (CVD) 83 that are stacked.
  • CVD first vapor deposition layer
  • CVD second vapor deposition layer
  • the touch function layer 90 includes a second buffer layer 201 , a bridging conductive layer 202 , a first passivation layer 203 , a sensing conductive layer 204 , a second passivation layer 205 , a polarizing layer 206 , an optical adhesive layer 207 and a window. Layer 208.
  • the bridging conductive layer 202 and the sensing conductive layer 204 constitute the touch function layer 20 .
  • top-emitting type flexible OLEDs are classified into two types: top-emitting type and bottom-emitting type according to different light-emitting positions.
  • the structure of the top-emitting OLED panel includes, from bottom to top, a thin film transistor array (TFT Array) substrate, an anode layer (Anode), a pixel definition layer (PDL/PS), an organic light-emitting layer (EL), a cathode layer (Cathode), A thin film encapsulation layer (TFE), and a touch electrode layer with a metal mesh (Metal Mesh) winding structure 26 located above the TFE.
  • TFT Array thin film transistor array
  • Al anode
  • PDL/PS pixel definition layer
  • EL organic light-emitting layer
  • Cathode cathode layer
  • TFE thin film encapsulation layer
  • touch electrode layer with a metal mesh (Metal Mesh) winding structure 26 located above the TFE Metal Mesh
  • the metal mesh (Metal Mesh) touch electrode layer located above the OLED thin film encapsulation layer (TFE) in the present invention includes a first electrode wiring 23 serving as a touch driving electrode and a touch sensing electrode.
  • the second electrode wiring 24, or the first electrode wiring 23 may be used as the touch sensing electrode, and the second electrode wiring 24 may be used as the touch driving electrode.
  • the touch driving electrodes and the touch sensing electrodes are connected to the touch chip (Touch IC).
  • AMOLED On-cell touch display its touch structure is a single-layer bridge structure mutual capacitance touch display, the material is hollow Metal Mesh.
  • Its cross-sectional structure includes a bridge layer, an insulating (Insulator) layer, and an electrode (Tx/Rx) layer from bottom to top; the electrode layer is located above the insulating layer, and the bridge layer is located below the insulating layer.
  • the first electrode traces 23 and the second electrode traces 24 are located on the same layer and are electrically insulated from each other; the first electrode traces 23 and the second electrode traces 24 are arranged orthogonally in the array, and are crossed at the cross position.
  • the isolated first electrode wiring 23 or the second electrode wiring 24 is connected to the bridging wiring 231 in the lower bridging layer through the intermediate insulating layer, so as to maintain electrical continuity.
  • the bridging trace 231 is connected to the cut off first electrode trace 23, the bridging trace 231 is a part of the first electrode trace 23; if the bridging trace 231 is connected to the cut off second electrode trace 24, then the bridging trace 231 is connected
  • the line 231 is a part of the second electrode trace 24 .
  • the bridge wiring 231 only occupies a small part of the first electrode wiring 23 or the second electrode wiring 24 , and may generally be composed of at least one metal wire (Mesh) with a very small number.
  • each of the first electrode wiring 23 and/or the second electrode wiring 24 includes at least one metal wire.
  • PS Photo Spacer
  • PDL pixel definition layer
  • the PDL layer is mainly used to define the specific positions of the light-emitting pixels, there are corresponding pixel openings, and are used to expose the anode electrodes (Anodes) of the corresponding light-emitting pixels, and to deposit multiple layers of light-emitting materials.
  • PS and PDL can be fabricated in one process, such as through a halftone yellow light process; then multiple layers of luminescent material (EL) are deposited on top of PS/PDL, and finally the entire cathode layer (Cathode) is fabricated on EL Above the /PS/PDL layer.
  • EL luminescent material
  • the touch electrodes include first electrode wirings 23 and second electrode wirings 24 .
  • PS is located in the middle of the gap between adjacent pixel openings on the PDL, and is fabricated on the upper surface of the PDL layer; at the same time, the Metal Mesh touch electrodes located above the EL layer/Cathode layer/Encapsulation layer (TFE) are also fabricated to avoid shading. at gap locations of adjacent PDL pixel openings.
  • TFE Electrode-Cathode layer/Encapsulation layer
  • the present disclosure provides a display panel and a display device. By arranging the wire winding structure 26 with the hollow portion 261 on the electrode traces of the touch function layer 20 , the touch function layer 20 and the cathode at the posts 30 can be reduced in size.
  • the parasitic capacitance between the layers 40 thereby balancing the overall consistency of the parasitic capacitance between the touch functional layer 20 and the cathode layer 40, avoids the noise caused by the unbalanced parasitic capacitance, and is beneficial to improve the overall touch reporting point rate and sensitivity.

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Abstract

一种显示面板和显示装置，通过在触控功能层（20）的电极走线上设置带有中空部（261）的绕线结构（26），可以减小立柱（30）处触控功能层（20）与阴极层（40）之间的寄生电容，进而均衡触控功能层（20）与阴极层（40）之间寄生电容的整体一致性，避免了由于寄生电容不均衡而带来的噪声，有利于提升整体的触控报点率及灵敏度。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及触控技术领域，具体涉及一种显示面板和显示装置。
 背景技术
柔性有机发光二极管(OLED，Organic Light-Emitting Diode )显示器具有主动发光、可视角度大、色域宽、亮度高、响应速度快、低功耗，以及结构上可弯曲等优点越来越受到市场的欢迎，有趋势逐渐取代LCD（Liquid Crystal Display，液晶显示器）成为显示技术的主流。
传统技术方案中的基板一侧设置有像素定义层（PDL，pixel define layer），像素定义层的表面设置有立柱（PS，photo spacer）。在OLED蒸镀过程中，该立柱用于支撑高精度金属掩模板（FMM，Fine Metal Mask），因此，该立柱存在一定的高度，使得其上的阴极层与触控电极层之间的距离变小，增加了寄生电容，导致触控信号受到的容抗和/或阻抗增大，其延时加长，严重影响了立柱投影区域及周边的触控灵敏度及触控报点率等。
 技术问题
本申请提供一种显示面板和显示装置，解决了由于立柱处阴极层与触控功能层之间的距离变小，导致寄生电容不均衡的问题。
 技术解决方案
第一方面，本申请提供一种显示面板，其包括：像素定义层；覆盖像素定义层的阴极层；位于像素定义层与阴极层之间的立柱；以及位于阴极层一侧且远离像素定义层的触控功能层，触控功能层设置有电极走线；其中，电极走线构造有带中空部的绕线结构，且中空部与立柱相对应，以降低立柱对应处阴极层与触控功能层之间的寄生电容。
基于第一方面，在第一方面的第一种实施方式中，立柱的正投影与中空部至少部分重叠，或者，中空部的正投影至少部分覆盖立柱。
基于第一方面，在第一方面的第二种实施方式中，绕线结构由第一宽度的电极走线围绕中空部形成；远离中空部的电极走线的宽度被配置为第二宽度，且第一宽度不大于第二宽度。
基于第一方面的第二种实施方式，在第一方面的第三种实施方式中，第一宽度不大于3微米；第二宽度不大于5微米。
基于第一方面的上述任一实施方式，在第一方面的第四种实施方式中，绕线结构与相邻的电极走线电性连接。
基于第一方面的第四种实施方式，在第一方面的第五种实施方式中，中空部设置有与电极走线相绝缘的遮光块。
基于第一方面的第五种实施方式，在第一方面的第六种实施方式中，遮光块的横截面形状与立柱的横截面形状相同。
基于第一方面的第六种实施方式，在第一方面的第七种实施方式中，遮光块的横截面面积不小于立柱的横截面面积的80%，且不大于立柱的横截面面积的120%。
基于第一方面，在第一方面的第八种实施方式中，显示面板还包括多个子像素；且电极走线的正投影位于相邻的子像素之间。
第二方面，本申请提供一种显示装置，其包括：像素定义层；覆盖像素定义层的阴极层；位于像素定义层与阴极层之间的立柱；以及位于阴极层一侧且远离像素定义层的触控功能层，触控功能层设置有第一电极走线和第二电极走线；其中，第一电极走线和/或第二电极走线构造有带中空部的绕线结构，且中空部与立柱相对应，以降低立柱对应处阴极层与触控功能层之间的寄生电容。
 附图说明
图1为本申请实施例提供的显示面板/显示装置的结构示意图之一。
图2为本申请实施例提供的触控功能层的结构示意图。
图3为本申请实施例提供的子像素与第一电极或第二电极的投影位置示意图。
图4为本申请实施例提供的子像素与绕线结构的投影位置示意图之一。
图5为本申请实施例提供的子像素与绕线结构的投影位置示意图之二。
图6为本申请实施例提供的子像素、立柱以及遮光块之间的投影位置示意图。
图7为本申请实施例提供的显示面板/显示装置的结构示意图之二。
图8为本申请实施例提供的显示面板/显示装置的结构示意图之三。
图9为图4中Y100处所示的局部放大示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1、图2所示，在其中一个实施例中，显示面板或者显示装置可以但不限于包括依次叠层设置的阳极层52、像素定义层51、发光层53、阴极层40以及触控功能层20。其中，位于像素定义层51与阴极层40之间设置有立柱30，立柱30将阴极层40的对应位置处抬高，使得立柱30对应处的阴极层40与触控功能层20之间的距离变小。鉴于此，本实施例中的触控功能层20设置有电极走线，其中电极走线构造有带中空部261的绕线结构26，中空部261与立柱30相对应，中空部261可以形成一个非电性区域，可以降低立柱30对应处的阴极层40与触控功能层20之间的电性耦合，进而降低由此而产生的寄生电容，以均衡触控功能层20与阴极层40之间寄生电容的整体一致性，避免了由于寄生电容不均衡而带来的噪声，有利于提升整体的触控报点率及灵敏度。
触控功能层20至少包括第一导电层、第二导电层以及位于第一导电层与第二导电层之间的绝缘层。第一导电层可以包括蚀刻后留存的桥接走线231；第二导电层设置有蚀刻后留存的电极走线，电极走线包括第一电极走线23和第二电极走线24；桥接走线231可以作为第一电极走线23或者第二电极走线24的一部分，在第一电极走线23与第二电极走线24交错处通过第一过孔接续第一电极走线23或者第二电极走线24，以电性隔离第一电极走线23与第二电极走线24。其中，电极走线构造有带中空部261的绕线结构26，且中空部261与立柱30相对应，以降低立柱30对应处阴极层40与触控功能层20之间的寄生电容。需要进行说明的是，本实施例中的电性隔离是指没有直接的电性连接，不排除两者可以通过第三者，例如人体或者触控笔等进行耦合的情况。
其中，如图9所示，绕线结构26由第一宽度D1的电极走线围绕中空部261形成；远离中空部261的电极走线的宽度被配置为第二宽度D2，且第一宽度D1不大于第二宽度D2。第一宽度D1不大于3微米；第二宽度D2不大于5微米。
其中，绕线结构26与相邻的电极走线电性连接，具体地，如图9所示，绕线结构26是通过第一宽度D1的电极走线与相邻的第二宽度D2的电极走线电性连接的，第一宽度D1的电极走线和第二宽度D2的电极走线的蚀刻过程可以同步形成。可以理解的是，在整个电极走线的形成过程中，如果遇到立柱30对应的位置处，则电极走线一分为二地连续设置，以避开立柱30的正投影位置处。
其中，立柱30的正投影与中空部261至少部分重叠，也可以完全重叠。或者，中空部261的正投影至少部分覆盖立柱30，也可以完全覆盖立柱30。
如图1所示，可以理解的是，在本实施例中，封装层54、触控缓冲层55可选择地叠层设置于阴极层40与触控功能层20之间。
如图1所示，在其中一个实施例中，显示面板或者显示装置还可以包括可选择地设置于触控功能层20一侧且远离所述阴极层40的钝化层56。
如图1所示，在其中一个实施例中，显示面板或者显示装置还可以包括可选择地叠层设置于阳极层52和/或像素定义层51一侧且远离发光层53的第一PI层121、第一缓冲层11、第二PI层122、第二缓冲层13、多晶硅层14、第一GI层15、第一栅极层16、第二GI层17、第二栅极层18、层间绝缘层19以及平坦层50。其中，多晶硅层14可以通过第二过孔与平坦层50连接；第二过孔依次经过第一GI层15、第二GI层17以及层间绝缘层19；至少部分的第二过孔通过位于平坦层50的第三过孔与阳极层52连接。
如图1至图6所示，在其中一个实施例中，显示面板或者显示装置中位于阴极层40一侧且远离触控功能层20的阳极层52；位于阴极层40与阳极层52之间的发光层53；其中，显示面板或者显示装置还可以包括多个子像素531；其中，像素定义层51设置有对应的像素开口，用于暴露构成各个子像素531的阳极层52，以定义子像素531对应的发光位置。发光层53位于像素开口内。
其中，第一电极走线23和/或第二电极走线24构成的金属网格的形状可以与子像素531的形状相对应。
如图4所示，需要进行说明的是，子像素531为多边形结构时，多边形结构可以为方型或者矩形等，那么限定第一电极走线23和/或第二电极走线24构成的金属网格的线型至少包括直线，即第一电极走线23和/或第二电极走线24的线型可以但不限于均为直线或者直线段，那么对应地，由此而限定出的第一电极走线23和/或第二电极走线24构成的金属网格也对应为多边形结构。
如图5所示，或者子像素531为弧形结构时，即子像素531的形状为存在曲边或者均为曲边组成的椭圆形，或者珍珠型，那么限定第一电极走线23和/或第二电极走线24构成的金属网格的线型至少包括曲线，或者均为曲线，两者的弯曲方向一致。
如图3或者图4所示，在其中一个实施例中，第一电极走线23和/或第二电极走线24的正投影与子像素531不重叠。需要进行说明的是，本实施例说明第一电极走线23和/或第二电极走线24总是位于相邻子像素531之间的空隙处，且位于空隙的正中位置。而且第一电极走线23和/或第二电极走线24的走线轨迹总是与子像素531的轮廓相一致，例如，当子像素531为多边形结构时，例如，为六边形结构时，限定的金属网格为四边形结构，那么金属网格的四边形中的任一边总是与六边形结构的其中一边相平行；当子像素531为第一曲边弧形结构时，对应地，金属网格也为第二曲边弧形结构，且第二曲边弧形结构的正投影包围第一曲边弧形结构，第二曲边弧形结构的正投影的内侧至第一曲边弧形结构的外侧的距离总是相等或者近似。
在其中一个实施例中，立柱30与像素定义层51通过半色调黄光制程同步成型，可以简化工艺，提高制程效率。
立柱30位于相邻的子像素531之间，且与发光层53不重叠。需要进行说明的是，并不是相邻的子像素531之间均设置有立柱30，而是每隔多个子像素531设置一个立柱30，其中，多个可以但不限于为8个，也可以是其它的整数个，例如4个，或者12个，或者16个等等。
具体地，如图9所示，图9为图4中Y100处所示的局部放大示意图，图中示出了中空部261、遮光块27以及立柱30在某一平面上的正投影之间的位置关系，立柱30的正投影与中空部261可以但不限于至少部分重叠，也可以是完全重叠；还可以是中空部261的正投影可以但不限于至少部分覆盖立柱30，也可以是完全覆盖，甚至中空部261的正投影覆盖立柱30及其周围的一部分区域；需要进行说明的是，通过中空部261与立柱30在对应的正投影上的重叠度或者覆盖度可以对应地调节阴极层40与触控功能层20之间的寄生电容。
需要进行说明的是，重叠度或者覆盖度是指绕线结构26或者中空部261与立柱30在正投影上两者之间的重叠面积或者覆盖面积，重叠面积或者覆盖面积越大，立柱30对应处阴极层40与触控功能层20之间的寄生电容就越小；反之，两者重叠面积或者覆盖面积越小，立柱30对应处阴极层40与触控功能层20之间的寄生电容就越大。
如图3所示，可以配置立柱30对应处的第一电极走线23和/或第二电极走线24的宽度D为较小的宽度，以降低立柱30对应处第一电极走线23和/或第二电极走线24与阴极层40之间的寄生电容。当然，也可以通过调节立柱30对应处的第一电极走线23和/或第二电极走线24的宽度，可以理解的是，在中空部261相同的情况下，第一电极走线23和/或第二电极走线24的宽度越小，寄生电容也越小，反之，第一电极走线23和/或第二电极走线24的宽度越大，寄生电容也越大。以此来实现微调立柱30对应处第一电极走线23和/或第二电极走线24与阴极层40之间的寄生电容，更有利于均衡阴极层40与触控功能层20之间的寄生电容。其中，DZ（Dead Zone，非透光区域）为相邻子像素531的非透光区域。
如图1或者图4所示，中空部261设置有与第一电极走线23和/或第二电极走线24绝缘的遮光块27。可以理解的是，该遮光块27可以但不限于与第一电极走线23和/或第二电极走线24位于同一膜层中，经过蚀刻之后，遮光块27与第一电极走线23和/或第二电极走线24形成电性隔离，即遮光块27是没有电性流经的，因此，遮光块27与其它导电层，或者，第一电极走线23和/或第二电极走线24之间不存在寄生电容，或者是，即使存在寄生电容，也是微弱到可以忽略的地步。
需要进行说明的是，遮光块27置于中空部261中，遮光块27可以无限接近于绕线结构26，或者填充于中空部261中，但是遮光块27与绕线结构26处于电性隔离状态，以保证遮光块27处于绝缘状态，可以避免由遮光块27产生寄生电容。
如图9所示，在其中一个实施例中，遮光块27的横截面形状与立柱30的横截面形状相同且对应设置。可以理解的是，两者的横截面形状相同且对应设置是指两者的形状相同或者相近，并且其中一者的正投影经过适当比例的缩放后，可以与另一者完全重合或者重叠。如此设置可以防止触控功能层20存在可以透光的小孔，而导致立柱30处上方的触控功能层20产生光学衍射或者光学干涉问题。
其中，遮光块27的横截面面积不小于立柱30的横截面面积的80%，且不大于立柱30的横截面面积的120%。可以理解的是，两者的面积关系限定可以防止触控功能层20存在可以透光的小孔，而导致立柱30处上方的触控功能层20产生光学衍射或者光学干涉问题。
立柱30的正投影与子像素531不重合；且第一电极走线23和/或第二电极走线24的正投影位于相邻的子像素531之间，具体地，可以位于相邻子像素531的正中间。
如图7所示，在其中一个实施例中，显示面板或者显示装置可以包括依次叠层设置的基板10、第一缓冲层104、有源层601、第一GI层15、第一栅极层16、第二GI层17、第二栅极层18、层间绝缘层19、源漏极层605、平坦层50、像素定义层51、阳极层52、发光层53、立柱30、阴极层40、第一气相沉积层（CVD）81、单体喷墨层82、第二气相沉积层（CVD）83、第二缓冲层201、桥接导电层202、第一钝化层203、感应导电层204以及第二钝化层205。其中，第一气相沉积层（CVD）81的材料可以为SiNx或者SiON。第二气相沉积层（CVD）83的材料可以为SiNx或者SiOx。第一钝化层203的材料可以为SiNx。
如图8所示，在其中一个实施例中，显示面板或者显示装置可以包括依次叠层设置的基板10、薄膜晶体管层60、发光功能层70、封装层80以及触控功能层90。
其中，基板10包括叠层设置的层保护膜101、双PI层102、SiNx/SiOx材料的阻障层（Barrier）103以及SiNx/SiOx材料的第一缓冲层104。
薄膜晶体管层60包括叠层设置的有源层601、栅极绝缘层602、栅极层603、层间绝缘层604以及源漏极层605。
发光功能层70包括叠层设置的像素定义层51、阳极层52、发光层53以及阴极层40。其中，阳极层52至少包括氧化铟锡、银两种材料中的一种。阴极层40可以为氟化锂（LiF）材料层或者己内酰胺（CPL）材料层。
封装层80包括叠层设置的第一气相沉积层（CVD）81、单体喷墨层82以及第二气相沉积层（CVD）83。
触控功能层90包括叠层设置的第二缓冲层201、桥接导电层202、第一钝化层203、感应导电层204、第二钝化层205、偏光层206、光学胶层207以及窗口层208。其中，桥接导电层202与感应导电层204构成触控功能层20。
在其中一个实施例中，柔性OLED按照其发光位置的不同分为顶发光型和底发光型两种。顶发光型OLED面板的结构从下往上依次包括薄膜晶体管阵列（TFT Array）基板，阳极层(Anode)，像素定义层(PDL/PS)，有机发光层(EL)，阴极层(Cathode)，薄膜封装层(TFE)，以及位于TFE上方的具有金属网格（Metal Mesh）的绕线结构26的触控电极层。
如图2所示，本发明中位于OLED 薄膜封装层（TFE）上方的金属网格（Metal Mesh）触控电极层包括作为触控驱动电极的第一电极走线23和作为触控感应电极的第二电极走线24，或者，也可以以第一电极走线23作为触控感应电极，以第二电极走线24作为触控驱动电极。其中，触控驱动电极、触控感应电极通过外围金属线路25连接至触控芯片（Touch IC）。
柔性AMOLED On-cell触控显示屏，其触控结构为单层架桥结构的互电容触控显示屏，材质为镂空的Metal Mesh。
其剖面结构从下往上依次包括桥接（Bridge）层、绝缘（Insulator）层以及电极（Tx/Rx）层；电极层位于绝缘层上方，桥接层极位于绝缘层下方。
第一电极走线23与第二电极走线24位于同一层，彼此之间电性绝缘；第一电极走线23与第二电极走线24阵列正交排布，并且在十字交叉位置处被隔断的第一电极走线23或者第二电极走线24透过中间的绝缘层，与下方的桥接层中桥接走线231连接，从而保持电性连续导通。
如果桥接走线231连接被隔断的第一电极走线23，则桥接走线231为第一电极走线23的一部分；如果桥接走线231连接被隔断的第二电极走线24，则桥接走线231为第二电极走线24的一部分。桥接走线231只占据第一电极走线23或者第二电极走线24的一小部分，通常可以由数量极少的至少一根金属线（Mesh）构成。
可以理解的是，第一电极走线23和/或第二电极走线24均至少包括一根金属线。
AMOLED Array基板上存在立柱30（PS，Photo Spacer）/像素定义层（PDL），PS是位于PDL表面上按照一定规律散布的立柱，用于在蒸镀RGB发光像素（Pixel）的制程中支撑FMM（Fine Metal Mask，高精度金属掩模板-在OLED蒸镀过程中用到）；如在PDL表面上，每间隔8个子像素（Sub-pixel）531设置一个PS立柱。
PDL层主要是用来定义发光像素的具体位置，存在对应的像素开口，用于暴露对应的发光像素的阳极电极（Anode），以及沉积多层发光材料。
PS与PDL可在一道制程中制作完成，如通过半色调（Halftone）黄光制程制作；接着多层发光材料（EL）沉积在PS/PDL上方，最后整面的阴极层（Cathode）制作在EL/PS/PDL层上方。
由于立柱30存在一定的高度，因此沉积在PS上方的Cathode与上方触控电极之间的距离相比沉积在非PS立柱位置处的Cathode与上方触控电极之间的距离更小。其中，触控电极包括第一电极走线23和第二电极走线24。
通常，PS位于PDL上相邻像素开口的中间间隙位置处，制作在PDL层的上表面；同时位于EL层/Cathode层/封装层（TFE）上方的Metal Mesh触控电极为了避免遮光，同样制作在相邻PDL像素开口的间隙位置处。
通常，PS立柱与Metal Mesh触控电极在垂直方向上存在重叠；因此，PS位置处上方触控电极的寄生电容比非PS位置处上方触控电极的寄生电容更大；更大的寄生电容会导致更大的显示噪声耦合，同时更大的寄生电容会导致触控信号的阻容延迟（RC Delay）更大，从而影响触控报点率以及灵敏度等特性。鉴于此，本公开提供了显示面板和显示装置，通过在触控功能层20的电极走线上设置带有中空部261的绕线结构26，可以减小立柱30处触控功能层20与阴极层40之间的寄生电容，进而均衡触控功能层20与阴极层40之间寄生电容的整体一致性，避免了由于寄生电容不均衡而带来的噪声，有利于提升整体的触控报点率及灵敏度。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    像素定义层；
    覆盖所述像素定义层的阴极层；
    位于所述像素定义层与所述阴极层之间的立柱；以及
    位于所述阴极层一侧且远离所述像素定义层的触控功能层，所述触控功能层设置有电极走线；
    其中，所述电极走线构造有带中空部的绕线结构，且所述中空部与所述立柱相对应，以降低所述立柱对应处所述阴极层与所述触控功能层之间的寄生电容；
    其中，所述显示面板还包括多个子像素；且所述电极走线的正投影位于相邻的所述子像素之间。
  2. 根据权利要求1所述的显示面板，其中，所述立柱的正投影与所述中空部至少部分重叠，或者，所述中空部的正投影至少部分覆盖所述立柱。
  3. 根据权利要求1所述的显示面板，其中，所述绕线结构由第一宽度的所述电极走线围绕所述中空部形成；远离所述中空部的所述电极走线的宽度被配置为第二宽度，且所述第一宽度不大于所述第二宽度。
  4. 根据权利要求3所述的显示面板，其中，所述第一宽度不大于3微米；所述第二宽度不大于5微米。
  5. 根据权利要求1所述的显示面板，其中，所述绕线结构与相邻的所述电极走线电性连接。
  6. 根据权利要求5所述的显示面板，其中，所述中空部设置有与所述电极走线相绝缘的遮光块。
  7. 根据权利要求6所述的显示面板，其中，所述遮光块的横截面形状与所述立柱的横截面形状相同。
  8. 一种显示面板，其中，包括：
    像素定义层；
    覆盖所述像素定义层的阴极层；
    位于所述像素定义层与所述阴极层之间的立柱；以及
    位于所述阴极层一侧且远离所述像素定义层的触控功能层，所述触控功能层设置有电极走线；
    其中，所述电极走线构造有带中空部的绕线结构，且所述中空部与所述立柱相对应，以降低所述立柱对应处所述阴极层与所述触控功能层之间的寄生电容。
  9. 根据权利要求8所述的显示面板，其中，所述立柱的正投影与所述中空部至少部分重叠，或者，所述中空部的正投影至少部分覆盖所述立柱。
  10. 根据权利要求8所述的显示面板，其中，所述绕线结构由第一宽度的所述电极走线围绕所述中空部形成；远离所述中空部的所述电极走线的宽度被配置为第二宽度，且所述第一宽度不大于所述第二宽度。
  11. 根据权利要求10所述的显示面板，其中，所述第一宽度不大于3微米；所述第二宽度不大于5微米。
  12. 根据权利要求8所述的显示面板，其中，所述绕线结构与相邻的所述电极走线电性连接。
  13. 根据权利要求12所述的显示面板，其中，所述中空部设置有与所述电极走线相绝缘的遮光块。
  14. 根据权利要求13所述的显示面板，其中，所述遮光块的横截面形状与所述立柱的横截面形状相同。
  15. 根据权利要求14所述的显示面板，其中，所述遮光块的横截面面积不小于所述立柱的横截面面积的80%，且不大于所述立柱的横截面面积的120%。
  16. 一种显示装置，其中，包括：
    像素定义层；
    覆盖所述像素定义层的阴极层；
    位于所述像素定义层与所述阴极层之间的立柱；以及
    位于所述阴极层一侧且远离所述像素定义层的触控功能层，所述触控功能层设置有第一电极走线和第二电极走线；
    其中，所述第一电极走线和/或第二电极走线构造有带中空部的绕线结构，且所述中空部与所述立柱相对应，以降低所述立柱对应处所述阴极层与所述触控功能层之间的寄生电容。
  17. 根据权利要求16所述的显示装置，其中，所述立柱的正投影与所述中空部至少部分重叠，或者，所述中空部的正投影至少部分覆盖所述立柱。
  18. 根据权利要求16所述的显示装置，其中，所述绕线结构由第一宽度的所述第一电极走线或者所述第二电极走线围绕所述中空部形成；远离所述中空部的所述第一电极走线或者所述第二电极走线的宽度被配置为第二宽度，且所述第一宽度不大于所述第二宽度。
  19. 根据权利要求18所述的显示装置，其中，所述第一宽度不大于3微米；所述第二宽度不大于5微米。
  20. 根据权利要求17所述的显示装置，其中，所述绕线结构与相邻的所述第一电极走线或者所述第二电极走线电性连接。
PCT/CN2020/110375 2020-08-11 2020-08-21 显示面板和显示装置 WO2022032704A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114995683A (zh) * 2022-08-04 2022-09-02 湖南兴威新材料有限公司 一种单面电容式触摸屏及制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112349761A (zh) * 2020-11-11 2021-02-09 深圳市华星光电半导体显示技术有限公司 一种显示面板、制程方法和显示装置
CN113629108B (zh) * 2021-07-19 2023-07-25 武汉华星光电技术有限公司 显示面板和显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103472951A (zh) * 2013-09-13 2013-12-25 京东方科技集团股份有限公司 一种触摸屏及其制作方法、显示装置
CN203535595U (zh) * 2013-09-13 2014-04-09 京东方科技集团股份有限公司 一种触摸屏及显示装置
US20160202817A1 (en) * 2015-01-14 2016-07-14 Samsung Display Co., Ltd. Display device
CN106371649A (zh) * 2015-07-20 2017-02-01 瑞鼎科技股份有限公司 内嵌式触控面板
CN107342370A (zh) * 2017-07-06 2017-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN206696569U (zh) * 2017-05-24 2017-12-01 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN110286803A (zh) * 2019-06-28 2019-09-27 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN212277199U (zh) * 2020-08-11 2021-01-01 武汉华星光电半导体显示技术有限公司 显示面板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106919284A (zh) * 2017-02-27 2017-07-04 京东方科技集团股份有限公司 触控基板及其制作方法、电子装置
TWI615764B (zh) * 2017-04-14 2018-02-21 智晶光電股份有限公司 有機發光二極體觸控面板
TWI627577B (zh) * 2017-12-25 2018-06-21 友達光電股份有限公司 觸控顯示裝置
CN110137206A (zh) * 2018-02-09 2019-08-16 京东方科技集团股份有限公司 一种像素排布结构及相关装置
CN110752246A (zh) * 2019-11-13 2020-02-04 昆山国显光电有限公司 一种阵列基板及显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103472951A (zh) * 2013-09-13 2013-12-25 京东方科技集团股份有限公司 一种触摸屏及其制作方法、显示装置
CN203535595U (zh) * 2013-09-13 2014-04-09 京东方科技集团股份有限公司 一种触摸屏及显示装置
US20160202817A1 (en) * 2015-01-14 2016-07-14 Samsung Display Co., Ltd. Display device
CN106371649A (zh) * 2015-07-20 2017-02-01 瑞鼎科技股份有限公司 内嵌式触控面板
CN206696569U (zh) * 2017-05-24 2017-12-01 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN107342370A (zh) * 2017-07-06 2017-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN110286803A (zh) * 2019-06-28 2019-09-27 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN212277199U (zh) * 2020-08-11 2021-01-01 武汉华星光电半导体显示技术有限公司 显示面板和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114995683A (zh) * 2022-08-04 2022-09-02 湖南兴威新材料有限公司 一种单面电容式触摸屏及制作方法

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