WO2021097798A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021097798A1
WO2021097798A1 PCT/CN2019/120221 CN2019120221W WO2021097798A1 WO 2021097798 A1 WO2021097798 A1 WO 2021097798A1 CN 2019120221 W CN2019120221 W CN 2019120221W WO 2021097798 A1 WO2021097798 A1 WO 2021097798A1
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WIPO (PCT)
Prior art keywords
area
layer
conductive pattern
insulating layer
base substrate
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PCT/CN2019/120221
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English (en)
French (fr)
Inventor
张波
董向丹
王蓉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2021569265A priority Critical patent/JP7343614B2/ja
Priority to CN201980002552.7A priority patent/CN113169216B/zh
Priority to EP19945439.8A priority patent/EP4064356A4/en
Priority to PCT/CN2019/120221 priority patent/WO2021097798A1/zh
Priority to US16/977,526 priority patent/US11882734B2/en
Publication of WO2021097798A1 publication Critical patent/WO2021097798A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the packaging technology of OLED display devices mainly includes cover type packaging and thin film packaging.
  • Thin-film encapsulation mainly includes encapsulation using an organic encapsulation layer and/or encapsulation using an inorganic encapsulation layer.
  • At least one embodiment of the present disclosure provides a display substrate that includes a display area and a peripheral area surrounding the display area; wherein the display area includes an opening, and the peripheral area includes a second at least partially surrounding the opening.
  • the display substrate includes a base substrate, a first conductive semiconductor pattern, a first conductive pattern, and a second conductive pattern;
  • a conductive semiconductor pattern is located on the base substrate, the first conductive pattern is located on the side of the first conductive semiconductor pattern away from the base substrate, and the first conductive semiconductor pattern
  • the second conductive pattern is located at a side of the first conductive pattern away from the first conductive semiconductor pattern, and is insulated at intervals to form a capacitor, and is insulated from the
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first insulating layer and a second insulating layer; wherein the first insulating layer is located on a part of the first conductive semiconductor pattern away from the base substrate.
  • the first conductive pattern is located on the side of the first insulating layer away from the first conductive semiconductor pattern
  • the second insulating layer is located on the side of the first conductive pattern away from the first insulating layer
  • the second conductive pattern is located on the side of the second insulating layer away from the first conductive pattern
  • the plurality of vias are located at least in the first insulating layer and the second insulating layer and It penetrates at least the first insulating layer and the second insulating layer.
  • the arrangement density of the plurality of vias in the spacer area is zero.
  • the first conductive semiconductor pattern and the second conductive pattern are also located in the second dam area.
  • the first conductive pattern is also located in the second dam area.
  • the arrangement density of the plurality of vias in the spacer area is smaller than the arrangement density in the second dam area.
  • the orthographic projection of the second conductive pattern on the base substrate and the second insulating layer on the base substrate overlap, and the orthographic projection area of the second conductive pattern on the base substrate is equal to the orthographic projection area of the second insulating layer on the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first electrode layer; wherein, the first electrode layer is located on a side of the second conductive pattern away from the base substrate and is electrically connected to the second conductive pattern.
  • the pattern is electrically connected; in the spacer area, the first electrode layer covers the second conductive pattern, and the surface of the first electrode layer facing the base substrate and the second conductive pattern The surface of the side facing away from the base substrate is in contact with each other.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first encapsulation layer; wherein the first encapsulation layer is located on a side of the first electrode layer away from the base substrate; in the spacer area , The first encapsulation layer covers the first electrode layer, and the surface of the first encapsulation layer facing the base substrate and the side of the first electrode layer facing away from the base substrate Surface contact.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first cofferdam structure and a second cofferdam structure, wherein the first cofferdam structure is located in the first cofferdam area, and the second cofferdam structure is The weir structure is located in the second cofferdam area; in the first cofferdam area, the first cofferdam structure is located on the side of the first electrode layer away from the base substrate, and the first package Layer is located on the side of the first cofferdam structure away from the first electrode layer and covers the first cofferdam structure; in the second cofferdam area, the second cofferdam structure is located in the second The conductive pattern is away from one side of the base substrate and a part of the second dam structure covers the first electrode layer. The first encapsulation layer is located on the first electrode layer and the second dam structure is far away One side of the second conductive pattern covers the first electrode layer and the second dam structure.
  • the surface of the portion of the first encapsulation layer located in the first dam area facing away from the base substrate is between the surface of the base substrate and the base substrate.
  • the maximum distance between the first encapsulation layer is greater than the maximum distance between the surface of the part of the first encapsulation layer located in the spacer area and the side facing away from the base substrate and the base substrate, and the first encapsulation layer is located at the The maximum distance between the surface of the portion of the second dam area facing away from the base substrate and the base substrate is greater than that of the portion of the first encapsulation layer located in the spacer area away from the liner.
  • the maximum distance between the surface of one side of the base substrate and the base substrate is greater than that of the portion of the first encapsulation layer located in the spacer area away from the liner.
  • the surface of the portion of the first encapsulation layer located in the first dam area facing away from the base substrate is between the surface of the base substrate and the base substrate.
  • the maximum distance therebetween is smaller than the maximum distance between the surface of the part of the first encapsulation layer that is located in the second dam area and the side away from the base substrate and the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a third insulating layer, a fourth insulating layer, and a fifth insulating layer located in the first peripheral region except for the spacer region; wherein, the first insulating layer
  • the dam structure includes a stack of the fourth insulating layer and the fifth insulating layer, and the second dam structure includes the third insulating layer, the fourth insulating layer, and the fifth insulating layer.
  • the fourth insulating layer is located on the side of the first electrode layer away from the base substrate, and the fifth insulating layer is located away from the fourth insulating layer
  • the first packaging layer is located on the side of the fifth insulating layer away from the fourth insulating layer, and covers a side of the fifth insulating layer away from the base substrate Side surface, at least one side surface of the fifth insulating layer, and at least one side surface of the fourth insulating layer
  • the third insulating layer is located at the The second conductive pattern is far away from the base substrate, the first electrode layer covers a part of the surface of the third insulating layer facing away from the base substrate, and the third insulating layer is close to the On the side surface of one side of the first dam, the fourth insulating layer is located on the side of the third insulating layer and the first electrode layer away from the second conductive pattern, and the fifth insulating layer is located The fourth insulating layer is located
  • the third insulating layer covers a part of the surface of the second conductive pattern on the side facing away from the base substrate And the side surface of the second conductive pattern away from the side of the first dam area.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a second encapsulation layer; wherein, the second encapsulation layer is located on a side of the first encapsulation layer away from the first electrode layer and covers the first encapsulation layer. Encapsulation layer.
  • the first conductive pattern includes a plurality of first traces arranged side by side in a first direction
  • the first conductive semiconductor pattern includes a second conductive pattern.
  • a plurality of second traces arranged in parallel in a direction, the first direction is different from the second direction.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a pixel structure located in the display area, wherein the pixel structure includes a pixel drive circuit located on the base substrate, and the pixel drive circuit includes a thin film transistor.
  • a storage capacitor the thin film transistor includes a gate, an active layer, a source and a drain, the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode, the active The layer is arranged in the same layer as the first conductive semiconductor pattern, the second capacitor electrode is arranged in the same layer as the first conductive pattern, and the source electrode and the drain electrode are arranged in the same layer as the second conductive pattern Set up.
  • the first capacitor electrode and the gate electrode are provided in the same layer.
  • the pixel structure further includes a first planarization layer and a light-emitting element, and the first planarization layer is located on the pixel drive circuit away from the base substrate.
  • One side is provided with a first planarized surface and includes a first via, and the light-emitting element is on the first planarized surface and is electrically connected to the pixel driving circuit through the first via, wherein
  • the display substrate includes the third insulating layer, the third insulating layer and the first planarization layer are provided in the same layer.
  • At least one embodiment of the present disclosure further provides a display substrate including a display area and a peripheral area surrounding the display area; wherein the display area includes an opening, and the peripheral area includes a display area at least partially surrounding the opening.
  • the display substrate includes a base substrate, a first conductive semiconductor pattern, a first conductive pattern, and a second conductive pattern;
  • the first conductive semiconductor pattern is located on the base substrate, and the first conductive pattern is located on the side of the first conductive semiconductor pattern away from the base substrate.
  • the patterns are insulated at intervals to form a capacitor, and the second conductive pattern is located on a side of the first conductive pattern away from the first conductive semiconductor pattern, and is insulated from the first conductive pattern to form a capacitor.
  • the first conductive pattern is configured to transmit electrical signals for the display area; the second conductive pattern is connected to the first conductive pattern through a plurality of vias provided in the first peripheral area
  • the semiconductor patterns are electrically connected; the first conductive semiconductor pattern, the first conductive pattern, and the second conductive pattern are located at least in the second dam area and the spacer area, and the plurality of vias are in The arrangement density of the spacer area is less than the arrangement density of the second cofferdam area.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate according to any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for preparing a display substrate, including: providing a base substrate; forming a first conductive semiconductor pattern on the base substrate; and forming a first conductive semiconductor pattern on the first conductive semiconductor pattern Forming a first conductive pattern, wherein the first conductive pattern is insulated from the first conductive semiconductor pattern so as to be able to form a capacitor; and a second conductive pattern is formed on the first conductive pattern, wherein The second conductive pattern is insulated from the first conductive pattern so as to be able to form a capacitor; wherein, the display substrate includes a display area and a peripheral area surrounding the display area, the display area includes an opening, and the peripheral area Includes a first peripheral area at least partially surrounding the opening; the first peripheral area includes a first cofferdam area, a second cofferdam area, and a spacer area, the first cofferdam area at least partially surrounds the opening, so The spacer area at least partially surrounds the first cofferdam area, and the second cofferdam area at
  • forming the first conductive pattern on the first conductive semiconductor pattern includes: forming the first conductive pattern on the first conductive semiconductor pattern Forming a first insulating layer, and forming the first conductive pattern on the first insulating layer; forming the second conductive pattern on the first conductive pattern includes: forming on the first conductive pattern A second insulating layer, and forming the second conductive pattern on the second insulating layer; wherein the plurality of vias are located at least in the first insulating layer and the second insulating layer and penetrate at least The first insulating layer and the second insulating layer.
  • the method for preparing a display substrate further includes: forming a first electrode layer on the second conductive pattern; wherein the first electrode layer is electrically connected to the second conductive pattern; In the spacer area, the first electrode layer covers the second conductive pattern, and the surface of the first electrode layer on the side facing the base substrate and the second conductive pattern are away from the liner. The surface of one side of the base substrate is in contact.
  • the method for preparing a display substrate further includes: forming a first encapsulation layer on the first electrode layer; wherein, in the spacer area, the first encapsulation layer covers the The first electrode layer, and the surface of the first encapsulation layer facing the base substrate is in contact with the surface of the first electrode layer facing away from the base substrate.
  • the method for manufacturing a display substrate further includes: forming a pixel drive circuit with a pixel structure on the base substrate in the display area; wherein the pixel drive circuit includes a thin film transistor and A storage capacitor, the thin film transistor includes a gate, an active layer, a source and a drain, the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode; the active layer It is arranged in the same layer as the first conductive semiconductor pattern, the second capacitor electrode is arranged in the same layer as the first conductive pattern, and the source electrode and the drain electrode are arranged in the same layer as the second conductive pattern .
  • the first capacitor electrode and the gate electrode are provided in the same layer.
  • FIG. 1 is a schematic plan view of an OLED display device
  • FIG. 2A is a schematic plan view of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 2B is a schematic plan view of the first peripheral area of the display substrate shown in FIG. 2A;
  • 2C is a schematic diagram of a partial cross-sectional structure of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3 is a schematic plan view of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of another partial cross-sectional structure of a display substrate provided by some embodiments of the present disclosure.
  • 6A and 6B are schematic diagrams of an arrangement of a plurality of via holes in a first peripheral area provided by some embodiments of the present disclosure
  • FIG. 7 is a schematic diagram of another partial cross-sectional structure of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 8 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided by some embodiments of the present disclosure.
  • 9A-9E are schematic diagrams of various layers of a pixel driving circuit in a display substrate provided by some embodiments of the present disclosure.
  • two barrier structures with different heights are provided in the frame area surrounding the display area to prevent water vapor or oxygen from penetrating into the interior of the display device, so as to avoid affecting the various functions of the display device. Layers cause undesirable effects.
  • the height of the cofferdam structure far away from the display area is set to be slightly larger than the height of the cofferdam structure close to the display area, and the organic film layers such as the pixel defining layer and the flat layer between the two cofferdam structures are exhausted. Possibly all are removed to form a "trench" area, and the encapsulation layer formed after encapsulation can effectively block, for example, water vapor or oxygen from penetrating into the interior of the display device.
  • FIG. 1 is a schematic plan view of an OLED display device.
  • the OLED display device 10 includes a display area 101 and a frame area 102 surrounding the display area 101.
  • the display area 101 is designed as an irregular shape having a notch 103 on at least one side. 10 can arrange devices such as a camera, a distance sensor, etc. in the area of the notch 103, thereby helping to realize a narrow frame display device.
  • two cofferdam structures with different heights can be set in the frame area 102 surrounding the display area 101, and the two cofferdam structures
  • the organic film layers such as the pixel defining layer and the flat layer are removed as much as possible to form a "trench" area.
  • the formed packaging layer can effectively block, for example, water vapor or oxygen from penetrating into the interior of the display device of the display device 10.
  • the display area 101 has the notch 103, it is usually necessary to provide a plurality of metal traces in the frame area 102 surrounding the notch 103 to electrically connect the rows of pixel units in the display area 101 on both sides of the notch 103.
  • a scanning signal for the multi-row pixel unit and the like are provided.
  • multiple signal compensation traces are usually designed under the metal traces so that capacitance can be formed between the signal compensation traces and the metal traces, thereby improving the metal traces.
  • the transmission load is compensated for the electrical signal transmission effect of the metal traces, thereby avoiding display abnormalities in the pixel units in the display area 101 located on both sides of the notch 103.
  • the frame area 102 is provided with auxiliary electrodes (and other electrodes covering and in contact with the auxiliary electrodes).
  • the multiple signal compensation traces are electrically connected to power signal lines that provide, for example, drive current signals or drive voltage signals, so that the multiple A signal compensation trace receives electrical signals required to form a compensation capacitor.
  • the auxiliary electrode is usually arranged above the plurality of signal compensation wires and the metal wires (that is, on the side close to the packaging layer), and is electrically connected to the signal compensation wires through a plurality of via holes provided in the frame area 102.
  • some metal traces need to be arranged in the "trench" area.
  • signal compensation traces also need to extend to the "trench" area to form a capacitance between the metal traces located in the "trench” area, so auxiliary electrodes and signal compensation traces need to be opened in the "trench” area Multiple vias for electrical connection.
  • the encapsulation layer formed will cover and directly in the "groove" area.
  • the surface of the film layer of the auxiliary electrode or other electrode covering the auxiliary electrode.
  • the multiple vias provided between the auxiliary electrode and the signal compensation trace will cause multiple pits on the surface of the auxiliary electrode (or other electrodes covering the auxiliary electrode), resulting in an up-and-down shape on the surface of the film. Uneven.
  • the film surface of the encapsulation layer formed on the auxiliary electrode will also be correspondingly undulating, resulting in
  • the film surface of the encapsulation layer becomes uneven, which makes the film surface of the encapsulation layer prone to cracks.
  • the generated cracks are easy to expand along the packaging layer and cause damage to the packaging layer, making it impossible or difficult for the packaging layer to prevent water vapor or oxygen from penetrating into the interior of the display device, resulting in corrosion or failure of the functional layer in the display device.
  • the performance of the display device causes serious adverse effects, thereby greatly reducing the yield of the display device and shortening the service life of the display device.
  • At least one embodiment of the present disclosure provides a display substrate including a display area and a peripheral area surrounding the display area.
  • the display area includes an opening, and the peripheral area includes a first peripheral area at least partially surrounding the opening;
  • the first peripheral area includes a first cofferdam area, a second cofferdam area, and a spacer area, the first cofferdam area at least partially surrounds the opening, and the spacer area
  • the first cofferdam area at least partially surrounds, and the second cofferdam area at least partially surrounds the spacer area.
  • the display substrate includes a base substrate, a first conductive semiconductor pattern, a first conductive pattern, and a second conductive pattern; the first conductive semiconductor pattern is located on the base substrate; the first conductive pattern is located on the first conductive semiconductor pattern The side far away from the base substrate is insulated from the first conductive semiconductor pattern to form a capacitor; the second conductive pattern is located on the side of the first conductive pattern away from the first conductive semiconductor pattern, and the first conductive pattern
  • the first conductive pattern is configured to transmit electrical signals for the display area; the second conductive pattern is electrically connected to the first conductive semiconductor pattern through a plurality of vias provided in the first peripheral area.
  • the first conductive semiconductor pattern, the first conductive pattern, and the second conductive pattern are located at least in the first dam area and the spacer area, and the arrangement density of a plurality of vias in the spacer area is less than that in the first dam area
  • the distribution density for example, the distance between adjacent via holes in the spacer area is greater than the distance between adjacent via holes in the first dam area.
  • the display substrate provided by the above-mentioned embodiments of the present disclosure reduces the arrangement density of the plurality of via holes in the spacer region that electrically connect the second conductive pattern with the first conductive semiconductor pattern, thereby weakening the second conductive pattern in the spacer region.
  • the up and down phenomenon of the patterned film surface due to the design of the via hole makes the film surface of the second conductive pattern flatter, and in turn covers the first electrode layer of the second conductive pattern and the film surface of the encapsulation layer Both can become flatter, thereby reducing or avoiding cracks on the surface of the packaging layer.
  • the display substrate provided by the above-mentioned embodiments of the present disclosure can improve the uniformity and consistency of the prepared packaging layer, and improve the packaging effect of the packaging layer on the display substrate, thereby effectively preventing water vapor or oxygen from penetrating into the interior of the display device. It causes adverse effects such as corrosion or failure on the functional layer of the display device, thereby improving the performance and yield of the display substrate, and prolonging the service life of the display substrate.
  • FIG. 2A is a schematic plan view of a display substrate provided by some embodiments of the present disclosure
  • FIG. 2B is a schematic plan view of a first peripheral area of the display substrate shown in FIG. 2A
  • FIG. 2C is a display provided by some embodiments of the present disclosure.
  • FIG. 2C is a schematic cross-sectional structure diagram of the display substrate shown in FIG. 2A along the line A-A'.
  • the display substrate 20 includes a display area 201 and a peripheral area 202 surrounding the display area 201.
  • the display area 201 includes an opening.
  • the opening may be a closed opening or a non-closed opening.
  • Devices such as a camera and a distance sensor may be arranged in the area where the opening is located, thereby helping to realize a narrow-frame display device.
  • the opening may be a notch (an example of a non-closed opening) formed on at least one side of the display area 201 as shown in FIG. 2A, and the peripheral area 202 includes a first peripheral area 203 at least partially surrounding the opening.
  • the first peripheral area 203 includes a first cofferdam area 204, a second cofferdam area 205, and a spacer area 206.
  • the first cofferdam area 204 at least partially surrounds the opening, and the spacer area 206 at least partially surrounds the first cofferdam area 204, and the second cofferdam area 204 at least partially surrounds the opening.
  • the cofferdam area 205 at least partially surrounds the spacer area 206, so that the first cofferdam area 204, the spacer area 206, and the second cofferdam area 205 are arranged from near to far relative to the opening.
  • the display substrate 20 includes a base substrate 210, a first conductive semiconductor pattern 220, a first conductive pattern 230, and a second conductive pattern 240.
  • the first conductive semiconductor pattern 220 is located on the base substrate 210;
  • the first conductive pattern 230 is located on the side of the first conductive semiconductor pattern 220 away from the base substrate 210, and is arranged at intervals and insulated from the first conductive semiconductor pattern 220 In order to be able to form a capacitor;
  • the second conductive pattern 240 is located on the side of the first conductive pattern 230 away from the first conductive semiconductor pattern 220, and is arranged at intervals and insulated from the first conductive pattern 230 to be able to form a capacitor.
  • the first conductive pattern 230 is configured to transmit an electrical signal for the display area 201.
  • the electrical signal may be one of a gate scan signal, a light emission control signal, a reset signal, etc., for a pixel driving circuit in the display area 201.
  • the second conductive pattern 240 is electrically connected to the first conductive semiconductor pattern 220 through a plurality of via holes 250 provided in the first peripheral region 203.
  • the first conductive semiconductor pattern 220, the first conductive pattern 230, and the second conductive pattern 240 are located at least in the first dam region 204 and the spacer region 206.
  • the arrangement density of the plurality of vias 250 in the spacer region 206 is less than that in the first conductive pattern.
  • the first conductive pattern 230 includes a plurality of first traces 231 arranged in parallel along the first direction R1
  • the first conductive semiconductor pattern 220 includes For the multiple second wirings 221 arranged in parallel in the direction R2, the first direction R1 is different from the second direction R2.
  • the first direction R1 may be perpendicular to the second direction R2, so that the plurality of first wirings 231 and the plurality of second wirings 221 are respectively arranged in a cross, so that the plurality of first wirings 231 and the plurality of second wirings Capacitors can be formed between the two traces 221, thereby increasing the transmission load of the multiple first traces 231, compensating for the electrical signal transmission effect on the multiple first traces 231, and making the display effect of each part in the display area 201 It can be uniform and consistent.
  • a via 250 is provided between two adjacent first traces 231; and in the spacer area In 206, one via is provided for every two first traces 231, and the distance between adjacent vias 250 in the spacer area 206 is greater than the distance between adjacent vias 250 in the first dam area 204 The distance makes the arrangement density of the vias 250 in the spacer area 206 smaller than the arrangement density in the first dam area 204.
  • the up and down fluctuations of the surface of the second conductive pattern 240 located in the spacer region 206 due to the via hole design can be reduced.
  • This phenomenon further flattens the film surface of the second conductive pattern 240.
  • the surface of the structural layer or the functional layer (for example, the first electrode layer 270 mentioned below) that covers the second conductive pattern 240, which faces away from the base substrate 210, can be made flatter, so that the surface of the display substrate 20 is flatter.
  • the surface of the formed encapsulation layer (for example, the first encapsulation layer 281 mentioned below) on the side away from the base substrate 210 can be made flatter, thereby reducing or avoiding cracks on the surface of the encapsulation layer , Improve the uniformity and consistency of the prepared encapsulation layer. Therefore, in the above-mentioned embodiment, the packaging effect of the display substrate 20 can be significantly improved, which can effectively prevent water vapor or oxygen from penetrating into the interior of the display device of the display substrate 20 and causing adverse effects on the display device, thereby improving the display substrate 20. The performance and yield rate of the display substrate are improved, and the service life of the display substrate 20 is extended.
  • a via 250 is provided between two adjacent first traces 231; in the spacer area 206 , A via is provided every two first wires 231 apart.
  • a via 250 may be provided in the first cofferdam area 204 between two adjacent first traces 231; in the spacer area 206, each Three or more first traces 231 are provided with a via 250.
  • a via 250 may be provided in the first cofferdam area 204 for every n (n is an integer greater than 1) first traces 231; in the spacer area 206 A via 250 is provided for every first wiring 231 separated by n+m (m is an integer greater than 0). That is, in the embodiment of the present disclosure, as long as the arrangement density of the multiple vias in the spacer area is less than the arrangement density in the first cofferdam area, the embodiment of the present disclosure compares the spacer area and the first cofferdam area. There are no restrictions on the specific arrangement or number of vias.
  • the specific number of the first traces 231 arranged along the first direction R1 in the first cofferdam region 204 and the spacer region 206 is only an exemplary illustration.
  • the number of the first wiring 231 may be determined according to the number of rows of pixel units located on both sides of the opening in the display area 201 or according to different actual requirements, and the first wiring 231
  • the number of first traces 231 arranged in the weir region 204 and the spacer region 206 can be based on, for example, the actual size of the first cofferdam region 204 and the spacer region 206, and the setting requirements of the first trace 231 (for example, the first trace 231 Width, etc.) are adjusted accordingly, which is not limited in the embodiments of the present disclosure.
  • the widths of the first cofferdam region 204, the spacer region 206, and the second cofferdam region 205 in the first direction R1 can all be set to about 40 ⁇ m, for example, Within the range of 35 ⁇ m ⁇ 45 ⁇ m.
  • the display substrate 20 further includes a first insulating layer 261 and a second insulating layer 262.
  • the first insulating layer 261 is located on the side of the first conductive semiconductor pattern 220 away from the base substrate 210
  • the first conductive pattern 230 is located on the side of the first insulating layer 261 away from the first conductive semiconductor pattern 220
  • the second insulating layer 261 is located away from the first conductive semiconductor pattern 220.
  • the layer 262 is located on the side of the first conductive pattern 230 away from the first insulating layer 261
  • the second conductive pattern 240 is located on the side of the second insulating layer 262 away from the first conductive pattern 230.
  • the plurality of via holes 250 are located at least in the first insulating layer 261 and the second insulating layer 262 and penetrate at least the first insulating layer 261 and the second insulating layer 262.
  • the plurality of second traces 221 in the first conductive semiconductor pattern 220 and the plurality of first traces 231 in the first conductive pattern 230 use the first insulating layer 261 as a dielectric material to form a capacitor, thereby improving
  • the transmission load of the multiple first wirings 231 compensates the electrical signal transmission effect on the multiple first wirings 231, so that the display effect of each part of the display area 201 of the display substrate 20 can be kept uniform.
  • the display substrate 20 further includes a first electrode layer 270.
  • the first electrode layer 270 is located on a side of the second conductive pattern 240 away from the base substrate 210 and is electrically connected to the second conductive pattern 240.
  • the first electrode layer 270 covers the second conductive pattern 240, and the surface of the first electrode layer 270 on the side facing the base substrate 210 and the surface of the second conductive pattern 240 on the side facing away from the base substrate 210 contact.
  • the display substrate 20 further includes a first encapsulation layer 281.
  • the first encapsulation layer 281 is located on the side of the first electrode layer 270 away from the base substrate 210. In the spacer region 206, the first encapsulation layer 281 covers the first electrode layer 270, and the surface of the first encapsulation layer 281 on the side facing the base substrate 210 and the surface of the first electrode layer 270 on the side facing away from the base substrate 210 contact.
  • the up-and-down phenomenon of the surface of the second conductive pattern 240 located in the spacer region 206 due to the via design is reduced.
  • the film surface of the second conductive pattern 240 becomes flatter, so that the film surface of the first electrode layer 270 covering the second conductive pattern 240 and the film layer of the first encapsulation layer 281 covering the first electrode layer 270 can both become It is flatter, thereby reducing or avoiding cracks on the surface of the first encapsulation layer 281.
  • the uniformity and consistency of the prepared first encapsulation layer 281 can be improved, the encapsulation effect of the first encapsulation layer 281 on the display device of the display substrate 20 can be improved, and the display of the display substrate 20 such as water vapor or oxygen can be effectively avoided.
  • the inside of the device may cause adverse effects on the display device, thereby improving the performance and yield of the display substrate 20, and prolonging the service life of the display substrate 20.
  • the display substrate 20 further includes a first cofferdam structure and a second cofferdam structure.
  • the first cofferdam structure is located in the first cofferdam area 204
  • the second cofferdam structure is located in the second cofferdam area 205.
  • the first dam structure is located on the side of the first electrode layer 270 away from the base substrate 210
  • the first encapsulation layer 281 is located on the side of the first dam structure away from the first electrode layer 270 and covers The first cofferdam structure.
  • the second dam structure is located on the side of the second conductive pattern 240 away from the base substrate 210 and a part of the second dam structure covers the first electrode layer 270, and the first encapsulation layer 281 is located on the first electrode.
  • the layer 270 and the second dam structure are away from a side of the second conductive pattern 240 and cover the first electrode layer 270 and the second dam structure.
  • the maximum distance D1 between the surface of the first encapsulation layer 281 on the side of the first dam area 204 facing away from the base substrate 210 and the base substrate 210 is greater than the first encapsulation layer 281.
  • the maximum distance D2 between the surface of the portion of the first encapsulation layer 281 on the side facing away from the base substrate 210 of the second dam area 205 and the base substrate 210 is greater than the deviation of the portion of the first encapsulation layer 281 located in the spacer area 206
  • the maximum distance D1 between the surface of the first encapsulation layer 281 on the side of the first dam area 204 facing away from the base substrate 210 and the base substrate 210 is smaller than the first encapsulation layer 281.
  • the maximum distance D2 between the surface of a part of the second dam area 205 facing away from the base substrate 210 and the base substrate 210 of an encapsulation layer 281 is located. Therefore, the first dam structure and the second dam structure with different heights from the base substrate 210 can more effectively prevent water vapor or oxygen from penetrating into the interior of the display device of the display substrate 20 after packaging, and further avoid interference.
  • Various functional layers or structural layers of the display device cause adverse effects.
  • the display substrate 20 further includes a third insulating layer 263, a fourth insulating layer 264 and a fifth insulating layer 265 located in the first peripheral region 203 except for the spacer region 206.
  • the first dam structure includes a stack of a fourth insulating layer 264 and a fifth insulating layer 265, and the second dam structure includes a stack of a third insulating layer 263, a fourth insulating layer 264, and a fifth insulating layer 265.
  • the fourth insulating layer 264 is located on the side of the first electrode layer 270 away from the base substrate 210, and the fifth insulating layer 265 is located on the side of the fourth insulating layer 264 away from the first electrode layer 270.
  • the first encapsulation layer 281 is located on the side of the fifth insulating layer 265 away from the fourth insulating layer 264, and covers the surface of the fifth insulating layer 265 on the side facing away from the base substrate 210 and the side of at least one side of the fifth insulating layer 265 The surface and the side surface of at least one side of the fourth insulating layer 264.
  • the third insulating layer 263 is located on the side of the second conductive pattern 240 away from the base substrate 210, and the first electrode layer 270 covers the part of the third insulating layer 263 on the side away from the base substrate 210
  • the fourth insulating layer 264 is located on the side of the third insulating layer 263 and the first electrode layer 270 away from the second conductive pattern 240
  • the fifth insulating layer 264 is located on the side of the third insulating layer 263 and the first electrode layer 270 away from the second conductive pattern 240.
  • the insulating layer 265 is located on the side of the fourth insulating layer 264 away from the third insulating layer 263 and the first electrode layer 270, and the first encapsulation layer 281 is located on the side of the fifth insulating layer 265 away from the fourth insulating layer 264, and covers the fifth insulating layer 264.
  • the surface of the insulating layer 265 on the side facing away from the base substrate 210, the side surface of at least one side of the fifth insulating layer 265, the side surface of at least one side of the fourth insulating layer 264, and the third insulating layer 263 away from the base substrate 210 A part of the surface on one side of and the side surface of the third insulating layer 263 on the side away from the first dam area 204.
  • the third insulating layer 263 covers a part of the surface of the second conductive pattern 240 facing away from the base substrate 210 and the second conductive pattern 240 is far away The side surface of one side of the first dam area 204.
  • the display substrate 20 further includes a second encapsulation layer 282.
  • the second encapsulation layer 282 is located on a side of the first encapsulation layer 281 away from the first electrode layer 270 and covers the first encapsulation layer 281.
  • both the first encapsulation layer 281 and the second encapsulation layer 282 may be organic encapsulation layers, and the stacking arrangement of the first encapsulation layer 281 and the second encapsulation layer 282 can further make it difficult for water vapor or oxygen to penetrate into the display of the display substrate 20. The inside of the device.
  • first insulating layer 261 is provided between the first conductive semiconductor pattern 220 and the first conductive pattern 230, and the first conductive pattern 230 and the first conductive pattern 230 Only one second insulating layer 262 is provided between the two conductive patterns 240.
  • other insulating layers or other structural layers or functional layers may be provided between the first conductive semiconductor pattern 220 and the first conductive pattern 230.
  • first conductive pattern 230 and the second conductive pattern 240 can also be provided between the first conductive pattern 230 and the second conductive pattern 240, as long as the via hole can penetrate the corresponding insulating layer so that the first
  • the conductive semiconductor pattern 220 can be electrically connected to the second conductive pattern 240, so that a compensation capacitor is formed between the first conductive pattern 230 and the first conductive semiconductor pattern 220, which is not specifically limited in the embodiment of the present disclosure.
  • the display substrate in the first peripheral area may further include, for example, the first conductive semiconductor pattern, the first conductive pattern, the second conductive pattern, and the semiconductor pattern shown in FIG. 2C. Structures or functional layers other than the first insulating layer, the second insulating layer, etc., as long as it can form a capacitance between the first conductive pattern and the first conductive semiconductor pattern to achieve a compensation effect.
  • the embodiments of the present disclosure do not limit this.
  • the cross-sectional structure shown in FIG. 2C may correspond to the cross-sectional structure of the display substrate 20 shown in FIG. 2A along the line AA'; or in some other embodiments of the present disclosure, the cross-sectional structure shown in FIG. 2C
  • the cross-sectional structure may also correspond to, for example, the cross-sectional structure of the display substrate 30 (including the display area 301) as shown in FIG. 3 along the BB′ line, and the opening of the display substrate 30 shown in FIG. 3 is closed. That is, the embodiments of the present disclosure do not impose restrictions on the specific shape and setting position of the opening of the display area of the display substrate.
  • the embodiment of the present disclosure does not limit the shape or outline of the display substrate.
  • the display substrate of the embodiment of the present disclosure may be a square as shown in FIG. 2A or FIG. Hexagonal, regular octagon and other suitable regular or irregular shapes, etc.
  • the embodiments of the present disclosure do not limit this.
  • the base substrate 210 may be a glass plate, a quartz plate, a metal plate, or a resin-like plate.
  • the material of the base substrate 210 may include an organic material.
  • the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate. Resin materials such as esters and polyethylene naphthalate.
  • the base substrate 210 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiment of the present disclosure.
  • the materials of the first insulating layer 261, the second insulating layer 262, the third insulating layer 263, the fourth insulating layer 264, and the fifth insulating layer 265 may include silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the embodiments of the present disclosure do not specifically limit the materials of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer.
  • the materials of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be the same or partially the same as each other, and may also be different from each other, which is not limited in the embodiments of the present disclosure. .
  • the material of the plurality of second traces 221 of the first conductive semiconductor pattern 220 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the plurality of first traces 231 of the first conductive pattern 230 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the material of the second conductive pattern 240 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer (For example, a three-layer metal laminate of titanium, aluminum and titanium (Al/Ti/Al)).
  • the material of the first electrode layer 270 may include at least one conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc., or may also include Metal with high reflectivity is used as the reflective layer, such as silver (Ag).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • Metal with high reflectivity is used as the reflective layer, such as silver (Ag).
  • the material of the first encapsulation layer 261 and the second encapsulation layer 262 may include insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride are highly dense and can prevent the intrusion of water and oxygen.
  • the arrangement density of the multiple vias in the spacer area may be set to 0, that is, no vias are provided in the spacer area.
  • the film surface of the first electrode layer covering the second conductive pattern and the film layer of the first packaging layer covering the first electrode layer can be kept uniform and flat, thereby avoiding or significantly reducing the phenomenon of cracks on the surface of the first packaging layer, and further The uniformity and consistency of the first packaging layer are improved, and the packaging effect of the first packaging layer on the display substrate is improved. Furthermore, the film surface of the second encapsulation layer covering the first encapsulation layer can be kept uniform and flat, and the phenomenon of cracks on the surface of the second encapsulation layer can be avoided or significantly reduced, thereby improving the uniformity and uniformity of the surface of the second encapsulation layer prepared. Consistency improves the packaging effect of the second packaging layer on the display substrate.
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 4 may also be a schematic cross-sectional structure diagram of the display substrate shown in FIG. 2A along the line A-A', or may also be a schematic cross-sectional structure diagram of the display substrate shown in FIG. 3 along the line B-B'.
  • the structure of the display substrate 40 shown in FIG. 4 except for the first conductive semiconductor pattern 420, the second conductive pattern 440, and the via 450 are basically the same as or similar to the display substrate 20 shown in FIG. 2C. No longer.
  • the first conductive semiconductor pattern 420, the second conductive pattern 440, and the plurality of vias 450 are located in the first dam area 404, the spacer area 406, and the second dam area 405. in.
  • the first conductor can be further improved.
  • the arrangement density of the plurality of vias 450 in the spacer area 406 may be set to zero.
  • the via 450 may not be provided in the spacer region 406 of the display substrate 40, thereby eliminating or The up-and-down phenomenon of the surface of the second conductive pattern 440 located in the spacer region 406 due to the via design is further reduced, so that the film surface of the second conductive pattern 440 remains uniform and flat.
  • the film surface of the first electrode layer 470 covering the second conductive pattern 440 and the first encapsulation layer 481 covering the first electrode layer 470 can be kept uniform and flat, thereby avoiding or significantly reducing the appearance of the surface of the first encapsulation layer 481.
  • the phenomenon of cracks further improves the uniformity and consistency of the first packaging layer 481, thereby improving the packaging effect of the first packaging layer 481 on the display substrate 40.
  • the film surface of the second encapsulation layer 482 covering the first encapsulation layer 481 can be kept uniform and flat, and the phenomenon of cracks on the surface of the second encapsulation layer 482 can be avoided or significantly reduced, thereby improving the surface of the second encapsulation layer 482 prepared.
  • the uniformity and consistency of the encapsulation improves the encapsulation effect of the second encapsulation layer 482 on the display substrate 40.
  • the arrangement density of the plurality of vias 450 in the first dam area 404 is the same as the arrangement density in the second dam area 405.
  • the arrangement density of the multiple vias in the first cofferdam area and the arrangement density of the second cofferdam area may also be different, which is not limited in the embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of a partial cross-sectional structure of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 5 may also be a schematic cross-sectional structure diagram of the display substrate shown in FIG. 2A along the line A-A', or may also be a schematic cross-sectional structure diagram of the display substrate shown in FIG. 3 along the line B-B'.
  • the structure of the display substrate 50 shown in FIG. 5 except for the first conductive semiconductor pattern 520, the first conductive pattern 530, the second conductive pattern 540, and the via 550 is basically the same as that of the display substrate 20 shown in FIG. 2C.
  • the same or similar, or other structures of the display substrate 40 shown in FIG. 5 except for the first conductive pattern 530 are basically the same or similar to the display substrate 40 shown in FIG. 4, and will not be repeated here.
  • the first conductive pattern 530 is also located in the second dam area 505. That is, the first conductive semiconductor pattern 520, the first conductive pattern 530, the second conductive pattern 540, and the plurality of vias 550 are all located at least in the first dam area 504, the second dam area 505, and the spacer area 506. in.
  • the arrangement density of the plurality of vias 550 in the spacer region 406 is zero. Therefore, under the condition that the electrical connection effect between the first conductive semiconductor pattern 520 and the second conductive pattern 540 is ensured, by not providing the via 550 in the spacer region 506 of the display substrate 50, it can be eliminated or further reduced.
  • the up-and-down phenomenon of the surface of the second conductive pattern 540 located in the spacer region 506 is caused by the through hole design, so that the film surface of the second conductive pattern 540 remains uniform and flat.
  • the film surface of the first electrode layer 570 covering the second conductive pattern 540 and the film layer of the first packaging layer 581 covering the first electrode layer 570 can be kept uniform and flat, thereby avoiding or significantly reducing the appearance of the surface of the first packaging layer 581.
  • the phenomenon of cracks further improves the uniformity and consistency of the prepared first packaging layer 581, and improves the packaging effect of the first packaging layer 581 on the display substrate 50.
  • the arrangement density of the vias 550 in the first cofferdam area 504 is the same as that of the second cofferdam area 505.
  • the arrangement density of the vias in the first cofferdam area and the arrangement density of the vias in the second cofferdam area may also be different.
  • the arrangement density of the vias in the first cofferdam area can be greater than the arrangement density in the second cofferdam area, and the arrangement density in the second cofferdam area is greater than the arrangement density in the spacer area; or, It is also possible to make the arrangement density of the vias in the second cofferdam area greater than the arrangement density in the first cofferdam area, and the arrangement density in the first cofferdam area is greater than the arrangement density in the spacer area. The embodiment does not limit this.
  • the arrangement density of the vias in the first cofferdam area when the arrangement density of the vias in the first cofferdam area is greater than the arrangement density of the spacer area, the arrangement density of the vias in the second cofferdam area can be set to It is the same as the arrangement density in the spacer area. For example, the arrangement density of the vias in the second cofferdam area and the arrangement density in the spacer area can both be set to zero.
  • the arrangement density of the vias in the first cofferdam area may be It is set to be the same as the arrangement density in the spacer area. For example, the arrangement density of the vias in the first dam area and the arrangement density in the spacer area can both be set to zero. The embodiment of the present disclosure does not limit this.
  • the interval Via holes can also be arranged in the area according to actual needs, as long as the arrangement density of the multiple via holes in the spacer area is less than the arrangement density in the first cofferdam area and the second cofferdam area.
  • the embodiment of the present disclosure does not limit this.
  • FIGS. 6A and 6B are schematic diagrams of an arrangement of a plurality of via holes in a first peripheral area provided by some embodiments of the present disclosure.
  • FIGS. 6A and 6B may be schematic diagrams of the arrangement of the plurality of via holes 550 in the display substrate 50 shown in FIG. 5 in the first peripheral region 503.
  • FIG. 6A only shows the arrangement relationship among the first conductive semiconductor pattern 520, the first conductive pattern 530, and the second conductive pattern 540
  • FIG. 6B shows the first conductive pattern.
  • the design of other structures or functional layers in the display substrate 50 can refer to conventional techniques in the art. The setting method will not be repeated here.
  • FIG. 6A shows that the first conductive semiconductor pattern 520, the first conductive pattern 530, and the second conductive pattern 540 are parallel to the surface of the base substrate 510.
  • FIG. 6B shows that the first conductive semiconductor pattern 520, the first conductive pattern 530, the second conductive pattern 540, and the first electrode layer 570 are parallel to each other.
  • the first conductive semiconductor pattern 520 includes a plurality of second traces 521 arranged along the second direction R2, and the first conductive pattern 530 includes With the plurality of first wiring lines 531 arranged by R1, the first direction R1 is perpendicular to the second direction R2.
  • the plurality of first wires 531 are arranged at intervals along the first direction R1, and each of the first wires 531 and the plurality of second wires 521 partially overlap each other.
  • the plurality of second traces 521 are arranged at intervals along the second direction R2, and each of the second traces 521 and the plurality of first traces 531 partially overlap each other.
  • the via 550 may be provided in a portion where the second wiring 521 does not overlap the first wiring 531, that is, in a gap between two adjacent first wirings 531.
  • the first electrode layer 570 covers the via 550 provided in the first dam area 504 and at least covers a part of the via 550 provided in the second dam area 505.
  • the first electrode layer 570 covers a plurality of first traces 531 and a plurality of second traces 521.
  • the first electrode layer 570 covers a part of the plurality of first traces 531, and respectively covers a part of each of the plurality of second traces 521.
  • the multiple first wirings 531 are all made of the same material, and in some other embodiments of the present disclosure, the multiple first wirings 531 are also Different materials can be alternately formed respectively, and the embodiments of the present disclosure are not limited thereto.
  • the multiple first wirings 531 may be formed in the same layer as a certain structure of the pixel structure in the display area.
  • the multiple first traces 531 can also be formed in the same layer as the two structures in the pixel structure in the display area, that is, a part of the first traces are formed in the same layer as one structure in the pixel structure, and the other part of the first traces are formed in the same layer as the pixel structure.
  • the other structure in the structure is formed in the same layer.
  • the two parts of the first wiring are alternately arranged to form a plurality of first wirings 531.
  • the multiple first traces 531 can also be formed in the same layer as the three structures in the pixel structure in the display area, that is, the first part of the first trace is formed in the same layer as the first structure in the pixel structure, and the second part is formed in the same layer as the first structure in the pixel structure.
  • the wiring is formed in the same layer as the second structure in the pixel structure, and the third part of the first wiring is formed in the same layer as the third structure in the pixel structure.
  • each of the three parts of the first traces has one trace, and the three traces are arranged in sequence as a group, and the multiple groups are arranged to form a plurality of first traces 531; in other embodiments, the three Each part of the part of the first wiring is as a group as a whole, and the three groups are arranged to form a plurality of first wirings 531.
  • the number of vias 550 opened on each second wiring 521 is only an exemplary illustration. In some other embodiments of the present disclosure, in the second direction R2, the number of vias opened on each second trace can be based on factors such as the width of the second trace in the second direction R2 or the precision of the manufacturing process. It is determined that the embodiment of the present disclosure does not limit this.
  • the orthographic projection of the second conductive pattern on the base substrate overlaps the orthographic projection of the second insulating layer on the base substrate, and the second conductive pattern is on the base substrate.
  • the area of the orthographic projection on the base substrate is equal to the area of the orthographic projection of the second insulating layer on the base substrate.
  • the second conductive pattern 540 may be arranged in a whole piece in the spacer area 506, and the second insulating layer 562 may also be arranged in a whole piece, and then in the spacer area 506
  • the via 550 is not provided, in the spacer area 506, the orthographic projection of the second conductive pattern 540 on the base substrate 510 overlaps with the orthographic projection of the second insulating layer 562 on the base substrate 510, and the second conductive pattern
  • the area of the orthographic projection of 540 on the base substrate 510 is equal to the area of the orthographic projection of the second insulating layer 562 on the base substrate 510.
  • the display substrate further includes a pixel structure located in the display area.
  • the pixel structure includes a pixel drive circuit on a base substrate.
  • the pixel drive circuit includes a thin film transistor and a storage capacitor; the thin film transistor includes a gate, an active layer, a source and a drain, and the storage capacitor includes a first capacitor electrode and a first capacitor electrode.
  • the second capacitor electrode opposite to the capacitor electrode, the active layer and the first conductive semiconductor pattern are arranged in the same layer, the gate electrode and the first capacitor electrode are arranged in the same layer, the second capacitor electrode is arranged in the same layer as the first conductive pattern, and the source electrode
  • the drain and the second conductive pattern are arranged in the same layer. Therefore, the manufacturing process of the display substrate can be simplified, and the manufacturing cost of the display substrate can be reduced.
  • “same layer arrangement” means that two functional layers or structural layers are formed of the same layer and the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be made of the same
  • the material layer is formed, and the required pattern and structure can be formed by the same patterning process.
  • the material layer can be formed by the patterning process after the material layer is formed first.
  • the first conductive pattern may also be provided in the same layer as the gate electrode and the first capacitor electrode; in some other embodiments of the present disclosure, it may also be a part of the first conductive pattern.
  • the pattern is arranged in the same layer as the second capacitor electrode, and another part of the first conductive pattern is arranged in the same layer as the gate and the first capacitor electrode, that is, the first conductive pattern includes two parts alternately formed, which is not limited in the embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of another partial cross-sectional structure of a display substrate provided by some embodiments of the present disclosure.
  • the portion of the first peripheral area 703 of the display substrate 70 shown in FIG. 7 is substantially the same as or similar to the portion of the first peripheral area 503 of the display substrate 50 shown in FIG. 5, and will not be repeated here.
  • the display substrate 70 further includes a pixel structure located in the display area 701 for implementing functions such as light emission driving and control.
  • the pixel structure includes a pixel driving circuit 7120 on a base substrate 710, a first planarization layer 7150, and a light-emitting element 7140.
  • the pixel driving circuits 7120 in the rows of pixel units located on the left and right sides of the opening in the display area 701 can be electrically connected correspondingly.
  • one or more electrical signals for the pixel driving circuit 7120 such as gate scan signals, light emission control signals, reset signals, and the like.
  • a first wiring 731 may be provided for each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 to transmit one of the above-mentioned electrical signals.
  • the first wiring 731 may be located in the display area 701.
  • the gate lines of each row of pixel driving circuits 7120 on the left and right sides of the opening are electrically connected to transmit gate scanning signals; it is also possible to provide multiple first wirings 731 corresponding to each row of pixel driving circuits 7120 on the left and right sides of the opening of the display area 701
  • the gate lines and the light-emitting control lines of each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 are electrically connected through the first wiring 731 to respectively transmit the gate scanning signals.
  • the embodiment of the present disclosure does not limit this.
  • a first conductive semiconductor pattern 720 for example, a plurality of second wirings 721 in the first conductive semiconductor pattern 720
  • a capacitor is formed between the plurality of first wirings 731, thereby increasing the transmission load of the first wiring 731, and compensating for the electrical signal transmission effect of the first wiring 731.
  • the display effect of the pixel units located on the left and right sides of the opening in the display area 701 can be kept consistent with the display effect of other pixel units in the display area 701, avoiding or reducing the display abnormality of the screen under different gray levels, thereby improving The screen display effect of the display substrate 70 is displayed.
  • the first conductive semiconductor pattern 720 is electrically connected to the second conductive pattern 740 through the via 750 and is further electrically connected to the first electrode layer 770.
  • the first electrode layer 770 may be configured to receive a low voltage signal (e.g., provide To the cathode signal of the light-emitting element 7140), and then the plurality of second wirings 721 in the first conductive semiconductor pattern 720 are applied with low voltage signals, so that the first wiring 731 that transmits, for example, the gate scan signal is connected to the second wiring 721 in the first conductive semiconductor pattern 720.
  • a capacitor can be formed between the second traces 721 to achieve the effect of compensation.
  • a first wiring 731 is provided for each row of pixel driving circuits 7120 located on the left and right sides of the opening of the display area 701 to transmit the gate scan signal (that is, the first wiring 731 will be located in the display area).
  • the gate lines of each row of pixel driving circuits 7120 on the left and right sides of the opening of 701 are electrically connected to transmit a gate scanning signal as an example.
  • the display substrate 70 will be described with reference to the specific structure of the pixel driving circuit 7120.
  • FIG. 8 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided by some embodiments of the present disclosure
  • FIGS. 9A-9E are schematic diagrams of various layers of a pixel driving circuit in a display substrate provided by some embodiments of the present disclosure
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of the display substrate 70 including the pixel driving circuit 7120 shown in FIGS. 8 and 9A.
  • the specific structure of the pixel driving circuit 7120 shown in FIG. 8 and FIG. 9A is only an exemplary description, and the embodiments of the present disclosure include but are not limited to this.
  • the pixel driving circuit 7120 includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, connected to a plurality of thin film transistors T1, T2, T3, T4, and T5.
  • T6 and T7 multiple signal lines and storage capacitor Cst
  • multiple signal lines include gate line GL, light emission control line EM, initialization line RL, data line DAT and the first power line VDD.
  • the gate line GL may include a first gate line GLn and a second gate line GLn-1.
  • the first gate line GLn may be used to transmit a gate scan signal
  • the second gate line GLn-1 may be used to transmit a reset signal.
  • the light emission control line EM can be used to transmit light emission control signals.
  • the pixel drive circuit 7120 is a 7T1C pixel drive circuit.
  • the pixel driving circuit 7120 may also adopt other types of circuit structures, such as a 7T2C structure or a 9T2C structure, which is not limited by the embodiments of the present disclosure.
  • the first gate line GLn of each row of pixel driving circuit 7120 located on the left and right sides of the opening of the display area 701 can be electrically connected through the first wiring 731 to transmit the gate scan signal, thereby achieving the compensation effect of the gate scan signal.
  • the first gate G1 of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4.
  • the first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5.
  • the first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.
  • the second gate G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scan signal
  • the second source S2 of the second thin film transistor T2 is configured
  • the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the third gate G3 of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source S3 of the third thin film transistor T3 is connected to the first gate line GLn of the first thin film transistor T1.
  • a drain electrode D1 is electrically connected, and the third drain electrode D3 of the third thin film transistor T3 is electrically connected to the first gate electrode G1 of the first thin film transistor T1.
  • the fourth gate G4 of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal
  • the fourth source S4 of the fourth thin film transistor T4 is configured
  • the fourth drain electrode D4 of the fourth thin film transistor T4 is electrically connected to the first gate electrode G1 of the first thin film transistor T1.
  • the fifth gate G5 of the fifth thin film transistor T5 is configured to be electrically connected to the emission control line EM to receive the emission control signal
  • the fifth source S5 of the fifth thin film transistor T5 is configured to be connected to the emission control line EM.
  • the first power line VDD is electrically connected to receive the first power signal
  • the fifth drain electrode D5 of the fifth thin film transistor T5 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the sixth gate G6 of the sixth thin film transistor T6 is configured to be electrically connected to the emission control line EM to receive the emission control signal, and the sixth source S6 of the sixth thin film transistor T6 is connected to the first thin film
  • the first drain D1 of the transistor T1 is electrically connected
  • the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (for example, the anode) of the light-emitting element 7140.
  • the seventh gate G7 of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal
  • the seventh source S7 of the seventh thin film transistor T7 is The first display electrode (for example, the anode) of the element 7140 is electrically connected
  • the seventh drain D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive the initialization signal.
  • the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.
  • the storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2.
  • the second capacitor electrode CE2 is electrically connected to the first power line VDD
  • the first capacitor electrode CE1 is electrically connected to the first gate G1 of the first thin film transistor T1 and the third drain D3 of the third thin film transistor T3.
  • the second display electrode (for example, the cathode) of the light-emitting element 7140 is electrically connected to the second power line VSS.
  • first power line VDD and the second power line VSS are a power line that provides a high voltage, and the other is a power line that provides a low voltage.
  • first power line VDD provides a constant first voltage
  • first voltage is a positive voltage
  • second power line VSS provides a constant second voltage
  • the second voltage may be a negative voltage.
  • the second voltage may be a ground voltage.
  • the first electrode layer 770 of the display substrate 70 may be configured to receive the second voltage provided by the second power line VSS, so that the second conductive pattern 740 electrically connected to the first electrode layer 770 and the second conductive pattern
  • the second voltage is applied to the first conductive semiconductor pattern 720 that is electrically connected to 740, thereby making the first wiring 731 and the first conductive semiconductor pattern that are electrically connected to the first gate line GLn and transmit the gate scan signal
  • a capacitor can be formed between the second traces 721 in 720 to achieve the effect of compensation.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to illustrate in detail.
  • the technical solution of the present disclosure that is, in the description of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 etc. can all be P-type transistors.
  • the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, the source and drain of all or part of the transistor can be as required Are interchangeable.
  • the pixel driving circuit 7120 includes the aforementioned thin film transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a plurality of thin film transistors T1, T2, T3. , T4, T5, T6, and T7 of the first gate line GLn, the second gate line GLn-1, the emission control line EM, the initialization line RL, the data line DAT, and the first power supply line VDD.
  • T4, T5, T6, and T7 of the first gate line GLn, the second gate line GLn-1, the emission control line EM, the initialization line RL, the data line DAT, and the first power supply line VDD Next, the structure of the pixel driving circuit 7120 will be described with reference to Figs. 8 and 9A-9E.
  • FIG. 9A is a schematic diagram of the stacked positional relationship of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer of the pixel driving circuit 7120.
  • FIG. 9B shows the semiconductor layer of the pixel driving circuit 7120.
  • the semiconductor layer shown in FIG. 9B may be the active layer 7122 shown in FIG. 7.
  • the semiconductor layer can be formed by patterning a semiconductor material.
  • the semiconductor layer can be used to make the aforementioned first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, fifth thin film transistor T5, sixth thin film transistor T6, and seventh thin film transistor T7.
  • the source layer, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • a gate insulating layer (for example, the gate insulating layer 7128 shown in FIG. 7 and not shown in FIGS. 9A-9E) is formed on the above-mentioned semiconductor layer for Protect the above-mentioned semiconductor layer.
  • FIG. 9C shows the first conductive layer of the pixel driving circuit 7120.
  • the first conductive layer of the pixel driving circuit 7120 is provided on the gate insulating layer so as to be insulated from the semiconductor layer shown in FIG. 9B.
  • the first conductive layer may include the first capacitor electrode CE1 of the storage capacitor Cst, the first gate line GLn, the second gate line GLn-1, the emission control line EM, and the first thin film transistor T1, the second thin film transistor T2, and the third The gates of the thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 (for example, the aforementioned first gate G1, second gate G2, and third gate The electrode G3, the fourth grid G4, the fifth grid G5, the sixth grid G6, and the seventh grid G7). As shown in FIG.
  • the gates of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are the first gate line GLn and the second gate line GLn- 1
  • the third thin film transistor T3 may be a thin film transistor with a double gate structure, and a gate of the third thin film transistor T3 may be the part where the first gate line GLn overlaps the semiconductor layer, and the third thin film transistor T3
  • the other gate of the transistor T3 may be a protrusion protruding from the first gate line GLn; the gate of the first thin film transistor T1 may be the first capacitor electrode CE1.
  • the fourth thin film transistor T4 may be a thin film transistor with a double-gate structure, and the two gates are respectively the overlapping portions of the second gate line GLn-1 and the semiconductor layer.
  • a first interlayer insulating layer (for example, the first interlayer insulating layer 7129 shown in FIG. 7, which is not shown in FIGS. 9A-9E) is formed on the above-mentioned first conductive layer. Shown), used to protect the above-mentioned first conductive layer.
  • FIG. 9D shows the second conductive layer of the pixel driving circuit 7120.
  • the second conductive layer of the pixel driving circuit 7120 includes the second capacitor electrode CE2 of the storage capacitor Cst and the initialization line RL.
  • the second capacitor electrode CE2 and the first capacitor electrode CE1 at least partially overlap to form a storage capacitor Cst.
  • the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792.
  • the orthographic projection of the first light shielding portion 791 on the base substrate 710 covers the active layer between the active layer of the second thin film transistor T2, the drain of the third thin film transistor T3 and the drain of the fourth thin film transistor T4, thereby Prevent external light from affecting the active layers of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4.
  • the orthographic projection of the second light shielding portion 792 on the base substrate 710 covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3.
  • the first light shielding portion 791 may be an integral structure with the second light shielding portion 792 of the adjacent pixel driving circuit, and is electrically connected to the first power line VDD through a via hole penetrating the second interlayer insulating layer.
  • a second interlayer insulating layer (for example, the second interlayer insulating layer 7131 shown in FIG. 7, which is not shown in FIGS. 9A-9E) is formed on the above-mentioned second conductive layer. Shown), used to protect the above-mentioned second conductive layer.
  • FIG. 9E shows the third conductive layer of the pixel driving circuit 7120.
  • the third conductive layer of the pixel driving circuit 7120 includes a data line DAT and a first power supply line VDD.
  • the data line DAT passes through at least one of the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer through at least one via hole (for example, via hole VH1) and the second semiconductor layer.
  • the source regions of the thin film transistor T2 are connected.
  • the first power supply line VDD passes through at least one via hole (for example via hole VH2) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer to the source region of the semiconductor layer corresponding to the fifth thin film transistor T5 Connected.
  • the first power line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via hole (for example, via hole VH3) in the second interlayer insulating layer.
  • the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3.
  • One end of the first connection portion CP1 passes through at least one via hole (for example, via hole VH4) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer and is connected to the drain of the third thin film transistor T3 in the semiconductor layer.
  • the polar regions are connected, and the other end of the first connecting portion CP1 is connected to the first thin film transistor T1 in the first conductive layer through at least one via hole (for example, via hole VH5) in the first interlayer insulating layer and the second interlayer insulating layer.
  • the gate is connected.
  • One end of the second connecting portion CP2 is connected to the initialization line RL through a via hole (for example, via VH6) in the second interlayer insulating layer, and the other end of the second connecting portion CP2 is connected to the gate insulating layer and the first interlayer insulating layer.
  • At least one via (for example, via VH7) in the layer and the second interlayer insulating layer is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
  • the third connection portion CP3 passes through at least one via hole (for example via hole VH8) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer and the drain region of the sixth thin film transistor T6 in the semiconductor layer. Connected.
  • via hole VH8 for example via hole VH8
  • a protective layer (for example, the first planarization layer 7150 shown in FIG. 7, not shown in FIGS. 9A-9E) is formed on the above-mentioned third conductive layer.
  • the first display electrode for example, anode
  • the first display electrode of the light-emitting element 7140 in the pixel structure may be disposed on the protective layer.
  • the first trace 731 in the first conductive pattern 730 may be provided in the same layer as the second capacitor electrode CE2 in the second conductive layer, and the first trace 731 may pass through at least one via hole in the first interlayer insulating layer. Connected to the first gate line GLn in the first conductive layer.
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of the display substrate 70 including the pixel driving circuit 7120 shown in FIGS. 8 and 9A.
  • the pixel structure further includes a buffer layer 7121 on the base substrate 710
  • the pixel driving circuit 7120 may include an active layer 7122 on the buffer layer 7121 (for example, as shown in FIG. 9B
  • the semiconductor layer of the pixel driving circuit 7120) the gate insulating layer 7128 located on the side of the active layer 7122 away from the base substrate 710, and the gate 7130 located on the gate insulating layer 7128 (for example, located in the pixel shown in FIG.
  • the first conductive semiconductor pattern 720 (for example, the plurality of second traces 721 in the first conductive semiconductor pattern 720) may be provided in the same layer as the active layer 7122.
  • the first insulating layer 761 may be provided in the same layer as the first interlayer insulating layer 7129
  • the second insulating layer 762 may be provided in the same layer as the second interlayer insulating layer 7131.
  • the source electrode 7125 and the drain electrode 7126 may be provided in the same layer as the second conductive pattern 740.
  • the above-mentioned structure or functional layer provided in the same layer can be formed in the same layer in the preparation process, for example, the same material layer is formed through a patterning process, thereby simplifying the preparation process of the display substrate 70 and reducing the preparation cost of the display substrate 70.
  • the buffer layer 7121 serves as a transition layer, which can prevent harmful substances in the base substrate 710 from intruding into the interior of the display substrate 710, and can increase the adhesion of the film layer in the display substrate 710 on the base substrate 710.
  • the material of the buffer layer 7121 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of one or more of the first interlayer insulating layer 7129, the second interlayer insulating layer 7131, and the gate insulating layer 7128 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the first interlayer insulating layer 7129, the second interlayer insulating layer 7131, and the gate insulating layer 7128 may be the same or different from each other, which is not limited in the embodiment of the present disclosure.
  • the active layer 7122 may include a source region 7123, a drain region 7124, and a channel region located between the source region 7123 and the drain region 7124.
  • the first interlayer insulating layer 7129, the second interlayer insulating layer 7131, and the gate insulating layer 7128 have via holes to expose the source region 7123 and the drain region 7124.
  • the source 7125 and the drain 7126 are electrically connected to the source region 7123 and the drain region 7124 through via holes, respectively.
  • the gate 7130 overlaps the channel region between the source region 7123 and the drain region 7124 in the active layer 7122 in a direction perpendicular to the base substrate 710.
  • the first planarization layer 7150 is located above the source electrode 7125 and the drain electrode 7126 for planarizing the surface of the pixel driving circuit 7120 away from the base substrate 710.
  • the first planarization layer 7150 can planarize the uneven surface caused by the pixel driving circuit 7120, and thus prevent the unevenness caused by the pixel driving circuit 7120 from causing defects in the light emitting element 7140.
  • the first planarization layer 7150 may be provided in the same layer as the third insulating layer 763 in the first peripheral region 703. Therefore, the two can be formed in the same layer in the preparation process, for example, the same material layer is used in a patterning process.
  • the material of the active layer 7122 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the gate 7130 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (for example, three layers of titanium, aluminum, and titanium). Metal stack (Al/Ti/Al)).
  • the material of the source electrode 7125 and the drain electrode 7126 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, Aluminum and titanium three-layer metal stack (Al/Ti/Al)).
  • the embodiments of the present disclosure do not specifically limit the materials of each structure or functional layer.
  • a via hole is formed in the first planarization layer 7150 to expose the source electrode 7125 or the drain electrode 7126 (shown in FIG. 7 is the case where the drain electrode 7126 is exposed), on the first planarization layer 7150
  • the light-emitting element 7140 is formed.
  • the light emitting element 7140 includes a first display electrode 7141 (for example, an anode), a light emitting layer 7142, and a second display electrode 7143 (for example, a cathode).
  • the first display electrode 7141 of the light emitting element 7140 is electrically connected to the drain 7126 through the via hole in the first planarization layer 7150.
  • a pixel defining layer 7144 is formed on the first display electrode 7141, and the pixel defining layer 7144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes the first display electrode 7141, and the light emitting layer 7142 is disposed in the plurality of openings of the pixel defining layer 7144.
  • the second display electrode 7143 may be disposed in a part or the entire display area 701, for example, so that it may be formed on the entire surface during the manufacturing process.
  • the first display electrode 7141 may be provided in the same layer as the first electrode layer 770 in the first peripheral region 703. Therefore, the two can be formed in the same layer in the preparation process, for example, the same material layer is used in a patterning process.
  • the pixel defining layer 7144 may be provided in the same layer as the fourth insulating layer 764 in the first peripheral region 703. Therefore, the two can be formed in the same layer in the preparation process, for example, the same material layer is used in a patterning process.
  • the first display electrode 7141 may include a reflective layer
  • the second display electrode 7143 may include a transparent layer or a semi-transparent layer.
  • the first display electrode 7141 can reflect the light emitted from the light-emitting layer 7142, and this part of the light is emitted into the external environment through the second display electrode 7143, so that the light emission rate can be improved.
  • the second display electrode 7143 includes a semi-transmissive layer, some light reflected by the first display electrode 7141 is reflected again by the second display electrode 7143, so the first display electrode 7141 and the second display electrode 7143 form a resonance structure, which can improve Light emission efficiency.
  • the material of the first display electrode 7141 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first display electrode 7141 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 7142 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may emit red light or green light. Light, blue light, or white light, etc.
  • the light-emitting layer 7142 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light emitting layer 7142 may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride Quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second display electrode 7143 may include various conductive materials.
  • the second display electrode 7143 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the material of the pixel defining layer 7144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • the display substrate 70 further includes an encapsulation layer 7160 on the light-emitting element 7140.
  • the encapsulation layer 7160 seals the light emitting element 7140, so that the deterioration of the light emitting element 7140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 7160 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 7160 may include a first inorganic encapsulation layer 7161 (ie, a first encapsulation layer 781), a first organic encapsulation layer 7162, a second inorganic encapsulation layer 7163 (ie, a second encapsulation layer 782) arranged in sequence.
  • the material of the encapsulation layer 7160 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride are highly dense and can prevent the intrusion of water and oxygen.
  • the material of the first organic encapsulation layer 7162 may be a polymer material containing a desiccant or a polymer material that can block water vapor, etc., for example, a polymer resin or the like may flatten the surface of the display area 701 of the display substrate 70, and It can relieve the stress of the first inorganic encapsulation layer 7161 and the second inorganic encapsulation layer 7163, and can also include water-absorbing materials such as a desiccant to absorb substances such as water and oxygen that have penetrated into the interior.
  • the pixel driving circuit 7120 may further include a first display metal layer 7127 (for example, the third conductive layer of the pixel driving circuit 7120 shown in FIG. 9E).
  • the first display metal layer 7127 includes the source electrode 7125 and the drain electrode 7126 in the thin film transistor of the pixel driving circuit 7120 shown in FIG. 7, and may also include electrodes in other circuits not shown.
  • the display substrate 70 further includes a storage capacitor 7170 (such as the storage capacitor Cst shown in FIG. 8 and FIG. 9A), and the storage capacitor 7170 may include a first capacitor electrode 7171 (such as in FIG. 8 and FIG. 9C).
  • the illustrated first capacitor electrode CE1 of the storage capacitor Cst) and the second capacitor electrode 7172 (for example, the second capacitor electrode CE2 of the storage capacitor Cst shown in FIGS. 8 and 9D).
  • the first capacitor electrode 7171 is disposed between the gate insulating layer 7128 and the first interlayer insulating layer 7129 (for example, located in the first conductive layer of the pixel driving circuit 7120 shown in FIG.
  • the second capacitor electrode 7172 is disposed on the first conductive layer. Between the interlayer insulating layer 7129 and the second interlayer insulating layer 7131 (for example, located in the second conductive layer of the pixel driving circuit 7120 shown in FIG. 9D). The first capacitor electrode 7171 and the second capacitor electrode 7172 overlap and at least partially overlap in a direction perpendicular to the base substrate 710. The first capacitor electrode 7171 and the second capacitor electrode 7172 use the first interlayer insulating layer 7129 as a dielectric material to form a storage capacitor 7170.
  • the second capacitor electrode 7172 may be provided in the same layer as the first conductive pattern 730 in the first peripheral region 703. Therefore, the two can be formed in the same layer in the preparation process, for example, the same material layer is formed through a patterning process, thereby simplifying the preparation process of the display substrate 70 and reducing the preparation cost of the display substrate 70.
  • the first capacitor electrode of the storage capacitor is still arranged on the same layer as the gate electrode, and the second capacitor electrode of the storage capacitor is arranged on the same layer as the source and drain electrodes of the thin film transistor.
  • the first capacitor electrode and the second capacitor electrode may use a stack of the first interlayer insulating layer and the second interlayer insulating layer as a dielectric material to form a storage capacitor.
  • the first capacitor electrode of the storage capacitor is no longer arranged in the same layer as the gate electrode, but is located between the first interlayer insulating layer and the second interlayer insulating layer, and the storage capacitor
  • the second capacitor electrode and the source electrode and the drain electrode of the thin film transistor are arranged in the same layer, so the first capacitor electrode and the second capacitor electrode use the second interlayer insulating layer as a dielectric material to form a storage capacitor.
  • cross-sectional structure in the display area of the display substrate 20 shown in FIG. 2C and the display substrate 40 shown in FIG. 4 may also adopt the same or similar structure as the display area 701 of the display substrate 70 shown in FIG. 7 Or, other suitable structures may also be adopted, which is not limited in the embodiments of the present disclosure.
  • the display substrates provided by the embodiments of the present disclosure such as the display substrate 20, the display substrate 30, the display substrate 40, the display substrate 50, and the display substrate 70 may be organic light emitting diode display substrates.
  • the display substrate provided by the embodiment of the present disclosure may also be a substrate with a display function such as a quantum dot light-emitting diode display substrate, an electronic paper display substrate, or other types of substrates, which is not limited in the embodiment of the present disclosure.
  • a display function such as a quantum dot light-emitting diode display substrate, an electronic paper display substrate, or other types of substrates, which is not limited in the embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for preparing a display substrate, the preparation method comprising: providing a base substrate; forming a first conductive semiconductor pattern on the base substrate; forming a first conductive semiconductor pattern on the first conductive semiconductor pattern A first conductive pattern, wherein the first conductive pattern and the first conductive semiconductor pattern are spaced apart to form a capacitor; and a second conductive pattern is formed on the first conductive pattern, wherein the second conductive pattern is connected to the first conductive pattern.
  • the patterns are insulated at intervals to be able to form capacitors.
  • the display substrate includes a display area and a peripheral area surrounding the display area, the display area includes an opening, and the peripheral area includes a first peripheral area at least partially surrounding the opening.
  • the first peripheral area includes a first cofferdam area, a second cofferdam area, and a partition area.
  • the first cofferdam area at least partially surrounds the opening
  • the partition area at least partially surrounds the first cofferdam area
  • the second cofferdam area at least partially surrounds the gap.
  • the first conductive pattern is configured to transmit an electric signal for the display area.
  • the second conductive pattern is electrically connected to the first conductive semiconductor pattern through a plurality of via holes provided in the first peripheral region.
  • the first conductive semiconductor pattern, the first conductive pattern, and the second conductive pattern are located at least in the first dam area and the spacer area, and the arrangement density of the plurality of vias in the spacer area is lower than that in the first dam area .
  • forming a first conductive pattern on the first conductive semiconductor pattern includes: forming a first insulating layer on the first conductive semiconductor pattern, And forming a first conductive pattern on the first insulating layer.
  • the forming of the second conductive pattern on the first conductive pattern includes: forming a second insulating layer on the first conductive pattern, and forming a second conductive pattern on the second insulating layer.
  • a plurality of via holes are located at least in the first insulating layer and the second insulating layer and penetrate at least the first insulating layer and the second insulating layer.
  • the method for preparing a display substrate further includes: forming a first electrode layer on the second conductive pattern.
  • the first electrode layer is electrically connected to the second conductive pattern.
  • the first electrode layer covers the second conductive pattern, and the surface of the first electrode layer facing the base substrate is in contact with the surface of the second conductive pattern facing away from the base substrate.
  • the method for preparing a display substrate further includes: forming a first encapsulation layer on the first electrode layer.
  • the first packaging layer covers the first electrode layer, and the surface of the first packaging layer facing the base substrate is in contact with the surface of the first electrode layer facing away from the base substrate.
  • the method for preparing a display substrate further includes: forming a pixel drive circuit with a pixel structure on the base substrate in the display area.
  • the pixel driving circuit includes a thin film transistor and a storage capacitor.
  • the thin film transistor includes a gate, an active layer, a source and a drain.
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode.
  • the active layer is arranged in the same layer as the first conductive semiconductor pattern
  • the second capacitor electrode is arranged in the same layer as the first conductive pattern
  • the source and drain electrodes are arranged in the same layer as the second conductive pattern.
  • the first capacitor electrode and the gate electrode are provided in the same layer.
  • the display substrate provided by the embodiment of the present disclosure such as the above-mentioned display substrate 20, display substrate 30, display substrate 40, display substrate 50, or display substrate 70, can be prepared by the method for preparing the display substrate provided by the embodiment of the present disclosure.
  • the technical effects of the manufacturing method of the display substrate provided by the embodiments of the present disclosure may refer to the technical effects of the display substrate provided by the above-mentioned embodiments of the present disclosure, and details are not described herein again.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate according to any embodiment of the present disclosure, for example, the display substrate 20, the display substrate 30, the display substrate 40, the display substrate 50, or the display substrate 70 may be included.
  • the display device provided by the embodiment of the present disclosure may be an organic light emitting diode display device.
  • the display device provided by the embodiment of the present disclosure may also be a device with a display function such as a quantum dot light-emitting diode display device, an electronic paper display device, or other types of devices, which is not limited by the embodiment of the present disclosure.
  • the display device provided by the embodiment of the present disclosure may be any product or component with display function, such as a display substrate, a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display substrate such as a liquid crystal display (LCD)
  • a display panel such as a liquid crystal display (LCD)
  • an electronic paper such as a liquid crystal display
  • a mobile phone such as a tablet computer
  • a television a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the disclosed embodiment does not limit this.

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Abstract

一种显示基板及其制备方法、显示装置，该显示基板包括显示区域和周边区域。显示区域包括开口，周边区域包括至少部分围绕开口的第一周边区域；第一周边区域包括第一围堰区、第二围堰区和间隔区；显示基板包括衬底基板、第一导体化的半导体图案、第一导电图案和第二导电图案；第一导电图案与第一导体化的半导体图案间隔绝缘设置，第二导电图案与第一导电图案间隔绝缘设置；第一导电图案被配置为传输用于显示区域的电信号；第二导电图案通过设置在第一周边区域中的多个过孔与第一导体化的半导体图案电连接；第一导体化的半导体图案、第一导电图案和第二导电图案至少位于第一围堰区和间隔区，多个过孔在间隔区的排布密度小于在第一围堰区的排布密度。

Description

显示基板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置具有厚度薄、重量轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，因此被越来越广泛地应用于手机、平板电脑、数码相机等显示领域。
在制备过程中，通常需要对OLED显示装置中的显示器件进行封装以防止例如水汽或氧气等的浸入。OLED显示装置的封装技术主要包括盖板式封装和薄膜封装。薄膜封装主要包括利用有机封装层进行封装和/或利用无机封装层进行封装。在利用薄膜封装技术对显示器件进行封装时，形成的有机封装层和无机封装层间隔堆叠，以使例如水汽或氧气等难以渗入显示器件的内部。
发明内容
本公开至少一个实施例提供一种显示基板，该显示基板包括显示区域和围绕所述显示区域的周边区域；其中，所述显示区域包括开口，所述周边区域包括至少部分围绕所述开口的第一周边区域；所述第一周边区域包括第一围堰区、第二围堰区和间隔区，所述第一围堰区至少部分围绕所述开口，所述间隔区至少部分围绕所述第一围堰区，所述第二围堰区至少部分围绕所述间隔区；所述显示基板包括衬底基板、第一导体化的半导体图案、第一导电图案和第二导电图案；所述第一导体化的半导体图案位于所述衬底基板上，所述第一导电图案位于所述第一导体化的半导体图案远离所述衬底基板的一侧，与所述第一导体化的半导体图案间隔绝缘设置以能够形成电容，所述第二导电图案位于所述第一导电图案远离所述第一导体化的半导体图案的一 侧，与所述第一导电图案间隔绝缘设置以能够形成电容；所述第一导电图案被配置为传输用于所述显示区域的电信号；所述第二导电图案通过设置在所述第一周边区域中的多个过孔与所述第一导体化的半导体图案电连接；所述第一导体化的半导体图案、所述第一导电图案和所述第二导电图案至少位于所述第一围堰区和所述间隔区，所述多个过孔在所述间隔区的排布密度小于在所述第一围堰区的排布密度。
例如，本公开至少一个实施例提供的显示基板还包括第一绝缘层和第二绝缘层；其中，所述第一绝缘层位于所述第一导体化的半导体图案远离所述衬底基板的一侧，所述第一导电图案位于所述第一绝缘层远离所述第一导体化的半导体图案的一侧，所述第二绝缘层位于所述第一导电图案远离所述第一绝缘层的一侧，所述第二导电图案位于所述第二绝缘层远离所述第一导电图案的一侧；所述多个过孔至少位于所述第一绝缘层和所述第二绝缘层内且至少贯穿所述第一绝缘层和所述第二绝缘层。
例如，在本公开至少一个实施例提供的显示基板中，所述多个过孔在所述间隔区的排布密度为0。
例如，在本公开至少一个实施例提供的显示基板中，所述第一导体化的半导体图案和所述第二导电图案还位于所述第二围堰区中。
例如，在本公开至少一个实施例提供的显示基板中，所述第一导电图案还位于所述第二围堰区中。
例如，在本公开至少一个实施例提供的显示基板中，所述多个过孔在所述间隔区的排布密度小于在所述第二围堰区的排布密度。
例如，在本公开至少一个实施例提供的显示基板中，在所述间隔区内，所述第二导电图案在所述衬底基板上的正投影与所述第二绝缘层在所述衬底基板上的正投影重叠，且所述第二导电图案在所述衬底基板上的正投影的面积等于所述第二绝缘层在所述衬底基板上的正投影的面积。
例如，本公开至少一个实施例提供的显示基板还包括第一电极层；其中，所述第一电极层位于所述第二导电图案远离所述衬底基板的一侧且与所述第二导电图案电连接；在所述间隔区内，所述第一电极层覆盖所述第二导电图案，且所述第一电极层面向所述衬底基板的一侧的表面与所述第二导电图案背离所述衬底基板的一侧的表面接触。
例如，本公开至少一个实施例提供的显示基板还包括第一封装层；其中，所述第一封装层位于所述第一电极层远离所述衬底基板的一侧；在所述间隔区内，所述第一封装层覆盖所述第一电极层，且所述第一封装层面向所述衬底基板的一侧的表面与所述第一电极层背离所述衬底基板的一侧的表面接触。
例如，本公开至少一个实施例提供的显示基板还包括第一围堰结构和第二围堰结构，其中，所述第一围堰结构位于所述第一围堰区内，所述第二围堰结构位于所述第二围堰区内；在所述第一围堰区，所述第一围堰结构位于所述第一电极层远离所述衬底基板的一侧，所述第一封装层位于所述第一围堰结构远离所述第一电极层的一侧且覆盖所述第一围堰结构；在所述第二围堰区，所述第二围堰结构位于所述第二导电图案远离所述衬底基板的一侧且部分所述第二围堰结构覆盖所述第一电极层，所述第一封装层位于所述第一电极层和所述第二围堰结构远离所述第二导电图案的一侧且覆盖所述第一电极层和所述第二围堰结构。
例如，在本公开至少一个实施例提供的显示基板中，所述第一封装层位于所述第一围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离大于所述第一封装层位于所述间隔区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离，所述第一封装层位于所述第二围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离大于所述第一封装层位于所述间隔区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离。
例如，在本公开至少一个实施例提供的显示基板中，所述第一封装层位于所述第一围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离小于所述第一封装层位于所述第二围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离。
例如，本公开至少一个实施例提供的显示基板还包括位于所述第一周边区域除所述间隔区之外的第三绝缘层、第四绝缘层和第五绝缘层；其中，所述第一围堰结构包括所述第四绝缘层和所述第五绝缘层的叠层，所述第二围堰结构包括所述第三绝缘层、所述第四绝缘层和所述第五绝缘层的叠层；在所述第一围堰区中，所述第四绝缘层位于所述第一电极层远离所述衬底基板 的一侧，所述第五绝缘层位于所述第四绝缘层远离所述第一电极层的一侧，所述第一封装层位于所述第五绝缘层远离所述第四绝缘层的一侧，且覆盖所述第五绝缘层背离所述衬底基板的一侧的表面、所述第五绝缘层的至少一侧的侧表面和所述第四绝缘层的至少一侧的侧表面；在所述第二围堰区中，所述第三绝缘层位于所述第二导电图案远离所述衬底基板的一侧，所述第一电极层覆盖所述第三绝缘层背离所述衬底基板的一侧的部分表面和所述第三绝缘层靠近所述第一围堰区的一侧的侧表面，所述第四绝缘层位于所述第三绝缘层和所述第一电极层远离所述第二导电图案的一侧，所述第五绝缘层位于所述第四绝缘层远离所述第三绝缘层和所述第一电极层的一侧，所述第一封装层位于所述第五绝缘层远离所述第四绝缘层的一侧，且覆盖所述第五绝缘层背离所述衬底基板的一侧的表面、所述第五绝缘层的至少一侧的侧表面、所述第四绝缘层的至少一侧的侧表面、所述第三绝缘层背离所述衬底基板的一侧的部分表面和所述第三绝缘层远离所述第一围堰区的一侧的侧表面。
例如，在本公开至少一个实施例提供的显示基板中，在所述第二围堰区内，所述第三绝缘层覆盖所述第二导电图案背离所述衬底基板的一侧的部分表面和所述第二导电图案远离所述第一围堰区的一侧的侧表面。
例如，本公开至少一个实施例提供的显示基板还包括第二封装层；其中，所述第二封装层位于所述第一封装层远离所述第一电极层的一侧且覆盖所述第一封装层。
例如，在本公开至少一个实施例提供的显示基板中，所述第一导电图案包括沿第一方向并列排布的多条第一走线，所述第一导体化的半导体图案包括沿第二方向并列排布的多条第二走线，所述第一方向不同于所述第二方向。
例如，本公开至少一个实施例提供的显示基板还包括位于所述显示区域的像素结构，其中，所述像素结构包括位于所述衬底基板上的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容；所述薄膜晶体管包括栅极、有源层、源极和漏极，所述存储电容包括第一电容电极和与所述第一电容电极相对的第二电容电极，所述有源层与所述第一导体化的半导体图案同层设置，所述第二电容电极与所述第一导电图案同层设置，所述源极和所述漏极与所述第二导电图案同层设置。
例如，在本公开至少一个实施例提供的显示基板中，所述第一电容电极 与所述栅极同层设置。
例如，在本公开至少一个实施例提供的显示基板中，所述像素结构还包括第一平坦化层以及发光元件，所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面且包括第一过孔，所述发光元件在所述第一平坦化表面上，且通过所述第一过孔与所述像素驱动电路电连接，其中，在所述显示基板包括所述第三绝缘层的情形，所述第三绝缘层与所述第一平坦化层同层设置。
本公开至少一个实施例还提供一种显示基板，该显示基板包括显示区域和围绕所述显示区域的周边区域；其中，所述显示区域包括开口，所述周边区域包括至少部分围绕所述开口的第一周边区域；所述第一周边区域包括第一围堰区、第二围堰区和间隔区，所述第一围堰区至少部分围绕所述开口，所述间隔区至少部分围绕所述第一围堰区，所述第二围堰区至少部分围绕所述间隔区；所述显示基板包括衬底基板、第一导体化的半导体图案、第一导电图案和第二导电图案；所述第一导体化的半导体图案位于所述衬底基板上，所述第一导电图案位于所述第一导体化的半导体图案远离所述衬底基板的一侧，与所述第一导体化的半导体图案间隔绝缘设置以能够形成电容，所述第二导电图案位于所述第一导电图案远离所述第一导体化的半导体图案的一侧，与所述第一导电图案间隔绝缘设置以能够形成电容；所述第一导电图案被配置为传输用于所述显示区域的电信号；所述第二导电图案通过设置在所述第一周边区域中的多个过孔与所述第一导体化的半导体图案电连接；所述第一导体化的半导体图案、所述第一导电图案和所述第二导电图案至少位于所述第二围堰区和所述间隔区，所述多个过孔在所述间隔区的排布密度小于在所述第二围堰区的排布密度。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的显示基板。
本公开至少一个实施例还提供一种显示基板的制备方法，包括：提供衬底基板；在所述衬底基板上形成第一导体化的半导体图案；在所述第一导体化的半导体图案上形成第一导电图案，其中，所述第一导电图案与所述第一导体化的半导体图案间隔绝缘设置以能够形成电容；以及在所述第一导电图案上形成第二导电图案，其中，所述第二导电图案与所述第一导电图案间隔 绝缘设置以能够形成电容；其中，所述显示基板包括显示区域和围绕所述显示区域的周边区域，所述显示区域包括开口，所述周边区域包括至少部分围绕所述开口的第一周边区域；所述第一周边区域包括第一围堰区、第二围堰区和间隔区，所述第一围堰区至少部分围绕所述开口，所述间隔区至少部分围绕所述第一围堰区，所述第二围堰区至少部分围绕所述间隔区；所述第一导电图案被配置为传输用于所述显示区域的电信号；所述第二导电图案通过设置在所述第一周边区域中的多个过孔与所述第一导体化的半导体图案电连接；所述第一导体化的半导体图案、所述第一导电图案和所述第二导电图案至少位于所述第一围堰区和所述间隔区，所述多个过孔在所述间隔区的排布密度小于在所述第一围堰区的排布密度。
例如，在本公开至少一个实施例提供的显示基板的制备方法中，在所述第一导体化的半导体图案上形成所述第一导电图案，包括：在所述第一导体化的半导体图案上形成第一绝缘层，以及在所述第一绝缘层上形成所述第一导电图案；在所述第一导电图案上形成所述第二导电图案，包括：在所述第一导电图案上形成第二绝缘层，以及在所述第二绝缘层上形成所述第二导电图案；其中，所述多个过孔至少位于所述第一绝缘层和所述第二绝缘层内且至少贯穿所述第一绝缘层和所述第二绝缘层。
例如，本公开至少一个实施例提供的显示基板的制备方法还包括：在所述第二导电图案上形成第一电极层；其中，所述第一电极层与所述第二导电图案电连接；在所述间隔区内，所述第一电极层覆盖所述第二导电图案，且所述第一电极层面向所述衬底基板的一侧的表面与所述第二导电图案背离所述衬底基板的一侧的表面接触。
例如，本公开至少一个实施例提供的显示基板的制备方法还包括：在所述第一电极层上形成第一封装层；其中，在所述间隔区内，所述第一封装层覆盖所述第一电极层，且所述第一封装层面向所述衬底基板的一侧的表面与所述第一电极层背离所述衬底基板的一侧的表面接触。
例如，本公开至少一个实施例提供的显示基板的制备方法还包括：在所述显示区域，在所述衬底基板上形成像素结构的像素驱动电路；其中，所述像素驱动电路包括薄膜晶体管和存储电容，所述薄膜晶体管包括栅极、有源层、源极和漏极，所述存储电容包括第一电容电极和与所述第一电容电极相 对的第二电容电极；所述有源层与所述第一导体化的半导体图案同层设置，所述第二电容电极与所述第一导电图案同层设置，所述源极和所述漏极与所述第二导电图案同层设置。
例如，在本公开至少一个实施例提供的显示基板的制备方法中，所述第一电容电极与所述栅极同层设置。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种OLED显示装置的平面示意图；
图2A为本公开一些实施例提供的一种显示基板的平面示意图；
图2B为图2A所示的显示基板的第一周边区域的平面示意图；
图2C为本公开一些实施例提供的一种显示基板的部分截面结构的示意图；
图3为本公开一些实施例提供的另一种显示基板的平面示意图；
图4为本公开一些实施例提供的另一种显示基板的部分截面结构的示意图；
图5为本公开一些实施例提供的再一种显示基板的部分截面结构的示意图；
图6A和图6B为本公开一些实施例提供的一种多个过孔在第一周边区域内的排布方式的示意图；
图7为本公开一些实施例提供的再一种显示基板的部分截面结构的示意图；
图8为本公开一些实施例提供的一种显示基板中的像素驱动电路的等效电路图；以及
图9A-9E为本公开一些实施例提供的一种显示基板中的像素驱动电路的各层的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
为了提高OLED显示装置中显示器件的封装效果，在围绕显示区域的边框区域设置两个高度不同的围堰结构以阻挡例如水汽或氧气等渗入到显示器件的内部，从而避免对显示器件的各功能层造成不良的影响。相关技术中，将远离显示区域的围堰结构的高度设置为稍大于靠近显示区域的围堰结构的高度，并且将两个围堰结构之间的例如像素界定层、平坦层等有机膜层尽可能地全部去掉以形成“沟槽”区域，进而在封装后形成的封装层可以有效地阻挡例如水汽或氧气等渗入到显示器件的内部。
而目前，随着电子显示产品的不断普及，用户对电子显示产品的功能、外观的要求进一步提高。为了满足用户的不同实际需求，电子显示产品的外观或显示区域有时会需要被设计为不规则或特殊的形状。
图1为一种OLED显示装置的平面示意图。例如，如图1所示，该OLED显示装置10包括显示区域101和围绕显示区域101的边框区域102，显示区域101被设计为例如在至少一侧具有凹口103的不规则形状，该显示装置10可以在凹口103的区域中布置例如摄像头、距离传感器等器件，由此有助于实现窄边框显示装置。
例如，为了避免对显示装置10中显示器件的各功能层造成不良的影响，在围绕显示区域101的边框区域102内可以设置两个高度不同的围堰结构，并且将两个围堰结构之间的例如像素界定层、平坦层等有机膜层尽可能地全 部去掉以形成“沟槽”区域。进而，在封装后，形成的封装层可以有效地阻挡例如水汽或氧气等渗入到显示装置10的显示器件的内部。
由于显示区域101具有凹口103，通常在围绕凹口103的边框区域102内需要设置多条金属走线以将位于凹口103两侧的显示区域101中的多行像素单元对应电连接，以提供例如用于该多行像素单元的扫描信号等。并且，由于金属走线传输电信号的负载较低，通常会在金属走线的下方设计多条信号补偿走线以使信号补偿走线与金属走线之间可以形成电容，从而提高金属走线的传输负载，对金属走线的电信号传输效果进行补偿，进而避免位于凹口103两侧的显示区域101中的像素单元出现显示异常。
通常，在边框区域102通过设置辅助电极(以及覆盖且接触辅助电极的其他电极)将该多条信号补偿走线与提供例如驱动电流信号或驱动电压信号的电源信号线电连接，以使该多条信号补偿走线接收形成补偿电容所需的电信号。辅助电极通常设置在该多条信号补偿走线以及金属走线的上方(即靠近封装层的一侧)，并且通过设置在边框区域102中的多个过孔与信号补偿走线电连接。同时，由于金属走线的数量要求，在围绕凹口103的边框区域102内，部分金属走线需要设置于“沟槽”区域中，相应地，为了对该部分金属走线上的传输负载进行补偿，信号补偿走线也需要延伸至“沟槽”区域以与位于“沟槽”区域的金属走线之间形成电容，因而在“沟槽”区域也需要开设使辅助电极和信号补偿走线电连接的多个过孔。
但是，由于需要将边框区域102内两个围堰结构之间的例如像素界定层、平坦层等有机膜层尽可能地去掉，因此，形成的封装层在“沟槽”区域内会覆盖且直接接触辅助电极(或覆盖辅助电极的其他电极)的膜层表面。辅助电极与信号补偿走线之间设置的多个过孔会使辅助电极(或覆盖辅助电极的其他电极)的膜层表面出现多个凹坑，导致膜层表面呈上下起伏的形状而变得不平坦。进而，在对OLED显示装置10的“沟槽”区域进行封装时，形成在辅助电极(或覆盖辅助电极的其他电极)上的封装层的膜层表面也会相应地呈上下起伏的形状，导致封装层的膜层表面变得不平坦，进而使封装层的膜层表面容易产生裂纹。所产生的裂纹容易沿封装层不断扩展，并对封装层造成破坏，使封装层无法或难以防止例如水汽或氧气等渗入显示器件的内部，从而导致显示器件中的功能层被腐蚀或失效，对显示装置的性能造成严重的 不良影响，进而大大降低显装置的良率，缩短显示装置的使用寿命。
本公开至少一个实施例提供一种显示基板，该显示基板包括显示区域和围绕显示区域的周边区域。显示区域包括开口，周边区域包括至少部分围绕开口的第一周边区域；第一周边区域包括第一围堰区、第二围堰区和间隔区，第一围堰区至少部分围绕开口，间隔区至少部分围绕第一围堰区，第二围堰区至少部分围绕间隔区。显示基板包括衬底基板、第一导体化的半导体图案、第一导电图案和第二导电图案；第一导体化的半导体图案位于衬底基板上；第一导电图案位于第一导体化的半导体图案远离衬底基板的一侧，与第一导体化的半导体图案间隔绝缘设置以能够形成电容；第二导电图案位于第一导电图案远离第一导体化的半导体图案的一侧，与第一导电图案间隔绝缘设置以能够形成电容；第一导电图案被配置为传输用于显示区域的电信号；第二导电图案通过设置在第一周边区域中的多个过孔与第一导体化的半导体图案电连接；第一导体化的半导体图案、第一导电图案和第二导电图案至少位于第一围堰区和间隔区，多个过孔在间隔区的排布密度小于在第一围堰区的排布密度，例如在间隔区中相邻过孔之间的距离大于在第一围堰区中相邻过孔之间的距离。
本公开上述实施例提供的显示基板通过减小使第二导电图案与第一导体化的半导体图案电连接的多个过孔在间隔区的排布密度，减弱了位于间隔区中的第二导电图案的膜层表面因过孔设计而产生的上下起伏现象，使第二导电图案的膜层表面变得更加平坦，并进而使覆盖第二导电图案的第一电极层以及封装层的膜层表面均可以变得更加平坦，从而减弱或避免封装层表面出现裂纹。由此，本公开上述实施例提供的显示基板可以提高制备的封装层的均匀性和一致性，改善封装层对显示基板的封装效果，从而有效地避免例如水汽或氧气等渗入显示器件的内部而对显示器件的功能层造成例如腐蚀或失效等不良影响，进而提升显示基板的性能和良率，延长显示基板的使用寿命。
下面，将参考附图详细地说明本公开的一些实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
图2A为本公开一些实施例提供的一种显示基板的平面示意图，图2B为图2A所示的显示基板的第一周边区域的平面示意图，图2C为本公开一些实施例提供的一种显示基板的部分截面结构的示意图。例如，图2C为图2A所 示的显示基板沿A-A’线的截面结构示意图。
例如，结合图2A-图2C所示，显示基板20包括显示区域201和围绕显示区域201的周边区域202。显示区域201包括开口，该开口可以为封闭开口或非封闭开口，在开口所在区域中可以布置例如摄像头、距离传感器等器件，由此有助于实现窄边框显示装置。例如，该开口可以为图2A中所示形成在显示区域201至少一侧的凹口(非封闭开口的示例)，周边区域202包括至少部分围绕该开口的第一周边区域203。第一周边区域203包括第一围堰区204、第二围堰区205和间隔区206，第一围堰区204至少部分围绕开口，间隔区206至少部分围绕第一围堰区204，第二围堰区205至少部分围绕间隔区206，由此相对于开口由近到远布置第一围堰区204、间隔区206和第二围堰区205。
显示基板20包括衬底基板210、第一导体化的半导体图案220、第一导电图案230和第二导电图案240。第一导体化的半导体图案220位于衬底基板210上；第一导电图案230位于第一导体化的半导体图案220远离衬底基板210的一侧，与第一导体化的半导体图案220间隔绝缘设置以能够形成电容；第二导电图案240位于第一导电图案230远离第一导体化的半导体图案220的一侧，与第一导电图案230间隔绝缘设置以能够形成电容。第一导电图案230被配置为传输用于显示区域201的电信号，例如该电信号可以为用于显示区域201中的像素驱动电路的栅极扫描信号、发光控制信号、复位信号等中的一种或多种。第二导电图案240通过设置在第一周边区域203中的多个过孔250与第一导体化的半导体图案220电连接。第一导体化的半导体图案220、第一导电图案230和第二导电图案240至少位于第一围堰区204和间隔区206，多个过孔250在间隔区206的排布密度小于在第一围堰区204的排布密度。
在一些实施例中，结合图2A和图2C所示，第一导电图案230包括沿第一方向R1并列排布的多条第一走线231，第一导体化的半导体图案220包括沿第二方向R2并列排布的多条第二走线221，第一方向R1不同于第二方向R2。例如，第一方向R1可以垂直于第二方向R2，以使多条第一走线231和多条第二走线221分别呈交叉排布，从而使多条第一走线231和多条第二走线221之间可以形成电容，进而提高多条第一走线231的传输负载，对多条 第一走线231上的电信号传输效果进行补偿，使显示区域201中各部分的显示效果可以保持均匀一致。
在一些实施例中，在图2C所示的显示基板20中，在第一围堰区204内，相邻的两条第一走线231之间均设置有一个过孔250；而在间隔区206内，每相隔两条第一走线231设置有一个过孔，进而在间隔区206内相邻过孔250之间的距离大于在第一围堰区204内相邻过孔250之间的距离，使过孔250在间隔区206的排布密度小于在第一围堰区204的排布密度。
在本公开的上述实施例中，通过减小多个过孔250在间隔区206的排布密度，可以减弱位于间隔区206中的第二导电图案240的表面因过孔设计而产生的上下起伏现象，进而使第二导电图案240的膜层表面变得更加平坦。由此，使覆盖第二导电图案240的结构层或功能层(例如下文中提到的第一电极层270)的背离衬底基板210一侧的表面可以更加平坦，进而在对显示基板20中的显示器件进行封装时，可以进一步使形成的封装层(例如下文中提到的第一封装层281)的背离衬底基板210一侧的表面可以更加平坦，从而减弱或避免封装层表面出现裂纹，提高制备的封装层的均匀性和一致性。因此，上述实施例中，显示基板20的封装效果可以得到显著地改善，可以有效地避免例如水汽或氧气等渗入显示基板20的显示器件的内部而对显示器件造成不良影响，进而提升显示基板20的性能和良率，延长显示基板20的使用寿命。
需要说明的是，在图2C所示的本公开实施例中，在第一围堰区204内，相邻的两条第一走线231之间设置有一个过孔250；在间隔区206内，每相隔两条第一走线231设置有一个过孔。而在本公开的其他一些实施例中，还可以是在第一围堰区204内，相邻的两条第一走线231之间设置有一个过孔250；在间隔区206内，每相隔三条或更多条第一走线231设置有一个过孔250。在本公开的其他一些实施例中，可以是在第一围堰区204内，每相隔n(n为大于1的整数)条第一走线231设置有一个过孔250；在间隔区206内，每相隔n+m(m为大于0的整数)条第一走线231设置有一个过孔250。也即，在本公开实施例中，只要多个过孔在间隔区的排布密度小于在第一围堰区的排布密度即可，本公开实施例对间隔区和第一围堰区内过孔的具体排布方式或排布数量等不作限制。
需要说明的是，在图2C所示的本公开实施例中，在第一围堰区204和间隔区206内沿第一方向R1排布的第一走线231的具体数量只是示例性说明。例如，在本公开的其他一些实施例中，第一走线231的设置数量可以根据显示区域201中位于开口两侧的像素单元的行数或者根据不同的实际需求而进行确定，而第一围堰区204和间隔区206内排布的第一走线231的数量可以根据例如第一围堰区204以及间隔区206的实际尺寸、第一走线231的设置需求(例如第一走线231的宽度等)而进行相应调整，本公开的实施例对此不作限制。
例如，在图2C所示的本公开实施例中，第一围堰区204、间隔区206、第二围堰区205在第一方向R1上的宽度均可以设置大约为40μm，例如可以设置在35μm～45μm的范围内。
在一些实施例中，如图2C所示，显示基板20还包括第一绝缘层261和第二绝缘层262。第一绝缘层261位于第一导体化的半导体图案220远离衬底基板210的一侧，第一导电图案230位于第一绝缘层261远离第一导体化的半导体图案220的一侧，第二绝缘层262位于第一导电图案230远离第一绝缘层261的一侧，第二导电图案240位于第二绝缘层262远离第一导电图案230的一侧。多个过孔250至少位于第一绝缘层261和第二绝缘层262内且至少贯穿第一绝缘层261和第二绝缘层262。
例如，第一导体化的半导体图案220中的多条第二走线221和第一导电图案230中的多条第一走线231使用第一绝缘层261作为介电材料以形成电容，进而提高多条第一走线231的传输负载，对多条第一走线231上的电信号传输效果进行补偿，使显示基板20的显示区域201中各部分的显示效果可以保持均匀一致。
在一些实施例中，如图2C所示，显示基板20还包括第一电极层270。第一电极层270位于第二导电图案240远离衬底基板210的一侧且与第二导电图案240电连接。在间隔区206内，第一电极层270覆盖第二导电图案240，且第一电极层270面向衬底基板210的一侧的表面与第二导电图案240背离衬底基板210的一侧的表面接触。
在一些实施例中，如图2C所示，显示基板20还包括第一封装层281。第一封装层281位于第一电极层270远离衬底基板210的一侧。在间隔区206 内，第一封装层281覆盖第一电极层270，且第一封装层281面向衬底基板210的一侧的表面与第一电极层270背离衬底基板210的一侧的表面接触。
在上述实施例中，通过减小多个过孔250在间隔区206的排布密度，减弱了位于间隔区206中的第二导电图240案的表面因过孔设计而产生的上下起伏现象，使第二导电图案240的膜层表面变得更加平坦，进而使覆盖第二导电图案240的第一电极层270以及覆盖第一电极层270的第一封装层281的膜层表面均可以变得更加平坦，从而减弱或避免第一封装层281表面出现裂纹。由此，可以提高制备的第一封装层281的均匀性和一致性，改善第一封装层281对显示基板20的显示器件的封装效果，有效地避免例如水汽或氧气等渗入显示基板20的显示器件的内部而对显示器件造成不良影响，进而提升显示基板20的性能和良率，延长显示基板20的使用寿命。
在一些实施例中，如图2C所示，显示基板20还包括第一围堰结构和第二围堰结构。第一围堰结构位于第一围堰区204内，第二围堰结构位于第二围堰区205内。在第一围堰区204，第一围堰结构位于第一电极层270远离衬底基板210的一侧，第一封装层281位于第一围堰结构远离第一电极层270的一侧且覆盖第一围堰结构。在第二围堰区205，第二围堰结构位于第二导电图案240远离衬底基板210的一侧且部分第二围堰结构覆盖第一电极层270，第一封装层281位于第一电极层270和第二围堰结构远离第二导电图案240的一侧且覆盖第一电极层270和第二围堰结构。
在一些实施例中，如图2C所示，第一封装层281位于第一围堰区204的部分的背离衬底基板210的一侧的表面与衬底基板210之间的最大距离D1大于第一封装层281位于间隔区206的部分的背离衬底基板210的一侧的表面与衬底基板210之间的最大距离D3。第一封装层281位于第二围堰区205的部分的背离衬底基板210的一侧的表面与衬底基板210之间的最大距离D2大于第一封装层281位于间隔区206的部分的背离衬底基板210的一侧的表面与衬底基板210之间的最大距离D3。因而，显示基板20将间隔区206内的例如像素界定层、平坦层等有机膜层去掉后，通过第一围堰结构和第二围堰结构在第一周边区域203内形成“沟槽”，从而在封装后可以有效地阻挡例如水汽或氧气等渗入到显示基板20的显示器件的内部，避免对显示器件的各功能层或结构层等造成不良的影响。
在一些实施例中，如图2C所示，第一封装层281位于第一围堰区204的部分的背离衬底基板210的一侧的表面与衬底基板210之间的最大距离D1小于第一封装层281位于第二围堰区205的部分的背离衬底基板210的一侧的表面与衬底基板210之间的最大距离D2。由此，通过距离衬底基板210高度不同的第一围堰结构和第二围堰结构可以在封装后更有效地阻挡例如水汽或氧气等渗入到显示基板20的显示器件的内部，进一步避免对显示器件的各功能层或结构层等造成不良的影响。
在一些实施例中，如图2C所示，显示基板20还包括位于第一周边区域203除间隔区206之外的第三绝缘层263、第四绝缘层264和第五绝缘层265。第一围堰结构包括第四绝缘层264和第五绝缘层265的叠层，第二围堰结构包括第三绝缘层263、第四绝缘层264和第五绝缘层265的叠层。
在第一围堰区204中，第四绝缘层264位于第一电极层270远离衬底基板210的一侧，第五绝缘层265位于第四绝缘层264远离第一电极层270的一侧，第一封装层281位于第五绝缘层265远离第四绝缘层264的一侧，且覆盖第五绝缘层265背离衬底基板210的一侧的表面、第五绝缘层265的至少一侧的侧表面和第四绝缘层264的至少一侧的侧表面。
在第二围堰区205中，第三绝缘层263位于第二导电图案240远离衬底基板210的一侧，第一电极层270覆盖第三绝缘层263背离衬底基板210的一侧的部分表面和第三绝缘层263靠近第一围堰区204的一侧的侧表面，第四绝缘层264位于第三绝缘层263和第一电极层270远离第二导电图案240的一侧，第五绝缘层265位于第四绝缘层264远离第三绝缘层263和第一电极层270的一侧，第一封装层281位于第五绝缘层265远离第四绝缘层264的一侧，且覆盖第五绝缘层265背离衬底基板210的一侧的表面、第五绝缘层265的至少一侧的侧表面、第四绝缘层264的至少一侧的侧表面、第三绝缘层263背离衬底基板210的一侧的部分表面和第三绝缘层263远离第一围堰区204的一侧的侧表面。
在一些实施例中，如图2C所示，在第二围堰区205内，第三绝缘层263覆盖第二导电图案240背离衬底基板210的一侧的部分表面和第二导电图案240远离第一围堰区204的一侧的侧表面。
在一些实施例中，如图2C所示，显示基板20还包括第二封装层282。 第二封装层282位于第一封装层281远离第一电极层270的一侧且覆盖第一封装层281。例如，第一封装层281和第二封装层282均可以为有机封装层，通过第一封装层281和第二封装层282的堆叠设置可以进一步使例如水汽或氧气等难以渗入显示基板20的显示器件的内部。
需要说明的是，在图2C所示的本公开实施例中，第一导体化的半导体图案220和第一导电图案230之间仅设置有一层第一绝缘层261，第一导电图案230和第二导电图案240之间仅设置有一层第二绝缘层262。而在本公开的其他一些实施例中，在第一导体化的半导体图案220和第一导电图案230之间除第一绝缘层261外还可以设置有其他绝缘层或其他结构层或功能层，在第一导电图案230和第二导电图案240之间除第二绝缘层262外同样还可以设置有其他绝缘层或其他结构层或功能层，只要满足过孔可以贯穿相应的绝缘层使第一导体化的半导体图案220能够和第二导电图案240电连接，进而使第一导电图案230与第一导体化的半导体图案220之间形成补偿电容即可，本公开实施例对此不作具体限制。
需要说明的是，在本公开的其他一些实施例中，显示基板在第一周边区域还可以包括除图2C所示的例如第一导体化的半导体图案、第一导电图案、第二导电图、第一绝缘层、第二绝缘层等以外的其他结构或功能层，只要满足可以使第一导电图案与第一导体化的半导体图案之间形成电容以实现补偿效果即可。本公开实施例对此不作限制。
需要说明的是，图2C所示的截面结构可以为对应于图2A所示的显示基板20沿A-A’线的截面结构；或者在本公开的其他一些实施例中，图2C所示的截面结构也可以为对应于例如如图3所示的显示基板30(包括显示区域301)沿B-B’线的截面结构，图3中所示的显示基板30的开口为封闭的。也即，本公开的实施例对显示基板的显示区域的开口的具体形状以及设置位置等均不作限制。
需要说明的是，本公开实施例对显示基板的形状或轮廓等也不作限制，例如本公开实施例的显示基板可以是如图2A或图3所示的方形，也可以是例如圆形、正六边形、正八边形等其他合适的规则形状或不规则形状等。本公开实施例对此不作限制。
在一些实施例中，衬底基板210可以为玻璃板、石英板、金属板或树脂 类板件等。例如，衬底基板210的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。例如，衬底基板210可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
在一些实施例中，第一绝缘层261、第二绝缘层262、第三绝缘层263、第四绝缘层264、第五绝缘层265的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层的材料均不做具体限定。例如，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层的材料可以彼此相同或部分相同，也可以彼此不相同，本公开的实施例对此不作限制。
在一些实施例中，第一导体化的半导体图案220的多条第二走线221的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。
在一些实施例中，第一导电图案230的多条第一走线231的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
在一些实施例中，第二导电图案240的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(例如钛、铝及钛三层金属叠层(Al/Ti/Al))。
在一些实施例中，第一电极层270的材料可以包括至少一种导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等，或者还可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
在一些实施例中，第一封装层261和第二封装层262的材料可以包括氮化硅、氧化硅、氮氧化硅等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入。
例如，在本公开的一些实施例中，多个过孔在间隔区的排布密度可以设置为0，也即在间隔区内不设置过孔。由此，可以消除或进一步减弱位于间隔区中的第二导电图案的表面因过孔设计而产生的上下起伏现象，使第二导电图案的膜层表面保持均匀平坦。进而，使覆盖第二导电图案的第一电极层以及覆盖第一电极层的第一封装层的膜层表面均可以保持均匀平坦，从而避 免或显著减弱第一封装层表面出现裂纹的现象，进一步提高第一封装层的均匀性和一致性，改善第一封装层对显示基板的封装效果。进一步，还可以使覆盖第一封装层的第二封装层的膜层表面保持均匀平坦，避免或显著减弱第二封装层表面出现裂纹的现象，从而提高制备的第二封装层表面的均匀性和一致性，改善第二封装层对显示基板的封装效果。
图4为本公开一些实施例提供的另一种显示基板的部分截面结构的示意图。例如，图4也可以为图2A所示的显示基板沿A-A’线的截面结构示意图，或者也可以为图3所示的显示基板沿B-B’线的截面结构示意图。例如，图4所示的显示基板40除第一导体化的半导体图案420、第二导电图案440和过孔450以外的其他结构均与图2C所示的显示基板20基本相同或相似，在此不再赘述。
在一些实施例中，如图4所示，第一导体化的半导体图案420、第二导电图案440和多个过孔450位于第一围堰区404、间隔区406和第二围堰区405中。由此，通过在第一围堰区404和第二围堰区405中均设置能够使第一导体化的半导体图案420和第二导电图案440电连接的过孔450，可以进一步提升第一导体化的半导体图案420和第二导电图案440之间的电连接效果。
在一些实施例中，如图4所示，多个过孔450在间隔区406的排布密度可以设置为0。也就是说，在保证第一导体化的半导体图案420和第二导电图案440之间的电连接效果的情形下，可以在显示基板40的间隔区406内不设置过孔450，从而可以消除或进一步减弱位于间隔区406中的第二导电图案440的表面因过孔设计而产生的上下起伏现象，使第二导电图案440的膜层表面保持均匀平坦。进而，使覆盖第二导电图案440的第一电极层470以及覆盖第一电极层470的第一封装层481的膜层表面均可以保持均匀平坦，从而避免或显著减弱第一封装层481表面出现裂纹的现象，进一步提高第一封装层481的均匀性和一致性，进而改善第一封装层481对显示基板40的封装效果。进一步，还可以使覆盖第一封装层481的第二封装层482的膜层表面保持均匀平坦，避免或显著减弱第二封装层482表面出现裂纹的现象，从而提高制备的第二封装层482表面的均匀性和一致性，改善第二封装层482对显示基板40的封装效果。
例如，在图4所示的本公开实施例中，多个过孔450在第一围堰区404的排布密度与在第二围堰区405的排布密度相同。而在本公开的其他一些实施例中，多个过孔在第一围堰区的排布密度与在第二围堰区的排布密度也可以不同，本公开的实施例对此不作限制。
图5为本公开一些实施例提供的再一种显示基板的部分截面结构的示意图。例如，图5也可以为图2A所示的显示基板沿A-A’线的截面结构示意图，或者也可以为图3所示的显示基板沿B-B’线的截面结构示意图。例如，图5所示的显示基板50除第一导体化的半导体图案520、第一导电图案530、第二导电图案540和过孔550以外的其他结构均与图2C所示的显示基板20基本相同或相似，或者图5所示的显示基板40除第一导电图案530以外的其他结构均与图4所示的显示基板40基本相同或相似，在此不再赘述。
在一些实施例中，如图5所示，相比于图4所示的显示基板40，第一导电图案530还位于第二围堰区505中。也就是说，第一导体化的半导体图案520、第一导电图案530、第二导电图案540和多个过孔550均至少位于第一围堰区504、第二围堰区505以及间隔区506中。
在一些实施例中，如图5所示，多个过孔550在间隔区406的排布密度为0。由此，在保证第一导体化的半导体图案520和第二导电图案540之间的电连接效果的情形下，通过在显示基板50的间隔区506内不设置过孔550，可以消除或进一步减弱位于间隔区506中的第二导电图案540的表面因过孔设计而产生的上下起伏现象，使第二导电图案540的膜层表面保持均匀平坦。进而，使覆盖第二导电图案540的第一电极层570以及覆盖第一电极层570的第一封装层581的膜层表面均可以保持均匀平坦，从而避免或显著减弱第一封装层581表面出现裂纹的现象，进而进一步提高制备的第一封装层581的均匀性和一致性，改善第一封装层581对显示基板50的封装效果。
例如，在图5所示的本公开实施例中，过孔550在第一围堰区504的排布密度和在第二围堰区505的排布密度相同。而在本公开的其他一些实施例中，过孔在第一围堰区的排布密度和在第二围堰区的排布密度也可以不同。例如，可以使过孔在第一围堰区的排布密度大于在第二围堰区的排布密度，且在第二围堰区的排布密度大于在间隔区的排布密度；或者，也可以使过孔在第二围堰区的排布密度大于在第一围堰区的排布密度，且在第一围堰区的 排布密度大于在间隔区的排布密度，本公开的实施例对此不作限制。
在本公开的其他一些实施例中，在过孔在第一围堰区的排布密度大于在间隔区的排布密度的情形，可以将过孔在第二围堰区的排布密度设置为与在间隔区的排布密度相同，例如可以将过孔在第二围堰区的排布密度和在间隔区的排布密度均设置为0。或者，在本公开的其他一些实施例中，在过孔在第二围堰区的排布密度大于在间隔区的排布密度的情形，可以将过孔在第一围堰区的排布密度设置为与在间隔区的排布密度相同，例如可以将过孔在第一围堰区的排布密度和在间隔区的排布密度均设置为0。本公开的实施例对此不作限制。
例如，在本公开的其他一些实施例中，在使第一导体化的半导体图案和第二导电图案通过设置在第一围堰区和第二围堰区的过孔电连接的情形下，间隔区内也可以根据实际需求设置过孔，只要满足多个过孔在间隔区的排布密度小于在第一围堰区和第二围堰区的排布密度即可。本公开的实施例对此不作限制。
图6A和图6B为本公开一些实施例提供的一种多个过孔在第一周边区域内的排布方式的示意图。例如，图6A和图6B可以为图5所示的显示基板50中的多个过孔550在第一周边区域503内的排布方式的示意图。需要说明的是，为了便于说明，图6A中仅示出了第一导体化的半导体图案520、第一导电图案530和第二导电图案540之间的设置关系，图6B中示出了第一导体化的半导体图案520、第一导电图案530、第二导电图案540和第一电极层570之间的设置关系，显示基板50中的其他结构或功能层的设计可以参考本领域技术内的常规设置方式，在此不再赘述。
例如，以图5所示的显示基板50为例，图6A中示出了第一导体化的半导体图案520、第一导电图案530和第二导电图案540在平行于衬底基板510的表面的平面内的位置关系以及多个过孔550的排布方式，图6B中示出了第一导体化的半导体图案520、第一导电图案530、第二导电图案540和第一电极层570在平行于衬底基板510的表面的平面内的位置关系以及多个过孔550的排布方式。
在一些实施例中，如图6A和图6B所示，第一导体化的半导体图案520包括沿第二方向R2排布的多条第二走线521，第一导电图案530包括沿第一 方向R1排布的多条第一走线531，第一方向R1垂直于第二方向R2。
例如，多条第一走线531沿第一方向R1间隔排布，且每条第一走线531与多条第二走线521彼此部分交叠。多条第二走线521沿第二方向R2间隔排布，且每条第二走线521与多条第一走线531彼此部分交叠。例如，过孔550可以设置在第二走线521未与第一走线531交叠的部分，也即设置在两条相邻的第一走线531之间的间隙内。
例如，第一电极层570覆盖设置在第一围堰区504内的过孔550，且至少覆盖设置在第二围堰区505内的部分过孔550。
例如，在第一围堰区504和间隔区506内，第一电极层570覆盖多条第一走线531和多条第二走线521。在第二围堰区505内，第一电极层570覆盖多条第一走线531中的部分走线，且分别覆盖多条第二走线521中的每条的一部分。
需要说明的是，在图6A和图6B所示的实施例中，多条第一走线531均采用相同的材料，而在本公开的其他一些实施例中，多条第一走线531也可以分别采用不同的材料交替形成，本公开的实施例对此不作限制。
多条第一走线531可以采用跟显示区域中像素结构中的某一结构同层形成。多条第一走线531也可以采用跟显示区域中像素结构中的两个结构同层形成，即一部分第一走线跟像素结构中的一个结构同层形成，另一部分第一走线跟像素结构中的另一个结构同层形成。在一些实施例中，这两部分第一走线交替排列形成多条第一走线531。多条第一走线531也可以采用跟显示区域中像素结构中的三个结构同层形成，即第一部分第一走线跟像素结构中的第一个结构同层形成，第二部分第一走线跟像素结构中的第二个结构同层形成，第三部分第一走线跟像素结构中的第三个结构同层形成。在一些实施例中，这三部分第一走线中各有一条走线，三条走线依次排列作为一组，多组排列形成多条第一走线531；在另一些实施例中，这三部分第一走线中的每一部分整体作为一个组，三组排列形成多条第一走线531。
需要说明的是，在第二方向R2上，每条第二走线521上开设的过孔550的数量只是示例性说明。在本公开的其他一些实施例中，在第二方向R2上，每条第二走线上开设的过孔的数量可以根据第二走线在第二方向R2上的宽度或制备工艺精度等因素而确定，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，在间隔区内，第二导电图案在衬底基板上的正投影与第二绝缘层在衬底基板上的正投影重叠，且第二导电图案在衬底基板上的正投影的面积等于第二绝缘层在衬底基板上的正投影的面积。
例如，以图5所示的显示基板50为例，第二导电图案540在间隔区506区内可以呈一整片设置，第二绝缘层562也可以呈一整片设置，进而在间隔区506不设置过孔550的情形，在间隔区506内，第二导电图案540在衬底基板510上的正投影与第二绝缘层562在衬底基板510上的正投影重叠，且第二导电图案540在衬底基板510上的正投影的面积等于第二绝缘层562在衬底基板510上的正投影的面积。
例如，在本公开的一些实施例中，显示基板还包括位于显示区域的像素结构。像素结构包括位于衬底基板上的像素驱动电路，像素驱动电路包括薄膜晶体管和存储电容；薄膜晶体管包括栅极、有源层、源极和漏极，存储电容包括第一电容电极和与第一电容电极相对的第二电容电极，有源层与第一导体化的半导体图案同层设置，栅极与第一电容电极同层设置，第二电容电极与第一导电图案同层设置，源极和漏极与第二导电图案同层设置。由此，可以简化显示基板的制备工艺，减少显示基板的制备成本。
需要说明的是，“同层设置”为两个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构，例如可以在先形成该材料层后，由该材料层经过构图工艺形成。
需要说明的是，在本公开的其他一些实施例中，第一导电图案也可以与栅极和第一电容电极同层设置；在本公开的其他一些实施例中，也可以是一部分第一导电图案与第二电容电极同层设置，另一部分第一导电图案与栅极和第一电容电极同层设置，即第一导电图案包括交替形成的两部分，本公开实施例对此不作限制。
下面以图5所示的显示基板50的第一周边区域503中的截面结构为例，对本公开实施例提供的显示基板的显示区域进行说明。
图7为本公开一些实施例提供的再一种显示基板的部分截面结构的示意图。例如，图7所示的显示基板70的第一周边区域703的部分与图5所示的显示基板50的第一周边区域503的部分基本相同或相似，在此不再赘述。
例如，如图7所示，显示基板70还包括位于显示区域701的像素结构，以用于实现发光驱动、控制等功能。该像素结构包括位于衬底基板710上的像素驱动电路7120、第一平坦化层7150及发光元件7140。
例如，通过第一导电图案730(例如第一导电图案730中的多条第一走线731)可以将显示区域701中位于开口左右两侧的多行像素单元中的像素驱动电路7120对应电连接，以传输用于像素驱动电路7120的例如栅极扫描信号、发光控制信号、复位信号等中的一种或多种电信号。
例如，可以对应位于显示区域701的开口左右两侧的每行像素驱动电路7120设置一条第一走线731以传输上述电信号中的一种，例如通过第一走线731将位于显示区域701的开口左右两侧的每行像素驱动电路7120的栅线电连接以传输栅极扫描信号；也可以对应位于显示区域701的开口左右两侧的每行像素驱动电路7120设置多条第一走线731以分别传输上述多种电信号，例如通过第一走线731分别将位于显示区域701的开口左右两侧的每行像素驱动电路7120的栅线和发光控制线电连接以分别传输栅极扫描信号和发光控制信号，本公开的实施例对此不作限制。
例如，通过在第一导电图案730的下方设置第一导体化的半导体图案720(例如第一导体化的半导体图案720中的多条第二走线721)，可以使多条第二走线721与多条第一走线731之间形成电容，从而提高第一走线731的传输负载，对第一走线731的电信号传输效果进行补偿。由此，使显示区域701中位于开口左右两侧的像素单元的显示效果可以与显示区域701中的其他像素单元的显示效果保持一致，避免或减弱画面在不同灰阶下出现显示异常，进而提升显示基板70的画面显示效果。
例如，第一导体化的半导体图案720通过过孔750与第二导电图案740电连接且进一步与第一电极层770电连接，例如第一电极层770可以被配置为接收低电压信号(例如提供给发光元件7140的阴极信号)，进而使第一导体化的半导体图案720中的多条第二走线721被施加低电压信号，由此使传输例如栅极扫描信号的第一走线731与第二走线721之间能够形成电容，以实现补偿的效果。
下面，本公开实施例以对应位于显示区域701的开口左右两侧的每行像素驱动电路7120设置一条第一走线731以传输栅极扫描信号(即，通过第一 走线731将位于显示区域701的开口左右两侧的每行像素驱动电路7120的栅线电连接以传输栅极扫描信号)为例，结合像素驱动电路7120的具体结构对显示基板70进行说明。
图8为本公开一些实施例提供的一种显示基板中的像素驱动电路的等效电路图，图9A-9E为本公开一些实施例提供的一种显示基板中的像素驱动电路的各层的示意图。例如，图7为包括图8和图9A中所示的像素驱动电路7120的显示基板70的部分截面结构的示意图。需要说明的是，图8和图9A中所示的像素驱动电路7120的具体结构只是示例性说明，本公开的实施例包括但并不仅限于此。
在一些实施例中，如图8所示，像素驱动电路7120包括多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的多个信号线和存储电容Cst，多个信号线包括栅线GL、发光控制线EM、初始化线RL、数据线DAT和第一电源线VDD。栅线GL可包括第一栅线GLn和第二栅线GLn-1，例如第一栅线GLn可用于传输栅极扫描信号，第二栅线GLn-1可用于传输复位信号。发光控制线EM可用于传输发光控制信号。由此，像素驱动电路7120为7T1C的像素驱动电路。
需要说明的是，本公开实施例包括但并不限于此，像素驱动电路7120也可采用其他类型的电路结构，例如7T2C结构或者9T2C结构等，本公开实施例对此不作限制。
例如，可以通过第一走线731将位于显示区域701的开口左右两侧的每行像素驱动电路7120的第一栅线GLn电连接以传输栅极扫描信号，从而实现栅极扫描信号的补偿效果。
例如，如图8所示，第一薄膜晶体管T1的第一栅极G1与第三薄膜晶体管T3的第三漏极D3和第四薄膜晶体管T4的第四漏极D4电连接。第一薄膜晶体管T1的第一源极S1与第二薄膜晶体管T2的第二漏极D2和第五薄膜晶体管T5的第五漏极D5电连接。第一薄膜晶体管T1的第一漏极D1与第三薄膜晶体管T3的第三源极S3和第六薄膜晶体管T6的第六源极S6电连接。
例如，如图8所示，第二薄膜晶体管T2的第二栅极G2被配置为与第一栅线GLn电连接以接收栅极扫描信号，第二薄膜晶体管T2的第二源极S2 被配置为与数据线DAT电连接以接收数据信号，第二薄膜晶体管T2的第二漏极D2与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图8所示，第三薄膜晶体管T3的第三栅极G3被配置为与第一栅线GLn电连接，第三薄膜晶体管T3的第三源极S3与第一薄膜晶体管T1的第一漏电极D1电连接，第三薄膜晶体管T3的第三漏极D3与第一薄膜晶体管T1的第一栅极G1电连接。
例如，如图8所示，第四薄膜晶体管T4的第四栅极G4被配置为与第二栅线GLn-1电连接以接收复位信号，第四薄膜晶体管T4的第四源极S4被配置为与初始化线RL电连接以接收初始化信号，第四薄膜晶体管T4的第四漏极D4与第一薄膜晶体管T1的第一栅极G1电连接。
例如，如图8所示，第五薄膜晶体管T5的第五栅极G5被配置为与发光控制线EM电连接以接收发光控制信号，第五薄膜晶体管T5的第五源极S5被配置为与第一电源线VDD电连接以接收第一电源信号，第五薄膜晶体管T5的第五漏极D5与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图8所示，第六薄膜晶体管T6的第六栅极G6被配置为与发光控制线EM电连接以接收发光控制信号，第六薄膜晶体管T6的第六源极S6与第一薄膜晶体管T1的第一漏极D1电连接，第六薄膜晶体管T6的第六漏极D6与发光元件7140的第一显示电极(例如阳极)电连接。
例如，如图8所示，第七薄膜晶体管T7的第七栅极G7被配置为与第二栅线GLn-1电连接以接收复位信号，第七薄膜晶体管T7的第七源极S7与发光元件7140的第一显示电极(例如阳极)电连接，第七薄膜晶体管T7的第七漏极D7被配置为与初始化线RL电连接以接收初始化信号。例如，第七薄膜晶体管T7的第七漏极D7可以通过连接到第四薄膜晶体管T4的第四源极S4以实现与初始化线RL电连接。
例如，如图8所示，存储电容Cst包括第一电容电极CE1和第二电容电极CE2。第二电容电极CE2与第一电源线VDD电连接，第一电容电极CE1与第一薄膜晶体管T1的第一栅极G1和第三薄膜晶体管T3的第三漏极D3电连接。
例如，如图8所示，发光元件7140的第二显示电极(例如阴极)与第二电源线VSS电连接。
需要说明的是，第一电源线VDD和第二电源线VSS之一为提供高电压的电源线，另一个为提供低电压的电源线。在如图8所示的实施例中，第一电源线VDD提供恒定的第一电压，第一电压为正电压；而第二电源线VSS提供恒定的第二电压，第二电压可以为负电压等。例如，在一些示例中，第二电压可以为接地电压。
需要说明的是，上述的复位信号和上述的初始化信号可为同一信号。
例如，显示基板70的第一电极层770可以被配置为接收由第二电源线VSS提供的第二电压，从而使与第一电极层770电连接的第二导电图案740以及与第二导电图案740电连接的第一导体化的半导体图案720被施加该第二电压，由此使与第一栅线GLn电连接且传输栅极扫描信号的第一走线731和第一导体化的半导体图案720中的第二走线721之间能够形成电容，以实现补偿的效果。
需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的，本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
在一些实施例中，如图9A所示，像素驱动电路7120包括上述的薄膜晶体管T1、T2、T3、T4、T5、T6和T7、存储电容Cst、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的第一栅线GLn、第二栅线GLn-1、发光控制线EM、初始化线RL、数据线DAT和第一电源线VDD。下面，结合 图8和图9A-9E对像素驱动电路7120的结构进行说明。
例如，图9A为像素驱动电路7120的半导体层、第一导电层、第二导电层和第三导电层的层叠位置关系的示意图。
图9B示出了像素驱动电路7120的半导体层。例如，图9B所示的该半导体层可以为图7中所示的有源层7122。如图9B所示，半导体层可采用半导体材料图案化形成。半导体层可用于制作上述的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，半导体层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
在本公开一些实施例提供的显示基板中，在上述的半导体层上形成有栅极绝缘层(例如图7中所示的栅极绝缘层7128，图9A-9E中未示出)，用于保护上述的半导体层。
图9C示出了像素驱动电路7120的第一导电层。例如，如图9C所示，像素驱动电路7120的第一导电层设置在栅极绝缘层上，从而与图9B所示的半导体层绝缘。第一导电层可包括存储电容Cst的第一电容电极CE1、第一栅线GLn、第二栅线GLn-1、发光控制线EM、以及第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极(例如，上述的第一栅极G1、第二栅极G2、第三栅极G3、第四栅极G4、第五栅极G5、第六栅极G6和第七栅极G7)。如图9C所示，第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极为第一栅线GLn、第二栅线GLn-1与半导体层交叠的部分，第三薄膜晶体管T3可为双栅结构的薄膜晶体管，第三薄膜晶体管T3的一个栅极可为第一栅线GLn与半导体层交叠的部分，第三薄膜晶体管T3的另一个栅极可为从第一栅线GLn突出的突出部；第一薄膜晶体管T1的栅极可为第一电容电极CE1。第四薄膜晶体管T4可为双栅结构的薄膜晶体管，两个栅极分别为第二栅线GLn-1与半导体层交叠的部分。
在本公开一些实施例提供的显示基板中，在上述的第一导电层上形成有 第一层间绝缘层(例如图7中所示的第一层间绝缘层7129，图9A-9E中未示出)，用于保护上述的第一导电层。
图9D示出了像素驱动电路7120的第二导电层。例如，如图9D所示，像素驱动电路7120的第二导电层包括存储电容Cst的第二电容电极CE2和初始化线RL。第二电容电极CE2与第一电容电极CE1至少部分重叠以形成存储电容Cst。
在一些实施例中，第二导电层还可包括第一遮光部791和第二遮光部792。第一遮光部791在衬底基板710上的正投影覆盖第二薄膜晶体管T2的有源层、第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的漏极之间的有源层，从而防止外界光线对第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4的有源层产生影响。第二遮光部792在衬底基板710上的正投影覆盖第三薄膜晶体管T3的两个栅极之间的有源层，从而防止外界光线对第三薄膜晶体管T3的有源层产生影响。第一遮光部791可与相邻像素驱动电路的第二遮光部792为一体结构，并通过贯穿第二层间绝缘层的过孔与第一电源线VDD电连接。
在本公开一些实施例提供的显示基板中，在上述的第二导电层上形成有第二层间绝缘层(例如图7中所示的第二层间绝缘层7131，图9A-9E中未示出)，用于保护上述的第二导电层。
图9E示出了像素驱动电路7120的第三导电层。例如，如图9E所示，像素驱动电路7120的第三导电层包括数据线DAT和第一电源线VDD。结合图9A和图9E所示，数据线DAT通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如过孔VH1)与半导体层中的第二薄膜晶体管T2的源极区域相连。第一电源线VDD通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如过孔VH2)与半导体层中对应第五薄膜晶体管T5的源极区域相连。第一电源线VDD通过第二层间绝缘层中的至少一个过孔(例如过孔VH3)与第二导电层中的第二电容电极CE2相连。
例如，第三导电层还包括第一连接部CP1、第二连接部CP2和第三连接部CP3。第一连接部CP1的一端通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如过孔VH4)与半导体层中对应第三薄膜晶 体管T3的漏极区域相连，第一连接部CP1的另一端通过第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如过孔VH5)与第一导电层中的第一薄膜晶体管T1的栅极相连。第二连接部CP2的一端通过第二层间绝缘层中的一个过孔(例如过孔VH6)与初始化线RL相连，第二连接部CP2的另一端通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如过孔VH7)与半导体层中的第七薄膜晶体管T7的源极区域和第四薄膜晶体管T4的源极区域相连。第三连接部CP3通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如过孔VH8)与半导体层中的第六薄膜晶体管T6的漏极区域相连。
在本公开一些实施例提供的显示基板中，在上述的第三导电层上形成有保护层(例如图7中所示的第一平坦化层7150，图9A-9E中未示出)，用于保护上述的第三导电层。像素结构中的发光元件7140的第一显示电极(例如阳极)可设置在保护层上。
例如，第一导电图案730中的第一走线731可以与第二导电层中的第二电容电极CE2同层设置，第一走线731可通过第一层间绝缘层中的至少一个过孔与第一导电层中的第一栅线GLn相连。
例如，结合图8和图9A中所示的像素驱动电路7120，图7为包括图8和图9A中所示的像素驱动电路7120的显示基板70的部分截面结构的示意图。
在一些实施例中，如图7所示，像素结构还包括位于衬底基板710上的缓冲层7121，像素驱动电路7120可以包括位于缓冲层7121上的有源层7122(例如图9B中所示的像素驱动电路7120的半导体层)、位于有源层7122远离衬底基板710一侧的栅极绝缘层7128、位于栅极绝缘层7128上的栅极7130(例如位于图9C中所示的像素驱动电路7120的第一导电层)、位于栅极7130远离衬底基板710一侧的第一层间绝缘层7129、位于第一层间绝缘层7129上的第二层间绝缘层7131以及位于第二层间绝缘层7131上的源极7125及漏极7126。
例如，第一导体化的半导体图案720(例如第一导体化的半导体图案720中的多条第二走线721)可以与有源层7122同层设置。例如，第一绝缘层761可以与第一层间绝缘层7129同层设置，第二绝缘层762可以与第二层间绝缘 层7131同层设置。例如，源极7125和漏极7126可以与第二导电图案740同层设置。例如，上述同层设置的结构或功能层可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化显示基板70的制备工艺，降低显示基板70的制备成本。
例如，缓冲层7121作为过渡层，其即可以防止衬底基板710中的有害物质侵入显示基板710的内部，又可以增加显示基板710中的膜层在衬底基板710上的附着力。例如，缓冲层7121的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。例如，第一层间绝缘层7129、第二层间绝缘层7131以及栅极绝缘层7128中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第一层间绝缘层7129、第二层间绝缘层7131以及栅极绝缘层7128的材料可以彼此相同，也可以彼此不相同，本公开的实施例对此不作限制。
例如，如图7所示，有源层7122可以包括源极区域7123、漏极区域7124以及位于源极区域7123和漏极区域7124之间的沟道区。第一层间绝缘层7129、第二层间绝缘层7131及栅极绝缘层7128中具有过孔，以暴露源极区7123和漏极区7124。源极7125及漏极7126分别通过过孔与源极区7123和漏极区7124电连接。栅极7130在垂直于衬底基板710的方向上与有源层7122中位于源极区7123和漏极区7124之间的沟道区重叠。
例如，第一平坦化层7150位于源极7125及漏极7126的上方用于平坦化像素驱动电路7120远离衬底基板710一侧的表面。第一平坦化层7150可以平坦化由像素驱动电路7120导致的不平坦表面，并因此防止由像素驱动电路7120引起的凹凸而导致在发光元件7140中出现的缺陷。
例如，第一平坦化层7150可以与第一周边区域703中的第三绝缘层763同层设置。因此，两者可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。
例如，有源层7122的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极7130的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(例如钛、铝及钛三层金属叠层(Al/Ti/Al))。源极7125及漏极7126的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结 构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。本公开的实施例对各结构或功能层的材料不作具体限定。
例如，如图7所示，第一平坦化层7150中形成过孔以暴露源极7125或漏极7126(图7中示出的为暴露漏极7126的情形)，第一平坦化层7150上形成发光元件7140。发光元件7140包括第一显示电极7141(例如阳极)、发光层7142和第二显示电极7143(例如阴极)。发光元件7140的第一显示电极7141通过第一平坦化层7150中的过孔与漏极7126电连接。第一显示电极7141上形成像素限定层7144，像素限定层7144包括多个开口，以限定多个像素单元。多个开口的每个暴露第一显示电极7141，发光层7142设置在像素限定层7144的多个开口中。第二显示电极7143例如可以设置在部分或整个显示区域701中，从而在制备工艺中可以整面形成。
例如，第一显示电极7141可以与第一周边区域703中的第一电极层770同层设置。因此，两者可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。
例如，像素限定层7144可以与第一周边区域703中的第四绝缘层764同层设置。因此，两者可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。
例如，第一显示电极7141可以包括反射层，第二显示电极7143可以包括透明层或半透明层。由此，第一显示电极7141可以反射从发光层7142发射的光，该部分光通过第二显示电极7143发射到外界环境中，从而可以提供光出射率。当第二显示电极7143包括半透射层时，由第一显示电极7141反射的一些光通过第二显示电极7143再次反射，因此第一显示电极7141和第二显示电极7143形成共振结构，从而可以改善光出射效率。
例如，第一显示电极7141的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。此外，第一显示电极7141可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，在显示基板70为有机发光二极管(OLED)显示基板的情形，发光层7142可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等。并且，根据实际不同需要，在不同的示例中，发光层7142还可以进一步包括电子注 入层、电子传输层、空穴注入层、空穴传输层等功能层。
在显示基板70为量子点发光二极管(QLED)显示基板的情形，发光层7142可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二显示电极7143可以包括各种导电材料。例如，第二显示电极7143可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层7144的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不作限制。
例如，如图7所示，显示基板70还包括位于发光元件7140上的封装层7160。封装层7160将发光元件7140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件7140的劣化。封装层7160可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构。例如，封装层7160可以包括依次设置的第一无机封装层7161(即第一封装层781)、第一有机封装层7162、第二无机封装层7163(即第二封装层782)。
例如，该封装层7160的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入。第一有机封装层7162的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等材料可以对显示基板70的显示区域701的表面进行平坦化处理，并且可以缓解第一无机封装层7161和第二无机封装层7163的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
例如，如图7所示，像素驱动电路7120还可以包括第一显示金属层7127(例如图9E中所示的像素驱动电路7120的第三导电层)。第一显示金属层7127包括图7中所示的像素驱动电路7120的薄膜晶体管中的源极7125和漏极7126，还可以包括其他未示出的电路中的电极等。
例如，如图7所示，显示基板70还包括存储电容7170(例如图8和图9A中所示的存储电容Cst)，存储电容7170可以包括第一电容电极7171(例如图8和图9C中所示的存储电容Cst的第一电容电极CE1)和第二电容电 极7172(例如图8和图9D中所示的存储电容Cst的第二电容电极CE2)。第一电容电极7171设置在栅极绝缘层7128与第一层间绝缘层7129之间(例如位于图9C中所示的像素驱动电路7120的第一导电层)，第二电容电极7172设置在第一层间绝缘层7129与第二层间绝缘层7131之间(例如位于图9D中所示的像素驱动电路7120的第二导电层)。第一电容电极7171和第二电容电极7172叠置，在垂直于衬底基板710的方向上至少部分重叠。第一电容电极7171和第二电容电极7172使用第一层间绝缘层7129作为介电材料来形成存储电容7170。
例如，第二电容电极7172可以与第一周边区域703中的第一导电图案730同层设置。因此，两者可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化显示基板70的制备工艺，降低显示基板70的制备成本。
例如，在本公开的其他一些实施例中，存储电容的第一电容电极仍然与栅极同层设置，而存储电容的第二电容电极与薄膜晶体管中的源极和漏极同层设置，由此第一电容电极和第二电容电极可以使用第一层间绝缘层以及第二层间绝缘层的叠层来作为介电材料以形成存储电容。
例如，在本公开的其他一些实施例中，存储电容的第一电容电极不再与栅极同层设置，而是位于第一层间绝缘层与第二层间绝缘层之间，而存储电容的第二电容电极与薄膜晶体管中的源极和漏极同层设置，由此第一电容电极和第二电容电极使用第二层间绝缘层来作为介电材料以形成存储电容。
需要说明的是，图2C所示的显示基板20、图4所示的显示基板40的显示区域中的截面结构也可以采用与图7所示的显示基板70的显示区域701相同或相似的结构，或者也可以采用其他合适的结构，本公开的实施例对此不作限制。
例如，本公开实施例提供的显示基板，例如显示基板20、显示基板30、显示基板40、显示基板50、显示基板70可以为有机发光二极管显示基板。
例如，本公开实施例提供的显示基板还可以为量子点发光二极管显示基板、电子纸显示基板等具有显示功能的基板或其他类型的基板，本公开的实施例对此不作限制。
本公开至少一个实施例还提供一种显示基板的制备方法，该制备方法包 括：提供衬底基板；在衬底基板上形成第一导体化的半导体图案；在第一导体化的半导体图案上形成第一导电图案，其中，第一导电图案与第一导体化的半导体图案间隔绝缘设置以能够形成电容；以及在第一导电图案上形成第二导电图案，其中，第二导电图案与第一导电图案间隔绝缘设置以能够形成电容。显示基板包括显示区域和围绕显示区域的周边区域，显示区域包括开口，周边区域包括至少部分围绕开口的第一周边区域。第一周边区域包括第一围堰区、第二围堰区和间隔区，第一围堰区至少部分围绕开口，间隔区至少部分围绕第一围堰区，第二围堰区至少部分围绕间隔区。第一导电图案被配置为传输用于显示区域的电信号。第二导电图案通过设置在第一周边区域中的多个过孔与第一导体化的半导体图案电连接。第一导体化的半导体图案、第一导电图案和第二导电图案至少位于第一围堰区和间隔区，多个过孔在间隔区的排布密度小于在第一围堰区的排布密度。
例如，在本公开至少一个实施例提供的显示基板的制备方法中，在第一导体化的半导体图案上形成第一导电图案，包括：在第一导体化的半导体图案上形成第一绝缘层，以及在第一绝缘层上形成第一导电图案。在第一导电图案上形成第二导电图案，包括：在第一导电图案上形成第二绝缘层，以及在第二绝缘层上形成第二导电图案。多个过孔至少位于第一绝缘层和第二绝缘层内且至少贯穿第一绝缘层和第二绝缘层。
例如，本公开至少一个实施例提供的显示基板的制备方法还包括：在第二导电图案上形成第一电极层。第一电极层与第二导电图案电连接。在间隔区内，第一电极层覆盖第二导电图案，且第一电极层面向衬底基板的一侧的表面与第二导电图案背离衬底基板的一侧的表面接触。
例如，本公开至少一个实施例提供的显示基板的制备方法还包括：在第一电极层上形成第一封装层。在间隔区内，第一封装层覆盖第一电极层，且第一封装层面向衬底基板的一侧的表面与第一电极层背离衬底基板的一侧的表面接触。
例如，本公开至少一个实施例提供的显示基板的制备方法还包括：在显示区域，在衬底基板上形成像素结构的像素驱动电路。像素驱动电路包括薄膜晶体管和存储电容，薄膜晶体管包括栅极、有源层、源极和漏极，存储电容包括第一电容电极和与第一电容电极相对的第二电容电极。有源层与第一 导体化的半导体图案同层设置，第二电容电极与第一导电图案同层设置，源极和漏极与第二导电图案同层设置。
例如，在本公开至少一个实施例提供的显示基板的制备方法中，第一电容电极与栅极同层设置。
例如，本公开实施例提供的显示基板，例如上述显示基板20、显示基板30、显示基板40、显示基板50或显示基板70，可以通过本公开实施例提供的显示基板的制备方法进行制备。
本公开实施例提供的显示基板的制备方法的技术效果可以参考上述本公开实施例提供的显示基板中的技术效果，在此不再赘述。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的显示基板，例如可以包括上述显示基板20、显示基板30、显示基板40、显示基板50或显示基板70。
本公开实施例提供的显示装置的结构、功能及技术效果等可以参考上述本公开实施例提供的显示基板中的相应描述，在此不再赘述。
例如，本公开实施例提供的显示装置可以为有机发光二极管显示装置。或者，本公开实施例提供的显示装置还可以为量子点发光二极管显示装置、电子纸显示装置等具有显示功能的装置或其他类型的装置，本公开的实施例对此不作限制。
例如，本公开实施例提供的显示装置可以为显示基板、显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，则该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (27)

  1. 一种显示基板，包括显示区域和围绕所述显示区域的周边区域；
    其中，所述显示区域包括开口，所述周边区域包括至少部分围绕所述开口的第一周边区域；
    所述第一周边区域包括第一围堰区、第二围堰区和间隔区，所述第一围堰区至少部分围绕所述开口，所述间隔区至少部分围绕所述第一围堰区，所述第二围堰区至少部分围绕所述间隔区；
    所述显示基板包括衬底基板、第一导体化的半导体图案、第一导电图案和第二导电图案；
    所述第一导体化的半导体图案位于所述衬底基板上，
    所述第一导电图案位于所述第一导体化的半导体图案远离所述衬底基板的一侧，与所述第一导体化的半导体图案间隔绝缘设置以能够形成电容，
    所述第二导电图案位于所述第一导电图案远离所述第一导体化的半导体图案的一侧，与所述第一导电图案间隔绝缘设置以能够形成电容；
    所述第一导电图案被配置为传输用于所述显示区域的电信号；
    所述第二导电图案通过设置在所述第一周边区域中的多个过孔与所述第一导体化的半导体图案电连接；
    所述第一导体化的半导体图案、所述第一导电图案和所述第二导电图案至少位于所述第一围堰区和所述间隔区，所述多个过孔在所述间隔区的排布密度小于在所述第一围堰区的排布密度。
  2. 根据权利要求1所述的显示基板，还包括第一绝缘层和第二绝缘层；
    其中，所述第一绝缘层位于所述第一导体化的半导体图案远离所述衬底基板的一侧，所述第一导电图案位于所述第一绝缘层远离所述第一导体化的半导体图案的一侧，所述第二绝缘层位于所述第一导电图案远离所述第一绝缘层的一侧，所述第二导电图案位于所述第二绝缘层远离所述第一导电图案的一侧；
    所述多个过孔至少位于所述第一绝缘层和所述第二绝缘层内且至少贯穿所述第一绝缘层和所述第二绝缘层。
  3. 根据权利要求1或2所述的显示基板，其中，所述多个过孔在所述间 隔区的排布密度为0。
  4. 根据权利要求1-3中任一项所述的显示基板，其中，所述第一导体化的半导体图案和所述第二导电图案还位于所述第二围堰区中。
  5. 根据权利要求4所述的显示基板，其中，所述第一导电图案还位于所述第二围堰区中。
  6. 根据权利要求4或5所述的显示基板，其中，所述多个过孔在所述间隔区的排布密度小于在所述第二围堰区的排布密度。
  7. 根据权利要求2所述的显示基板，其中，在所述间隔区内，所述第二导电图案在所述衬底基板上的正投影与所述第二绝缘层在所述衬底基板上的正投影重叠，且所述第二导电图案在所述衬底基板上的正投影的面积等于所述第二绝缘层在所述衬底基板上的正投影的面积。
  8. 根据权利要求1-7中任一项所述的显示基板，还包括第一电极层；
    其中，所述第一电极层位于所述第二导电图案远离所述衬底基板的一侧且与所述第二导电图案电连接；
    在所述间隔区内，所述第一电极层覆盖所述第二导电图案，且所述第一电极层面向所述衬底基板的一侧的表面与所述第二导电图案背离所述衬底基板的一侧的表面接触。
  9. 根据权利要求8所述的显示基板，还包括第一封装层；
    其中，所述第一封装层位于所述第一电极层远离所述衬底基板的一侧；
    在所述间隔区内，所述第一封装层覆盖所述第一电极层，且所述第一封装层面向所述衬底基板的一侧的表面与所述第一电极层背离所述衬底基板的一侧的表面接触。
  10. 根据权利要求9所述的显示基板，还包括第一围堰结构和第二围堰结构，
    其中，所述第一围堰结构位于所述第一围堰区内，所述第二围堰结构位于所述第二围堰区内；
    在所述第一围堰区，所述第一围堰结构位于所述第一电极层远离所述衬底基板的一侧，所述第一封装层位于所述第一围堰结构远离所述第一电极层的一侧且覆盖所述第一围堰结构；
    在所述第二围堰区，所述第二围堰结构位于所述第二导电图案远离所述 衬底基板的一侧且部分所述第二围堰结构覆盖所述第一电极层，所述第一封装层位于所述第一电极层和所述第二围堰结构远离所述第二导电图案的一侧且覆盖所述第一电极层和所述第二围堰结构。
  11. 根据权利要求10所述的显示基板，其中，所述第一封装层位于所述第一围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离大于所述第一封装层位于所述间隔区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离，
    所述第一封装层位于所述第二围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离大于所述第一封装层位于所述间隔区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离。
  12. 根据权利要求11所述的显示基板，其中，所述第一封装层位于所述第一围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离小于所述第一封装层位于所述第二围堰区的部分的背离所述衬底基板的一侧的表面与所述衬底基板之间的最大距离。
  13. 根据权利要求10-12中任一项所述的显示基板，还包括位于所述第一周边区域除所述间隔区之外的第三绝缘层、第四绝缘层和第五绝缘层；
    其中，所述第一围堰结构包括所述第四绝缘层和所述第五绝缘层的叠层，所述第二围堰结构包括所述第三绝缘层、所述第四绝缘层和所述第五绝缘层的叠层；
    在所述第一围堰区中，所述第四绝缘层位于所述第一电极层远离所述衬底基板的一侧，所述第五绝缘层位于所述第四绝缘层远离所述第一电极层的一侧，
    所述第一封装层位于所述第五绝缘层远离所述第四绝缘层的一侧，且覆盖所述第五绝缘层背离所述衬底基板的一侧的表面、所述第五绝缘层的至少一侧的侧表面和所述第四绝缘层的至少一侧的侧表面；
    在所述第二围堰区中，所述第三绝缘层位于所述第二导电图案远离所述衬底基板的一侧，所述第一电极层覆盖所述第三绝缘层背离所述衬底基板的一侧的部分表面和所述第三绝缘层靠近所述第一围堰区的一侧的侧表面，所述第四绝缘层位于所述第三绝缘层和所述第一电极层远离所述第二导电图案的一侧，所述第五绝缘层位于所述第四绝缘层远离所述第三绝缘层和所述第 一电极层的一侧，
    所述第一封装层位于所述第五绝缘层远离所述第四绝缘层的一侧，且覆盖所述第五绝缘层背离所述衬底基板的一侧的表面、所述第五绝缘层的至少一侧的侧表面、所述第四绝缘层的至少一侧的侧表面、所述第三绝缘层背离所述衬底基板的一侧的部分表面和所述第三绝缘层远离所述第一围堰区的一侧的侧表面。
  14. 根据权利要求13所述的显示基板，其中，在所述第二围堰区内，所述第三绝缘层覆盖所述第二导电图案背离所述衬底基板的一侧的部分表面和所述第二导电图案远离所述第一围堰区的一侧的侧表面。
  15. 根据权利要求9-14中任一项所述的显示基板，还包括第二封装层；
    其中，所述第二封装层位于所述第一封装层远离所述第一电极层的一侧且覆盖所述第一封装层。
  16. 根据权利要求1-15中任一项所述的显示基板，其中，所述第一导电图案包括沿第一方向并列排布的多条第一走线，
    所述第一导体化的半导体图案包括沿第二方向并列排布的多条第二走线，所述第一方向不同于所述第二方向。
  17. 根据权利要求1-16中任一项所述的显示基板，还包括位于所述显示区域的像素结构，
    其中，所述像素结构包括位于所述衬底基板上的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容；
    所述薄膜晶体管包括栅极、有源层、源极和漏极，所述存储电容包括第一电容电极和与所述第一电容电极相对的第二电容电极，
    所述有源层与所述第一导体化的半导体图案同层设置，所述第二电容电极与所述第一导电图案同层设置，所述源极和所述漏极与所述第二导电图案同层设置。
  18. 根据权利要求17所述的显示基板，其中，所述第一电容电极与所述栅极同层设置。
  19. 根据权利要求17或18所述的显示基板，其中，所述像素结构还包括第一平坦化层以及发光元件，
    所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供 第一平坦化表面且包括第一过孔，
    所述发光元件在所述第一平坦化表面上，且通过所述第一过孔与所述像素驱动电路电连接，
    其中，在所述显示基板包括所述第三绝缘层的情形，所述第三绝缘层与所述第一平坦化层同层设置。
  20. 一种显示基板，包括显示区域和围绕所述显示区域的周边区域；
    其中，所述显示区域包括开口，所述周边区域包括至少部分围绕所述开口的第一周边区域；
    所述第一周边区域包括第一围堰区、第二围堰区和间隔区，所述第一围堰区至少部分围绕所述开口，所述间隔区至少部分围绕所述第一围堰区，所述第二围堰区至少部分围绕所述间隔区；
    所述显示基板包括衬底基板、第一导体化的半导体图案、第一导电图案和第二导电图案；
    所述第一导体化的半导体图案位于所述衬底基板上，
    所述第一导电图案位于所述第一导体化的半导体图案远离所述衬底基板的一侧，与所述第一导体化的半导体图案间隔绝缘设置以能够形成电容，
    所述第二导电图案位于所述第一导电图案远离所述第一导体化的半导体图案的一侧，与所述第一导电图案间隔绝缘设置以能够形成电容；
    所述第一导电图案被配置为传输用于所述显示区域的电信号；
    所述第二导电图案通过设置在所述第一周边区域中的多个过孔与所述第一导体化的半导体图案电连接；
    所述第一导体化的半导体图案、所述第一导电图案和所述第二导电图案至少位于所述第二围堰区和所述间隔区，所述多个过孔在所述间隔区的排布密度小于在所述第二围堰区的排布密度。
  21. 一种显示装置，包括如权利要求1-20中任一项所述的显示基板。
  22. 一种显示基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上形成第一导体化的半导体图案；
    在所述第一导体化的半导体图案上形成第一导电图案，其中，所述第一导电图案与所述第一导体化的半导体图案间隔绝缘设置以能够形成电容；以 及
    在所述第一导电图案上形成第二导电图案，其中，所述第二导电图案与所述第一导电图案间隔绝缘设置以能够形成电容；
    其中，所述显示基板包括显示区域和围绕所述显示区域的周边区域，所述显示区域包括开口，所述周边区域包括至少部分围绕所述开口的第一周边区域；
    所述第一周边区域包括第一围堰区、第二围堰区和间隔区，所述第一围堰区至少部分围绕所述开口，所述间隔区至少部分围绕所述第一围堰区，所述第二围堰区至少部分围绕所述间隔区；
    所述第一导电图案被配置为传输用于所述显示区域的电信号；
    所述第二导电图案通过设置在所述第一周边区域中的多个过孔与所述第一导体化的半导体图案电连接；
    所述第一导体化的半导体图案、所述第一导电图案和所述第二导电图案至少位于所述第一围堰区和所述间隔区，所述多个过孔在所述间隔区的排布密度小于在所述第一围堰区的排布密度。
  23. 根据权利要求22所述的显示基板的制备方法，其中，在所述第一导体化的半导体图案上形成所述第一导电图案，包括：
    在所述第一导体化的半导体图案上形成第一绝缘层，以及
    在所述第一绝缘层上形成所述第一导电图案；
    在所述第一导电图案上形成所述第二导电图案，包括：
    在所述第一导电图案上形成第二绝缘层，以及
    在所述第二绝缘层上形成所述第二导电图案；
    其中，所述多个过孔至少位于所述第一绝缘层和所述第二绝缘层内且至少贯穿所述第一绝缘层和所述第二绝缘层。
  24. 根据权利要求22或23所述的显示基板的制备方法，还包括：
    在所述第二导电图案上形成第一电极层；
    其中，所述第一电极层与所述第二导电图案电连接；
    在所述间隔区内，所述第一电极层覆盖所述第二导电图案，且所述第一电极层面向所述衬底基板的一侧的表面与所述第二导电图案背离所述衬底基板的一侧的表面接触。
  25. 根据权利要求24所述的显示基板的制备方法，还包括：
    在所述第一电极层上形成第一封装层；
    其中，在所述间隔区内，所述第一封装层覆盖所述第一电极层，且所述第一封装层面向所述衬底基板的一侧的表面与所述第一电极层背离所述衬底基板的一侧的表面接触。
  26. 根据权利要求22-25中任一项所述的显示基板的制备方法，还包括：
    在所述显示区域，在所述衬底基板上形成像素结构的像素驱动电路；
    其中，所述像素驱动电路包括薄膜晶体管和存储电容，
    所述薄膜晶体管包括栅极、有源层、源极和漏极，所述存储电容包括第一电容电极和与所述第一电容电极相对的第二电容电极；
    所述有源层与所述第一导体化的半导体图案同层设置，所述第二电容电极与所述第一导电图案同层设置，所述源极和所述漏极与所述第二导电图案同层设置。
  27. 根据权利要求26所述的显示基板的制备方法，其中，所述第一电容电极与所述栅极同层设置。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023093252A1 (zh) * 2021-11-25 2023-06-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115136316A (zh) * 2020-02-18 2022-09-30 谷歌有限责任公司 减小显示器中的孔边框区域
EP4152401A4 (en) * 2020-05-13 2023-08-02 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND METHOD FOR PRODUCTION THEREOF, AND DISPLAY DEVICE
CN113707673B (zh) * 2021-08-27 2023-12-26 成都京东方光电科技有限公司 一种显示基板及其制备方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107221536A (zh) * 2017-05-25 2017-09-29 上海天马微电子有限公司 阵列基板、异形显示器及显示装置
CN107275363A (zh) * 2016-04-05 2017-10-20 三星显示有限公司 显示装置
CN108155216A (zh) * 2016-12-06 2018-06-12 三星显示有限公司 显示设备
CN109728194A (zh) * 2018-12-28 2019-05-07 上海天马微电子有限公司 显示面板和显示装置
CN110211998A (zh) * 2019-05-31 2019-09-06 武汉天马微电子有限公司 一种有机发光显示面板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7830591B2 (en) 2006-11-20 2010-11-09 Seiko Epson Corporation Active-matrix circuit board and display
KR102364863B1 (ko) 2015-03-10 2022-02-18 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
KR102490891B1 (ko) 2015-12-04 2023-01-25 삼성디스플레이 주식회사 표시 장치
JP6815159B2 (ja) 2016-10-14 2021-01-20 株式会社ジャパンディスプレイ 表示装置
KR102333549B1 (ko) * 2017-07-05 2021-11-30 엘지디스플레이 주식회사 표시장치
CN111937489B (zh) 2018-03-30 2023-07-04 夏普株式会社 显示装置
EP4152401A4 (en) * 2020-05-13 2023-08-02 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND METHOD FOR PRODUCTION THEREOF, AND DISPLAY DEVICE

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275363A (zh) * 2016-04-05 2017-10-20 三星显示有限公司 显示装置
CN108155216A (zh) * 2016-12-06 2018-06-12 三星显示有限公司 显示设备
CN107221536A (zh) * 2017-05-25 2017-09-29 上海天马微电子有限公司 阵列基板、异形显示器及显示装置
CN109728194A (zh) * 2018-12-28 2019-05-07 上海天马微电子有限公司 显示面板和显示装置
CN110211998A (zh) * 2019-05-31 2019-09-06 武汉天马微电子有限公司 一种有机发光显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023093252A1 (zh) * 2021-11-25 2023-06-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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