WO2020124915A1 - 一种具有电容的阵列基板及其制备方法 - Google Patents

一种具有电容的阵列基板及其制备方法 Download PDF

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Publication number
WO2020124915A1
WO2020124915A1 PCT/CN2019/084039 CN2019084039W WO2020124915A1 WO 2020124915 A1 WO2020124915 A1 WO 2020124915A1 CN 2019084039 W CN2019084039 W CN 2019084039W WO 2020124915 A1 WO2020124915 A1 WO 2020124915A1
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Prior art keywords
layer
capacitor
insulating layer
dielectric insulating
source
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PCT/CN2019/084039
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English (en)
French (fr)
Inventor
胡俊艳
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/482,254 priority Critical patent/US20200203393A1/en
Publication of WO2020124915A1 publication Critical patent/WO2020124915A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate with a capacitor and a preparation method thereof.
  • the existing flat display devices mainly include a liquid crystal display device (Liquid Crystal Display, LCD for short) and an organic light emitting diode display device (Organic Light Emitting Display, OLED for short). Due to the advantages of light weight, self-illumination, wide viewing angle, low driving voltage, high luminous efficiency, low power consumption, and fast response speed, the application range of OLED is becoming wider and wider.
  • OLED can be divided into passive OLED (PM-OLED) and active OLED (AM-OLED) according to driving type.
  • PM-OLED passive OLED
  • AM-OLED active OLED
  • Existing AM-OLED devices generally have a storage capacitor sandwiched between two transistors.
  • the storage capacitor is the main means of maintaining the potential of the pixel electrode.
  • the storage capacitor is usually composed of the gate of the driver TFT, the second metal layer, and the insulating layer therebetween.
  • the array substrate includes a substrate 111, a barrier layer (M/B) 112, a buffer layer (Buffer) 113, a first gate insulating layer (GI1) 114, a second gate insulating layer (GI2) 115, and a dielectric insulating layer (ILD ) 116, a flat layer (PLN) 117, an anode (ANO) 118, a pixel definition layer (PDL) 119, a photoresist layer (Photo Spacer, PS for short) 120, a thin film transistor, and a capacitor.
  • M/B barrier layer
  • Buffer buffer layer
  • GI1 first gate insulating layer
  • GI2 second gate insulating layer
  • ILD dielectric insulating layer
  • the thin film transistor includes an active layer (Act) 121 formed on the buffer layer 113, a first gate layer (GE1) 122 formed on the first gate insulating layer 114, and a dielectric insulating layer (ILD) The source/drain electrode (S/D) 123 on 116.
  • the capacitance is formed by the overlapping area of the first gate layer (GE1) 122 formed on the first gate insulating layer 114 and the second gate layer (GE2) 124 formed on the second gate insulating layer 115.
  • This capacitor setting method can save space and facilitate the development of high-resolution display technology. However, it requires two deposition processes of the gate insulating layer (GI1, GI2), and two deposition and patterning processes of the gate layer (GE1, GE2). The production process is complicated and increases the production cost.
  • the purpose of the present application is to provide an array substrate with a capacitor and a preparation method for the problems in the prior art, which can simplify the production process, save production costs, save space, and facilitate the development of high-resolution display technology.
  • the present application provides a method for manufacturing an array substrate with a capacitor.
  • the method includes the following steps: (1) providing a substrate on which a barrier layer, a buffer layer, and an active layer are sequentially formed Layer; (2) depositing a gate insulating layer and a first metal layer in sequence on the active layer, and patterning the first metal layer to form gate electrodes and scan line traces, wherein the scan lines The trace serves as the lower plate of the capacitor; (3) deposit a dielectric insulating layer on the first metal layer, and partially etch the dielectric insulating layer using a halftone mask process to form a source/ A drain electrode contact hole and a trench, wherein the source/drain electrode contact hole is formed at a position corresponding to both ends of the active layer, and the trench is formed at a position corresponding to the lower plate of the capacitor Position; (4) deposit a second metal layer on the dielectric insulating layer, and pattern the second metal layer to form source/drain electrodes and power line traces, wherein the source/d
  • the present application also provides a method for preparing an array substrate having a capacitor, the preparation method includes the following steps: (1) providing a substrate on which a barrier layer, a buffer layer and an Source layer; (2) depositing a gate insulating layer and a first metal layer in sequence on the active layer, and patterning the first metal layer to form a gate electrode and a scan line trace, wherein, the scan The wire trace serves as the lower plate of the capacitor; (3) A dielectric insulating layer is deposited on the first metal layer, and the dielectric insulating layer is patterned to form source/drain electrode contact holes, wherein , The source/drain electrode contact holes are formed at positions corresponding to both ends of the active layer; (4) depositing a second metal layer on the dielectric insulating layer, and performing the second metal layer Patterning to form source/drain electrodes and power line traces, wherein the source/drain electrodes are electrically connected to the active layer through the source/drain electrode contact holes, and the power line traces are used
  • the present application also provides an array substrate with a capacitor
  • the array substrate includes: a substrate; a barrier layer, a buffer layer, and an active layer sequentially provided on the substrate; A gate insulating layer on the layer, the gate insulating layer covering the active layer; the gate electrode provided on the gate insulating layer and the lower plate of the capacitor; the gate electrode provided on the gate electrode and the capacitor A dielectric insulating layer on the lower electrode plate, the dielectric insulating layer covering the gate electrode and the lower electrode plate of the capacitor; the source/drain electrodes provided on the dielectric insulating layer and the capacitor A polar plate, wherein the source/drain electrode is electrically connected to the active layer through a source/drain electrode contact hole, and the lower plate of the capacitor and the upper plate of the capacitor are insulated by the dielectric Layer insulation; a flat layer, an anode, a pixel definition layer and a photoresist layer provided on the source/drain electrode and the upper plate of the capacitor in this order.
  • This application uses the overlapping area of the scan line trace and the power line trace to form a capacitor.
  • the size of the capacitor can be adjusted by the area of the overlap area and the thickness of the dielectric insulating layer between the two layers of metal.
  • the dielectric insulating layer can be partially etched through a half-tone mask process to achieve the purpose of reducing the thickness of the dielectric insulating layer in the capacitor region and increasing the capacitance, while ensuring that the thickness of the dielectric insulating layer in other regions is not affected.
  • the application of the array substrate preparation method with capacitance can simplify the production process, improve production efficiency and product yield, save production costs, at the same time can effectively save space, improve product competitiveness, and benefit high Development of resolution display technology.
  • FIG. 1 is a schematic diagram of a layered structure of an array substrate with capacitors in the prior art
  • FIG. 2 is a schematic flow chart of a method for preparing an array substrate with a capacitor of this application
  • 3A-3F a schematic diagram of the production process of the method for preparing an array substrate with a capacitor of this application;
  • FIG. 4 is a schematic diagram of a layered structure of an array substrate with capacitors in this application.
  • the first feature “above” or “below” the second feature may include the direct contact of the first and second features, or may include the first and second features Not direct contact but contact through another feature between them.
  • the first feature is “above”, “above” and “above” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below”, and “below” the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is less horizontal than the second feature.
  • the method for preparing an array substrate with a capacitor of the present application uses an overlapping area of a scan line (scan) trace and a power line (VDD) trace to form a capacitor (that is, the trace acts as a capacitor), and the size of the capacitor can be determined by the area of the overlap area and The thickness of the dielectric insulation layer between the two metals is adjusted.
  • the dielectric insulating layer can be partially etched through a halftone masking process to achieve the purpose of reducing the thickness of the dielectric insulating layer in the capacitor area and increasing the capacitance, while ensuring that the thickness of the dielectric insulating layer in other areas is not affected .
  • the application of the capacitor array preparation method can simplify the production process, improve production efficiency and product yield, save production costs, at the same time can save space, improve product competitiveness, and facilitate high resolution Rate display technology development.
  • FIG. 2 is a schematic flow chart of a method for manufacturing an array substrate with a capacitor of the present application
  • FIGS. 3A-3F are a schematic flow chart of a manufacturing method of an array substrate with a capacitor of the present application
  • 4 is a schematic diagram of the layered structure of the array substrate with capacitance of the present application.
  • the preparation method includes the following steps: S21: providing a substrate on which a barrier layer, a buffer layer and an active layer are sequentially formed; S22: depositing a gate insulating layer and a first metal layer on the active layer in sequence And patterning the first metal layer to form gate electrodes and scan line traces, wherein the scan line traces serve as the lower plate of the capacitor; S23: deposit on the first metal layer A dielectric insulating layer, and patterning the dielectric insulating layer to form source/drain electrode contact holes, wherein the source/drain electrode contact holes are formed at positions corresponding to both ends of the active layer; S24: Deposit a second metal layer on the dielectric insulating layer, and pattern the second metal layer to form source/drain electrodes and power line traces, wherein the source/drain electrodes pass through the The source/drain electrode contact hole is electrically connected to the active layer, the power line trace serves as the upper plate of the capacitor, and the lower plate of the capacitor and the upper plate of the capacitor pass through the The dielectric
  • step S21 providing a substrate on which a barrier layer, a buffer layer and an active layer are sequentially formed, please refer to FIG. 2 and FIG. 3A together, where FIG. 3A is an embodiment of the present application in which a barrier is sequentially formed on the substrate Schematic diagram of layers, buffer layers and active layers.
  • the substrate 211 may be a glass substrate or a flexible substrate made of a flexible base material (PI).
  • PI flexible base material
  • a substrate 211 is provided, and a barrier layer (M/B) 212 is deposited on the substrate 211; a buffer layer (Buffer) 213 is formed on the barrier layer 212; and the thin film transistor 220 of the array substrate is formed on the buffer layer 213 Source layer (Act) 221.
  • M/B barrier layer
  • Buffer buffer layer
  • Act Source layer
  • the active layer 221 is crystallized and patterned so that the active layer 221 includes a polysilicon region 2211 and source/drain electrodes formed at both ends of the polysilicon region 2211 Contact area 2212.
  • step S22 depositing a gate insulating layer and a first metal layer in sequence on the active layer, and patterning the first metal layer to form a gate electrode and a scan line trace, wherein the scan line trace The line serves as the lower plate of the capacitor.
  • FIG. 3B is a schematic diagram of forming gate electrodes and scan line traces according to an embodiment of the present application.
  • a gate electrode (GE1) 222 and a scan line trace 231 are formed respectively; the gate electrode 222 is located in the active layer Above the polysilicon region 2211 of 221, the scan line trace 231 serves as the lower plate 231 of the capacitor 230 of the array substrate. That is, the gate electrode 222 and the lower electrode plate 231 of the capacitor 230 are fabricated at the same time and are located on the same layer (both are formed on the gate insulating layer 214).
  • the material of the first metal layer may be titanium, aluminum, molybdenum or copper, and the metal thickness is 1000A-5000A. That is, the material of the lower plate 231 of the capacitor 230 may be titanium, aluminum, molybdenum, or copper, and the metal thickness is 1000A-5000A.
  • step S23 depositing a dielectric insulating layer on the first metal layer, and patterning the dielectric insulating layer to form source/drain electrode contact holes, wherein the source/drain electrode contact holes are formed in
  • FIG. 3C is a schematic diagram of depositing and patterning a dielectric insulating layer according to an embodiment of the present application.
  • the dielectric insulating layer (ILD) 215 is partially etched using a halftone mask process to form source/drain on the dielectric insulating layer 215
  • the pole contact hole 2151 and a trench 2152 are examples of depositing a dielectric insulating layer on the first metal layer, and patterning the dielectric insulating layer to form source/drain electrode contact holes, wherein the source/drain electrode contact holes are formed in
  • FIG. 3C is a schematic diagram of depositing and patterning a dielectric insulating layer according to an embodiment of the present application.
  • the dielectric insulating layer (ILD) 215 is partially etched using a halftone mask process
  • the bottom of the source/drain electrode contact hole 2151 is located in the source/drain contact region 2212 of the active layer 221; the trench 2152 is formed under the scan line trace 231 (ie, the capacitor 230 The corresponding position of the electrode plate 231). That is, the dielectric insulating layer of the capacitor 230 is composed of the remaining dielectric insulating layer at the trench 2152.
  • the trench 2152 is a preferred arrangement for reducing the thickness of the dielectric insulating layer in the capacitor region and increasing the capacitance. In other embodiments, only the source/drain electrodes may be formed on the dielectric insulating layer 215 Contact hole 2151.
  • the material of the dielectric insulating layer 215 is silicon nitride (SiNx), silicon dioxide (SiO2), or a combination of silicon nitride and silicon dioxide.
  • SiNx silicon nitride
  • SiO2 silicon dioxide
  • the depth of the trench 2152 can be adjusted to adjust the thickness of the remaining dielectric insulating layer at the trench 2152, thereby increasing or decreasing the capacitance.
  • the thickness of the remaining dielectric insulating layer at the trench 2152 is 500A-6000A, that is, the thickness of the dielectric insulating layer between the upper and lower plates of the capacitor 230 is 500A-6000A.
  • step S24 depositing a second metal layer on the dielectric insulating layer and patterning the second metal layer to form source/drain electrodes and power line traces, wherein the source/drain electrodes pass through
  • the source/drain electrode contact hole is electrically connected to the active layer
  • the power line trace serves as an upper plate of the capacitor
  • the lower plate of the capacitor passes through the upper plate of the capacitor
  • FIG. 3D is a schematic diagram of forming source/drain electrodes and power line traces according to an embodiment of the present application.
  • a source/drain electrode (S/D) 224 and a power line trace 232 are formed respectively.
  • the source/drain electrode 223 is electrically connected to the active layer 221 through the source/drain electrode contact hole 2151 (specifically, the source/drain electrode 223 is connected to the active layer through the source/drain electrode contact hole 2151
  • the source/drain contact region 2212 of the active layer 221 is electrically connected;
  • the power line trace 232 serves as the upper plate 232 of the capacitor 230 of the array substrate, the lower plate 231 of the capacitor 230 and the The upper plate 232 of the capacitor 230 is insulated by the dielectric insulating layer 215.
  • the source/drain electrode 223 and the upper plate 232 of the capacitor 230 are fabricated at the same time and are both formed on the dielectric insulating layer 215.
  • the upper plate 232 of the capacitor 230 is formed in the trench 2152 on the dielectric insulating layer 215.
  • the source/drain electrode 223 and the upper plate 232 of the capacitor 230 may also be fabricated simultaneously and located on the same layer (both are formed on the dielectric insulating layer 215).
  • the material of the second metal layer may be titanium, aluminum, molybdenum or copper, and the metal thickness is 1000A-5000A. That is, the material of the upper plate 232 of the capacitor 230 may be titanium, aluminum, molybdenum, or copper, and the metal thickness is 1000A-5000A.
  • the lower plate 231 of the capacitor 230 is composed of scan traces 231 formed by the first metal layer.
  • the metal may be titanium, aluminum, molybdenum, copper and other metals, and the metal thickness is 1000A-5000A;
  • the upper plate 232 of 230 is composed of a power line (VDD) trace 232 formed by a second metal layer.
  • the metal may be titanium, aluminum, molybdenum, copper and other metals, and the metal thickness is 1000A-5000A;
  • the electrically insulating layer is composed of the remaining dielectric insulating layer 215 at the trench 2152.
  • the dielectric insulating layer 215 may be silicon nitride, silicon dioxide, or a combination of silicon nitride and silicon dioxide, and its thickness is 500A-6000A, and It can be adjusted by the halftone process; the size of the capacitor 230 can be adjusted by the area of the overlapping area of the scan trace (scan) trace and the power trace (VDD) trace and the depth of the trench 2152.
  • step S25 forming a flat layer, an anode, a pixel definition layer and a photoresist layer on the second metal layer in sequence
  • FIGS. 2, 3E-3F and FIG. 4 together, where FIG. 3E is an implementation of this application
  • FIG. 3E is an implementation of this application
  • FIG. 3F is a schematic diagram of forming an anode according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a layered structure of an array substrate according to an embodiment of the present application.
  • an organic film layer is coated on the source/drain electrode 223 and the power line trace 232 on the dielectric insulating layer 17 and patterned to form a flat layer (PLN) 216, as shown in FIG. 3E.
  • an anode metal PE
  • ANO anode
  • PE anode metal
  • the anode 217 is located above the source/drain electrode 223 and is electrically connected to the source/drain electrode 223.
  • an organic photoresist is coated and patterned over the anode 217 to form the pixel definition layer (PDL) 218 and the photoresist layer (Photo Spacer, PS for short) 219.
  • PDL pixel definition layer
  • Photoresist layer Photo Spacer, PS for short
  • the array substrate prepared by the preparation method described in this application uses the overlapping area of the scan line (scan) trace and the power line (VDD) trace to form a capacitor.
  • the size of the capacitor can be determined by the area of the overlapping area and the gap between the two layers of metal
  • the thickness of the dielectric insulating layer is adjusted.
  • the dielectric insulating layer can be partially etched through a halftone masking process to achieve the purpose of reducing the thickness of the dielectric insulating layer in the capacitor area and increasing the capacitance, while ensuring that the thickness of the dielectric insulating layer in other areas is not affected .
  • the array substrate preparation method with capacitance of the present application can simplify the production process, improve production efficiency and product yield, save production costs, and at the same time continue the advantages of maximizing space utilization, which can effectively save space, To enhance the competitiveness of products and facilitate the development of high-resolution display technology.
  • the present invention is a schematic diagram of a layered structure of an array substrate with a capacitor.
  • the array substrate of the present application includes: a substrate 211, a barrier layer 212, a buffer layer 213, and an active layer 221 provided on the substrate 211 in sequence, and a gate insulating layer 214 provided on the active layer 221, provided on the The gate electrode 222 on the gate insulating layer 214 and the lower plate 231 of the capacitor 230 are provided on the gate electrode 222 and the dielectric insulating layer 215 on the lower plate 231 of the capacitor 230 are provided on the dielectric
  • the source/drain electrode 223 on the electrically insulating layer 215 and the upper plate 232 of the capacitor 230, the source/drain electrode 224 is electrically connected to the active layer 221 through the source/drain electrode contact hole 2151, and is provided in order A flat layer 216, an anode 217, a pixel definition layer 218, and a photoresist layer 219 on the source/drain electrode
  • the gate insulating layer 214 covers the active layer 221
  • the dielectric insulating layer 215 covers the gate electrode 222 and the lower plate 231 of the capacitor 230
  • the lower plate 231 of the capacitor 230 and The upper plate 232 of the capacitor 230 is insulated by the dielectric insulating layer 215.
  • the active layer 221 includes a polysilicon region 2211 and source/drain contact regions 2212 formed at both ends of the polysilicon region 2211.
  • the bottom of the source/drain electrode contact hole 2151 is located at the source/ of the active layer 221 In the drain contact region 2212, the source/drain electrode 223 is electrically connected to the source/drain contact region 2212 of the active layer 221 through the source/drain electrode contact hole 2151.
  • the lower plate 231 of the capacitor 230 is composed of a scan line formed simultaneously with the gate electrode 222.
  • the metal of the lower plate 231 may be a metal such as titanium, aluminum, molybdenum, copper, etc. Thickness is 1000A ⁇ 5000A; the upper plate 232 of the capacitor 230 is composed of a power line (VDD) trace formed simultaneously with the source/drain electrode 223.
  • VDD power line
  • the metal of the upper plate 232 may be titanium, aluminum, molybdenum, copper
  • the thickness of the metal is 1000A ⁇ 5000A
  • the dielectric insulation layer of the capacitor 230 is composed of the dielectric insulation layer 215 between the scan line (scan) trace and the power line (VDD) trace, the dielectric insulation layer 215 It can be silicon nitride, silicon dioxide, or a combination of silicon nitride and silicon dioxide, and its thickness is 500A ⁇ 6000A
  • the size of the capacitor 230 can be run through scan lines (scan) and power lines (VDD) Adjust the area of the line overlapping area.
  • a groove 2152 is provided on the dielectric insulating layer 215 at a position corresponding to the lower plate 231 of the capacitor 230, and the upper plate 232 of the capacitor 230 is formed in the groove
  • the dielectric insulating layer of the capacitor 230 is composed of the remaining dielectric insulating layer 215 at the trench 2152.
  • the trench 2152 may be formed at the same time as the source/drain electrode contact hole 2151, and its depth may be adjusted by the halftone process. Therefore, the size of the capacitor 230 can be adjusted by the area of the overlapping area of the scan trace (scan) trace and the power trace (VDD) trace and the depth of the trench 2152.
  • the overlapping area of the scan line (scan) trace and the power line (VDD) trace is used to form a capacitor.
  • the size of the capacitor can be determined by the area of the overlapping area and the thickness of the dielectric insulating layer between the two layers of metal Adjustment.
  • the dielectric insulating layer can be partially etched through a halftone masking process to achieve the purpose of reducing the thickness of the dielectric insulating layer in the capacitor area and increasing the capacitance, while ensuring that the thickness of the dielectric insulating layer in other areas is not affected .
  • the production preparation process can be simplified, the production efficiency and product yield can be improved, and the production cost can be saved. At the same time, space can be effectively saved, the competitiveness of the product can be improved, and the development of high-resolution display technology is facilitated.

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Abstract

一种具有电容的阵列基板及其制备方法，利用扫描线走线(231)和电源线走线(232)的重叠区域形成电容，电容的大小可通过重叠区域面积大小及两层金属之间的介电绝缘层厚度进行调整，可以简化生产工艺，提高生产效率与产品良率，节约生产成本，同时可以有效节约空间，提升产品的竞争力，利于高分辨率显示技术的开发。

Description

一种具有电容的阵列基板及其制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种具有电容的阵列基板及其制备方法。
 背景技术
现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，简称LCD)及有机发光二极管显示器件(Organic Light Emitting Display，简称OLED)。OLED由于重量轻、自发光、广视角、驱动电压低、发光效率高、功耗低、响应速度快等优点，应用范围越来越广泛。OLED按照驱动类型可分为无源OLED(PM-OLED)和有源OLED(AM-OLED)。现有的AM-OLED器件一般为两个晶体管之间夹着一个存储电容，存储电容是维持像素电极电位的主要手段。存储电容通常由驱动晶体管(driver TFT)的栅极、第二金属层及二者之间的绝缘层构成。
 技术问题
参考图1，现有技术中具有电容的阵列基板的层状结构示意图。所述阵列基板包括基板111，阻挡层(M/B)112，缓冲层(Buffer)113，第一栅绝缘层(GI1)114，第二栅绝缘层(GI2)115，介电绝缘层(ILD)116，平坦层(PLN)117，阳极(ANO)118，像素定义层(PDL)119，光阻层 (Photo Spacer，简称PS)120，薄膜晶体管以及电容。所述薄膜晶体管包括形成在缓冲层113上的有源层(Act)121，形成在第一栅绝缘层114上的第一栅极层(GE1)122，以及形成在介电绝缘层(ILD)116上的源/漏电极(S/D)123。通过形成在第一栅绝缘层114上的第一栅极层(GE1)122和形成在第二栅绝缘层115上的第二栅极层(GE2)124的重叠区域形成所述电容。这种电容设置方式，可以节约空间，利于高分辨率显示技术的开发。但其需要两次栅绝缘层(GI1、GI2)的沉积工艺，以及两次栅极层(GE1、GE2)的沉积并图案化工艺，生产工艺较复杂，且增加了生产成本。
因此，如何简化生产工艺，节约生产成本，同时可以延续空间利用最大化的优点，是阵列基板技术发展过程中亟待解决的问题。
 技术解决方案
本申请的目的在于，针对现有技术存在的问题，提供一种具有电容的阵列基板及其制备方法，可以简化生产工艺，节约生产成本，同时可以节约空间，利于高分辨率显示技术的开发。
为实现上述目的，本申请提供了一种具有电容的阵列基板的制备方法，所述制备方法包括如下步骤：(1)提供一基板，在所述基板上依次形成阻挡层、缓冲层和有源层；(2)在所述有源层上依次沉积栅绝缘层和第一金属层，并对所述第一金属层进行图案化，形成栅电极和扫描线走线，其中，所述扫描线走线作为所述电容的下极板；(3)在所述第一金属层上沉积介电绝缘层，并采用半色调掩膜工艺对所述介电绝缘层进行部分刻蚀，形成源/漏电极接触孔以及一沟槽，其中，所述源/漏电极接触孔形成在与所述有源层的两端对应的位置，所述沟槽形成在与所述电容的下极板对应的位置；(4)在所述介电绝缘层上沉积第二金属层，并对所述第二金属层进行图案化，形成源/漏电极和电源线走线，其中，所述源/漏电极通过所述源/漏电极接触孔与所述有源层电连接，所述电源线走线形成在所述沟槽内并作为所述电容的上极板，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘；(5)在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层。
为实现上述目的，本申请还提供了一种具有电容的阵列基板的制备方法，所述制备方法包括如下步骤：(1)提供一基板，在所述基板上依次形成阻挡层、缓冲层和有源层；(2)在所述有源层上依次沉积栅绝缘层和第一金属层，并对所述第一金属层进行图案化，形成栅电极和扫描线走线，其中，所述扫描线走线作为所述电容的下极板；(3)在所述第一金属层上沉积介电绝缘层，并对所述介电绝缘层进行图案化，形成源/漏电极接触孔，其中，所述源/漏电极接触孔形成在与所述有源层的两端对应的位置；(4)在所述介电绝缘层上沉积第二金属层，并对所述第二金属层进行图案化，形成源/漏电极和电源线走线，其中，所述源/漏电极通过所述源/漏电极接触孔与所述有源层电连接，所述电源线走线作为所述电容的上极板，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘；(5)在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层。
为实现上述目的，本申请还提供了一种具有电容的阵列基板，所述阵列基板包括：基板；依次设于所述基板上的阻挡层、缓冲层和有源层；设于所述有源层上的栅绝缘层，所述栅绝缘层覆盖所述有源层；设于所述栅绝缘层上的栅电极和所述电容的下极板；设于所述栅电极和所述电容的下极板上的介电绝缘层，所述介电绝缘层覆盖所述栅电极和所述电容的下极板；设于所述介电绝缘层上的源/漏电极和所述电容的上极板，其中，所述源/漏电极通过源/漏电极接触孔与所述有源层电连接，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘；依次设于所述源/漏电极和所述电容的上极板上的平坦层、阳极、像素定义层以及光阻层。
 有益效果
本申请利用扫描线走线和电源线走线的重叠区域形成电容，电容的大小可通过重叠区域面积大小及两层金属之间的介电绝缘层厚度进行调整。可以通过半色调掩膜工艺对介电绝缘层进行部分刻蚀，达到电容区域介电绝缘层厚度减薄、电容增大的目的，同时可保证其它区域介电绝缘层厚度不受影响。相比现有阵列基板的制备方法，本申请具有电容的阵列基板制备方法可以简化生产工艺，提高生产效率与产品良率，节约生产成本，同时可以有效节约空间，提升产品的竞争力，利于高分辨率显示技术的开发。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1，现有技术中具有电容的阵列基板的层状结构示意图；
图2，本申请具有电容的阵列基板制备方法的流程示意图；
图3A-3F，本申请具有电容的阵列基板制备方法的生产流程示意图；
图4，本申请具有电容的阵列基板的层状结构示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请具有电容的阵列基板制备方法，利用扫描线(scan)走线和电源线(VDD)走线的重叠区域形成电容(即利用走线充当电容)，电容的大小可通过重叠区域面积大小及两层金属之间的介电绝缘层厚度进行调整。可以通过半色调(halftone)掩膜工艺对介电绝缘层进行部分刻蚀，达到电容区域介电绝缘层厚度减薄、电容增大的目的，同时可保证其它区域介电绝缘层厚度不受影响。相比现有阵列基板的制备方法，本申请具有电容的阵列基板制备方法可以简化生产工艺，提高生产效率与产品良率，节约生产成本，同时可以节约空间，提升产品的竞争力，利于高分辨率显示技术的开发。
参考图2、图3A-3F以及图4，其中，图2为本申请具有电容的阵列基板制备方法的流程示意图，图3A-3F为本申请具有电容的阵列基板制备方法的生产流程示意图，图4为本申请具有电容的阵列基板的层状结构示意图。所述制备方法包括如下步骤：S21：提供一基板，在所述基板上依次形成阻挡层、缓冲层和有源层；S22：在所述有源层上依次沉积栅绝缘层和第一金属层，并对所述第一金属层进行图案化，形成栅电极和扫描线走线，其中，所述扫描线走线作为所述电容的下极板；S23：在所述第一金属层上沉积介电绝缘层，并对所述介电绝缘层进行图案化，形成源/漏电极接触孔，其中，所述源/漏电极接触孔形成在与所述有源层的两端对应的位置；S24：在所述介电绝缘层上沉积第二金属层，并对所述第二金属层进行图案化，形成源/漏电极和电源线走线，其中，所述源/漏电极通过所述源/漏电极接触孔与所述有源层电连接，所述电源线走线作为所述电容的上极板，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘；S25：在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层。以下对本申请所述制备方法做详细说明。
关于步骤S21：提供一基板，在所述基板上依次形成阻挡层、缓冲层和有源层，请一并参考图2以及图3A，其中图3A为本申请一实施例在基板上依次形成阻挡层、缓冲层和有源层的示意图。其中，基板211可以为玻璃(glass)基板或由柔性基底材料(PI)制成的柔性基板。具体的，提供一基板211，在基板211上沉积形成阻挡层(M/B)212；在阻挡层212上形成缓冲层(Buffer)213；在缓冲层213上形成阵列基板的薄膜晶体管220的有源层(Act)221。其中，通过在缓冲层213上沉积有源层221，对有源层221进行结晶，并进行图案化，使得所述有源层221包括多晶硅区2211以及形成在多晶硅区2211两端的源/漏极接触区2212。
关于步骤S22：在所述有源层上依次沉积栅绝缘层和第一金属层，并对所述第一金属层进行图案化，形成栅电极和扫描线走线，其中，所述扫描线走线作为所述电容的下极板，请一并参考图2以及图3B，其中图3B为本申请一实施例形成栅电极和扫描线走线的示意图。具体的，通过对沉积在栅绝缘层(GI1)214上的第一金属层进行图案化，分别形成栅电极(GE1)222和扫描线走线231；所述栅电极222位于所述有源层221的多晶硅区2211的上方，所述扫描线走线231作为所述阵列基板的电容230的下极板231。也即，所述栅电极222和所述电容230的下极板231同时制作且位于同一层(均形成在栅绝缘层214上)。
其中，所述第一金属层的材料可以为钛、铝、钼或铜，金属厚度为1000A~5000A。也即，所述电容230的下极板231的材料可以为钛、铝、钼或铜，金属厚度为1000A~5000A。
关于步骤S23：在所述第一金属层上沉积介电绝缘层，并对所述介电绝缘层进行图案化，形成源/漏电极接触孔，其中，所述源/漏电极接触孔形成在与所述有源层的两端对应的位置，请一并参考图2以及图3C，其中图3C为本申请一实施例沉积并图案化介电绝缘层的示意图。具体的，在图3C所示实施例中，采用半色调(halftone)掩膜工艺对所述介电绝缘层(ILD)215进行部分刻蚀，在所述介电绝缘层215上形成源/漏电极接触孔2151以及一沟槽2152。其中，源/漏电极接触孔2151的底部位于所述有源层221的源/漏极接触区2212；所述沟槽2152形成在与所述扫描线走线231(即所述电容230的下极板231)对应的位置。也即，所述电容230的介电绝缘层由沟槽2152处剩余的介电绝缘层组成。其中，沟槽2152为优选设置方案，用于减薄电容区域的介电绝缘层厚度、增大电容，在其它实施例中，在所述介电绝缘层215上也可以仅形成源/漏电极接触孔2151。
其中，所述介电绝缘层215的材料为氮化硅(SiNx)、二氧化硅(SiO2)、或氮化硅与二氧化硅的组合。通过在所述介电绝缘层215上形成沟槽2152，可以达到减薄电容区域的介电绝缘层厚度、增大电容的目的，同时可保证其它区域介电绝缘层厚度不受影响。通过halftone 工艺，可以进行沟槽2152深浅的调整，来调整沟槽2152处剩余的介电绝缘层厚度，从而增大或缩小电容。优选的，沟槽2152处剩余的介电绝缘层厚度为500A~6000A，也即，所述电容230的上下极板之间的介电绝缘层的厚度为500A~6000A。
关于步骤S24：在所述介电绝缘层上沉积第二金属层，并对所述第二金属层进行图案化，形成源/漏电极和电源线走线，其中，所述源/漏电极通过所述源/漏电极接触孔与所述有源层电连接，所述电源线走线作为所述电容的上极板，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘，请一并参考图2以及图3D，其中图3D为本申请一实施例形成源/漏电极和电源线走线的示意图。具体的，通过在介电绝缘层215上沉积第二金属层，并对第二金属层进行图案化，分别形成源/漏电极(S/D)224和电源线走线232。其中，所述源/漏电极223通过所述源/漏电极接触孔2151与所述有源层221电连接(具体的，所述源/漏电极223通过所述源/漏电极接触孔2151与所述有源层221的源/漏极接触区2212电连接)；所述电源线走线232作为所述阵列基板的电容230的上极板232，所述电容230的下极板231和所述电容230的上极板232之间通过所述介电绝缘层215绝缘。也即，所述源/漏电极223和所述电容230的上极板232同时制作且均形成在所述介电绝缘层215上。在本实施例中，所述电容230的上极板232形成在所述介电绝缘层215上的沟槽2152内。在其它实施例中，所述源/漏电极223和所述电容230的上极板232也可以为同时制作且位于同一层(均形成在所述介电绝缘层215上)。
其中，所述第二金属层的材料可以为钛、铝、钼或铜，金属厚度为1000A~5000A。也即，所述电容230的上极板232的材料可以为钛、铝、钼或铜，金属厚度为1000A~5000A。
至此，本申请所述阵列基板的电容230制作完毕。所述电容230的下极板231由第一金属层形成的扫描线(scan)走线231组成，该金属可以是钛，铝，钼，铜等金属，金属厚度为1000A~5000A；所述电容230的上极板232由第二金属层形成的电源线(VDD)走线232组成，该金属可以是钛，铝，钼，铜等金属，金属厚度为1000A~5000A；所述电容230的介电绝缘层由沟槽2152处剩余介电绝缘层215组成，介电绝缘层215可以为氮化硅，二氧化硅，或氮化硅&二氧化硅的组合，其厚度为500A~6000A，且可以通过halftone 工艺进行调整；所述电容230的大小可以通过扫描线(scan)走线和电源线(VDD)走线重叠区域面积及沟槽2152的深度进行调整。
关于步骤S25：在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层，请一并参考图2、图3E-3F以及图4，其中图3E为本申请一实施例形成平坦层的示意图，图3F为本申请一实施例形成阳极的示意图，图4为本申请一实施例阵列基板的层状结构示意图。
具体的，在所述介电绝缘层17上的源/漏电极223和电源线走线232上方涂布有机膜层，并进行图案化，形成平坦层(PLN)216，如图3E所示。
具体的，在所述平坦层216上方沉积阳极金属(PE)并进行图案化，形成所述阳极(ANO)217，如图3F所示。其中，所述阳极217位于所述源/漏电极223上方并与所述源/漏电极223电连接。
具体的，在阳极217上方涂布有机光阻并进行图案化，形成所述像素定义层(PDL)218以及所述光阻层(Photo Spacer，简称PS)219。至此，本申请阵列基板即制作完成，其层状结构示意图如图4所示。
采用本申请所述制备方法制备的阵列基板，利用扫描线(scan)走线和电源线(VDD)走线的重叠区域形成电容，电容的大小可通过重叠区域面积大小及两层金属之间的介电绝缘层厚度进行调整。可以通过半色调(halftone)掩膜工艺对介电绝缘层进行部分刻蚀，达到电容区域介电绝缘层厚度减薄、电容增大的目的，同时可保证其它区域介电绝缘层厚度不受影响。相比现有阵列基板的制备方法，本申请具有电容的阵列基板制备方法可以简化生产工艺，提高生产效率与产品良率，节约生产成本，同时延续空间利用最大化的优点，可以有效节约空间，提升产品的竞争力，利于高分辨率显示技术的开发。
参考图4，本申请具有电容的阵列基板的层状结构示意图。本申请阵列基板包括：基板211，依次设于所述基板211上的阻挡层212、缓冲层213和有源层221，设于所述有源层221上的栅绝缘层214，设于所述栅绝缘层214上的栅电极222和所述电容230的下极板231，设于所述栅电极222和所述电容230的下极板231上的介电绝缘层215，设于所述介电绝缘层215上的源/漏电极223和所述电容230的上极板232，所述源/漏电极224通过源/漏电极接触孔2151与所述有源层221电连接，依次设于所述源/漏电极223和所述电容239的上极板232上的平坦层216、阳极217、像素定义层218以及光阻层219。其中，所述栅绝缘层214覆盖所述有源层221，所述介电绝缘层215覆盖所述栅电极222和所述电容230的下极板231，所述电容230的下极板231和所述电容230的上极板232之间通过所述介电绝缘层215绝缘。
具体的，所述有源层221包括多晶硅区2211以及形成在多晶硅区2211两端的源/漏极接触区2212，所述源/漏电极接触孔2151的底部位于所述有源层221的源/漏极接触区2212，所述源/漏电极223通过所述源/漏电极接触孔2151与所述有源层221的源/漏极接触区2212电连接。
具体的，所述电容230的下极板231由与所述栅电极222同时形成的扫描线(scan)走线组成，下极板231的金属可以是钛，铝，钼，铜等金属，金属厚度为1000A~5000A；所述电容230的上极板232由与所述源/漏电极223同时形成的电源线(VDD)走线组成，上极板232金属可以是钛，铝，钼，铜等金属，金属厚度为1000A~5000A；所述电容230的介电绝缘层由扫描线(scan)走线和电源线(VDD)走线之间的介电绝缘层215组成，介电绝缘层215可以为氮化硅，二氧化硅，或氮化硅&二氧化硅的组合，其厚度为500A~6000A；所述电容230的大小可以通过扫描线(scan)走线和电源线(VDD)走线重叠区域面积进行调整。
优选的，在本实施例中，所述介电绝缘层215上与所述电容230的下极板231对应的位置设有一沟槽2152，所述电容230的上极板232形成在所述沟槽2152内，所述电容230的介电绝缘层由沟槽2152处剩余介电绝缘层215组成。所述沟槽2152可以与所述源/漏电极接触孔2151同时形成，其深度可以通过halftone 工艺进行调整。从而，所述电容230的大小可以通过扫描线(scan)走线和电源线(VDD)走线重叠区域面积及沟槽2152的深度进行调整。
采用本申请阵列基板，利用扫描线(scan)走线和电源线(VDD)走线的重叠区域形成电容，电容的大小可通过重叠区域面积大小及两层金属之间的介电绝缘层厚度进行调整。可以通过半色调(halftone)掩膜工艺对介电绝缘层进行部分刻蚀，达到电容区域介电绝缘层厚度减薄、电容增大的目的，同时可保证其它区域介电绝缘层厚度不受影响。可以简化生产制备工艺，提高生产效率与产品良率，节约生产成本，同时可以有效节约空间，提升产品的竞争力，利于高分辨率显示技术的开发。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (20)

  1. 一种具有电容的阵列基板的制备方法，其中，所述制备方法包括如下步骤： (1)提供一基板，在所述基板上依次形成阻挡层、缓冲层和有源层； (2)在所述有源层上依次沉积栅绝缘层和第一金属层，并对所述第一金属层进行图案化，形成栅电极和扫描线走线，并且其中，所述扫描线走线作为所述电容的下极板； (3)在所述第一金属层上沉积介电绝缘层，并采用半色调掩膜工艺对所述介电绝缘层进行部分刻蚀，形成源/漏电极接触孔以及一沟槽，并且其中，所述源/漏电极接触孔形成在与所述有源层的两端对应的位置，所述沟槽形成在与所述电容的下极板对应的位置； (4)在所述介电绝缘层上沉积第二金属层，并对所述第二金属层进行图案化，形成源/漏电极和电源线走线，并且其中，所述源/漏电极通过所述源/漏电极接触孔与所述有源层电连接，所述电源线走线形成在所述沟槽内并作为所述电容的上极板，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘； (5)在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层。
  2. 如权利要求1所述的制备方法，其中，所述电容的下极板与所述电容的上极板的金属厚度均为1000A~5000A。
  3. 如权利要求1所述的制备方法，其中，所述电容的下极板与所述电容的上极板之间的介电绝缘层的厚度为500A~6000A。
  4. 如权利要求1所述的制备方法，其中，所述第一金属层与所述第二金属层的材料为钛、铝、钼或铜。
  5. 如权利要求1所述的制备方法，其中，所述介电绝缘层的材料为氮化硅、二氧化硅、或氮化硅与二氧化硅的组合。
  6. 如权利要求1所述的制备方法，其中，步骤(5)所述的在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层进一步包括：在所述第二金属层上涂布有机膜层并进行图案化，形成所述平坦层；在所述平坦层上沉积阳极金属并进行图案化，形成所述阳极；在所述阳极上方涂布有机光阻并进行图案化，形成所述像素定义层以及所述光阻层。
  7. 一种具有电容的阵列基板的制备方法，其中，所述制备方法包括如下步骤： (1)提供一基板，在所述基板上依次形成阻挡层、缓冲层和有源层； (2)在所述有源层上依次沉积栅绝缘层和第一金属层，并对所述第一金属层进行图案化，形成栅电极和扫描线走线，并且其中，所述扫描线走线作为所述电容的下极板； (3)在所述第一金属层上沉积介电绝缘层，并对所述介电绝缘层进行图案化，形成源/漏电极接触孔，并且其中，所述源/漏电极接触孔形成在与所述有源层的两端对应的位置； (4)在所述介电绝缘层上沉积第二金属层，并对所述第二金属层进行图案化，形成源/漏电极和电源线走线，并且其中，所述源/漏电极通过所述源/漏电极接触孔与所述有源层电连接，所述电源线走线作为所述电容的上极板，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘； (5)在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层。
  8. 如权利要求7所述的制备方法，其中，步骤(3)中所述对所述介电绝缘层进行图案化进一步包括：采用半色调掩膜工艺对所述介电绝缘层进行部分刻蚀。
  9. 如权利要求7所述的制备方法，其中，步骤(3)中所述对所述介电绝缘层进行图案化进一步包括：在与所述电容的下极板对应的位置形成一沟槽；步骤(4)进一步包括：所述电容的上极板形成在所述沟槽内。
  10. 如权利要求7所述的制备方法，其中，所述第一金属层与所述第二金属层的材料为钛、铝、钼或铜。
  11. 如权利要求7所述的制备方法，其中，所述介电绝缘层的材料为氮化硅、二氧化硅、或氮化硅与二氧化硅的组合。
  12. 如权利要求7所述的制备方法，其中，所述电容的下极板与所述电容的上极板的金属厚度均为1000A~5000A。
  13. 如权利要求7所述的制备方法，其中，所述电容的下极板与所述电容的上极板之间的介电绝缘层的厚度为500A~6000A。
  14. 如权利要求7所述的制备方法，其中，步骤(5)所述的在所述第二金属层上依次形成平坦层、阳极、像素定义层以及光阻层进一步包括：在所述第二金属层上涂布有机膜层并进行图案化，形成所述平坦层；在所述平坦层上沉积阳极金属并进行图案化，形成所述阳极；在所述阳极上方涂布有机光阻并进行图案化，形成所述像素定义层以及所述光阻层。
  15. 一种具有电容的阵列基板，其中，所述阵列基板包括：基板；依次设于所述基板上的阻挡层、缓冲层和有源层；设于所述有源层上的栅绝缘层，所述栅绝缘层覆盖所述有源层；设于所述栅绝缘层上的栅电极和所述电容的下极板；设于所述栅电极和所述电容的下极板上的介电绝缘层，所述介电绝缘层覆盖所述栅电极和所述电容的下极板；设于所述介电绝缘层上的源/漏电极和所述电容的上极板，并且其中，所述源/漏电极通过源/漏电极接触孔与所述有源层电连接，所述电容的下极板和所述电容的上极板之间通过所述介电绝缘层绝缘；依次设于所述源/漏电极和所述电容的上极板上的平坦层、阳极、像素定义层以及光阻层。
  16. 如权利要求15所述的阵列基板，其中，所述介电绝缘层上与所述电容的下极板对应的位置设有一沟槽，所述电容的上极板形成在所述沟槽内。
  17. 如权利要求15所述的阵列基板，其中，所述第一金属层与所述第二金属层的材料为钛、铝、钼或铜。
  18. 如权利要求15所述的阵列基板，其中，所述介电绝缘层的材料为氮化硅、二氧化硅、或氮化硅与二氧化硅的组合。
  19. 如权利要求15所述的阵列基板，其中，所述电容的下极板与所述电容的上极板的金属厚度均为1000A~5000A。
  20. 如权利要求15所述的阵列基板，其中，所述电容的下极板与所述电容的上极板之间的介电绝缘层的厚度为500A~6000A。
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