WO2013063971A1 - 薄膜晶体管阵列基板 - Google Patents

薄膜晶体管阵列基板 Download PDF

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Publication number
WO2013063971A1
WO2013063971A1 PCT/CN2012/080382 CN2012080382W WO2013063971A1 WO 2013063971 A1 WO2013063971 A1 WO 2013063971A1 CN 2012080382 W CN2012080382 W CN 2012080382W WO 2013063971 A1 WO2013063971 A1 WO 2013063971A1
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Prior art keywords
layer
semiconductor
semiconductor layer
array substrate
insulating
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PCT/CN2012/080382
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English (en)
French (fr)
Inventor
刘翔
薛建设
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020127030279A priority Critical patent/KR101456354B1/ko
Priority to JP2014539219A priority patent/JP2015501549A/ja
Priority to EP12791676.5A priority patent/EP2779249B1/en
Priority to US13/701,877 priority patent/US9263594B2/en
Publication of WO2013063971A1 publication Critical patent/WO2013063971A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • Embodiments of the present invention relate to a Thin Film Transistor (TFT) array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the process of fabricating a TFT array substrate in the prior art generally includes: depositing a gate metal film, a gate insulating film, a metal oxide film (semiconductor film), a source/drain metal film, a passivation layer film, and a transparent conductive on the substrate.
  • the film is formed by sequentially forming a pattern of a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, a drain electrode, a passivation layer, and a transparent pixel electrode by a plurality of photolithography processes.
  • a photolithography process includes processes such as film formation, exposure, development, etching, and lift-off, and the etching process includes dry etching and wet etching.
  • wet etching has the disadvantages of poor anisotropy, severe undercut, poor controllability to the pattern, inability to be used for small feature sizes, and large amounts of chemical waste liquid; relatively speaking, dry engraving Corrosion is widely used in TFT array substrates due to its good anisotropy, controllability, flexibility, repeatability, safe operation, easy automation, no chemical waste, no pollution introduced into the process, and high cleanliness. In the lithography process.
  • the formation of the semiconductor layer and the source electrode and the drain electrode is performed in a continuous process, that is, a semiconductor layer film is deposited first, and a source/drain metal film is deposited.
  • an etch barrier layer is generally deposited on the semiconductor film, and then the source and drain metal films are deposited. After the patterning process is completed, the etch stop layer remains in the channel between the source and drain electrodes above the semiconductor layer.
  • One side of the semiconductor layer contacts the etch barrier layer and the other side contacts the gate insulating layer.
  • the etch barrier layer and the gate insulating layer are generally made of an insulating material such as SiN x , A1 2 0 3 or SiO x . If the semiconductor layer is made of a metal oxide material, and the etch barrier layer and the gate insulating layer are made of SiN x , the etch barrier layer and the SiN x in the gate insulating layer are taken up to constitute Metal oxide of the semiconductor layer Oxygen ions in the compound cause oxygen loss in the metal oxide in the semiconductor layer, resulting in unstable performance of the TFT array substrate.
  • the etch barrier layer and the gate insulating layer may also be made of A1 2 0 3 or SiO x .
  • A1 2 0 3 or SiO x is used to form a pattern of an etch barrier layer and a gate insulating layer, the etching rate is low, which is disadvantageous for mass production.
  • One of the technical problems to be solved by the embodiments of the present invention is to provide a TFT array substrate which can improve the stability of a thin film transistor (TFT) device and is suitable for mass production in view of the above problems existing in the prior art.
  • TFT thin film transistor
  • An embodiment of the present invention provides a TFT array substrate, including: a base substrate and a thin film transistor as a switching element, the thin film transistor including a gate electrode, a semiconductor layer, a semiconductor protective layer, a source electrode, and a drain electrode, wherein The semiconductor protective layer is adjacent to the semiconductor layer, and the semiconductor protective layer comprises a composite layer structure comprising a protective layer made of an insulating material capable of avoiding oxygen loss of the semiconductor layer and contacting the semiconductor layer and being easily etched An insulating layer made of insulating material.
  • the gate electrode is on the base substrate and the semiconductor layer is above the gate electrode.
  • the semiconductor protective layer includes a gate insulating composite layer structure between the gate electrode and the semiconductor layer and adjacent to a lower side of the semiconductor layer, the gate insulating composite layer structure including insulation capable of avoiding oxygen loss of the semiconductor layer
  • a gate insulating protective layer made of a material in contact with the semiconductor layer and a gate insulating layer made of an easily etchable insulating material.
  • the source electrode and the drain electrode are located on the semiconductor layer with a channel disposed therebetween.
  • An etch barrier composite layer structure comprising an etch barrier protective layer made of an insulating material capable of avoiding oxygen loss of the semiconductor layer and being made of an etchable insulating material The barrier insulating layer is etched.
  • the semiconductor layer is on the base substrate and the gate electrode is on the semiconductor layer.
  • the semiconductor protective layer is located between the base substrate and the semiconductor layer and adjacent to the lower side of the semiconductor layer
  • the modified insulating composite layer structure includes A modified insulating protective layer made of an insulating material de-oxygenated with a conductor layer in contact with the semiconductor layer and a modified insulating layer made of an easily etchable insulating material.
  • the source electrode and the drain electrode are located on the semiconductor layer with a channel interposed therebetween.
  • the semiconductor protective layer includes an etch barrier composite layer structure located in the channel and adjacent to an upper side of the semiconductor layer, the etch barrier composite layer structure including an insulating material capable of avoiding oxygen loss of the semiconductor layer
  • An etch barrier protective layer is formed in contact with the semiconductor layer and an etch barrier insulating layer made of an easily etchable insulating material.
  • the semiconductor layer is formed of a metal oxide semiconductor material.
  • the thickness ratio of the protective layer to the insulating layer is 1/10 to 3/5.
  • the thickness of the protective layer ranges from 300A to 1500A
  • the thickness of the insulating layer ranges from 1000A to 20000 A.
  • the etch barrier protective layer is made of silicon oxide or a metal oxide
  • the etch barrier insulating layer is made of a nitride or an organic insulating material.
  • the protective layer is made of SiOx or A1203
  • the insulating layer is made of SiNx or an organic resin.
  • the array substrate further includes a passivation layer and a transparent pixel electrode.
  • the reaction gas corresponding to the formation of SiN x is Si 3 ⁇ 4, NH 3 and N 2 , or SiH 2 Cl 2 , Li 3 and N 2 .
  • the semiconductor protective layer adjacent to the semiconductor layer is provided with a composite layer structure, and in the composite layer structure, the protective layer in contact with the semiconductor layer is used to prevent the semiconductor layer from being deoxidized.
  • the material is made of, for example, silicon oxide or metal oxide, which can avoid the oxygen loss of the semiconductor layer, and is beneficial to improving the stability of the TFT array substrate; and is in contact with the protective layer (ie, not with the semiconductor)
  • the layer of the insulating layer is made of an easily etchable insulating material, such as a nitride or an organic insulating material. This structure is advantageous for improving the overall etching speed of the array substrate, and is advantageous for increasing productivity. Mass production.
  • FIGS. 1(a)-(f) are structural diagrams of a TFT array substrate in Embodiment 1 of the present invention, wherein: (a) is a schematic structural view of a TFT array substrate after the first photolithography process in Embodiment 1 is completed. ;
  • FIG. 1(b) is a schematic view showing the structure of a TFT array substrate after completion of the second photolithography process in Embodiment 1;
  • FIG. 1(c) is a schematic view showing the structure of a TFT array substrate after the third photolithography process in Embodiment 1 is completed;
  • FIG. 1(d) is a schematic view showing the structure of a TFT array substrate after the fourth photolithography process in Embodiment 1 is completed;
  • FIG. 1(e) is a schematic view showing the structure of a TFT array substrate after the fifth photolithography process in Embodiment 1 is completed;
  • FIG. 1(f) is a schematic view showing the structure of a TFT array substrate after the sixth photolithography process in Embodiment 1 is completed;
  • FIG. 2(a)-(f) are schematic diagrams showing the structure of a TFT array substrate in Embodiment 2 of the present invention; wherein: FIG. 2(a) is a schematic structural view of a TFT array substrate after the first photolithography process in Embodiment 2 is completed. ;
  • FIG. 2(b) is a schematic view showing the structure of a TFT array substrate after completion of the second photolithography process in Embodiment 2;
  • FIG. 2(c) is a schematic view showing the structure of a TFT array substrate after the third photolithography process in Embodiment 2 is completed;
  • FIG. 2(d) is a schematic view showing the structure of the TFT array substrate after the fourth photolithography process in Embodiment 2 is completed;
  • FIG. 2(e) is a schematic view showing the structure of a TFT array substrate after the fifth photolithography process in Embodiment 2 is completed;
  • Fig. 2(f) is a view showing the structure of the TFT array substrate after completion of the sixth photolithography process in the second embodiment.
  • 4-gate insulating protective layer 5-semiconductor layer; 6-etch barrier protective layer;
  • the TFT array substrate includes: a base substrate 1 and a thin film transistor as a switching element.
  • the thin film transistor includes a gate electrode 2, a semiconductor layer 5, a semiconductor protective layer, a source electrode 8, and a drain electrode 9.
  • the semiconductor protective layer adjacent to the semiconductor layer 5 has a composite layer structure.
  • the composite layer structure includes a protective layer made of an insulating material capable of avoiding oxygen loss of the semiconductor layer 5, and an insulating layer made of an easily etchable insulating material.
  • the TFT array substrate includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other to define a plurality of pixel regions arranged in an array, each of the pixel regions including a thin film transistor as a switching element, a gate of the thin film transistor
  • the poles are connected or integrally formed with the corresponding gate lines, and the sources are connected or integrally formed with the corresponding data lines.
  • the following description is only for a thin film transistor of one pixel region, but the description is applicable to thin film transistors of other pixel regions.
  • the TFT array substrate includes: a base substrate 1; a gate electrode 2 formed on the base substrate 1, covering the gate electrode 2 and extending onto the base substrate 1 a gate insulating layer 3; a gate insulating protective layer 4 overlying the gate insulating layer 3; a semiconductor layer 5 formed on the gate insulating protective layer 4; and a source electrode 8 and a drain electrode 9 formed on the semiconductor layer 5.
  • a channel 15 is formed between the source electrode 8 and the drain electrode 9; a composite layer structure formed in the channel 15 , the composite layer structure including an etch barrier protection layer 6 and an etch barrier insulating layer 7
  • the etch barrier protection layer 6 is located under the etch barrier insulating layer 7 and is in contact with the semiconductor layer 5; the passivation layer 10 completely covers the source electrode 8, the etch barrier insulating layer 7, and the drain electrode. 9 and a gate insulating protective layer 4, the portion of the passivation layer 10 covering the drain electrode 9 is provided with a via hole 12; a transparent pixel electrode 11 formed on the passivation layer 10, the transparent pixel electrode 11 passing through the via hole 12 It is connected to the drain electrode 9.
  • the semiconductor protective layer adjacent to the semiconductor layer 5 includes a composite layer structure formed in the channel 15, that is, including an etch barrier protective layer 6 and an etch barrier insulating layer 7, above the semiconductor layer 5. .
  • the semiconductor protective layer adjacent to the semiconductor layer 5 includes a composite layer structure composed of the gate insulating layer 3 and the gate insulating protective layer 4, under the semiconductor layer 5, at the semiconductor layer 5 and the gate electrode 2. between.
  • the semiconductor protective layer adjacent to the semiconductor layer 5 includes both of the above cases, so that the semiconductor layer 5 can be protected on both the upper and lower sides thereof.
  • the TFT array substrate of the present embodiment is used, for example, for a vertical drive type or a horizontal drive type liquid crystal display device, but the present invention is not limited thereto.
  • the gate insulating layer 3/etch barrier insulating layer 7 has a thickness ranging, for example, from 1000 A to 20000 A, which may be made of nitride or an organic insulating material, such as SiN x or organic. Made of resin.
  • the gate insulating protective layer 4/etch barrier protective layer 6 has a thickness ranging, for example, from 300A to 1500A, and can be made of silicon oxide or metal oxide, such as SiO x or A1. 2 0 3 made.
  • the gate insulating layer 3, the gate insulating protective layer 4, the etch barrier protective layer 6, and the etch barrier insulating layer 7 may be, for example, a plasma enhanced chemical vapor deposition (PECVD) or a germanium. It is formed by sputtering.
  • PECVD plasma enhanced chemical vapor deposition
  • germanium germanium
  • the gate insulating protective layer 4 and the etch barrier protective layer 6 in contact with the semiconductor layer 5 are both made of a material that avoids oxygen loss of the semiconductor layer 5, but the material is difficult to etch;
  • the gate insulating layer 3 and the etch barrier insulating layer 7 which are in contact with the semiconductor layer 5 are each made of an easily etchable material.
  • the thickness ratio of the gate insulating protective layer 4 to the gate insulating layer 3 is, for example, 1/10 to 3/5.
  • the thickness ratio of the etch barrier protective layer 6 to the etch barrier insulating layer 7 is, for example, 1/10 to 3/5.
  • the base substrate 1 may be a transparent alkali-free glass substrate or a quartz substrate, or may be used with other transparent substrates having a certain hardness.
  • the semiconductor layer 5 is formed of, for example, a metal oxide semiconductor material of a transparent amorphous oxide semiconductor IGZO (In-Ga-Zn-0), for example, formed by sputtering, and has a thickness ranging, for example, from 50 A to 1000 A. .
  • IGZO transparent amorphous oxide semiconductor
  • the gate electrode 2, the source electrode 8 and the drain electrode 9 are formed by sputtering or thermal evaporation, and have a thickness ranging, for example, from 4000 ⁇ to 15,000 ⁇ .
  • the gate electrode 2, the source electrode 8 and the drain electrode 9 may be made of a single layer film formed of any one of Cr, W, Cu, Ti, Ta or Mo, or may be made of an alloy of any of the above metals, or ⁇ Made of a multilayer film formed by any combination of the above metals.
  • the passivation layer 10 is formed, for example, by PECVD, and has a thickness ranging, for example, from 1000 A to 3000 A.
  • the passivation layer 10 can be made of an oxide, a nitride or an oxynitride compound.
  • the reaction gas is formed corresponding to the nitride may be Si3 ⁇ 4, NH 3 and N 2, or Si3 ⁇ 4Cl 2, NH 3 and N 2.
  • the transparent pixel electrode 11 is formed by sputtering or thermal evaporation, and has a thickness ranging, for example, from 300 A to 1500 A.
  • the transparent pixel electrode 11 can be made of a transparent metal oxide material, for example, an ITO film or an IZO film. .
  • the TFT array substrate can be formed by using six photolithography processes.
  • An example process flow is illustrated below in conjunction with Figure 1 (a) - Figure 1 (f).
  • Step (1) depositing a gate metal film on the base substrate 1, and then forming a gate electrode 3 and a gate scan line (not shown) by a first photolithography process Graphics.
  • Step (2) sequentially depositing a gate insulating film, a metal oxide film for forming a semiconductor layer on the base substrate on which the step (1) is completed, and then passing through a second photolithography process A pattern of the gate insulating layer 3, the gate insulating protective layer 4, and the semiconductor layer 5 is formed.
  • the gate insulating layer 3 covers the gate electrode 2 and extends onto the base substrate 1.
  • the gate insulating protective layer 4 is overlaid on the gate insulating layer 3, and its planar area size is substantially equal to the planar area size of the gate insulating layer 3.
  • Step (3) depositing two etching barrier insulating films on the substrate on which step (2) is completed, and then forming an etch barrier protective layer 6 and etching by a third photolithography process.
  • the pattern of the insulating layer 7 is blocked.
  • the etch barrier insulating layer 7 is overlaid on the etch barrier protective layer 6 and has the same planar size, and the etch barrier protective layer 6 is located on and in contact with the semiconductor layer 5. Etching The barrier protective layer 6 and the etch barrier insulating layer 7 substantially correspond to the channel region of the thin film transistor to be formed.
  • Step (4) depositing a source/drain metal film on the base substrate on which step (3) is completed, and then forming a source electrode 8, a drain electrode 9, and a data scan through a fourth photolithography process.
  • a graphic of a line (not shown).
  • the source electrode 8 and the drain electrode 9 are located on the semiconductor layer 5 and are respectively located on both sides of the etch barrier protection layer 6 and the etch barrier insulating layer 7, forming a trench therebetween.
  • Step (5) depositing a passivation layer film on the base substrate on which the step (4) is completed, and then forming a pattern of the passivation layer 10 having the via holes 12 by the fifth photolithography process
  • the via hole 12 is located above the drain electrode 9 to expose a portion of the drain electrode 9.
  • Step (6) depositing a transparent conductive film on the base substrate on which step (5) is completed, and then forming a pattern of the transparent pixel electrode 11 by a sixth photolithography process, so that the transparent pixel The electrode 11 is positioned above the via hole 12, and the transparent pixel electrode 11 is connected to the drain electrode 9 through the via hole 12.
  • the etching process in each photolithography process can be completed by dry etching.
  • the TFT array substrate includes: a base substrate 1; a modified insulating layer 14 covering the base substrate 1, and a modified insulating protective layer 13 covering the modified insulating layer 14; a semiconductor layer 5 on the insulating protective layer 13; a source electrode 8 and a drain electrode 9 formed on the semiconductor layer 5, and a channel 15 disposed between the source electrode 8 and the drain electrode 9; a composite layer structure including an etch barrier protective layer 6 and an etch barrier insulating layer 7 under the etch barrier insulating layer 7 and in contact with the semiconductor layer 5; a gate insulating layer 3, the gate insulating layer 3 completely covering the source electrode 8, the etch barrier insulating layer 7, the drain electrode 9, and the gate insulating protective layer 4, the gate insulating layer 3 covering the drain electrode 9.
  • a via hole 12 is partially formed; a transparent pixel electrode 11 formed on the gate insulating layer 3, and the transparent pixel electrode 11 is connected to the drain electrode 9 through the via hole 12.
  • the semiconductor protective layer adjacent to the semiconductor layer 5 includes a composite layer structure formed in the channel 15, i.e., including an etch barrier protective layer 6 and an etch barrier insulating layer 7.
  • the semiconductor protective layer adjacent to the semiconductor layer 5 includes a composite insulating layer 14 and a modified insulating protective layer 13 , and is located on the semiconductor layer 5 and the base substrate 1 between.
  • the semiconductor protective layer adjacent to the semiconductor layer 5 includes both of the above cases, so that the semiconductor layer 5 can be protected on both the upper and lower sides thereof.
  • the TFT array substrate of the present embodiment is used, for example, for a vertical drive type or a horizontal drive type liquid crystal display device, but the present invention is not limited thereto.
  • the material, thickness, and formation method of the modified insulating layer 14 may be the same as that of the gate insulating layer 3/etch barrier insulating layer 7 in Embodiment 1.
  • the material, thickness, and formation method of the modified insulating protective layer 13 may be the same as the gate insulating protective layer 4/etch barrier protective layer 6 in Embodiment 1.
  • the gate insulating layer 3 is not in direct contact with the semiconductor layer 5, so that a single layer structure can be used.
  • the material, thickness and formation method of the single layer structure can be the same as the gate insulating layer 3 in the embodiment 1.
  • the etch barrier insulating layer 7 is the same, and may be the same as the gate insulating protective layer 4/etch barrier protective layer 6 in Embodiment 1.
  • the material, thickness, and formation method of the other layers of the array substrate structure are the same as those in the first embodiment, and will not be described again.
  • the semiconductor layer 5 is formed, for example, of a metal oxide semiconductor material of a transparent amorphous oxide semiconductor IGZO (In-Ga-Zn-0), and is formed, for example, by sputtering, and has a thickness ranging, for example, from 50 A to 1000 ⁇ .
  • IGZO transparent amorphous oxide semiconductor
  • the semiconductor protective layer of the composite layer structure made of the above materials neither captures the oxygen ions in the semiconductor layer 5, the stability of the TFT array substrate can be improved, and the gate insulating layer and the etch barrier layer can be improved.
  • the etching speed is beneficial to increase production capacity and is suitable for mass production.
  • the TFT array substrate of this embodiment can be formed, for example, by using a photolithography process six times.
  • An example process flow is illustrated below in conjunction with Figures 2(a) -2(f).
  • Step (1) as shown in FIG. 2(a), two layers of a modified insulating film and a metal oxide film are sequentially deposited on the base substrate 1, and then a modified insulating layer 14 and a modified insulating protective layer are formed by a first photolithography process. 13 and the pattern of the semiconductor layer 5, the modified insulating protective layer 13 is overlaid on the modified insulating layer 14 and has the same planar size, and the modified insulating layer 14 is overlaid on the base substrate 1.
  • Step (2) depositing two etching barrier insulating films on the base substrate on which step (1) is completed, and forming an etching barrier protective layer 6 and engraving by a second photolithography process Eclipse a pattern of a composite layer structure of the barrier insulating layer 7 overlying the etch barrier protection layer 6 and having the same planar dimension, the etch barrier protection layer 6 being located on the semiconductor layer 5 and contact;
  • Step (3) depositing a source/drain metal film on the base substrate on which the step (2) is completed, and forming the source electrode 8, the drain electrode 9, and the data scan line by a third photolithography process a pattern (not shown), the source electrode 8 and the drain electrode 9 are located on the semiconductor layer 5, and are respectively located on both sides of the etch barrier protection layer 6 and the etch barrier insulating layer 7;
  • Step (4) depositing a gate insulating film on the base substrate on which the step (3) is completed, and forming a pattern of the gate insulating layer 3 and the via 12 by a fourth photolithography process. Having the via 12 above the drain electrode 9;
  • Step (5) depositing a transparent conductive film on the base substrate on which the step (4) is completed, and forming a pattern of the transparent pixel electrode 11 by a fifth photolithography process, so that the transparent pixel electrode 11 is located above the via hole 12, and connects the transparent pixel electrode 11 to the drain electrode 9 through the via hole 12;
  • Step (6) depositing a gate metal film on the base substrate on which step (5) is completed, and forming a gate electrode 3 and a gate scan line by a sixth photolithography process (not shown) Show) the graphics.
  • the etching process in each photolithography process can be completed by dry etching.
  • Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

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Abstract

一种TFT阵列基板，包括：基底基板（1）和薄膜晶体管，该薄膜晶体管包括栅电极（2）、半导体层（5）、半导体保护层、源电极（8）和漏电极（9），半导体保护层与半导体层（5）相邻且采用复合层结构，该复合层结构包括由能够避免半导体层（5）失氧的绝缘材料制成的与半导体层（5）接触的保护层（6）和由易刻蚀的绝缘材料制成的绝缘层（7）。

Description

薄膜晶体管阵列基板 技术领域
本发明的实施例涉及一种薄膜晶体管（Thin Film Transistor, TFT )阵列 基板。 背景技术
随着显示器制造技术的发展， 薄膜晶体管液晶显示器 （Thin Film Transistor Liquid Crystal Display, TFT-LCD ) 因具有体积小、 功耗低、 无辐 射等特点， 在当前的平板显示器市场中逐渐占据了主导地位。
现有技术中制作 TFT阵列基板的工艺过程一般包括： 在基板上沉积栅 极金属薄膜、 栅极绝缘薄膜、 金属氧化物薄膜（半导体薄膜）、 源漏极金属 薄膜、钝化层薄膜以及透明导电薄膜，并通过数次光刻工艺依次形成栅电极、 栅极绝缘层、半导体层、源电极、漏电极、钝化层以及透明像素电极的图形。 通常， 一次光刻工艺依次包括成膜、 曝光、 显影、 刻蚀和剥离等工艺， 刻蚀 工艺包括干法刻蚀和湿法刻蚀。湿法刻蚀存在各向异性较差、钻刻（ undercut ) 严重、对图形的控制性较差、 不能用于小的特征尺寸、产生大量的化学废液 等缺点； 相对而言， 干法刻蚀因具备各向异性好， 可控性、 灵活性、 重复性 好， 操作安全， 易实现自动化， 无化学废液， 处理过程未引入污染， 洁净度 高等优点而被广泛应用于 TFT阵列基板的光刻工艺中。
在上述制作 TFT阵列基板的工艺过程中， 半导体层与源电极以及漏电 极的形成是在连续的工艺下完成的， 即先沉积半导体层薄膜，再沉积源漏极 金属薄膜。为防止在沉积源漏极金属薄膜时对半导体薄膜的破坏，一般会在 半导体薄膜上面沉积一层刻蚀阻挡层，然后再沉积源漏极金属薄膜。构图工 艺完成之后，刻蚀阻挡层保留于半导体层上方的源电极和漏电极之间的沟道 之中。 半导体层的一面接触刻蚀阻挡层， 另一面接触栅极绝缘层。 刻蚀阻挡 层与栅极绝缘层一般釆用 SiNx、 A1203或 SiOx等绝缘材料制成。如果半导体 层是釆用金属氧化物材料制成的，且所述刻蚀阻挡层与栅极绝缘层釆用 SiNx 制成， 则刻蚀阻挡层与栅极绝缘层中的 SiNx会夺取构成半导体层的金属氧 化物中的氧离子， 造成半导体层中的金属氧化物失氧， 从而导致 TFT阵列 基板的性能不稳定。
为了提高 TFT 阵列基板的稳定性， 刻蚀阻挡层与栅极绝缘层也可釆用 A1203或 SiOx制成。 但是， 釆用干法刻蚀时， 如果釆用 A1203或 SiOx来形成 刻蚀阻挡层与栅极绝缘层的图形， 那么刻蚀速率较低， 不利于大批量生产。 发明内容
本发明的实施例所要解决的技术问题之一是针对现有技术中存在的上 述问题， 提供一种既能提高薄膜晶体管（TFT )器件的稳定性， 又适合大批 量生产的 TFT阵列基板。
本发明的一个实施例提供了一种 TFT阵列基板， 包括： 基底基板和作 为开关元件的薄膜晶体管， 所述薄膜晶体管包括栅电极、 半导体层、 半导体 保护层、 源电极和漏电极， 其中， 所述半导体保护层与半导体层相邻， 该半 导体保护层包括复合层结构 ,所述复合层结构包括由能够避免半导体层失氧 的绝缘材料制成的与半导体层接触的保护层和由易刻蚀的绝缘材料制成的 绝缘层。
例如，所述栅电极在所述基底基板上，所述半导体层在所述栅电极之上。 例如，所述半导体保护层包括位于栅电极和半导体层之间且与半导体层 的下侧相邻的栅极绝缘复合层结构，该栅极绝缘复合层结构包括由能够避免 半导体层失氧的绝缘材料制成的与半导体层接触的栅极绝缘保护层和由易 刻蚀的绝缘材料制成的栅极绝缘层。
例如， 所述源电极与漏电极位于所述半导体层上， 之间设置有沟道。 的刻蚀阻挡复合层结构 ,该刻蚀阻挡复合层结构包括由能够避免半导体层失 氧的绝缘材料制成的与半导体层接触的刻蚀阻挡保护层和由易刻蚀的绝缘 材料制成的刻蚀阻挡绝缘层。
例如，所述半导体层位于所述基底基板上，所述栅电极位于所述半导体 层上。
例如，所述半导体保护层位于基底基板和半导体层之间且与半导体层的 下侧相邻的修饰绝缘复合层结构，该修饰绝缘复合层结构包括由能够避免半 导体层失氧的绝缘材料制成的与半导体层接触的修饰绝缘保护层和由易刻 蚀的绝缘材料制成的修饰绝缘层。
例如， 所述源电极与漏电极位于所述半导体层上， 在之间设置有沟道。 例如，所述半导体保护层包括位于所述沟道之中且与半导体层的上侧相 邻的刻蚀阻挡复合层结构，该刻蚀阻挡复合层结构包括由能够避免半导体层 失氧的绝缘材料制成的与半导体层接触的刻蚀阻挡保护层和由易刻蚀的绝 缘材料制成的刻蚀阻挡绝缘层。
例如， 所述半导体层由金属氧化物半导体材料形成。
例如， 所述保护层与绝缘层的厚度比例为 1/10 ~ 3/5。
例如， 所述保护层的厚度范围为 300A ~ 1500A, 所述绝缘层的厚度范 围为 1000A ~ 20000 A。
例如，所述刻蚀阻挡保护层釆用硅氧化物或金属氧化物制成，所述刻蚀 阻挡绝缘层釆用釆用氮化物或者有机绝缘材料制成。
例如， 所述保护层釆用 SiOx或者 A1203制成， 所述绝缘层釆用 SiNx 或者有机树脂制成。
例如， 所述阵列基板中还包括有钝化层与透明像素电极。
例如， 生成 SiNx所对应的反应气体为 Si¾、 NH3与 N2, 或者 SiH2Cl2、 丽 3与 N2。
本发明实施例的 TFT阵列基板中，与半导体层相邻的半导体保护层釆用 复合层结构， 在所述复合层结构中， 与半导体层接触的保护层釆用能够避免 半导体层失氧的绝缘材料制成， 例如可釆用硅氧化物或金属氧化物制成， 此 种结构可以避免半导体层失氧， 有利于提升 TFT阵列基板的稳定性； 而与所 述保护层接触（即未与半导体层接触）的绝缘层釆用易刻蚀的绝缘材料制成， 例如釆用氮化物或有机绝缘材料制成， 此种结构有利于提升该阵列基板的整 体刻蚀速度， 有利于提升产能， 适合大批量的生产。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。 图 1 ( a ) - ( f )为本发明实施例 1中 TFT阵列基板的结构示意图， 其中： 图 1 (a)为实施例 1中第一次光刻工艺完成之后的 TFT阵列基板的结构 示意图；
图 1 (b)为实施例 1 中第二次光刻工艺完成之后的 TFT阵列基板的结 构示意图；
图 1 (c)为实施例 1中第三次光刻工艺完成之后的 TFT阵列基板的结构 示意图；
图 1 (d)为实施例 1 中第四次光刻工艺完成之后的 TFT阵列基板的结 构示意图；
图 1 (e)为实施例 1中第五次光刻工艺完成之后的 TFT阵列基板的结构 示意图；
图 1 (f)为实施例 1中第六次光刻工艺完成之后的 TFT阵列基板的结构 示意图；
图 2 ( a ) - ( f )为本发明实施例 2中 TFT阵列基板的结构示意图； 其中： 图 2(a)为实施例 2中第一次光刻工艺完成之后的 TFT阵列基板的结构 示意图；
图 2 (b)为实施例 2中第二次光刻工艺完成之后的 TFT阵列基板的结 构示意图；
图 2(c)为实施例 2中第三次光刻工艺完成之后的 TFT阵列基板的结构 示意图；
图 2 (d)为实施例 2中第四次光刻工艺完成之后的 TFT阵列基板的结 构示意图；
图 2(e)为实施例 2中第五次光刻工艺完成之后的 TFT阵列基板的结构 示意图；
图 2 (f)为实施例 2中第六次光刻工艺完成之后的 TFT阵列基板的结构 示意图。
1 _基板； 2 -栅电极； 3 _栅极绝缘层；
4-栅极绝缘保护层； 5-半导体层； 6-刻蚀阻挡保护层；
7-刻蚀阻挡绝缘层； 8-源电极； 9-漏电极；
10-钝化层； 11 -透明像素电极； 12-过孔； 13 -修饰绝缘保护层； 14 -修饰绝缘层； 15-沟道。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。基于所描 述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例中， TFT阵列基板包括： 基底基板 1和作为开关元件 的薄膜晶体管。 所述薄膜晶体管包括栅电极 2、 半导体层 5、半导体保护层、 源电极 8和漏电极 9。与所述半导体层 5相邻的半导体保护层釆用复合层结 构。所述复合层结构包括由能够避免半导体层 5失氧的绝缘材料制成的与半 导体层 5接触的保护层和由易刻蚀的绝缘材料制成的绝缘层。
TFT阵列基板上包括多条栅线和多条数据线，这些栅线和数据线彼此交 叉以定义呈阵列排列的多个像素区域，每个像素区域包括作为开关元件的薄 膜晶体管，薄膜晶体管的栅极与对应的栅线连接或一体形成， 源极与对应的 数据线连接或一体形成。在下面的描述仅针对一个像素区域的薄膜晶体管进 行， 但是该描述适用于其他像素区域的薄膜晶体管。
实施例 1
如图 1 ( f )所示， 本实施例中， TFT阵列基板包括： 基底基板 1 ; 形成 在基底基板 1上的栅电极 2;覆盖在栅电极 2上并延伸至所述基底基板 1上 的栅极绝缘层 3; 覆盖在栅极绝缘层 3上的栅极绝缘保护层 4; 形成在栅极 绝缘保护层 4上的半导体层 5;形成在半导体层 5上的源电极 8与漏电极 9, 所述源电极 8与漏电极 9之间形成有沟道 15; 形成在所述沟道 15之中的复 合层结构， 该复合层结构包括刻蚀阻挡保护层 6与刻蚀阻挡绝缘层 7 , 所述 刻蚀阻挡保护层 6位于刻蚀阻挡绝缘层 7下方并与半导体层 5接触；钝化层 10, 所述钝化层 10完全覆盖源电极 8、刻蚀阻挡绝缘层 7、 漏电极 9以及栅 极绝缘保护层 4, 所述钝化层 10覆盖漏电极 9的部分开有过孔 12; 形成在 钝化层 10上的透明像素电极 11 , 所述透明像素电极 11通过过孔 12与漏电 极 9连接。 在一个示例中， 与半导体层 5相邻的半导体保护层包括形成在沟道 15 之中的复合层结构， 即包括刻蚀阻挡保护层 6与刻蚀阻挡绝缘层 7, 在半导 体层 5之上。
在另一个示例中， 与半导体层 5相邻的半导体保护层包括栅极绝缘层 3 和栅极绝缘保护层 4构成的复合层结构，在半导体层 5之下，位于半导体层 5与栅电极 2之间。
在再一个示例中，与半导体层 5相邻的半导体保护层包括同时包括上述 两种情况， 从而半导体层 5在其上下两侧均能够得到保护。
本实施例的 TFT阵列基板例如用于垂直驱动型或水平驱动型液晶显示 装置， 然而本发明不限于此。
本实施例中， 所述栅极绝缘层 3/刻蚀阻挡绝缘层 7的厚度范围例如为 1000 A - 20000 A, 其可釆用氮化物或者有机绝缘材料制成， 如釆用 SiNx或 者有机树脂制成。 生成 SiNx所对应的反应气体为 Si¾、 N¾与 N2, 或者 Si¾Cl2、 丽 3与 N2。
本实施例中，所述栅极绝缘保护层 4/刻蚀阻挡保护层 6的厚度范围例如 为 300A ~ 1500A, 其可釆用硅氧化物或金属氧化物制成， 如釆用 SiOx或 A1203制成。
所述栅极绝缘层 3、 栅极绝缘保护层 4、 刻蚀阻挡保护层 6与刻蚀阻挡 绝缘层 7 例如可以釆用等离子体增强化学气相沉积法 （ Plasma Enhanced Chemical Vapor Deposition, PECVD)或者釆用溅射的方法形成。
在一个示例之中，与半导体层 5接触的栅极绝缘保护层 4和刻蚀阻挡保 护层 6均釆用避免半导体层 5失氧的材料制成，但所述材料较难刻蚀； 未与 半导体层 5接触的栅极绝缘层 3和刻蚀阻挡绝缘层 7均釆用易刻蚀的材料制 成。
在本实施例中，在作为半导体保护层的复合层结构之中，栅极绝缘保护 层 4与栅极绝缘层 3的厚度比例例如为 1/10 ~ 3/5。 或者， 在作为半导体保 护层的复合层结构之中，刻蚀阻挡保护层 6与刻蚀阻挡绝缘层 7的厚度比例 例如为 1/10 ~ 3/5。
由于釆用上述材料制成的复合层结构的半导体保护层既不会夺取半导 体层 5中的氧离子， 从而可提升 TFT阵列基板的稳定性， 又可以提升栅极 绝缘层与刻蚀阻挡层的刻蚀速度， 有利于提升产能， 适合大批量的生产。 所述基底基板 1可釆用透明的无碱玻璃基板或者石英基板，或者釆用其 他具有一定硬度的透明基板。
所述半导体层 5例如为透明非结晶氧化物半导体 IGZO ( In-Ga-Zn-0 ) 的金属氧化物半导体材料形成，例如釆用溅射的方法形成，其厚度范围例如 为 50 A ~ 1000 A。
所述栅电极 2、 源电极 8与漏电极 9釆用溅射或热蒸发的方法形成， 其 厚度范围例如为 4000A ~ 15000A。 栅电极 2、 源电极 8与漏电极 9可釆用 Cr、 W、 Cu、 Ti、 Ta或 Mo中任一所形成的单层膜制成， 或者釆用以上任 一金属的合金制成， 或者釆用以上金属的任意组合所形成的多层膜制成。
所述钝化层 10例如釆用 PECVD形成，其厚度范围例如为 1000A ~ 3000 A。 钝化层 10可釆用氧化物、 氮化物或者氧氮化合物制成。 形成所述氮化 物对应的反应气体可以为 Si¾、 NH3与 N2, 或者 Si¾Cl2、 NH3与 N2。
透明像素电极 11 釆用溅射或热蒸发的方法形成， 其厚度范围例如为 300A - 1500 A, 透明像素电极 11可釆用透明金属氧化物材料制成， 例如釆 用 ITO薄膜或 IZO薄膜制成。
本实施例 TFT阵列基板可以釆用六次光刻工艺过程形成。 一个示例的 工艺流程结合图 1 ( a ) -图 1 ( f)说明如下。
步骤（1 ), 如图 1 ( a )所示， 在基底基板 1上沉积栅极金属薄膜， 然 后通过第一次光刻工艺形成栅电极 3和栅极扫描线（图中未示出 ) 的图形。
步骤（2), 如图 1 ( b )所示， 在完成步骤（1 )的基底基板上依次沉积 栅极绝缘薄膜、用于形成半导体层的金属氧化物薄膜， 然后通过第二次光刻 工艺形成栅极绝缘层 3、 栅极绝缘保护层 4与半导体层 5的图形。 所述栅极 绝缘层 3覆盖在栅电极 2上并延伸至基底基板 1上。所述栅极绝缘保护层 4 覆盖在栅极绝缘层 3上，其平面面积尺寸与栅极绝缘层 3的平面面积尺寸基 本相等。
步骤 （3), 如图 1 ( c )所示， 在完成步骤（2 ) 的基板上沉积两层刻蚀 阻挡绝缘薄膜，然后通过第三次光刻工艺形成刻蚀阻挡保护层 6与刻蚀阻挡 绝缘层 7的图形。所述刻蚀阻挡绝缘层 7覆盖在刻蚀阻挡保护层 6上并与其 平面尺寸相同，所述刻蚀阻挡保护层 6位于半导体层 5上并与之接触。刻蚀 阻挡保护层 6与刻蚀阻挡绝缘层 7基本对应于要形成的薄膜晶体管的沟道区 域。
步骤（4) , 如图 1 ( d )所示， 在完成步骤（3 )的基底基板上沉积源漏 极金属薄膜， 然后通过第四次光刻工艺形成源电极 8、 漏电极 9与数据扫描 线（图中未示出）的图形。 所述源电极 8与漏电极 9位于半导体层 5上， 并 分别位于刻蚀阻挡保护层 6与刻蚀阻挡绝缘层 7的两侧，在它们之间形成沟 道。
步骤 （5), 如图 1 ( e )所示， 在完成步骤（4 ) 的基底基板上沉积钝化 层薄膜， 然后通过第五次光刻工艺形成具有过孔 12的钝化层 10的图形，所 述过孔 12位于漏电极 9上方， 暴露漏电极 9的一部分。
步骤（6 ), 如图 1 ( f )所示， 在完成步骤（5 ) 的基底基板上沉积透明 导电薄膜， 然后通过第六次光刻工艺形成透明像素电极 11的图形， 使所述 透明像素电极 11位于过孔 12上方，并使透明像素电极 11通过过孔 12与漏 电极 9连接。
本实施例中， 各次光刻工艺中的刻蚀工艺可都釆用干法刻蚀完成。 实施例 2
如图 2 ( f )所示， 本实施例中， TFT阵列基板包括： 基底基板 1 ; 覆盖 在基底基板 1上的修饰绝缘层 14;覆盖在修饰绝缘层 14上的修饰绝缘保护 层 13; 形成在修饰绝缘保护层 13上的半导体层 5; 形成在半导体层 5上的 源电极 8与漏电极 9,所述源电极 8与漏电极 9之间设置有沟道 15; 形成在 所述沟道 15之中的复合层结构， 该复合层结构包括刻蚀阻挡保护层 6与刻 蚀阻挡绝缘层 7 ,所述刻蚀阻挡保护层 6位于刻蚀阻挡绝缘层 7下方并与半 导体层 5接触； 栅极绝缘层 3 , 所述栅极绝缘层 3将源电极 8、 刻蚀阻挡绝 缘层 7、 漏电极 9以及栅极绝缘保护层 4完全覆盖， 所述栅极绝缘层 3覆盖 漏电极 9的部分开有过孔 12; 形成在栅极绝缘层 3上的透明像素电极 11 , 所述透明像素电极 11通过过孔 12与漏电极 9连接。
在一个示例中， 与半导体层 5相邻的半导体保护层包括形成在沟道 15 之中的复合层结构， 即包括刻蚀阻挡保护层 6与刻蚀阻挡绝缘层 7。
在另一个示例中， 与半导体层 5 相邻的半导体保护层包括修饰绝缘层 14和修饰绝缘保护层 13构成的复合层结构， 位于半导体层 5与基底基板 1 之间。
在再一个示例中，与半导体层 5相邻的半导体保护层包括同时包括上述 两种情况， 从而半导体层 5在其上下两侧均能够得到保护。
同样， 本实施例的 TFT阵列基板例如用于垂直驱动型或水平驱动型液 晶显示装置， 然而本发明不限于此。
在本实施例中， 所述修饰绝缘层 14的材质、 厚度及形成方法可与实施 例 1中的栅极绝缘层 3/刻蚀阻挡绝缘层 7相同。
在本实施例中， 所述修饰绝缘保护层 13的材质、 厚度及形成方法可与 实施例 1中的栅极绝缘保护层 4/刻蚀阻挡保护层 6相同。
本实施例中，栅极绝缘层 3不与半导体层 5直接接触， 因而可釆用单层 结构， 该单层结构的材质、 厚度及形成方法可与实施例 1 中的栅极绝缘层 3/刻蚀阻挡绝缘层 7相同，也可与实施例 1中的栅极绝缘保护层 4/刻蚀阻挡 保护层 6相同。
组成本实施例阵列基板结构的其他各层的材质、厚度及形成方法与实施 例 1相同， 不再赘述。
半导体层 5例如由透明非结晶氧化物半导体 IGZO ( In-Ga-Zn-0 ) 的金 属氧化物半导体材料形成， 例如釆用溅射的方法形成， 其厚度范围例如为 50 A ~ 1000 A。
由于釆用上述材料制成的复合层结构的半导体保护层既不会夺取半导 体层 5中的氧离子， 从而可提升 TFT阵列基板的稳定性， 又可以提升栅极 绝缘层与刻蚀阻挡层的刻蚀速度， 有利于提升产能， 适合大批量的生产。
本实施例 TFT阵列基板例如可以釆用六次光刻工艺过程形成。 一个示 例的工艺流程结合图 2 ( a ) -2 ( f )说明如下。
步骤（1 ), 如图 2 ( a )所示， 在基底基板 1上依次沉积两层修饰绝缘 薄膜、 金属氧化物薄膜， 然后通过第一次光刻工艺形成修饰绝缘层 14、 修 饰绝缘保护层 13与半导体层 5的图形，所述修饰绝缘保护层 13覆盖在修饰 绝缘层 14上并与其平面尺寸相同， 所述修饰绝缘层 14覆盖在基底基板 1 上。
步骤（2 ), 如图 2 ( b )所示， 在完成步骤（ 1 )的基底基板上沉积两层 刻蚀阻挡绝缘薄膜，通过第二次光刻工艺形成包括刻蚀阻挡保护层 6与刻蚀 阻挡绝缘层 7的复合层结构的图形，所述刻蚀阻挡绝缘层 7覆盖在刻蚀阻挡 保护层 6上并与其平面尺寸相同， 所述刻蚀阻挡保护层 6位于半导体层 5 上并与之接触；
步骤（3), 如图 2 (c)所示， 在完成步骤（2) 的基底基板上沉积源漏 极金属薄膜，通过第三次光刻工艺形成源电极 8、漏电极 9与数据扫描线（图 中未示出）的图形， 所述源电极 8与漏电极 9位于半导体层 5上， 并分别位 于刻蚀阻挡保护层 6与刻蚀阻挡绝缘层 7的两侧；
步骤（4), 如图 2 (d)所示， 在完成步骤（3)的基底基板上沉积栅极 绝缘薄膜， 通过第四次光刻工艺形成栅极绝缘层 3及过孔 12的图形， 使所 述过孔 12位于漏电极 9上方；
步骤（5), 如图 2 (e)所示， 在完成步骤（4) 的基底基板上沉积透明 导电薄膜， 通过第五次光刻工艺形成透明像素电极 11的图形， 使所述透明 像素电极 11位于过孔 12上方，并使透明像素电极 11通过过孔 12与漏电极 9连接；
步骤（6), 如图 2 (f)所示， 在完成步骤（5) 的基底基板上沉积栅极 金属薄膜， 通过第六次光刻工艺形成栅电极 3和栅极扫描线（图中未示出） 的图形。
本实施例中， 各次光刻工艺中的刻蚀工艺都可以釆用干法刻蚀完成。 对于本领域内的普通技术人员而言， 在不脱离本发明的精神和实质的情 况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims

权利要求书
1、 一种薄膜晶体管 （TFT) 阵列基板， 包括： 基底基板（1)和作为 开关元件的薄膜晶体管， 所述薄膜晶体管包括栅电极（2)、 半导体层（5)、 半导体保护层、 源电极（8)和漏电极（9),
其中， 所述半导体保护层与半导体层（5)相邻， 该半导体保护层包括 复合层结构， 所述复合层结构包括由能够避免半导体层（5)失氧的绝缘材 料制成的与半导体层（5)接触的保护层和由易刻蚀的绝缘材料制成的绝缘 层。
2、 根据权利要求 1所述的 TFT阵列基板， 其中， 所述栅电极在所述 基底基板（ 1 )上， 所述半导体层 ( 5 )在所述栅电极 ( 2 )之上。
3、 根据权利要求 2所述的 TFT阵列基板， 其中， 所述半导体保护层 包括位于栅电极（2)和半导体层（5)之间且与半导体层（5) 的下侧相邻 的栅极绝缘复合层结构， 该栅极绝缘复合层结构包括由能够避免半导体层 (5)失氧的绝缘材料制成的与半导体层（ 5 )接触的栅极绝缘保护层（ 4 ) 和由易刻蚀的绝缘材料制成的栅极绝缘层（3 )。
4、根据权利要求 2或 3所述的 TFT阵列基板， 其中， 所述源电极 ( 8 ) 与漏电极（9)位于所述半导体层（5)上， 之间设置有沟道（15)。
5、 根据权利要求 2-4任一所述的 TFT阵列基板， 其中， 所述半导体 保护层包括在所述沟道（ 15 )之中且与半导体层（ 5 ) 的上侧相邻的刻蚀阻 挡复合层结构， 该刻蚀阻挡复合层结构包括由能够避免半导体层（5) 失氧 的绝缘材料制成的与半导体层（ 5 )接触的刻蚀阻挡保护层（ 6 )和由易刻蚀 的绝缘材料制成的刻蚀阻挡绝缘层（ 7 )。
6、 根据权利要求 1所述的 TFT阵列基板， 其中， 所述半导体层 （5) 位于所述基底基板（ 1 )上， 所述栅电极 ( 2 )位于所述半导体层（ 5 )上。
7、 根据权利要求 6所述的 TFT阵列基板， 其中， 所述半导体保护层 ( 5 )位于基底基板（ 1 )和半导体层（ 5 )之间且与半导体层（ 5 )的下侧相 邻的修饰绝缘复合层结构，该修饰绝缘复合层结构包括由能够避免半导体层 (5) 失氧的绝缘材料制成的与半导体层（5)接触的修饰绝缘保护层（13) 和由易刻蚀的绝缘材料制成的修饰绝缘层 ( 14 )。
8、根据权利要求 6或 7所述的 TFT阵列基板， 其中， 所述源电极 ( 8 ) 与漏电极（9 )位于所述半导体层（5 )上， 在之间设置有沟道（15 )。
9、 根据权利要求 6-8任一所述的 TFT阵列基板， 其中， 所述半导体 保护层包括位于所述沟道（15 )之中且与半导体层（5 ) 的上侧相邻的刻蚀 阻挡复合层结构， 该刻蚀阻挡复合层结构包括由能够避免半导体层（5 )失 氧的绝缘材料制成的与半导体层（ 5 )接触的刻蚀阻挡保护层（ 6 )和由易刻 蚀的绝缘材料制成的刻蚀阻挡绝缘层 ( 7 )。
10、 根据权利要求 1-9任一所述的 TFT阵列基板， 其中， 所述半导体 层（5 ) 由金属氧化物半导体材料形成。
11、 根据权利要求 1-10任一所述的 TFT阵列基板， 其中， 所述保护层 与绝缘层的厚度比例为 1/10 ~ 3/5。
12、 根据权利要求 11所述的 TFT阵列基板， 其中， 所述保护层的厚度 范围为 300A ~ 1500A, 所述绝缘层的厚度范围为 1000A ~ 20000 A。
13、 根据权利要求 1-12任一所述的 TFT阵列基板， 其中， 所述刻蚀阻 挡保护层釆用硅氧化物或金属氧化物制成，所述刻蚀阻挡绝缘层釆用釆用氮 化物或者有机绝缘材料制成。
14、 根据权利要求 1-13任一所述的 TFT阵列基板， 其中， 所述保护层 釆用 SiOx或者 A1203制成， 所述绝缘层采用 SiNx或者有机树脂制成。
15、根据权利要求 1-14任一所述的 TFT阵列基板，还包括有钝化层（ 10 ) 与透明像素电极（11 )。
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Families Citing this family (12)

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Publication number Priority date Publication date Assignee Title
CN102956713B (zh) 2012-10-19 2016-03-09 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN103000628B (zh) * 2012-12-14 2015-04-22 京东方科技集团股份有限公司 显示装置、阵列基板及其制作方法
CN103904127A (zh) * 2012-12-26 2014-07-02 鸿富锦精密工业（深圳）有限公司 薄膜晶体管
CN103456745B (zh) * 2013-09-10 2016-09-07 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN103676386B (zh) * 2013-12-27 2016-10-05 京东方科技集团股份有限公司 一种显示面板及显示装置
TWI532192B (zh) * 2014-02-20 2016-05-01 友達光電股份有限公司 薄膜電晶體及畫素結構
JP6427595B2 (ja) * 2014-11-28 2018-11-21 シャープ株式会社 半導体装置およびその製造方法
CN105589276A (zh) * 2016-03-14 2016-05-18 深圳市华星光电技术有限公司 阵列基板、液晶显示面板及液晶显示装置
KR101818339B1 (ko) * 2016-04-29 2018-02-21 고려대학교 산학협력단 광안정성 확보를 위한 비정질 산화물 박막 트랜지스터
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CN110112212A (zh) * 2019-04-25 2019-08-09 深圳市华星光电技术有限公司 薄膜晶体管和阵列基板
CN110098201A (zh) * 2019-05-16 2019-08-06 合肥京东方光电科技有限公司 晶体管器件及其制造方法、显示基板、显示装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101884109A (zh) * 2007-12-04 2010-11-10 佳能株式会社 包含绝缘层的氧化物半导体器件和使用该器件的显示装置

Family Cites Families (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW223178B (en) * 1992-03-27 1994-05-01 Semiconductor Energy Res Co Ltd Semiconductor device and its production method
JPH08107254A (ja) * 1994-09-14 1996-04-23 Xerox Corp マルチ波長レーザダイオードアレイ
US5514891A (en) * 1995-06-02 1996-05-07 Motorola N-type HIGFET and method
US5614739A (en) * 1995-06-02 1997-03-25 Motorola HIGFET and method
US5793072A (en) * 1996-02-28 1998-08-11 International Business Machines Corporation Non-photosensitive, vertically redundant 2-channel α-Si:H thin film transistor
JP3323889B2 (ja) * 1996-10-28 2002-09-09 三菱電機株式会社 薄膜トランジスタの製造方法
JP3968484B2 (ja) * 1998-02-18 2007-08-29 ソニー株式会社 薄膜トランジスタの製造方法
KR100312259B1 (ko) * 1999-02-05 2001-11-03 구본준, 론 위라하디락사 액정표시장치의 불량패턴 제거방법 및 액정표시장치 구조
US6503772B1 (en) * 1999-03-26 2003-01-07 Fuji Xerox Co., Ltd. Method of manufacturing a thin film transistor-integrated color filter
KR100638525B1 (ko) 1999-11-15 2006-10-25 엘지.필립스 엘시디 주식회사 컬러 액정표시장치용 어레이기판 제조방법
KR100577410B1 (ko) * 1999-11-30 2006-05-08 엘지.필립스 엘시디 주식회사 엑스레이 영상 감지소자 및 그 제조방법
US6646284B2 (en) * 2000-12-12 2003-11-11 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
SG111923A1 (en) * 2000-12-21 2005-06-29 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
SG118117A1 (en) * 2001-02-28 2006-01-27 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
TW548860B (en) * 2001-06-20 2003-08-21 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
US6639246B2 (en) * 2001-07-27 2003-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4090716B2 (ja) 2001-09-10 2008-05-28 雅司 川崎 薄膜トランジスタおよびマトリクス表示装置
US6815723B2 (en) * 2001-12-28 2004-11-09 Semiconductor Energy Laboratory Co., Ltd. Light emitting device, method of manufacturing the same, and manufacturing apparatus therefor
US6853052B2 (en) * 2002-03-26 2005-02-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a buffer layer against stress
KR101006439B1 (ko) * 2003-11-12 2011-01-06 삼성전자주식회사 박막 트랜지스터 표시판의 제조 방법
CN1918708B (zh) * 2004-02-06 2013-07-17 株式会社半导体能源研究所 半导体装置
WO2005088704A1 (en) * 2004-03-12 2005-09-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7282380B2 (en) * 2004-03-25 2007-10-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7791107B2 (en) * 2004-06-16 2010-09-07 Massachusetts Institute Of Technology Strained tri-channel layer for semiconductor-based electronic devices
US7211456B2 (en) * 2004-07-09 2007-05-01 Au Optronics Corporation Method for electro-luminescent display fabrication
TWI234288B (en) * 2004-07-27 2005-06-11 Au Optronics Corp Method for fabricating a thin film transistor and related circuits
US8269227B2 (en) * 2005-06-09 2012-09-18 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and electronic device
WO2007011061A1 (en) * 2005-07-22 2007-01-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP5234301B2 (ja) * 2005-10-03 2013-07-10 Ｎｌｔテクノロジー株式会社 薄膜トランジスタ、薄膜トランジスタアレイ基板、液晶表示装置およびそれらの製造方法
WO2007088795A1 (en) * 2006-02-03 2007-08-09 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of memory element, laser irradiation apparatus, and laser irradiation method
JP2007248987A (ja) * 2006-03-17 2007-09-27 Toshiba Matsushita Display Technology Co Ltd 表示装置用のアレイ基板
KR100759681B1 (ko) * 2006-03-29 2007-09-17 삼성에스디아이 주식회사 유기 전계 발광표시장치
US7768000B2 (en) * 2006-09-29 2010-08-03 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
KR101410926B1 (ko) * 2007-02-16 2014-06-24 삼성전자주식회사 박막 트랜지스터 및 그 제조방법
KR101365411B1 (ko) * 2007-04-25 2014-02-20 엘지디스플레이 주식회사 박막 트랜지스터의 제조 방법과 액정표시장치의 제조 방법
US20090090915A1 (en) * 2007-10-05 2009-04-09 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, display device having thin film transistor, and method for manufacturing the same
JP5311957B2 (ja) * 2007-10-23 2013-10-09 株式会社半導体エネルギー研究所 表示装置及びその作製方法
JP5311955B2 (ja) * 2007-11-01 2013-10-09 株式会社半導体エネルギー研究所 表示装置の作製方法
US7786485B2 (en) * 2008-02-29 2010-08-31 Semicondutor Energy Laboratory Co., Ltd. Thin-film transistor and display device
KR101496148B1 (ko) * 2008-05-15 2015-02-27 삼성전자주식회사 반도체소자 및 그 제조방법
KR101602252B1 (ko) * 2008-06-27 2016-03-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 트랜지스터, 반도체장치 및 전자기기
KR101516415B1 (ko) * 2008-09-04 2015-05-04 삼성디스플레이 주식회사 박막트랜지스터 기판, 이의 제조 방법, 및 이를 갖는 표시장치
JP5525224B2 (ja) * 2008-09-30 2014-06-18 株式会社半導体エネルギー研究所 表示装置
JP5552753B2 (ja) * 2008-10-08 2014-07-16 ソニー株式会社 薄膜トランジスタおよび表示装置
KR20100064657A (ko) * 2008-12-05 2010-06-15 엘지디스플레이 주식회사 박막트랜지스터 어레이기판과 그 제조방법
JP5538797B2 (ja) * 2008-12-12 2014-07-02 キヤノン株式会社 電界効果型トランジスタ及び表示装置
US8575713B2 (en) * 2009-02-19 2013-11-05 Sharp Kabushiki Kaisha Semiconductor device and display device
WO2011052285A1 (ja) * 2009-10-28 2011-05-05 シャープ株式会社 新規な化合物、電界効果トランジスタ及び太陽電池ならびにこれらの製造方法、有機半導体層用組成物、ならびにｐ型半導体層用組成物
US8685803B2 (en) * 2009-12-09 2014-04-01 Sharp Kabushiki Kaisha Semiconductor device and method for producing same
DE102009060446A1 (de) 2009-12-22 2011-06-30 Treofan Germany GmbH & Co. KG, 66539 Mikroporöse Separator-Folie für Doppelschichtkondensatoren
US8759917B2 (en) * 2010-01-04 2014-06-24 Samsung Electronics Co., Ltd. Thin-film transistor having etch stop multi-layer and method of manufacturing the same
KR20110080118A (ko) 2010-01-04 2011-07-12 삼성전자주식회사 다층의 식각 정지층을 구비한 박막 트랜지스터 및 그 제조방법
KR101978106B1 (ko) * 2010-01-20 2019-05-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2011187626A (ja) * 2010-03-08 2011-09-22 Sony Corp 薄膜トランジスタおよび電子機器
JP5523896B2 (ja) * 2010-03-31 2014-06-18 富士フイルム株式会社 薄膜トランジスタおよびその製造方法
WO2011135874A1 (ja) * 2010-04-30 2011-11-03 シャープ株式会社 半導体装置およびその製造方法ならびに表示装置
WO2011141954A1 (ja) * 2010-05-11 2011-11-17 パナソニック株式会社 表示装置用薄膜半導体装置及びその製造方法
KR101889748B1 (ko) * 2011-01-10 2018-08-21 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법
JP5352599B2 (ja) * 2011-01-17 2013-11-27 株式会社半導体エネルギー研究所 半導体装置
JPWO2012098575A1 (ja) * 2011-01-18 2014-06-09 パナソニック株式会社 薄膜トランジスタ装置の製造方法、薄膜トランジスタおよび表示装置
TWI500163B (zh) * 2012-10-15 2015-09-11 Innocom Tech Shenzhen Co Ltd 低溫多晶矽薄膜電晶體、其製備方法及顯示裝置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101884109A (zh) * 2007-12-04 2010-11-10 佳能株式会社 包含绝缘层的氧化物半导体器件和使用该器件的显示装置

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